Device reset method, apparatus and system, and electronic device

Abstract

The present application provides a device reset method, apparatus and system, and an electronic device. The method comprises: acquiring a restart signal of a first host, wherein the restart signal carries a port identifier of the first host; and determining, from preset configuration information, target switch domain information corresponding to the port identifier of the first host, wherein the configuration information comprises port identifiers of different hosts and switch domain information corresponding to each port identifier. In the technical solution, configuration information of switch uplink ports connected to host ports and configuration information of devices connected to downlink ports corresponding to the uplink ports are preset; and upon receiving a host restart signal, an electronic device accurately determines, on the basis of pre-bound switch domain information, which switch uplink ports connected to host ports and which devices connected to downlink ports need to be reset, and sends a reset signal to the corresponding ports and downlink connection devices, thereby guaranteeing normal operation of other uplink ports of switches connected to hosts and other devices connected to downlink ports of said switches.

Description

Equipment reset methods, devices, systems and electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202411044178.6, filed on July 31, 2024, entitled “Device Reset Method, Apparatus, System and Electronic Equipment”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of Internet technology, and in particular to a device reset method, apparatus, system and electronic device. Background Technology

[0003] In the field of Internet technology, a host contains one or more central processing unit (CPU) chips, and multiple high-speed serial computer expansion bus standard (Peripheral Component Interconnect express, PCIe) devices establish a connection with at least one host through the uplink port of at least one PCIe switch.

[0004] When a host needs to perform a DC power restart, all switches connected to that host will be reset. As a result, PCIe devices connected to the downstream ports of the switches will also be restarted or reset. This causes the upstream ports of switches connected to non-target hosts, as well as the associated PCIe devices, to be restarted or reset, interrupting ongoing services.

[0005] Therefore, how to prevent related devices not in the host from being restarted or reset when the host restarts has become an urgent technical problem to be solved. Summary of the Invention

[0006] This application provides a device reset method, apparatus, system, and electronic device to solve the technical problem in the prior art where, when a host restarts, related devices not in that host are restarted or reset.

[0007] In a first aspect, embodiments of this application provide a device reset method, including:

[0008] Obtain the restart signal from the first host, wherein the restart signal carries the port identifier of the first host;

[0009] The target switch domain information corresponding to the port identifier of the first host is determined from the pre-set configuration information. The configuration information includes the port identifiers of different hosts and the switch domain information corresponding to each port identifier. Each switch domain information includes: the uplink port identifier of the switch corresponding to the port identifier of the host, the downlink port identifier of the switch corresponding to the uplink port identifier of the switch, and the device identifier corresponding to the downlink port identifier of the switch.

[0010] Send a reset signal to the target switch and target device involved in the target switch domain information to reset the uplink port of the target switch and the target device.

[0011] In one possible design of the first aspect, before determining the target switch domain information corresponding to the port identifier of the first host from pre-defined configuration information, the method further includes:

[0012] Obtain the uplink port identifier of each switch, the downlink port identifier corresponding to the uplink port identifier of each switch, the port identifier of the corresponding host, and the device identifier corresponding to each downlink port identifier;

[0013] The configuration information is constructed based on the uplink port identifier of each switch, the port identifier of the host corresponding to the uplink port identifier of each switch, the downlink port identifier corresponding to the uplink port identifier of each switch, and the device identifier corresponding to the downlink port identifier.

[0014] Store the configuration information.

[0015] In another possible design of the first aspect, storing the configuration information includes:

[0016] For each port identifier in each host, a register value is generated based on the uplink port identifier of the switch corresponding to the port identifier and the device identifier corresponding to the downlink port identifier, respectively.

[0017] A register address is configured for the port identifier in the electronic device, and the register value is stored under the register address. The register value under the register address is used to represent the switch domain information.

[0018] In another possible design in the first aspect, generating a register value based on the device identifier corresponding to the uplink port identifier of the switch and the downlink port identifier of the switch, respectively, includes:

[0019] Based on the sequence number of the uplink port identifier of the switch corresponding to the port identifier among all uplink ports in the switch, determine the first N bits of the register value, where N is an integer greater than 0;

[0020] Based on the device identifier corresponding to the downlink port identifier of the switch and the sequence number of all downlink ports of the switch, determine the N+1 to M bits of the register value, where M is an integer greater than N+1.

[0021] In another possible design within the first aspect, determining the target switch domain information corresponding to the port identifier of the first host from pre-defined configuration information includes:

[0022] Based on the port identifier of the first host, the target register address is determined from at least one register address;

[0023] The target register value is determined from the target register address;

[0024] Based on the target register value, the target switch domain information is determined.

[0025] In another possible design of the first aspect, the information transmission method between the electronic device and the switch is an integrated circuit bus I. 2 C.

[0026] Secondly, embodiments of this application provide a device reset apparatus, comprising:

[0027] An acquisition module is used to acquire a restart signal from the first host, wherein the restart signal carries the port identifier of the first host;

[0028] The determination module is used to determine the target switch domain information corresponding to the port identifier of the first host in the pre-set configuration information. The configuration information includes the port identifiers of different hosts and the switch domain information corresponding to each port identifier. Each switch domain information includes: the uplink port identifier of the switch corresponding to the port identifier of the host, the downlink port identifier of the switch corresponding to the uplink port identifier of the switch, and the device identifier corresponding to the downlink port identifier of the switch.

[0029] The sending module is used to send a reset signal to the target switch and target device involved in the target switch domain information, so as to reset the uplink port of the target switch and the target device.

[0030] In one possible design of the second aspect, before determining the target switch domain information corresponding to the port identifier of the first host in the pre-set configuration information, the acquisition module is further configured to acquire the uplink port identifier of each switch, the downlink port identifier corresponding to the uplink port identifier of each switch and the port identifier of the corresponding host, and the device identifier corresponding to each downlink port identifier.

[0031] The construction module is used to construct the configuration information based on the uplink port identifier of each switch, the port identifier of the host corresponding to the uplink port identifier of each switch, the downlink port identifier corresponding to the uplink port identifier of each switch, and the device identifier corresponding to the downlink port identifier.

[0032] The storage module is used to store the configuration information.

[0033] In another possible design of the second aspect, the storage module stores the configuration information, specifically for:

[0034] For each port identifier in each host, a register value is generated based on the uplink port identifier of the switch corresponding to the port identifier and the device identifier corresponding to the downlink port identifier, respectively.

[0035] A register address is configured for the port identifier in the electronic device, and the register value is stored under the register address. The register value under the register address is used to represent the switch domain information.

[0036] In another possible design, the construction module generates a register value based on the device identifier corresponding to the uplink port identifier of the switch and the downlink port identifier of the switch, respectively. This value is specifically used for:

[0037] Based on the sequence number of the uplink port identifier of the switch corresponding to the port identifier among all uplink ports in the switch, determine the first N bits of the register value, where N is an integer greater than 0;

[0038] Based on the device identifier corresponding to the downlink port identifier of the switch and the sequence number of all downlink ports of the switch, determine the N+1 to M bits of the register value, where M is an integer greater than N+1.

[0039] In another possible design, the determining module determines the target switch domain information corresponding to the port identifier of the first host from pre-set configuration information, specifically for:

[0040] Based on the port identifier of the first host, the target register address is determined from at least one register address;

[0041] The target register value is determined from the target register address;

[0042] Based on the target register value, the target switch domain information is determined.

[0043] In another possible design, the information transmission method between the electronic device and the switch is an integrated circuit bus I. 2 C.

[0044] Thirdly, embodiments of this application provide a device reset system, including: an electronic device, at least one host, at least one switch, and at least one device;

[0045] In response to a reset request, the first host of the at least one host sends a reset signal to the electronic device, the reset signal carrying the port identifier of the first host;

[0046] The electronic device is used to perform the method described in the first aspect or any of the above methods to reset the uplink port of the target switch in the at least one switch and the target device in the at least one device.

[0047] Fourthly, embodiments of this application provide an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0048] The memory stores computer-executed instructions;

[0049] The processor executes computer execution instructions stored in the memory to implement the method as described in the first aspect or any of the above methods.

[0050] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method described in the first aspect or any of the above-described methods.

[0051] Sixthly, embodiments of this application provide a computer program, the computer program product including a computer program stored in a computer-readable storage medium, at least one processor can read the computer program from the computer-readable storage medium, and the at least one processor can implement the method described in the first aspect or any of the above methods when executing the computer program.

[0052] The device reset method, apparatus, system, and electronic device provided in this application embodiment acquire a restart signal from a first host, the restart signal carrying the port identifier of the first host; determine the target switch domain information corresponding to the port identifier of the first host in pre-set configuration information, the configuration information including port identifiers of different hosts and switch domain information corresponding to each port identifier, each switch domain information including: the uplink port identifier of the switch corresponding to the port identifier of the host, the downlink port identifier of the switch corresponding to the uplink port identifier of the switch, and the device identifier corresponding to the downlink port identifier of the switch; send a reset signal to the target switch and target device involved in the target switch domain information to reset the uplink port of the target switch and the target device. In this technical solution, the configuration information of the uplink port of the switch connected to the host port and the device connected to the corresponding downlink port are pre-set. When the host restart signal is received, the configuration information of the uplink port and downlink port connected to the switch of the pre-bound switch domain information is used to accurately determine which uplink ports and downlink port connected devices of the host port need to be reset, and a reset signal is sent to the corresponding port and downlink connected device, ensuring that the other uplink ports and downlink port connected devices of the switch connected to the host operate normally. Attached Figure Description

[0053] Figure 1 is a schematic diagram of restarting in a distributed system provided by existing technology;

[0054] Figure 2 is a schematic flowchart of the device reset method provided in an embodiment of this application;

[0055] Figure 3 is a schematic diagram of the interaction in the distributed system provided in an embodiment of this application;

[0056] Figure 4 is a schematic flowchart of the device reset method provided in the embodiment of this application.

[0057] Figure 5 is a schematic flowchart of the device reset method provided in the embodiment of this application.

[0058] Figure 6 is a schematic diagram of the device reset device provided in an embodiment of this application;

[0059] Figure 7 is a schematic diagram of the structure of the electronic device provided in the embodiment of this application. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0061] First, the terms used in the embodiments of this application will be explained:

[0062] Host: A computer or device that runs network services, applications, or data. It can refer to a specific server or computer system that a domain name points to.

[0063] Multiple high-speed serial computer expansion bus standards (Peripheral Component Interconnect Express, PCIe): These are the main expansion interface standards in computer systems, used to connect expansion cards (such as graphics cards, network adapters, storage controllers, etc.) to the system bus on the motherboard. They provide devices with high-speed, low-latency data transmission channels.

[0064] PCIe switch: A hardware device used to manage and expand PCIe bus device connections in a computer system.

[0065] Uplink port: Describes the port on which a device connects to a higher-level network infrastructure (such as the core network or other switches).

[0066] A domain is a collection of ports on a host and PCIe switches, including upstream and downstream ports and the connected devices (i.e., downstream devices) that are assigned to it.

[0067] Before introducing the embodiments of this application, the application background of the embodiments of this application will be explained first:

[0068] During large-scale AI training, PCIe switch-connected devices may require remote device reset management due to software errors, communication failures, or routine maintenance. Device reset methods allow administrators to trigger device restarts or initializations from remote locations or automated management systems to address technical issues such as fault recovery and maintenance system reliability, resource reallocation and load balancing, firmware upgrades and configuration changes, system debugging and diagnostics.

[0069] Currently, PCIe switches are primarily used in single-uplink scenarios, as the computing power of a single host may be insufficient to handle complex models and large-scale datasets. Due to the rapid development of large model training, the multi-uplink functionality of PCIe switches is being rapidly adopted. Utilizing the multi-uplink functionality of a PCIe switch allows for the allocation of PCIe devices mounted below, ensuring that the switch's downstream devices are evenly distributed across different uplink ports and their corresponding host ports.

[0070] In some application scenarios that require centralized management and high-performance computing, it is necessary to control multiple PCIe switches through a single host to improve CPU utilization, reduce cross-host transmission, and achieve resource sharing within the host to improve data interaction performance.

[0071] In addition, in some application scenarios that require distributed resource management and redundant access, multiple hosts are used to cross-control different PCIe Switch technologies, such as in GPU Box product applications.

[0072] However, the above-mentioned application scenarios may have the following technical problems: When multiple hosts cross-control different PCIe switches, coupling is formed between different PCIe switches and hosts. When a host needs to perform a DC restart, the entire PCIe switch it is connected to will be reset and the devices connected to it will also be restarted and reset synchronously. This will inevitably cause the PCIe devices connected to the uplink and downlink ports in the domain of other hosts to also interrupt their services, resulting in irreparable losses.

[0073] In other words, Figure 1 is a schematic diagram of restarting in a distributed system provided by existing technology. As shown in Figure 1, the technical problems existing in the prior art are introduced:

[0074] This application scenario includes: multiple hosts, multiple switches, and multiple downlink devices (in this embodiment, host 101, host 102, host 103, switch 201, switch 202, switch 203, device 301, device 302, ... device 312 are used as examples. In reality, the number of each type of entity is determined based on the pre-defined business needs).

[0075] Taking host 101 as an example, after host 101 receives the restart signal, host 101 sends restart signals to switch 201 and switch 202 through its own ports port0 and port1 respectively.

[0076] At this time, based on the restart signal, switch 201 sends restart commands to devices 301, 302, 303, and 304 corresponding to DS0, DS1, DS2, and DS3 under switch 201, respectively. That is, switch 201 is reset, and devices 301, 302, 303, and 304 are restarted.

[0077] Furthermore, based on the restart signal, switch 202 sends restart commands to devices 305, 306, and 307 corresponding to DS0, DS1, and DS2 under switch 201, respectively, that is, switch 202 is reset, and devices 305, 306, and 307 are restarted.

[0078] However, the implementation in Figure 1 violates the original intention of restarting host 101, that is, the target of restarting host 101 is the UP0 port in switch 201, the DS0 and DS1 corresponding to the UP0 port are respectively the devices 301 and 302; and the UP0 port in switch 202, the DS0 and DS1 corresponding to the UP0 port are respectively the devices 305 and 306.

[0079] In other words, the uplink ports of the switch that did not need to be reset were reset, and the downlink devices that did not need to be restarted were restarted, which seriously affected the current task processes on related devices that did not need to be operated.

[0080] To address the technical problems existing in the prior art, the inventors of this application propose the following technical concept: a mapping relationship based on the uplink port (connected to the corresponding host port) and downlink port (bound to the corresponding downlink device) within a PCIe Switch can be designed and stored in the electronic device. When any host needs to perform a DC restart, the electronic device, upon receiving the restart signal, can locate the corresponding PCIe Switch's uplink port and the downlink device connected to the downlink port with the mapping relationship. Then, a reset signal is sent to the corresponding PCIe Switch's uplink port and the device connected to the downlink port to perform a reset operation. During this process, the normal operation of other PCIe Switches and other downlink devices will not be affected.

[0081] The technical solution of this application will now be described in detail through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0082] It is worth noting that the application fields of the methods, apparatus, devices and storage media involved in the embodiments of this application are not limited.

[0083] It should be understood that the execution subject of the embodiments of this application is an electronic device, specifically any server, management server, or computing device in a distributed system, such as a CPLD.

[0084] Figure 2 is a schematic flowchart of a device reset method provided in an embodiment of this application. As shown in Figure 2, the method may include the following steps:

[0085] The embodiment shown in Figure 2 will be described with reference to Figure 3. Figure 3 is an interactive schematic diagram of the distributed system provided by the embodiment of this application. As shown in Figure 3, based on Figure 1, the schematic diagram also includes: CPLD.

[0086] Step 21: Obtain the restart signal from the first host.

[0087] The restart signal carries the identifier of the first host.

[0088] In this step, when the user or system requires the first host to be restarted, the first host sends a restart signal to the electronic device. The electronic device receives the restart signal and parses out the identifier of the first host.

[0089] In one possible implementation, referring to Figure 3, the host 101 obtains the user's restart command and generates a DC signal based on the restart command.

[0090] Step 22: Determine the target switch domain information corresponding to the port identifier of the first host in the pre-set configuration information.

[0091] The configuration information includes port identifiers for different hosts and switch domain information corresponding to each port identifier. Each switch domain information includes: the uplink port identifier of the switch corresponding to the host's port identifier, the downlink port identifier of the switch corresponding to the uplink port identifier of the switch, and the device identifier corresponding to the downlink port identifier of the switch.

[0092] In this step, the configuration information records the port identifiers of different hosts. After obtaining the port identifier of the first host, the port identifier that matches the port identifier of the first host can be determined from the port identifiers of the different hosts, and the switch domain information corresponding to the matching port identifier is used as the target switch domain information. That is, the configuration information actually provides a mapping relationship based on the switch domain information corresponding to the port identifiers of different hosts.

[0093] Furthermore, the target switch domain information includes the uplink port identifier of the switch corresponding to the port identifier of the first host, the downlink port identifier of the switch corresponding to the uplink port identifier of the switch, and the device identifier corresponding to the downlink port identifier of the switch.

[0094] The process of determining the configuration information can be implemented based on the embodiment shown in Figure 4 below, which will not be described in detail here.

[0095] Step 23: Send a reset signal to the target switch and target device involved in the target switch domain information to reset the uplink port of the target switch and the target device.

[0096] In this step, after determining the uplink port of the switch (denoted as the target switch) involved in the restart of the first host and the device (denoted as the target device) corresponding to the downlink port involved, a reset signal is sent to the target switch and the target device respectively.

[0097] Afterwards, upon receiving the reset signal, the target device performs a restart operation; upon receiving the reset signal, the target switch performs a reset operation on the corresponding uplink port in the target switch.

[0098] Referring to Figure 3, in one possible implementation, the reset signal can be an A signal (e.g., a PERST signal) sent by the CPLD.

[0099] Optionally, the information transmission method between the electronic device and the switch is a serial peripheral interface (Inter-Integrated Circuit, I... 2 C).

[0100] Among them, I 2 C-bus is a serial communication protocol that enables communication between devices using a small number of pins and lines. It supports the connection of multiple masters and slaves (e.g., multiple switches), allowing various devices to interact conveniently.

[0101] The device reset method provided in this application embodiment obtains a restart signal from a first host, the restart signal carrying the port identifier of the first host; determines the target switch domain information corresponding to the port identifier of the first host in pre-set configuration information, the configuration information including the port identifiers of different hosts and the switch domain information corresponding to each port identifier, each switch domain information including: the uplink port identifier of the switch corresponding to the host's port identifier, the downlink port identifier of the switch corresponding to the uplink port identifier of the switch, and the device identifier corresponding to the downlink port identifier of the switch; and sends a reset signal to the target switch and target device involved in the target switch domain information to reset the uplink port of the target switch and the target device. In this technical solution, the configuration information of the uplink port of the switch connected to the host port and the device connected to the corresponding downlink port are pre-set. When the host restart signal is received, the method accurately determines which host ports' uplink ports and downlink ports' connected devices need to be reset based on the pre-bound switch domain information, and sends a reset signal to the corresponding port and downlink connected device, ensuring the normal operation of other uplink ports and downlink ports' connected devices in the switch connected to the host.

[0102] Based on the above embodiments, Figure 4 is a second schematic flowchart of the device reset method provided in this application embodiment. As shown in Figure 4, before step 22 above, the method may further include the following steps:

[0103] Step 41: Obtain the uplink port identifier of each switch, the downlink port identifier corresponding to the uplink port identifier of each switch, the port identifier of the corresponding host, and the device identifier corresponding to each downlink port identifier.

[0104] In this step, in order for the electronic device to determine the specific downlink device that needs to be restarted and the port of the switch that needs to be reset after receiving the restart signal, it is necessary to obtain in advance the uplink port identifier of the switch corresponding to the host, the downlink port identifier corresponding to the uplink port identifier of the switch, and the downlink device connected to the downlink port identifier involved.

[0105] Then, for each host, the relevant identifiers and devices corresponding to that host are recorded.

[0106] Using Figures 1 and 3 as examples, the acquisition process will be explained as follows:

[0107] Taking host 101 as an example, ports Port0 and Port1 of host 101 are connected to UP0 port of switch 201 and UP0 port of switch 202, respectively.

[0108] Furthermore, the UP0 port of switch 201 corresponds to the downlink ports DS0 and DS1, and the UP0 port of switch 202 also corresponds to the downlink ports DS0 and DS1. The downlink ports DS0 and DS1 of switch 201 are connected to devices 301 and 302, respectively; the downlink port DS0 of switch 202 is connected to device 305, and DS1 is connected to device 306.

[0109] The aforementioned correspondence can be port mapping, for example, mapping an uplink port in a switch to a downlink port in a switch.

[0110] Step 42: Construct configuration information based on the uplink port identifier of each switch, the port identifier of the host corresponding to the uplink port identifier of each switch, the downlink port identifier corresponding to the uplink port identifier of each switch, and the device identifier corresponding to the downlink port identifier;

[0111] In this step, in order to quickly determine the uplink and downlink ports of the switch corresponding to the host when the host is restarted, as well as the device corresponding to the downlink port, the port identifier and device identifier obtained above need to be assigned to the corresponding port of the host.

[0112] Referring to Figure 3 as an example, taking Port0 and Port1 of host 101 as an example, the CPLD obtains the UP0 and UP1 ports of switch 201. For the UP0 port of switch 201, its configuration information can be the downlink ports DS0 and DS1 of switch 201, and the connection of DS0 and DS1 to devices 301 and 302 respectively. The UP1 port of switch 201 is similar and will not be described in detail here.

[0113] Step 43: Store configuration information.

[0114] In this step, the configuration information obtained above will be stored.

[0115] Optionally, step 43 can be implemented in the following ways:

[0116] Step 1: For each port identifier in each host, generate register values ​​based on the device identifiers corresponding to the uplink and downlink port identifiers of the switch corresponding to the port identifiers.

[0117] In this implementation, switches and electronic devices use I... 2 C transmits configuration information, and the electronic device stores the configuration information in registers. Table 1 is a register value mapping table provided in this application, as shown in Table 1:

[0118] Table 1

[0119] The implementation of the embodiments of this application will be described in detail with reference to Table 1 and Figure 1.

[0120] For example:

[0121] First, the first N bits of the register value can be determined based on the sequence number of the uplink port identifier of the switch among all uplink ports in the switch, where N is an integer greater than 0.

[0122] In one possible implementation, a switch has two uplink ports. The first N bits of the first byte can be set to correspond to the uplink ports of the switch, that is, the first N bits indicate that the switch has N uplink ports.

[0123] Optional, I 2 The minimum data size that C can transmit is one byte, or 8 bits, meaning the register value is in 8-bit binary format.

[0124] That is, in the application scenario shown in Figure 1, the switch has two uplink ports. For example, if the uplink port identifier is the first in the sequence number of all uplink ports in the switch, then the first byte is set to 1; if the uplink port identifier is the second in the sequence number of all uplink ports in the switch, then the second byte is set to 1, and if it does not exist, then it is set to 0.

[0125] It should be understood that if a switch has 3 uplink ports, then N is 3, and so on. The first N bits of the register value identify one-to-one with the uplink ports of the switch.

[0126] Secondly, based on the device identifier corresponding to the downlink port identifier of the switch and the corresponding uplink port identifier, determine the N+1 to M bits in the register value, where M is an integer greater than N+1.

[0127] In one possible implementation, the switch's downlink port can connect to multiple devices, and an 8-bit register can cover all of them. Depending on the specific scenario and the number of devices, the CPLD controller can select a register with more bits.

[0128] That is, after all the uplink bits, the next bit is the downlink device within the switch domain. The bits corresponding to the downlink port connected to the uplink port within the same switch domain are all 1, and the values ​​of the other bits are all 0, indicating that they are not in the same switch domain.

[0129] Specifically, when the uplink port identifier is the first in the sequence number of all uplink ports in the switch, and the corresponding downlink port is the first or second in the sequence number of all downlink ports, then the N+1 and N+2 bits have a value of 1, and the N+3 to M bits have a value of 0.

[0130] That is, combining Table 1 and Figure 1, one implementation is as follows:

[0131] Taking the first Domain0 of switch 201 as an example, the first bit value represents the UP0 port in switch 201. The mapping relationship between the UP0 port and DS0 and DS1 indicates that the UP0 port is in the first Domain0 of switch 201, so the first bit value is 1. The second bit value represents the UP1 port in switch 201, but the UP1 port is not in the first Domain0 of switch 201, so the second bit value is 0. The third and fourth bits represent the downstream ports DS0 and DS1 of switch 201 connecting to devices 301 and 302, so the third and fourth bits value is 1. Since the first Domain0 of switch 201 has no other connected devices, bits 4 to 8 are 0. Therefore, the register address of the first Domain0 of switch 201 can be obtained as 00001101.

[0132] Step 2: Configure the register address for the port identifier in the electronic device and store the register value under the register address.

[0133] The register value at the register address is used to represent switch domain information.

[0134] In this implementation, based on the above configuration, after obtaining the host's port identifier, the corresponding register address can be directly found, and the register value used to represent the switch domain information can be obtained from the register address.

[0135] The device reset method provided in this application obtains the uplink port identifier of each switch, the downlink port identifier corresponding to the uplink port identifier of each switch, the port identifier of the corresponding host, and the device identifier corresponding to each downlink port identifier; constructs configuration information based on the uplink port identifier of each switch, the port identifier of the corresponding host, the downlink port identifier of each switch, and the device identifier corresponding to each downlink port identifier; and stores the configuration information. In this technical solution, the electronic device constructs configuration information based on the obtained uplink port identifier of the switch, the downlink port identifier corresponding to the uplink port identifier of each switch, the port identifier of the corresponding host, and the device identifier corresponding to each downlink port identifier, and stores it in registers, which enables rapid determination of the device corresponding to the uplink port and downlink port of the switch to which the host is located.

[0136] Based on the above embodiments, Figure 5 is a schematic flowchart of the device reset method provided in this application embodiment. As shown in Figure 5, step 22 above may include the following steps:

[0137] Step 51: Determine the target register address from at least one register address based on the port identifier of the first host.

[0138] In this step, in conjunction with the above embodiments, the electronic device obtains the DC signal sent by the first host, and the electronic device pulls the pin of the corresponding general purpose input / output (GPIO) port high. The electronic device determines the target register address based on the port identifier of the first host.

[0139] GPIO is a common interface standard in microcontrollers or embedded systems. It allows chips to interact with external devices using digital signals; it can act as an input to receive external signals or as an output to send signals to external devices.

[0140] Step 52: Determine the value of the target register from the target register address;

[0141] In this implementation, after obtaining the target register address, the electronic device can obtain the register value at the target register address and use the register value as the target register value.

[0142] For example, the register values ​​corresponding to the switch domains where the first host ports Port0 and Port1 are located are 00001101 and 00001101, respectively.

[0143] Step 53: Determine the target switch domain information based on the target register value.

[0144] In this step, after obtaining the target register value, the device identifier represented by each position in the target register value, as well as the uplink port identifier of the switch, can be read, which is the target switch domain information.

[0145] This facilitates sending reset signals to the corresponding target switch and downlink device (i.e., target device) to reset the uplink port of the target switch and the target device.

[0146] For example, the CPLD can look up register values ​​00001101 and 00001101 in the pre-set table 1 to obtain the corresponding target switch domain information, which specifically includes the port Port0 of the first host, the uplink ports UP0 of switches 201 and 202, the devices 301 and 302 connected to the downlink ports DS0 and DS1 of switch 201, and the devices 305 and 306 connected to the downlink ports DS0 and DS1 of switch 202, with corresponding switch IDs of 0 and 1 respectively.

[0147] The device reset method provided in this application determines a target register address from at least one register address based on the port identifier of the first host; determines a target register value from the target register address; and determines the target switch domain information based on the target register value. This technical solution can quickly determine the register address based on the port identifier of the first host, extract the register value from the register address, and directly determine the uplink port of the switch to be reset, as well as the downlink device connected to the downlink port corresponding to the uplink port to be restarted.

[0148] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0149] Figure 6 is a schematic diagram of the device reset device provided in an embodiment of this application. As shown in Figure 6, the device includes:

[0150] The acquisition module 61 is used to acquire the restart signal of the first host, and the restart signal carries the port identifier of the first host;

[0151] The determination module 62 is used to determine the target switch domain information corresponding to the port identifier of the first host in the pre-set configuration information. The configuration information includes the port identifiers of different hosts and the switch domain information corresponding to each port identifier. Each switch domain information includes: the uplink port identifier of the switch corresponding to the port identifier of the host, the downlink port identifier of the switch corresponding to the uplink port identifier of the switch, and the device identifier corresponding to the downlink port identifier of the switch.

[0152] The sending module 63 is used to send a reset signal to the target switch and target device involved in the target switch domain information, so as to reset the uplink port of the target switch and the target device.

[0153] In one possible implementation, before determining the target switch domain information corresponding to the port identifier of the first host in the pre-set configuration information, the acquisition module 61 is further configured to acquire the uplink port identifier of each switch, the downlink port identifier corresponding to the uplink port identifier of each switch and the port identifier of the corresponding host, and the device identifier corresponding to each downlink port identifier.

[0154] The building module is used to build configuration information based on the uplink port identifier of each switch, the port identifier of the host corresponding to the uplink port identifier of each switch, the downlink port identifier corresponding to the uplink port identifier of each switch, and the device identifier corresponding to the downlink port identifier.

[0155] The storage module is used to store configuration information.

[0156] In one possible implementation, the storage module stores configuration information, specifically for:

[0157] For each port identifier in each host, a register value is generated based on the device identifier corresponding to the uplink port identifier and downlink port identifier of the switch corresponding to the port identifier.

[0158] Configure a register address for the port identifier in the electronic device and store the register value under the register address. The register value under the register address is used to represent the switch domain information.

[0159] In one possible implementation, the construction module generates a register value based on the device identifier corresponding to the uplink port identifier of the switch and the downlink port identifier of the switch, respectively. This value is specifically used for:

[0160] Based on the sequence number of the uplink port identifier of the switch corresponding to the port identifier among all uplink ports in the switch, determine the first N bits of the register value, where N is an integer greater than 0;

[0161] Based on the device identifier corresponding to the downlink port identifier of the switch and the corresponding uplink port identifier, determine the N+1 to M bits in the register value, where M is an integer greater than N+1.

[0162] In one possible implementation, the determining module 62 determines the target switch domain information corresponding to the port identifier of the first host from the pre-set configuration information, specifically for:

[0163] The target register address is determined from at least one register address based on the port identifier of the first host.

[0164] The target register value is determined from the target register address;

[0165] Based on the target register value, the target switch domain information is determined.

[0166] In one possible implementation, the information transmission method between the electronic device and the switch is an integrated circuit bus I. 2 C.

[0167] The device reset device provided in this application embodiment can be used to execute the determination method in any of the above embodiments. Its implementation principle and technical effect are similar, and will not be described again here.

[0168] It should be noted that the division of the various modules in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. Additionally, these modules can be fully or partially integrated together, or implemented independently. The processing element mentioned here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above modules can be completed through the integrated logic circuits in the hardware of the processor element or through software instructions.

[0169] Figure 7 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. As shown in Figure 7, the electronic device may include: a processor 71, a memory 72, and computer program instructions stored in the memory 72 and executable on the processor 71. When the processor 71 executes the computer program instructions, it implements the method provided in any of the foregoing embodiments.

[0170] Optionally, the various components of the electronic device can be connected via a system bus.

[0171] The memory 72 can be a separate memory unit or a memory unit integrated into the processor 71. The number of processors 71 can be one or more.

[0172] It should be understood that the processor 71 can be a Central Processing Unit (CPU), or other general-purpose processors 71, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor 71 can be a microprocessor 71, or any conventional processor 71. The steps of the method disclosed in this application can be directly manifested as being executed by the hardware processor 71, or being executed by a combination of hardware and software modules within the processor 71.

[0173] The system bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The system bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the figure, but this does not indicate that there is only one bus or one type of bus. Memory 72 may include Random Access Memory (RAM) 72, and may also include Non-Volatile Memory (NVM) 72, such as at least one disk storage device 72.

[0174] All or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a readable memory 72. When the program is executed, it performs the steps of the above method embodiments; and the aforementioned memory 72 (storage medium) includes: read-only memory 72 (ROM), RAM, flash memory 72, hard disk, solid-state hard disk, magnetic tape, floppy disk, optical disk, and any combination thereof.

[0175] The electronic device provided in this application embodiment can be used to execute the device reset method provided in any of the above method embodiments. Its implementation principle and technical effect are similar, and will not be described again here.

[0176] This application provides a device reset system, comprising: an electronic device, at least one host, at least one switch, and at least one device;

[0177] In response to a reset request, the first host in at least one host sends a reset signal to the electronic device, the reset signal carrying the port identifier of the first host;

[0178] An electronic device is used to execute the device reset method provided in any of the above method embodiments to reset the uplink port of the target switch in at least one switch and the target device in at least one device.

[0179] The device reset system provided in this application embodiment can be used to execute the device reset method provided in any of the above method embodiments. The implementation principle and technical effect are similar, and will not be described again here.

[0180] This application provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the computer to perform the device reset method of any of the above embodiments.

[0181] The aforementioned computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory, electrically erasable programmable read-only memory, erasable programmable read-only memory, programmable read-only memory, read-only memory, magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0182] Optionally, a readable storage medium can be coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Alternatively, the readable storage medium can be an integral part of the processor. Both the processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components within the device.

[0183] This application also provides a computer program product, which includes a computer program stored in a computer-readable storage medium. At least one processor can read the computer program from the computer-readable storage medium, and when the at least one processor executes the computer program, it can implement the device reset method of any of the above embodiments.

[0184] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A device reset method, comprising: The method is applied to an electronic device, and the method comprises: obtaining a restart signal of a first host, the restart signal carrying a port identifier of the first host; determining target switch domain information corresponding to the port identifier of the first host in preset configuration information, the configuration information comprising port identifiers of different hosts and switch domain information corresponding to each port identifier, each switch domain information comprising an uplink port identifier of a switch corresponding to the port identifier of the host, a downlink port identifier of the switch corresponding to the uplink port identifier of the switch, and a device identifier corresponding to the downlink port identifier of the switch; sending a reset signal to a target switch and a target device involved in the target switch domain information, so as to reset the uplink port of the target switch and the target device.

2. The method of claim 1, wherein, Before the step of determining the target switch domain information corresponding to the port identifier of the first host in the preset configuration information, the method further comprises: obtaining an uplink port identifier of each switch, a downlink port identifier corresponding to the uplink port identifier of each switch and a port identifier of a corresponding host, and a device identifier corresponding to each downlink port identifier; constructing the configuration information according to the uplink port identifier of each switch, the port identifier of the corresponding host corresponding to the uplink port identifier of each switch, the downlink port identifier corresponding to the uplink port identifier of each switch, and the device identifier corresponding to each downlink port identifier; storing the configuration information.

3. The method according to claim 1 or 2, characterized in that, The step of storing the configuration information comprises: generating a register value according to the uplink port identifier of the switch corresponding to the port identifier, and the device identifier corresponding to the downlink port identifier respectively, for each port identifier in each host; configuring a register address in the electronic device for the port identifier, and storing the register value under the register address, the register value under the register address being used to represent the switch domain information.

4. The method according to any one of claims 1 to 3, characterized in that, The step of generating a register value according to the uplink port identifier of the switch corresponding to the port identifier, and the device identifier corresponding to the downlink port identifier respectively comprises: determining the first N bits in the register value according to the sequence number of the uplink port identifier of the switch corresponding to the port identifier in all uplink ports of the switch, the N being an integer greater than 0; determining the N+1th to Mth bits in the register value according to the sequence number of the device identifier corresponding to the downlink port identifier corresponding to the uplink port identifier of the switch in all downlink ports of the switch, the M being an integer greater than N+1.

5. The method according to any one of claims 1-4, characterized in that, The step of determining the target switch domain information corresponding to the port identifier of the first host in the preset configuration information comprises: determining a target register address in at least one register address according to the port identifier of the first host; determining a target register value in the target register address; determining the target switch domain information based on the target register value.

6. The method according to any one of claims 1-5, characterized in that, The information transmission mode between the electronic device and the switch is an integrated circuit bus I2C.

7. An apparatus reset device, comprising: The device is applied to an electronic device, and the device comprises: An acquisition module is configured to acquire a restart signal of a first host, the restart signal carrying a port identifier of the first host; A determination module is configured to determine target switch domain information corresponding to the port identifier of the first host in preset configuration information, the configuration information including port identifiers of different hosts and switch domain information corresponding to each port identifier, each switch domain information including an uplink port identifier of a switch corresponding to the port identifier of the host, a downlink port identifier of the switch corresponding to the uplink port identifier of the switch, and a device identifier corresponding to the downlink port identifier of the switch; A sending module is configured to send a reset signal to target switches and target devices involved in the target switch domain information, so as to reset uplink ports of the target switches and the target devices.

8. A device reset system, comprising: The system includes an electronic device, at least one host, at least one switch, and at least one device. A first host in the at least one host sends a reset signal to the electronic device in response to a reset request, the reset signal carrying a port identifier of the first host. The electronic device is configured to perform the method in any one of claims 1-6, so as to reset uplink ports of a target switch in the at least one switch and a target device in the at least one device.

9. An electronic device, comprising: Comprise: A processor and a memory connected to the processor in communication; The memory stores computer execution instructions; The processor executes the computer execution instructions stored in the memory to implement the method in any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the processor to implement the method in any one of claims 1-6.

11. A computer program, characterized in that, The computer program product includes a computer program stored in a computer readable storage medium, at least one processor can read the computer program from the computer readable storage medium, and the at least one processor executes the computer program to implement the method in any one of claims 1-6.

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