Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises at least one memory cell located on a substrate, the memory cell comprising: an annular semiconductor layer (30), which extends in a direction perpendicular to the substrate (01); a first conductive layer (11), which is located inside the semiconductor layer (30); a reference node layer (14), which is connected to the semiconductor layer (30) and is configured to provide a reference voltage to the memory cell; a read word line (R_WL) and a write word line (W_WL), which both extend in a row direction parallel to the substrate (01) and at least partially surround an outer side wall of the semiconductor layer (30); and a bit line, which extends in a column direction parallel to the substrate (01) and at least partially surrounds the outer side wall of the semiconductor layer (30), wherein the reference node layer (14), the read word line (R_WL), the write word line (W_WL) and the bit line (BL) are spaced apart in the direction perpendicular to the substrate (01); a gate insulating layer (40) is provided between each of the read word line (R_WL), the write word line (W_WL) and the first conductive layer (11), and the semiconductor layer (30); each memory cell is connected to only one bit line (BL); and the extension direction of the reference node layer (14) is the same as or different from that of the bit line (BL).

Description

Semiconductor device, manufacturing method thereof, and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411081421.1, filed on August 7, 2024, and entitled "Semiconductor device, manufacturing method thereof, and electronic device", the content of which is hereby incorporated by reference into the present application. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and number of devices contained in a single chip are also increasing, so that small differences in process production can affect the performance of the devices.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of protection of the present application.

[0007] Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device. The semiconductor device has a simple structure, is easy to manufacture, and has a small footprint.

[0008] Embodiments of the present application provide a semiconductor device, the semiconductor device comprising at least one memory cell on a substrate, the memory cell comprising:

[0009] a semiconductor layer extending in a direction perpendicular to the substrate; the semiconductor layer is a hollow annular structure having an outer sidewall;

[0010] a first conductive layer located inside the annular structure of the semiconductor layer;

[0011] a reference node layer connected to the semiconductor layer and configured to provide a reference voltage to the memory cell;

[0012] a read word line extending in a row direction parallel to the substrate and at least partially surrounding the outer sidewall of the semiconductor layer;

[0013] a write word line extending in a row direction parallel to the substrate and at least partially surrounding the outer sidewall of the semiconductor layer;

[0014] a bit line extending along a column direction parallel to the substrate and at least partially surrounding an outer sidewall of the semiconductor layer;

[0015] The reference node layer, the read word line, the write word line and the bit line are spaced apart along a direction perpendicular to the substrate; the read word line and the semiconductor layer, the write word line and the semiconductor layer, the first conductive layer and the semiconductor layer have a gate insulating layer therebetween;

[0016] Each of the memory cells is connected to only one of the bit lines.

[0017] The reference node layer and the bit line extend in the same direction or different directions.

[0018] In some embodiments, the reference node layers of the plurality of memory cells are spaced apart or connected together.

[0019] In some embodiments, the reference node layer is located between the semiconductor layer and the substrate; or,

[0020] The reference node layer is located on an outer sidewall of the semiconductor layer and at least partially surrounds the outer sidewall of the semiconductor layer.

[0021] In some embodiments, the gate insulating layer between the write word line and the semiconductor layer and the gate insulating layer between the read word line and the semiconductor layer in the same memory cell are connected together.

[0022] In some embodiments, the gate insulating layers on the outer sidewalls of the semiconductor layers of two adjacent semiconductor layers are at least partially connected together.

[0023] In some embodiments, the gate insulating layer at least partially exposes the read word line.

[0024] In some embodiments, the gate insulating layer at least partially exposes the write word line.

[0025] In some embodiments, the memory cell further comprises:

[0026] a read transistor comprising a first gate electrode, a second gate electrode and a first semiconductor layer; the first gate electrode is connected to the read word line; one end of the first semiconductor layer is connected to the bit line and the other end is connected to the reference node layer;

[0027] a write transistor comprising a third gate electrode and a second semiconductor layer; one end of the second semiconductor layer is electrically connected to the second gate electrode and the other end is connected to the bit line; the third gate electrode is connected to the write word line;

[0028] The read transistor and the write transistor are stacked along a direction perpendicular to the substrate.

[0029] In some embodiments, the semiconductor layer comprises the first semiconductor layer and the second semiconductor layer which are sequentially distributed along a direction perpendicular to the substrate.

[0030] The first gate electrode is part of the read word line;

[0031] The second gate electrode is part of the first conductive layer;

[0032] The third gate electrode is part of the write word line.

[0033] In some embodiments, the write transistor further comprises a fourth gate electrode, and the fourth gate electrode is part of the first conductive layer;

[0034] The second gate electrode and the fourth gate electrode are distributed along a direction perpendicular to the substrate.

[0035] In some embodiments, the read transistor is located between the write transistor and the substrate;

[0036] The first semiconductor layer and the second semiconductor layer are sequentially distributed on the semiconductor layer along a direction away from the substrate;

[0037] The reference node layer, the read word line, the bit line and the write word line are sequentially and spacedly distributed along a direction away from the substrate.

[0038] In some embodiments, the write transistor is located between the read transistor and the substrate;

[0039] The first semiconductor layer and the second semiconductor layer are sequentially distributed on the semiconductor layer along a direction close to the substrate;

[0040] The write word line, the bit line, the read word line and the reference node layer are sequentially and spacedly distributed along a direction away from the substrate.

[0041] In some embodiments, the storage unit further comprises a storage node, and the second gate electrode and the fourth gate electrode are connected with the storage node respectively;

[0042] The storage node is part of the first conductive layer; or the semiconductor device further comprises a second conductive layer which is connected with the semiconductor layer and located between the semiconductor layer and the substrate, and the storage node is part of the second conductive layer.

[0043] The embodiments of the present application further provide a manufacturing method of a semiconductor device, the manufacturing method comprising:

[0044] forming reference node layers, bit lines, dummy read word lines and dummy write word lines on a substrate, the reference node layers, the bit lines, the dummy read word lines and the dummy write word lines being spaced and insulated in a direction perpendicular to the substrate;

[0045] forming first vias at least through the bit lines, the dummy read word lines and the dummy write word lines, the first vias exposing the reference node layers or penetrating the reference node layers;

[0046] sequentially depositing semiconductor layers, gate insulating layers and first conductive layers in the first vias, the semiconductor layers being connected with the reference node layers;

[0047] removing the dummy read word lines to form read word lines;

[0048] removing the dummy write word lines to form write word lines.

[0049] In some embodiments, the forming reference node layers, bit lines, dummy read word lines and dummy write word lines on a substrate, the reference node layers, the bit lines, the dummy read word lines and the dummy write word lines being spaced and insulated in a direction perpendicular to the substrate, comprises:

[0050] forming a plurality of spaced reference node layers on the substrate or forming a continuous reference node layer;

[0051] sequentially forming the dummy read word lines, the bit lines and the dummy write word lines on a side of the reference node layers away from the substrate, the dummy read word lines and the dummy write word lines extending in a row direction parallel to the substrate, the bit lines extending in a column direction parallel to the substrate; the reference node layers, the dummy read word lines, the bit lines and the dummy write word lines being insulated by insulating layers;

[0052] the forming first vias at least through the bit lines, the dummy read word lines and the dummy write word lines, the first vias exposing the reference node layers or penetrating the reference node layers, comprises:

[0053] etching the dummy write word lines, the bit lines and the dummy read word lines in a direction towards the substrate to form a plurality of first vias through the dummy write word lines, the bit lines and the dummy read word lines, the first vias exposing the reference node layers.

[0054] In some embodiments, the removing the dummy read word lines to form read word lines; and removing the dummy write word lines to form write word lines, comprises:

[0055] forming second vias through the dummy read word lines and the dummy write word lines between two first vias adjacent in the row direction;

[0056] etching the dummy read word line and the dummy write word line in the second via hole, so that the second via hole expands towards the semiconductor layer;

[0057] forming a gate insulating layer on the inner wall of the expanded second via hole, and filling a gate electrode layer in the second via hole;

[0058] disconnecting the gate electrode layer in the second via hole in a direction perpendicular to the substrate, to form a read word line and a write word line which are spaced apart in a direction perpendicular to the substrate.

[0059] In some embodiments, the disconnecting the gate electrode layer in the second via hole in a direction perpendicular to the substrate, to form a read word line and a write word line which are spaced apart in a direction perpendicular to the substrate, comprises:

[0060] etching the gate electrode layer in the second via hole in a direction towards the substrate, until the gate electrode layer in the region corresponding to the original dummy read word line is exposed;

[0061] filling an insulating layer in the second via hole;

[0062] etching the insulating layer in the second via hole, until the insulating layer in the region corresponding to the original dummy write word line is etched away;

[0063] filling a gate electrode layer in the second via hole;

[0064] etching the gate electrode layer in the second via hole in a direction towards the substrate, until the gate electrode layer in the region corresponding to the original dummy write word line is exposed;

[0065] filling an insulating layer in the second via hole;

[0066] the gate electrode layer in the region corresponding to the original dummy read word line forms the read word line, and the gate electrode layer in the region corresponding to the original dummy write word line forms the write word line.

[0067] In some embodiments, the manufacturing method further comprises:

[0068] forming a third conductive layer on the surface of the first via hole, the third conductive layer covering the end surface of the semiconductor layer and the end surface of the first conductive layer exposed by the first via hole.

[0069] In some embodiments, the forming a reference node layer, a bit line, a dummy read word line and a dummy write word line which are spaced apart and insulated in a direction perpendicular to the substrate on the substrate, comprises:

[0070] forming a second conductive layer on the substrate, and performing a patterned etching on the second conductive layer, the patterned second conductive layer comprising a plurality of conductive patterns spaced apart along a row direction and a column direction parallel to the substrate, the conductive patterns comprising storage nodes of the semiconductor devices;

[0071] forming the dummy write word line, the bit line and the dummy read word line on a side of the patterned second conductive layer away from the substrate in sequence, the dummy read word line and the dummy write word line both extending along the row direction parallel to the substrate, and the bit line extending along the column direction parallel to the substrate;

[0072] forming a plurality of reference node layers spaced apart or forming a continuous reference node layer on a side of the dummy read word line away from the substrate;

[0073] insulating the patterned second conductive layer, the dummy read word line, the bit line, the dummy write word line and the reference node layer by an insulating layer;

[0074] forming a first via at least through the bit line, the dummy read word line and the dummy write word line, the first via exposing the reference node layer or penetrating through the reference node layer, comprising:

[0075] performing an etching on the reference node layer, the dummy read word line, the bit line and the dummy write word line in a direction towards the substrate, forming a plurality of first vias through the reference node layer, the dummy read word line, the bit line and the dummy write word line, the first vias exposing the patterned second conductive layer.

[0076] In some embodiments, the removing the dummy read word line forms a read word line, and the removing the dummy write word line forms a write word line, comprising:

[0077] forming a second via through the dummy read word line and the dummy write word line between two adjacent first vias along the row direction;

[0078] performing an etching on the dummy read word line and the dummy write word line in the second via, so that the second via expands towards the semiconductor layer;

[0079] forming a gate insulating layer on an inner wall of the expanded second via, and filling a gate electrode layer in the second via;

[0080] disconnecting the gate electrode layer in the second via in a direction perpendicular to the substrate, forming a read word line and a write word line spaced apart in the direction perpendicular to the substrate.

[0081] In some embodiments, the breaking of the gate electrode layer in the second via in a direction perpendicular to the substrate to form the read word lines and the write word lines spaced apart in a direction perpendicular to the substrate comprises:

[0082] etching the gate electrode layer in the second via in a direction towards the substrate until the gate electrode layer in the region corresponding to the dummy read word line is exposed;

[0083] filling the second via with an insulating layer;

[0084] etching the insulating layer in the second via until the insulating layer in the region corresponding to the dummy read word line is etched away;

[0085] filling the second via with a gate electrode layer;

[0086] etching the gate electrode layer in the second via in a direction towards the substrate until the gate electrode layer in the region corresponding to the dummy read word line is exposed;

[0087] filling the second via with an insulating layer;

[0088] the gate electrode layer in the region corresponding to the dummy read word line forms the read word lines, and the gate electrode layer in the region corresponding to the dummy write word line forms the write word lines.

[0089] Embodiments of the present application also provide an electronic device comprising the semiconductor device described above, or comprising the semiconductor device obtained by the manufacturing method described above.

[0090] Other features and advantages of the present application will be set forth in the following description, and in part will be apparent from the description, or can be learned by practice of the present application. Other advantages of the present application will be realized and attained by the methods and solutions particularly pointed out in the written description and claims hereof.

[0091] SUMMARY

[0092] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, illustrate embodiments of the present application, and are used to explain the technical solutions of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0093] Fig. 1A is a schematic view of a cross section parallel to a substrate of a semiconductor device according to an exemplary embodiment of the present application;

[0094] Fig. 1B is a schematic view of a longitudinal cross section perpendicular to the substrate of the semiconductor device shown in Fig. 1A, taken along line AA in Fig. 2A;

[0095] FIG. 2A is a cross-sectional view parallel to the substrate of another semiconductor device according to an example embodiment of the present application;

[0096] FIG. 2B is a longitudinal cross-sectional view perpendicular to the substrate of the semiconductor device shown in FIG. 2A, taken along line AA in FIG. 2A;

[0097] FIG. 3A is a logic circuit diagram of a semiconductor device according to an example embodiment of the present application;

[0098] FIG. 3B is a logic circuit diagram of another semiconductor device according to an example embodiment of the present application;

[0099] FIG. 4 is a process flow diagram of a method of manufacturing a semiconductor device according to an example embodiment of the present application;

[0100] FIG. 5A is a cross-sectional view parallel to the substrate of a method of manufacturing a semiconductor device according to an example embodiment of the present application, after forming a reference node;

[0101] FIG. 5B is a longitudinal cross-sectional view perpendicular to the substrate of the device shown in FIG. 5A, taken along line AA;

[0102] FIG. 5C is a cross-sectional view parallel to the substrate of another method of manufacturing a semiconductor device according to an example embodiment of the present application, after forming a reference node;

[0103] FIG. 6A is a cross-sectional view parallel to the substrate of a method of manufacturing a semiconductor device according to an example embodiment of the present application, after forming a dummy word line;

[0104] FIG. 6B is a longitudinal cross-sectional view perpendicular to the substrate of the device shown in FIG. 6A, taken along line AA;

[0105] FIG. 7A is a cross-sectional view parallel to the substrate of a method of manufacturing a semiconductor device according to an example embodiment of the present application, after forming a first via;

[0106] FIG. 7B is a longitudinal cross-sectional view perpendicular to the substrate of the device shown in FIG. 7A, taken along line AA;

[0107] FIG. 8A is a cross-sectional view parallel to the substrate of a method of manufacturing a semiconductor device according to an example embodiment of the present application, after filling the first conductive layer in the first via;

[0108] FIG. 8B is a longitudinal cross-sectional view perpendicular to the substrate of the device shown in FIG. 8A, taken along line AA;

[0109] FIG. 9A is a cross-sectional view parallel to the substrate of a method of manufacturing a semiconductor device according to an example embodiment of the present application, after disconnecting the semiconductor layer, the gate insulating layer, and the first conductive layer between the first vias;

[0110] Fig. 9B is a longitudinal sectional view taken along the line AA of the device shown in Fig. 9A, perpendicular to the substrate;

[0111] Fig. 10A is a horizontal sectional view taken parallel to the substrate of a semiconductor device manufacturing method according to an exemplary embodiment of the present application, after forming a patterned third conductive layer;

[0112] Fig. 10B is a longitudinal sectional view taken along the line AA of the device shown in Fig. 10A, perpendicular to the substrate;

[0113] Fig. 11A is a horizontal sectional view taken parallel to the substrate of a semiconductor device manufacturing method according to an exemplary embodiment of the present application, after forming a second via;

[0114] Fig. 11B is a longitudinal sectional view taken along the line AA of the device shown in Fig. 11A, perpendicular to the substrate;

[0115] Fig. 12A is a horizontal sectional view taken parallel to the substrate of a semiconductor device manufacturing method according to an exemplary embodiment of the present application, after filling the second via with a gate electrode layer;

[0116] Fig. 12B is a longitudinal sectional view taken along the line AA of the device shown in Fig. 12A, perpendicular to the substrate;

[0117] Fig. 13A is a horizontal sectional view taken parallel to the substrate of another semiconductor device manufacturing method according to an exemplary embodiment of the present application, after forming a storage node;

[0118] Fig. 13B is a longitudinal sectional view taken along the line AA of the device shown in Fig. 13A, perpendicular to the substrate;

[0119] Fig. 14A is a horizontal sectional view taken parallel to the substrate of another semiconductor device manufacturing method according to an exemplary embodiment of the present application, after forming a reference node;

[0120] Fig. 14B is a longitudinal sectional view taken along the line AA of the device shown in Fig. 14A, perpendicular to the substrate;

[0121] Fig. 15A is a horizontal sectional view taken parallel to the substrate of another semiconductor device manufacturing method according to an exemplary embodiment of the present application, after forming a first via;

[0122] Fig. 15B is a longitudinal sectional view taken along the line AA of the device shown in Fig. 15A, perpendicular to the substrate;

[0123] Fig. 16A is a horizontal sectional view taken parallel to the substrate of another semiconductor device manufacturing method according to an exemplary embodiment of the present application, after filling the first via with a first conductive layer;

[0124] Fig. 16B is a longitudinal sectional view taken along the line AA of the device shown in Fig. 16A, perpendicular to the substrate;

[0125] Fig. 17A is a horizontal sectional view taken parallel to the substrate of another semiconductor device manufacturing method according to an exemplary embodiment of the present application, after forming a second via hole;

[0126] Fig. 17B is a longitudinal sectional view taken along the line AA of the device shown in Fig. 17A, perpendicular to the substrate;

[0127] Fig. 18A is a horizontal sectional view taken parallel to the substrate of another semiconductor device manufacturing method according to an exemplary embodiment of the present application, after filling the second via hole with a gate electrode layer;

[0128] Fig. 18B is a longitudinal sectional view taken along the line AA of the device shown in Fig. 18A, perpendicular to the substrate.

[0129] The meanings of the reference symbols in the drawings are as follows: 01 - substrate; 10 - insulating layer; 11 - first conductive layer; 12 - second conductive layer; 13 - third conductive layer; 14 - reference node layer; 15 - hard mask; 21 - dummy read word line; 22 - dummy write word line; 30 - semiconductor layer; 31 - first semiconductor layer; 32 - second semiconductor layer; 40 - gate insulating layer; 41 - gate electrode layer; 51 - first gate electrode; 52 - second gate electrode; 53 - third gate electrode; 54 - fourth gate electrode; Tr_r - read transistor; Tr_w - write transistor; R_WL - read word line; W_WL - write word line; BL - bit line; SN - storage node; RN - reference node; K1 - first via hole; K2 - second via hole.

[0130] DETAILED DESCRIPTION

[0131] For the purpose of making the object, technical scheme and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the drawings. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0132] For the purpose of making the object, technical scheme and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the drawings. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0133] The embodiments of the present application are not necessarily limited to the sizes shown in the drawings, and the shapes and sizes of the components in the drawings are preferred embodiments, and other shapes and sizes can also be used. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values shown in the drawings.

[0134] The size and ratio relationship between each film layer or component in the drawings of the present application can be used as a reference in the actual process, which is a good technical effect implementation, but is not limited thereto. For example, the width-length ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs.

[0135] The ordinal numbers "first", "second", etc. in the present application are set to avoid confusion of the constituent elements, and do not represent any order, number or importance.

[0136] In the present application, for the convenience, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the constituent elements with reference to the drawings, which is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. The positional relationship of the constituent elements is appropriately changed according to the direction of describing each constituent element. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0137] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific situation.

[0138] In the present application, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present application, the channel region refers to the region through which current mainly flows.

[0139] In the present application, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor or a circuit working with opposite polarity or changing the current direction, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in the present application, if not specifically described, "source electrode" and "drain electrode" can be exchanged with each other.

[0140] In the present application, "electrically connected" or "connected" includes a case where components are connected together through an element having some electrical action, such as an electrical signal connection (coupled to) or a physical direct connection. The element having some electrical action is not particularly limited as long as it can perform the transmission and reception of an electrical signal between the components to be connected. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0141] In the present application, "parallel" means approximately parallel or almost parallel, such as a state in which two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state in which two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0142] In the present application, "film" and "layer" can be interchanged. For example, "conductive layer" can be replaced with "conductive film" at times. Similarly, "insulating film" can be replaced with "insulating layer" at times.

[0143] The substrate in the present application embodiment can be a support structure such as a silicon substrate, or a support structure on which other film layers or functions or circuits have been distributed, and the device to which the inventive configuration of the present application embodiment relates is provided on a main surface of the support structure.

[0144] In recent years, more and more 2T structure DRAM memory cells have been developed. The currently common 2T 0C structure memory cell includes a write transistor and a read transistor; and the write transistor and the read transistor are respectively connected to different bit lines, in which the write transistor is connected to a write bit line and the read transistor is connected to a read bit line.

[0145] In addition, the threshold voltage (V th ) of the read transistor can change, such as a large change in the threshold voltage of the read transistor due to the production process and the use time of the transistor, which inevitably adversely affects the reading of data, resulting in an impact on the accuracy of data reading.

[0146] The present application embodiment provides a new memory cell circuit design, so that the semiconductor device of the present application embodiment can perform V th compensation function or not perform V th compensation function according to actual needs.

[0147] Fig. 1A is a schematic view of a semiconductor device according to an exemplary embodiment of the present application, in a cross section parallel to a substrate; Fig. 1B is a schematic view of the semiconductor device shown in Fig. 1A, in a longitudinal section perpendicular to the substrate, taken along the line AA in Fig. 2A; Fig. 2A is a schematic view of another semiconductor device according to an exemplary embodiment of the present application, in a cross section parallel to a substrate; Fig. 2B is a schematic view of the semiconductor device shown in Fig. 2A, in a longitudinal section perpendicular to the substrate, taken along the line AA in Fig. 2A; Fig. 3A is a schematic view of a logic circuit of a semiconductor device according to an exemplary embodiment of the present application; Fig. 3B is a schematic view of another logic circuit of a semiconductor device according to an exemplary embodiment of the present application.

[0148] As shown in Figs. 1A to 3B, the semiconductor device includes at least one memory cell on a substrate 01, the memory cell including: a semiconductor layer 30, a first conductive layer 11, a reference node layer 14, a read word line R_WL, a write word line W_WL, and a bit line BL;

[0149] The semiconductor layer 30 extends in a direction perpendicular to the substrate 01; the semiconductor layer 30 is a hollow ring structure having an outer sidewall;

[0150] The first conductive layer 11 is located inside the ring structure of the semiconductor layer 30;

[0151] The reference node layer 14 is connected to the semiconductor layer 30 and is configured to provide a reference voltage to the memory cell; the reference node layer 14 includes a reference node RN;

[0152] The read word line R_WL extends in a row direction parallel to the substrate 01 and at least partially surrounds the outer sidewall of the semiconductor layer 30;

[0153] The write word line extends in a row direction parallel to the substrate 01 and at least partially surrounds the outer sidewall of the semiconductor layer 30;

[0154] The bit line BL extends in a column direction parallel to the substrate 01 and at least partially surrounds the outer sidewall of the semiconductor layer 30;

[0155] The reference node layer 14, the read word line R_WL, the write word line W_WL, and the bit line BL are spaced apart in a direction perpendicular to the substrate 01; the read word line R_WL and the semiconductor layer 30, the write word line W_WL and the semiconductor layer 30, and the first conductive layer 11 and the semiconductor layer 30 have a gate insulating layer 40 therebetween;

[0156] Each of the memory cells is connected to only one bit line BL.

[0157] The reference node layer 14 and the bit line BL have the same or different extension directions.

[0158] The reference node layer of the semiconductor device of the embodiments of the present application has a different function from the bit line, and the function of the reference node layer is to provide a reference voltage to the memory cell, so that the memory cell is connected to only one bit line, thereby simplifying the device structure. Moreover, the extension direction of the reference node layer can be different from that of the bit line.

[0159] In some embodiments, as shown in FIG. 1B and FIG. 2B, the reference node layers 14 of the plurality of memory cells can be distributed at intervals. In other embodiments, the reference node layers 14 of the plurality of memory cells can be connected together, for example, the reference node layers 14 of a row of memory cells distributed along a row direction parallel to the substrate can be connected together, for another example, can be connected together in a manner of sharing one reference node layer 14 extending along the row direction. For another example, all the reference node layers 14 in the entire semiconductor device can be connected as one continuous film layer.

[0160] In some embodiments, as shown in FIG. 1B, the reference node layer 14 is located between the semiconductor layer 30 and the substrate 01.

[0161] In some embodiments, as shown in FIG. 2B, the reference node layer 14 is located on the outer sidewall of the semiconductor layer 30 and at least partially surrounds the outer sidewall of the semiconductor layer 30.

[0162] In some embodiments, as shown in FIG. 1B and FIG. 2B, the gate insulating layer 40 between the write word line W_WL and the semiconductor layer 30 and the gate insulating layer 40 between the read word line R_WL and the semiconductor layer 30 in the same memory cell are connected together.

[0163] In some embodiments, as shown in FIG. 1B and FIG. 2B, the gate insulating layers 40 on the outer sidewalls of the adjacent two semiconductor layers 30 are at least partially connected together.

[0164] In some embodiments, as shown in FIG. 1B and FIG. 2B, the gate insulating layer 40 is at least partially exposed to the read word line R_WL.

[0165] In some embodiments, as shown in FIG. 1B and FIG. 2B, the gate insulating layer 40 is at least partially exposed to the write word line W_WL.

[0166] In some embodiments, as shown in FIG. 1A to FIG. 3B, the memory cell can include a read transistor Tr_r and a write transistor Tr_w;

[0167] The read transistor Tr_r includes a first gate electrode 51, a second gate electrode 52 and a first semiconductor layer 31; the first gate electrode 51 is connected to the read word line R_WL; one end of the first semiconductor layer 31 is connected to the bit line BL, and the other end is connected to the reference node layer 14 (reference node RN);

[0168] The write transistor Tr_w includes a third gate electrode 53 and a second semiconductor layer 32; one end of the second semiconductor layer 32 is electrically connected with the second gate electrode 52, and the other end is connected with the bit line BL; the third gate electrode 53 is connected with the write word line W_WL;

[0169] The read transistor Tr_r and the write transistor Tr_w are stacked along a direction perpendicular to the substrate 01.

[0170] The semiconductor device of the embodiment of the present application stacks the read transistor and the write transistor (for example, stacks in a direction perpendicular to the substrate), which is beneficial to reduce the area of the memory cell of the semiconductor device and thus increase the storage density of the device.

[0171] The read transistor has independent double gates (the first gate electrode and the second gate electrode), one of which is used for data storage, and the other of which is used for controlling the operation of the unit.

[0172] Due to the above circuit connection relationship, the read transistor of the semiconductor device of the embodiment of the present application can form a diode connection under the control of the write transistor, and thus form compensation for the threshold voltage of the read transistor in the data writing stage, which can improve the accuracy of data reading.

[0173] For example, in the data writing stage, current is provided to the bit line BL, if the read transistor is not turned on, the current will all flow into the storage node SN, charge the storage node SN, and the voltage of the storage node SN will rise; after charging to a stable state, the voltage of the storage node SN will no longer increase, the turn-on characteristic of the read transistor will continuously increase until it is turned on, and the current will flow out through the read transistor, thereby realizing compensation for the threshold voltage of the read transistor.

[0174] In some embodiments, the memory cell can be a 2T0C structure, that is, including one read transistor Tr_r and one write transistor Tr_w.

[0175] In some embodiments, as shown in FIG. 1B and FIG. 2B, the semiconductor layer 30 includes a first semiconductor layer 31 and a second semiconductor layer 32 which are sequentially distributed in a direction perpendicular to the substrate 01.

[0176] In some embodiments, as shown in FIG. 1B and FIG. 2B, the gate insulating layer 40 on the outer sidewall of the first semiconductor layer 31 in the same memory cell is connected with the gate insulating layer 40 on the outer sidewall of the second semiconductor layer 32.

[0177] In some embodiments, as shown in FIG. 1B and FIG. 2B, the first gate electrode 51 is part of the read word line R_WL, and the second gate electrode 52 is part of the first conductive layer 11; the third gate electrode 53 is part of the write word line W_WL.

[0178] In some embodiments, as shown in FIG. IB and FIG. 2B, the write transistor Tr_w further comprises a fourth gate electrode 54, which is a part of the first conductive layer 11.

[0179] The second gate electrode 52 and the fourth gate electrode 54 are distributed on the first conductive layer 11 in a direction perpendicular to the substrate 01.

[0180] In some embodiments, as shown in FIG. IB and FIG. 2B, the read word line R_WL, the bit line BL and the write word line W_WL are sequentially distributed on different regions of the outer sidewall of the semiconductor layer 30 in a direction perpendicular to the substrate 01.

[0181] In some embodiments, as shown in FIG. IB, the read transistor Tr_r is located between the write transistor Tr_w and the substrate 01; the first semiconductor layer 31 and the second semiconductor layer 32 are sequentially distributed on the semiconductor layer in a direction away from the substrate 01.

[0182] The reference node layer 14, the read word line R_WL, the bit line BL and the write word line W_WL are sequentially and spacedly distributed in a direction away from the substrate 01.

[0183] In some embodiments, as shown in FIG. 2B, the write transistor Tr_w is located between the read transistor Tr_r and the substrate 01.

[0184] The first semiconductor layer 31 and the second semiconductor layer 32 are sequentially distributed on the semiconductor layer 30 in a direction close to the substrate 01.

[0185] The write word line W_WL, the bit line BL, the read word line R_WL and the reference node layer 14 are sequentially and spacedly distributed in a direction away from the substrate 01.

[0186] In some embodiments, as shown in FIG. 2B, the write word line W_WL, the bit line BL, the read word line R_WL and the reference node layer 14 are sequentially distributed on different regions of the outer sidewall of the semiconductor layer 30 in a direction perpendicular to the substrate 01.

[0187] In some embodiments, as shown in FIG. 1A to FIG. 3B, the storage unit further comprises a storage node SN, and the second gate electrode 52 and the fourth gate electrode 54 are connected with the storage node SN respectively.

[0188] In some embodiments, as shown in FIG. IB, the storage node SN is a part of the first conductive layer 11.

[0189] In some embodiments, as shown in FIG. 2B, the semiconductor device further comprises a second conductive layer 12, which is connected with the semiconductor layer 30 and located between the semiconductor layer 30 and the substrate 01, and the storage node SN is a part of the second conductive layer 12.

[0190] In the present application, the semiconductor layer can be understood as a semiconductor material, where the shape configuration is not emphasized, and only the function is emphasized.

[0191] Exemplarily, the material of the semiconductor layer can be silicon or polycrystalline silicon, etc. with a band gap less than 1.65 eV, or a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0192] For example, the material of the metal oxide semiconductor layer or channel can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide can also include compounds containing other elements, such as N, Si, etc.; and can also include other small amounts of doped elements.

[0193] In some embodiments, the material of the metal oxide semiconductor layer or channel can include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc., as long as the drain current of the transistor meets the requirements, which can be adjusted according to actual conditions.

[0194] These materials have a wide band gap and low drain current. For example, when the metal oxide material is IGZO, the drain current of the transistor is less than or equal to 10 -18 A. Thus, the working performance of the dynamic memory can be improved.

[0195] The above-mentioned material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0196] In some embodiments, the material of the bit line can be selected from any one or more of tungsten, molybdenum, cobalt, and other metal materials having similar properties. The bit line can be a single layer or a multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0197] In some embodiments, the electrode material of the gate electrode can be any one or more of the following different types of materials:

[0198] For example, containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; can be a metal alloy containing the aforementioned metals;

[0199] It can also be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, and other metal oxide materials with high conductivity; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials;

[0200] Of course, it can also be a polysilicon material; it can also be a conductive material doped with a semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; and other materials that exhibit conductivity.

[0201] In some embodiments, the material of the gate insulating layer can include one or more layers of Low-K and / or High-K dielectric materials, or two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0202] Low-K materials, such as silicon oxide.

[0203] High-K materials, such as dielectric materials with a dielectric constant K≥3.9. In some embodiments, it can include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it can include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0204] In some embodiments, the semiconductor device can be a 3D memory, such as a 3D DRAM memory. The 3D memory can be a 2T0C structure containing a read transistor and a write transistor.

[0205] The present application also provides a manufacturing method of a semiconductor device. FIG. 4 is a process flow diagram of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application.

[0206] As shown in FIG. 4, the manufacturing method comprises:

[0207] forming reference node layers, bit lines, dummy read word lines and dummy write word lines on a substrate, the reference node layers, the bit lines, the dummy read word lines and the dummy write word lines being spaced and insulated in a direction perpendicular to the substrate;

[0208] forming first vias at least through the bit lines, the dummy read word lines and the dummy write word lines, the first vias exposing the reference node layers or penetrating the reference node layers;

[0209] sequentially depositing semiconductor layers, gate insulating layers and first conductive layers in the first vias, the semiconductor layers being connected with the reference node layers;

[0210] removing the dummy read word lines to form read word lines;

[0211] removing the dummy write word lines to form write word lines.

[0212] In some embodiments, the forming reference node layers, bit lines, dummy read word lines and dummy write word lines on a substrate, the reference node layers, the bit lines, the dummy read word lines and the dummy write word lines being spaced and insulated in a direction perpendicular to the substrate, comprises:

[0213] forming a plurality of spaced reference node layers or forming a continuous reference node layer on the substrate;

[0214] sequentially forming the dummy read word lines, the bit lines and the dummy write word lines on a side of the reference node layers away from the substrate, the dummy read word lines and the dummy write word lines extending in a row direction parallel to the substrate, the bit lines extending in a column direction parallel to the substrate, and the reference node layers, the dummy read word lines, the bit lines and the dummy write word lines being insulated by insulating layers;

[0215] the forming first vias at least through the bit lines, the dummy read word lines and the dummy write word lines, the first vias exposing the reference node layers or penetrating the reference node layers, comprises:

[0216] etching the dummy write word lines, the bit lines and the dummy read word lines in a direction towards the substrate to form a plurality of first vias through the dummy write word lines, the bit lines and the dummy read word lines, the first vias exposing the reference node layers.

[0217] In some embodiments, the removing the dummy read word lines to form read word lines and the removing the dummy write word lines to form write word lines, comprises:

[0218] forming second vias through the dummy read word lines and the dummy write word lines between two first vias adjacent in the row direction;

[0219] etching the dummy read word line and the dummy write word line in the second via hole so that the second via hole expands toward the semiconductor layer;

[0220] forming a gate insulating layer on the inner wall of the expanded second via hole and filling a gate electrode layer in the second via hole;

[0221] disconnecting the gate electrode layer in the second via hole in a direction perpendicular to the substrate to form the read word line and the write word line which are spaced apart in a direction perpendicular to the substrate.

[0222] In some embodiments, the disconnecting the gate electrode layer in the second via hole in a direction perpendicular to the substrate to form the read word line and the write word line which are spaced apart in a direction perpendicular to the substrate comprises:

[0223] etching the gate electrode layer in the second via hole in a direction toward the substrate until the gate electrode layer in the region corresponding to the dummy read word line is exposed;

[0224] filling an insulating layer in the second via hole;

[0225] etching the insulating layer in the second via hole until the insulating layer in the region corresponding to the dummy write word line is etched away;

[0226] filling a gate electrode layer in the second via hole;

[0227] etching the gate electrode layer in the second via hole in a direction toward the substrate until the gate electrode layer in the region corresponding to the dummy write word line is exposed;

[0228] filling an insulating layer in the second via hole;

[0229] the gate electrode layer in the region corresponding to the dummy read word line forms the read word line and the gate electrode layer in the region corresponding to the dummy write word line forms the write word line.

[0230] In some embodiments, the manufacturing method further comprises:

[0231] forming a third conductive layer on the surface of the first via hole, the third conductive layer covering the end surface of the semiconductor layer and the end surface of the first conductive layer exposed by the first via hole.

[0232] In some embodiments, the forming the reference node layer, the bit line, the dummy read word line and the dummy write word line which are spaced apart and insulated in a direction perpendicular to the substrate on the substrate comprises:

[0233] forming a second conductive layer on the substrate, and performing a patterned etching on the second conductive layer, the patterned second conductive layer comprising a plurality of conductive patterns spaced apart along a row direction and a column direction parallel to the substrate, the conductive patterns comprising storage nodes of the semiconductor devices;

[0234] forming the dummy write word line, the bit line and the dummy read word line on a side of the patterned second conductive layer away from the substrate in sequence, the dummy read word line and the dummy write word line both extending along the row direction parallel to the substrate, and the bit line extending along the column direction parallel to the substrate;

[0235] forming a plurality of reference node layers spaced apart or forming a continuous reference node layer on a side of the dummy read word line away from the substrate;

[0236] insulating the patterned second conductive layer, the dummy read word line, the bit line, the dummy write word line and the reference node layer by an insulating layer;

[0237] forming a first via at least through the bit line, the dummy read word line and the dummy write word line, the first via exposing the reference node layer or penetrating through the reference node layer, comprising:

[0238] performing an etching on the reference node layer, the dummy read word line, the bit line and the dummy write word line along a direction towards the substrate, forming a plurality of first vias through the reference node layer, the dummy read word line, the bit line and the dummy write word line, the first vias exposing the patterned second conductive layer.

[0239] In some embodiments, the removing the dummy read word line forms a read word line, and the removing the dummy write word line forms a write word line, comprising:

[0240] forming a second via through the dummy read word line and the dummy write word line between two first vias adjacent along the row direction;

[0241] performing an etching on the dummy read word line and the dummy write word line in the second via, so that the second via expands towards the semiconductor layer;

[0242] forming a gate insulating layer on an inner wall of the expanded second via, and filling a gate electrode layer in the second via;

[0243] disconnecting the gate electrode layer in the second via in a direction perpendicular to the substrate, forming a read word line and a write word line spaced apart in the direction perpendicular to the substrate.

[0244] In some embodiments, the breaking of the gate electrode layer in the second via hole in a direction perpendicular to the substrate forms read word lines and write word lines that are spaced apart in a direction perpendicular to the substrate, including:

[0245] etching the gate electrode layer in the second via hole in a direction towards the substrate until the gate electrode layer in the region corresponding to the original dummy read word line is exposed;

[0246] filling the second via hole with an insulating layer;

[0247] etching the insulating layer in the second via hole until the insulating layer in the region corresponding to the original dummy read word line is etched away;

[0248] filling the second via hole with a gate electrode layer;

[0249] etching the gate electrode layer in the second via hole in a direction towards the substrate until the gate electrode layer in the region corresponding to the original dummy read word line is exposed;

[0250] filling the second via hole with an insulating layer;

[0251] the gate electrode layer in the region corresponding to the original dummy read word line forms the read word line, and the gate electrode layer in the region corresponding to the original dummy write word line forms the write word line.

[0252] The technical solutions of the embodiments of the present application are further described below through the manufacturing process of a semiconductor device in an exemplary embodiment. In the present embodiment, "patterned etching" includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, and stripping of photoresist, etc. In the present embodiment, "photolithography" process includes coating of a film layer, mask exposure, and development. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which are not specifically limited herein.

[0253] FIGS. 5A to 12B and FIGS. 1A to 1B are cross-sectional and longitudinal cross-sectional schematic views of intermediate steps of a manufacturing method of a semiconductor device and the final device produced according to an exemplary embodiment of the present application. As shown in FIGS. 1A, 1B, and 5A to 12B, in an exemplary embodiment, the manufacturing method of the memory can include the following processes.

[0254] S10: depositing an insulating layer 10 on a substrate, depositing an initial reference node layer on the insulating layer 10, and patterning the initial reference node layer, the patterned initial reference node layer including a plurality of reference node layers 14 that are spaced apart and arrayed in a row direction and a column direction parallel to the substrate; each reference node layer 14 including a reference node RN;

[0255] The insulating layer 10 is deposited on the patterned reference node layer 14 and is planarized until the reference node layers 14 are exposed, as shown in FIGS. 5A and 5B, where the cross section parallel to the substrate in FIG. 5A passes through the reference node layers 14.

[0256] In the description of the embodiments of the present application, the row direction and the column direction intersect each other, for example, can be perpendicular to each other. For example, the row direction can be the X direction as shown in FIG. 5A, and the column direction can be the Y direction as shown in FIG. 5A.

[0257] In other embodiments, the plurality of reference node layers 14 can be connected, for example, as shown in FIG. 5C, the plurality of reference node layers 14 can be connected as one reference node layer 14 extending along the row direction. Alternatively, the initial reference node layer is not patterned, and the plurality of memory cells of the entire semiconductor device share one continuous reference node layer 14.

[0258] In some embodiments, the material forming the insulating layer can be a low-K dielectric material, i.e., a dielectric material with a dielectric constant K < 3.9, including but not limited to oxides of silicon, such as silicon dioxide (SiO2) or other silicon-containing films, etc.

[0259] S20: sequentially forming a dummy read word line 21, a bit line BL, and a dummy write word line 22 on the surface of the reference node layer 14, as shown in FIGS. 6A and 6B, where the cross section parallel to the substrate in FIG. 6A passes through the dummy write word line.

[0260] For example, step S20 can include:

[0261] S21: depositing the insulating layer 10 on the surface of the reference node layer 14 and planarizing the same;

[0262] S22: depositing a dummy read word line layer on the surface of the substrate obtained in step S21, and patterning the dummy read word line layer, the patterned dummy read word line layer including a plurality of dummy read word lines 21 extending along the row direction and spaced apart in the column direction;

[0263] S23: depositing the insulating layer 10 on the surface of the patterned dummy read word line layer and planarizing the same;

[0264] S24: depositing a bit line layer on the surface of the structure obtained in step S23, and patterning the bit line layer, the patterned bit line layer including a plurality of bit lines BL, each bit line BL extending along the column direction, and the plurality of bit lines BL being spaced apart in the row direction;

[0265] S25: depositing the insulating layer 10 on the surface of the patterned bit line layer and planarizing the same;

[0266] S26: A dummy write word line layer is deposited on the structure surface obtained in step S25, and the dummy write word line layer is patterned, the patterned dummy write word line layer comprising a plurality of dummy write word lines 22 extending along the row direction and spaced apart in the column direction, as shown in FIGS. 6A and 6B.

[0267] S30: The dummy write word lines 22, the bit lines BL and the dummy read word lines 21 are etched along a direction towards the substrate, a plurality of first through holes K1 penetrating the dummy write word lines 22, the bit lines BL and the dummy read word lines 21 are formed, and one first through hole K1 penetrates one dummy read word line 21, one bit line BL and one dummy write word line 22, as shown in FIGS. 7A and 7B, wherein the cross section parallel to the substrate in FIG. 7A penetrates the bit line BL.

[0268] As shown in FIGS. 7A and 7B, the orthographic projection of each first through hole K1 on the substrate falls completely within the orthographic projection of the bit line BL penetrated by the first through hole K1 on the substrate, i.e. the sidewall of the first through hole K1 exposes the bit line BL.

[0269] Exemplarily, each first through hole K1 can extend into but not penetrate the reference node layer 14; the first through hole K1 can extend along a direction perpendicular to the substrate.

[0270] S40: A semiconductor layer 30 and a gate insulating layer 40 are sequentially deposited on the inner wall (including the sidewall and the bottom wall) of the first through hole K1, and the first conductive layer 11 fills the first through hole K1, as shown in FIGS. 8A and 8B, wherein the cross section parallel to the substrate in FIG. 8A penetrates the bit line BL.

[0271] Exemplarily, the semiconductor layer 30, the gate insulating layer 40 and the first conductive layer 11 can also cover the area between each first through hole K1.

[0272] S50: Each memory cell is isolated.

[0273] Exemplarily, step S50 can comprise:

[0274] S51: The semiconductor layer 30, the gate insulating layer 40 and the first conductive layer 11 located between each first through hole K1 are disconnected, and the semiconductor layer 30, the gate insulating layer 40, the first conductive layer 11 filled in the first through hole K1 and the area between each first through hole K1 are exposed, as shown in FIGS. 9A and 9B;

[0275] S52: depositing a third conductive layer 13 on the exposed regions between the first vias K1, and patterning and etching the third conductive layer 13, the patterned third conductive layer 13 surrounding the openings of the first vias K1 and connecting with the semiconductor layer 30 and the first conductive layer 11 in each first via K1, but the patterned third conductive layer 13 is disconnected between the first vias K1;

[0276] S53: depositing an insulating layer 10 on the substrate obtained in step S52 to cover the exposed regions between the first vias K1, as shown in FIG. 10A and FIG. 10B, wherein the cross section parallel to the substrate in FIG. 10A goes through the first conductive layer and the first via.

[0277] S60: removing the dummy read word line 21 and the dummy write word line 22.

[0278] Exemplarily, step S60 can include:

[0279] S61: etching the dummy read word line 21, the dummy write word line 22 and the insulating layer 10 between two first vias K1 adjacent in the row direction along a direction towards the substrate, forming a second via K2 going through the dummy read word line 21 and the dummy write word line 22, the second via K2 exposing the dummy read word line 21 and the dummy write word line 22;

[0280] S62: etching and removing the dummy read word line 21 and the dummy write word line 22 in the second via K2, for example, wet etching can be used to remove the dummy read word line 21 and the dummy write word line 22, so that the second via K2 expands towards the semiconductor layer 30, as shown in FIG. 11A and FIG. 11B, wherein the cross section parallel to the substrate in FIG. 11A goes through the third conductive layer and the first via.

[0281] S70: depositing a gate insulating layer 40 on the inner wall of the second via K2 obtained in step S62, and filling the gate electrode layer 41 in the second via K2, as shown in FIG. 12A and FIG. 12B, wherein the cross section parallel to the substrate in FIG. 12A goes through the third conductive layer and the first via.

[0282] S80: disconnecting the gate electrode layer 41 in the second via K2 in a direction perpendicular to the substrate, forming the read word line R_WL and the write word line W_WL which are spaced apart in the direction perpendicular to the substrate, as shown in FIG. 2A and FIG. 2B, wherein the cross section parallel to the substrate in FIG. 2A goes through the read word line.

[0283] Exemplarily, step S80 can include:

[0284] S81: etching the gate electrode layer 41 in the second via K2 along a direction towards the substrate until the gate electrode layer 41 in the region corresponding to the original dummy read word line 21 is exposed;

[0285] S82: filling the insulating layer 10 in the second via hole K2;

[0286] S83: etching the insulating layer 10 in the second via hole K2 until the insulating layer 10 in the region corresponding to the original dummy write word line 22 is etched off;

[0287] S84: filling the gate electrode layer 41 in the second via hole K2;

[0288] S85: etching the gate electrode layer 41 in the second via hole K2 in the direction towards the substrate until the gate electrode layer 41 in the region corresponding to the original dummy write word line 22 is exposed;

[0289] S86: filling the insulating layer 10 in the second via hole K2;

[0290] S87: the gate electrode layer 41 in the region corresponding to the original dummy read word line 21 forms the read word line R_WL, and the gate electrode layer 41 in the region corresponding to the original dummy write word line 22 forms the write word line W_WL;

[0291] S88: forming the hard mask 15 on the insulating layer 10 covering the first via hole K1, to obtain the semiconductor device as shown in FIG. 1A and FIG. 1B.

[0292] FIG. 13A to FIG. 18B and FIG. 2A to FIG. 2B are intermediate processes of another manufacturing method of a memory provided by the exemplary embodiments of the present application and structural schematic diagrams of the finally obtained device. As shown in FIG. 2A, FIG. 2B and FIG. 13A to FIG. 18B, in the exemplary embodiments, the manufacturing method of the memory can include the following processes.

[0293] S100: depositing the insulating layer 10 on the substrate, depositing the second conductive layer 12 on the insulating layer 10, and patterning the second conductive layer 12, the patterned second conductive layer 12 including a plurality of storage nodes SN, the plurality of storage nodes SN being spaced and arrayed in a row direction and a column direction parallel to the substrate;

[0294] depositing the insulating layer 10 on the patterned second conductive layer 12 and planarizing the insulating layer 10 until each storage node SN is exposed, as shown in FIG. 13A and FIG. 13B, wherein the cross section parallel to the substrate in FIG. 13A passes through the storage node SN.

[0295] S200: sequentially forming the dummy write word line 22, the bit line BL, the dummy read word line 21 and the reference node RN on the surface of the patterned second conductive layer 12, as shown in FIG. 14A and FIG. 14B, wherein the cross section parallel to the substrate in FIG. 14A passes through the bit line BL.

[0296] Exemplarily, the step S200 can include:

[0297] S201: depositing an insulating layer 10 on the surface of the patterned second conductive layer 12 and planarizing;

[0298] S202: depositing a dummy word line layer on the surface of the substrate obtained in step S201 and patterning the dummy word line layer, the patterned dummy word line layer comprising a plurality of dummy word lines 22 extending along the row direction and spaced apart in the column direction;

[0299] S203: depositing an insulating layer 10 on the surface of the patterned dummy word line layer and planarizing;

[0300] S204: depositing a bit line layer on the surface of the structure obtained in step S203 and patterning the bit line layer, the patterned bit line layer comprising a plurality of bit lines BL, each bit line BL extending along the column direction, and the plurality of bit lines BL being spaced apart in the row direction;

[0301] S205: depositing an insulating layer 10 on the surface of the patterned bit line layer and planarizing;

[0302] S206: depositing a dummy read word line layer on the surface of the structure obtained in step S205 and patterning the dummy read word line layer, the patterned dummy read word line layer comprising a plurality of dummy read word lines 21 extending along the row direction and spaced apart in the column direction;

[0303] S207: depositing an insulating layer 10 on the surface of the patterned dummy read word line layer and planarizing;

[0304] S208: depositing an initial reference node layer on the surface of the structure obtained in step S207 and patterning the initial reference node layer, the patterned initial reference node layer comprising a plurality of reference node layers 14, the plurality of reference node layers 14 being spaced apart and arrayed in the row direction and the column direction parallel to the substrate, and each reference node layer 14 comprising a reference node RN, as shown in FIGS. 14A and 14B.

[0305] S300: etching the dummy word lines 22, the bit lines BL, the dummy read word lines 21, and the reference node layers 14 in a direction toward the substrate, forming first through holes K1 penetrating the dummy word lines 22, the bit lines BL, the dummy read word lines 21, and the reference node layers 14, and causing one first through hole K1 to penetrate one dummy read word line 21, one bit line BL, one dummy word line 22, and one reference node layer 14, as shown in FIGS. 15A and 15B, wherein the cross section parallel to the substrate in FIG. 15A penetrates the bit line BL.

[0306] S400: sequentially depositing a semiconductor layer 30 and a gate insulating layer 40 on the inner wall of the first through hole K1 and filling the first conductive layer 11 in the first through hole K1.

[0307] Exemplarily, the step S400 can include:

[0308] S401: sequentially depositing the semiconductor layer 30 and the gate insulating layer 40 on the structure surface obtained in the step S300 to cover the inner walls (including the side walls and the bottom walls) of the first through holes K1 and the exposed regions between the first through holes K1;

[0309] S402: etching to remove the semiconductor layer 30 and the gate insulating layer 40 on the bottom walls of the first through holes K1, so as to expose the storage nodes SN;

[0310] S403: filling the first conductive layer 11 in the first through holes K1, wherein the first conductive layer 11 in each first through hole K1 is connected with the storage node SN;

[0311] S404: depositing the insulating layer 10 on the structure obtained in the step S403 to cover the first conductive layer 11 in the first through holes K1 and the exposed regions between the first through holes K1, as shown in FIG. 16A and FIG. 16B, wherein the cross section parallel to the substrate in FIG. 16A passes through the bit line BL.

[0312] S500: isolating the storage units.

[0313] Exemplarily, the step S500 can include:

[0314] S501: disconnecting the semiconductor layer 30, the gate insulating layer 40 and the first conductive layer 11 between the first through holes K1 to expose the semiconductor layer 30, the gate insulating layer 40, the first conductive layer 11 filled in the first through holes K1 and the regions between the first through holes K1;

[0315] S502: depositing the insulating layer 10 on the substrate obtained in the step S501 to cover the exposed regions between the first through holes K1.

[0316] S600: removing the dummy read word line 21 and the dummy write word line 22.

[0317] Exemplarily, the step S600 can include:

[0318] S601: etching the dummy read word line 21, the dummy write word line 22 and the insulating layer 10 between two first through holes K1 adjacent in the row direction in a direction towards the substrate to form a second through hole K2 passing through the dummy read word line 21 and the dummy write word line 22, wherein the second through hole K2 exposes the dummy read word line 21 and the dummy write word line 22;

[0319] S602: etching and removing the dummy read word line 21 and the dummy write word line 22 in the second via hole K2, for example, wet etching can be used to remove the dummy read word line 21 and the dummy write word line 22, so that the second via hole K2 expands towards the semiconductor layer 30, as shown in FIG. 17A and FIG. 17B, wherein the cross section in FIG. 17A is parallel to the substrate and passes through the first via hole.

[0320] S700: depositing the gate insulating layer 40 on the inner wall of the second via hole K2 obtained in step S602, and filling the gate electrode layer 41 in the second via hole K2, as shown in FIG. 18A and FIG. 18B, wherein the cross section in FIG. 18A is parallel to the substrate and passes through the first via hole.

[0321] S800: disconnecting the gate electrode layer 41 in the second via hole K2 in a direction perpendicular to the substrate, to form the read word line R_WL and the write word line W_WL which are spaced apart in the direction perpendicular to the substrate, as shown in FIG. 2A and FIG. 2B, wherein the cross section in FIG. 2A is parallel to the substrate and passes through the read word line.

[0322] Exemplarily, step S800 can include:

[0323] S801: etching the gate electrode layer 41 in the second via hole K2 in a direction towards the substrate, until the gate electrode layer 41 in the region corresponding to the original dummy write word line 22 is exposed;

[0324] S802: filling the insulating layer 10 in the second via hole K2;

[0325] S803: etching the insulating layer 10 in the second via hole K2, until the insulating layer 10 in the region corresponding to the original dummy read word line 21 is etched away;

[0326] S804: filling the gate electrode layer 41 in the second via hole K2;

[0327] S805: etching the gate electrode layer 41 in the second via hole K2 in a direction towards the substrate, until the gate electrode layer 41 in the region corresponding to the original dummy read word line 21 is exposed;

[0328] S806: filling the insulating layer 10 in the second via hole K2;

[0329] S807: the gate electrode layer 41 in the region corresponding to the original dummy read word line 21 forms the read word line R_WL, and the gate electrode layer 41 in the region corresponding to the original dummy write word line 22 forms the write word line W_WL;

[0330] S808: forming the hard mask 15 on the insulating layer 10 covering the first via hole K1, to obtain the semiconductor device as shown in FIG. 2A and FIG. 2B.

[0331] The application also provides an electronic device comprising the semiconductor device or obtained by the manufacturing method.

[0332] In some embodiments of the application, the electronic device can be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0333] Although the embodiments of the application are disclosed as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the application, and is not intended to limit the application. Any person skilled in the art of the application can make any modification and change in the form and details without departing from the spirit and scope of the application disclosed. The protection scope of the application shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising at least one memory cell on a substrate, the memory cell comprising: a semiconductor layer extending in a direction perpendicular to the substrate; the semiconductor layer being a hollow ring structure having an outer sidewall; a first conductive layer inside the ring structure of the semiconductor layer; a reference node layer connected to the semiconductor layer and configured to provide a reference voltage to the memory cell; a read word line extending in a row direction parallel to the substrate and at least partially surrounding the outer sidewall of the semiconductor layer; a write word line extending in the row direction parallel to the substrate and at least partially surrounding the outer sidewall of the semiconductor layer; and a bit line extending in a column direction parallel to the substrate and at least partially surrounding the outer sidewall of the semiconductor layer; the reference node layer, the read word line, the write word line and the bit line being spaced apart in a direction perpendicular to the substrate; and gate insulating layers being provided between the read word line and the semiconductor layer, between the write word line and the semiconductor layer, and between the first conductive layer and the semiconductor layer; wherein each memory cell is connected to only one bit line; and wherein the reference node layer has the same or different extension direction as the bit line. 2.The semiconductor device of claim 1, wherein the reference node layers of a plurality of memory cells are spaced apart or connected together. 3.The semiconductor device of claim 1, wherein the reference node layer is located between the semiconductor layer and the substrate; or wherein the reference node layer is located on the outer sidewall of the semiconductor layer and at least partially surrounds the outer sidewall of the semiconductor layer. 4.The semiconductor device of claim 1, wherein the gate insulating layer between the write word line and the semiconductor layer and the gate insulating layer between the read word line and the semiconductor layer in the same memory cell are connected together. 5.The semiconductor device of claim 1, wherein the gate insulating layers on the outer sidewalls of adjacent semiconductor layers are at least partially connected together. 6.The semiconductor device of claim 1, wherein the gate insulating layer at least partially exposes either or both of the read word line and the write word line. 7.The semiconductor device of any one of claims 1 to 6, further comprising: a read transistor comprising a first gate electrode, a second gate electrode and a first semiconductor layer; the first gate electrode being connected to the read word line; one end of the first semiconductor layer being connected to the bit line and the other end being connected to the reference node layer; and a write transistor comprising a third gate electrode and a second semiconductor layer; one end of the second semiconductor layer being connected to the second gate electrode and the other end being connected to the bit line; and the third gate electrode being connected to the write word line; wherein the read transistor and the write transistor are stacked in a direction perpendicular to the substrate. 8.The semiconductor device of claim 7, wherein the semiconductor layer comprises the first semiconductor layer and the second semiconductor layer being sequentially arranged in a direction perpendicular to the substrate; the first gate electrode is part of the read word line; and the second gate electrode is part of the first conductive layer. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The third gate electrode is part of the write word line.

9. The semiconductor device of claim 8, the write transistor further comprising a fourth gate electrode, the fourth gate electrode being part of the first conductive layer; The second gate electrode and the fourth gate electrode are distributed along a direction perpendicular to the substrate.

10. The semiconductor device of claim 7, the read transistor being located between the write transistor and the substrate; The first semiconductor layer and the second semiconductor layer are sequentially distributed on the semiconductor layer along a direction away from the substrate; The reference node layer, the read word line, the bit line and the write word line are sequentially and spacedly distributed along a direction away from the substrate.

11. The semiconductor device of claim 7, the write transistor being located between the read transistor and the substrate; The first semiconductor layer and the second semiconductor layer are sequentially distributed on the semiconductor layer along a direction close to the substrate; The write word line, the bit line, the read word line and the reference node layer are sequentially and spacedly distributed along a direction away from the substrate.

12. The semiconductor device of claim 9, the memory cell further comprising a memory node, the second gate electrode and the fourth gate electrode being connected to the memory node respectively; wherein The memory node is part of the first conductive layer; or, the semiconductor device further comprises a second conductive layer, the second conductive layer being connected to the semiconductor layer and located between the semiconductor layer and the substrate, the memory node being part of the second conductive layer.

13. A method for manufacturing a semiconductor device, comprising: forming, on a substrate, a reference node layer, a bit line, a dummy read word line and a dummy write word line which are spaced and insulatively distributed along a direction perpendicular to the substrate; forming a first via hole which at least penetrates the bit line, the dummy read word line and the dummy write word line, the first via hole exposing the reference node layer or penetrating the reference node layer; sequentially depositing, in the first via hole, a semiconductor layer, a gate insulating layer and a first conductive layer, the semiconductor layer being connected to the reference node layer; removing the dummy read word line to form a read word line; removing the dummy write word line to form a write word line.

14. The method of claim 13, the forming, on a substrate, a reference node layer, a bit line, a dummy read word line and a dummy write word line which are spaced and insulatively distributed along a direction perpendicular to the substrate, comprising: forming a plurality of reference node layers which are spaced or forming a continuous reference node layer on the substrate; sequentially forming, on a side of the reference node layer away from the substrate, the dummy read word line, the bit line and the dummy write word line, the dummy read word line and the dummy write word line both extending along a row direction parallel to the substrate, the bit line extending along a column direction parallel to the substrate; insulating between the reference node layer, the dummy read word line, the bit line and the dummy write word line by an insulating layer. The first via hole is formed through at least the bit line, the dummy read word line and the dummy write word line, and exposes the reference node layer or penetrates through the reference node layer, comprising: The dummy write word line, the bit line and the dummy read word line are etched along the direction towards the substrate to form a plurality of first via holes penetrating through the dummy write word line, the bit line and the dummy read word line, and the first via holes expose the reference node layer.

15. The manufacturing method of claim 14, the removing the dummy read word line forms a read word line. The dummy write word line is removed to form a write word line, comprising: A second via hole is formed through the dummy read word line and the dummy write word line between two adjacent first via holes along the row direction; The dummy read word line and the dummy write word line are etched and removed in the second via hole, so that the second via hole expands towards the semiconductor layer; A gate insulating layer is formed on the inner wall of the expanded second via hole, and a gate electrode layer is filled in the second via hole; The gate electrode layer in the second via hole is disconnected in the direction perpendicular to the substrate to form read word lines and write word lines which are spaced apart in the direction perpendicular to the substrate.

16. The manufacturing method of claim 15, wherein the gate electrode layer in the second via hole is disconnected in the direction perpendicular to the substrate to form read word lines and write word lines which are spaced apart in the direction perpendicular to the substrate, comprising: The gate electrode layer in the second via hole is etched along the direction towards the substrate until the gate electrode layer in the region corresponding to the original dummy read word line is exposed; An insulating layer is filled in the second via hole; The insulating layer in the second via hole is etched until the insulating layer in the region corresponding to the original dummy write word line is etched away; A gate electrode layer is filled in the second via hole; The gate electrode layer in the second via hole is etched along the direction towards the substrate until the gate electrode layer in the region corresponding to the original dummy write word line is exposed; An insulating layer is filled in the second via hole; The gate electrode layer in the region corresponding to the original dummy read word line forms the read word line, and the gate electrode layer in the region corresponding to the original dummy write word line forms the write word line.

17. The manufacturing method of any one of claims 14 to 16, further comprising: A third conductive layer is formed on the surface of the first via hole, and the third conductive layer covers the end surface of the semiconductor layer exposed by the first via hole and the end surface of the first conductive layer.

18. The manufacturing method of claim 13, wherein the reference node layer, the bit line, the dummy read word line and the dummy write word line are formed on the substrate and spaced apart and insulated in the direction perpendicular to the substrate, comprising: A second conductive layer is formed on the substrate, and the second conductive layer is patterned and etched, and the patterned second conductive layer comprises a plurality of conductive patterns which are spaced apart and distributed along the row direction and the column direction parallel to the substrate; the conductive patterns comprise the storage node of the semiconductor device. forming, on a side of the patterned second conductive layer away from the substrate, the dummy write word line, the bit line, and the dummy read word line in sequence, the dummy read word line and the dummy write word line both extending along a row direction parallel to the substrate, and the bit line extending along a column direction parallel to the substrate; forming, on a side of the dummy read word line away from the substrate, a plurality of reference node layers spaced apart or forming a continuous reference node layer; insulating the patterned second conductive layer, the dummy read word line, the bit line, the dummy write word line, and the reference node layer by an insulating layer; the forming of the first via at least through the bit line, the dummy read word line, and the dummy write word line, the first via exposing the reference node layer or penetrating through the reference node layer, comprises: etching the reference node layer, the dummy read word line, the bit line, and the dummy write word line in a direction towards the substrate to form a plurality of first vias penetrating through the reference node layer, the dummy read word line, the bit line, and the dummy write word line, the first vias exposing the patterned second conductive layer. removing the dummy write word line to form a write word line, comprises:

19. The manufacturing method of claim 18, the removing the dummy read word line forms a read word line. forming, between two first vias adjacent in the row direction, a second via penetrating through the dummy read word line and the dummy write word line; etching and removing the dummy read word line and the dummy write word line in the second via so that the second via expands towards the semiconductor layer; forming a gate insulating layer on an inner wall of the expanded second via and filling a gate electrode layer in the second via; disconnecting the gate electrode layer in the second via in a direction perpendicular to the substrate to form a read word line and a write word line spaced apart in a direction perpendicular to the substrate.

20. The manufacturing method of claim 19, wherein the disconnecting of the gate electrode layer in the second via in a direction perpendicular to the substrate to form a read word line and a write word line spaced apart in a direction perpendicular to the substrate, comprises: etching the gate electrode layer in the second via in a direction towards the substrate until exposing the gate electrode layer in a region corresponding to the original dummy write word line; filling an insulating layer in the second via; etching the insulating layer in the second via until etching away the insulating layer in a region corresponding to the original dummy read word line; filling a gate electrode layer in the second via; etching the gate electrode layer in the second via in a direction towards the substrate until exposing the gate electrode layer in a region corresponding to the original dummy read word line; filling an insulating layer in the second via; the gate electrode layer in a region corresponding to the original dummy read word line forms the read word line, and the gate electrode layer in a region corresponding to the original dummy write word line forms the write word line.

21. An electronic device comprising the semiconductor device of any one of claims 1 to 12, or comprising the semiconductor device obtained by the manufacturing method of any one of claims 13 to 20. ​

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