Planar JFET with buried gate

Abstract

A field-effect transistor with a buried gate, and a method of making the same. A volume of semiconductor material includes first and second ends and left and right sides. A source is located at the first end, a drain is provided, a left first gate structure is located at the left side, and a right first gate structure is located at the right side. A second, buried gate is located between and spaced apart from the source and the drain and the left and right first gate structures so as to be surrounded in first and second dimensions by the semiconductor material. The second gate divides a channel into multiple paths for current to flow between the source and the drain. The second gate includes a projection extending in a third dimension and presenting an exposed surface operable to receive a voltage.

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