Pixel driving circuit, display panel, and light-emitting control method

Abstract

The present disclosure relates to the technical field of display, and disclosed are a pixel driving circuit, a display panel, and a light-emitting control method. The pixel driving circuit comprises: a driving transistor, a first capacitor, a light-emitting device, a first switching transistor, a second switching transistor, a data writing sub-circuit, and a first light-emitting control sub-circuit. A control end of the first switching transistor and a control end of the second switching transistor are coupled to an initialization control end; the light-emitting device has an anode coupled to a first power end and a cathode coupled to a first end of the driving transistor; the data writing sub-circuit is coupled to a first end of the first capacitor; and the first light-emitting control sub-circuit is coupled to a second end of the driving transistor. The coupling of the control end of the first switching transistor and the control end of the second switching transistor to the initialization control end optimizes the layout and wiring, thereby facilitating the formation of narrow bezels.

Description

A pixel driving circuit, a display panel, and a light emission control method Technical Field

[0001] This disclosure relates to the field of display technology, and provides a pixel driving circuit, a display panel, and a light emission control method. Background Technology

[0002] Currently, the demand for narrow bezels in the display industry is increasing. However, each switching transistor in the existing pixel driving circuit needs to be connected to different control terminal signal lines to control the on and off of the relevant switching transistors. Considering that there are many switching transistors in the pixel driving circuit, there are also many control terminal signal lines that need to be connected, which makes the layout and wiring of the display panel more complicated and is not conducive to the formation of narrow bezels.

[0003] Summary of the Invention

[0004] This disclosure provides a pixel driving circuit, a display panel, and a light emission control method.

[0005] The specific technical solution provided in this disclosure is as follows:

[0006] In a first aspect, embodiments of this disclosure provide a pixel driving circuit, including: a driving transistor, a first capacitor, a light-emitting device, a first switching transistor, a second switching transistor, a data writing sub-circuit, and a first light-emitting control sub-circuit, wherein the control terminal of the first switching transistor and the control terminal of the second switching transistor are coupled to an initialization control terminal, the anode of the light-emitting device is coupled to a first power supply terminal, and the cathode of the light-emitting device is coupled to a first terminal of the driving transistor.

[0007] The first terminal of the first switching transistor is coupled to the first terminal of the first capacitor, and the second terminal of the first switching transistor is coupled to the third power supply terminal.

[0008] The first terminal of the second switching transistor is coupled to the first setting terminal, and the second terminal of the second switching transistor is coupled to the third power supply terminal. The first setting terminal is either the first or second terminal of the driving transistor, and the second terminal of the first capacitor is coupled to the control terminal of the driving transistor.

[0009] The data writing sub-circuit is coupled to the first terminal of the first capacitor. The data writing sub-circuit is configured to provide the data voltage of the data signal terminal to the first terminal of the first capacitor in response to the signal of the scan signal terminal.

[0010] The first light-emitting control sub-circuit is coupled to the second terminal of the driving transistor and is configured to turn on the second terminal and the second power supply terminal of the driving transistor in response to a signal from the light-emitting control signal terminal.

[0011] In some possible implementations provided in this disclosure, a compensation sub-circuit is also included, which is coupled to the control terminal of the driving transistor;

[0012] The compensation sub-circuit is configured to connect the control terminal of the driving transistor to the second setting terminal in response to the signal of the compensation control terminal, wherein the second setting terminal is either the first terminal or the second terminal of the driving transistor.

[0013] In some possible implementations provided in this disclosure, the first setting terminal and the second setting terminal are the same signal terminal.

[0014] In some possible implementations provided in this disclosure, the compensation sub-circuit includes: a third switching transistor;

[0015] The control terminal of the third switching transistor is coupled to the compensation control terminal, the first terminal of the third switching transistor is coupled to the control terminal of the driving transistor, and the second terminal of the third switching transistor is coupled to the second setting terminal.

[0016] In some possible implementations provided in this disclosure, the compensation control terminal and the initialization control terminal are the same signal terminal.

[0017] In some possible implementations provided in this disclosure, the data writing sub-circuit includes: a fourth switching transistor;

[0018] The control terminal of the fourth switching transistor is coupled to the scan signal terminal, the first terminal of the fourth switching transistor is coupled to the first terminal of the first capacitor, and the second terminal of the fourth switching transistor is coupled to the data signal terminal.

[0019] In some possible implementations provided in this disclosure, the first light-emitting control sub-circuit includes: a fifth switching transistor;

[0020] The control terminal of the fifth switching transistor is coupled to the light-emitting control signal terminal, the first terminal of the fifth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the fifth switching transistor is coupled to the second power supply terminal.

[0021] In some possible implementations provided in this disclosure, a second light-emitting control sub-circuit is also included, wherein the second light-emitting control sub-circuit is coupled to the cathode of the light-emitting device and the first terminal of the driving transistor;

[0022] The second light-emitting control sub-circuit is configured to conduct the cathode of the light-emitting device to the first terminal of the driving transistor in response to the signal at the light-emitting control signal terminal.

[0023] In some possible implementations provided in this disclosure, the second light-emitting control sub-circuit includes: a sixth switching transistor;

[0024] The control terminal of the sixth switching transistor is coupled to the light-emitting control signal terminal, the first terminal of the sixth switching transistor is coupled to the cathode of the light-emitting device, and the second terminal of the sixth switching transistor is coupled to the first terminal of the driving transistor.

[0025] In some possible implementations provided in this disclosure, a third light-emitting control sub-circuit is also included, wherein the third light-emitting control sub-circuit is coupled to the first power supply terminal and the anode of the light-emitting device;

[0026] The third light-emitting control sub-circuit is configured to connect the first power supply terminal to the anode of the light-emitting device in response to a signal from the light-emitting control signal terminal.

[0027] In some possible implementations provided in this disclosure, the third light-emitting control sub-circuit includes: a seventh switching transistor;

[0028] The control terminal of the seventh switching transistor is coupled to the light-emitting control signal terminal, the first terminal of the seventh switching transistor is coupled to the first power supply terminal, and the second terminal of the seventh switching transistor is coupled to the anode of the light-emitting device.

[0029] In some possible implementations provided in this disclosure, a first reset sub-circuit is also included, wherein the first reset sub-circuit is coupled to the control terminal of the driving transistor;

[0030] The first reset sub-circuit is configured to provide a signal from the first reset signal terminal to the control terminal of the driving transistor in response to a signal from the first reset control terminal.

[0031] In some possible implementations provided in this disclosure, the first reset circuit includes: an eighth switching transistor;

[0032] The control terminal of the eighth switching transistor is coupled to the first reset control terminal, the first terminal of the eighth switching transistor is coupled to the first reset signal terminal, and the second terminal of the eighth switching transistor is coupled to the control terminal of the driving transistor.

[0033] In some possible implementations provided in this disclosure, the first reset signal terminal is a first power supply terminal, the cathode of a light-emitting device, or the first terminal of a first capacitor.

[0034] In some possible implementations provided in this disclosure, a second reset circuit is also included, wherein the second reset circuit is coupled to the cathode of the light-emitting device;

[0035] The second reset sub-circuit is configured to provide a signal from the second reset signal terminal to the cathode of the light-emitting device in response to a signal from the second reset control terminal.

[0036] In some possible implementations provided in this disclosure, the second reset circuit includes: a ninth switching transistor;

[0037] The control terminal of the ninth switching transistor is coupled to the second reset control terminal, the first terminal of the ninth switching transistor is coupled to the second reset signal terminal, and the second terminal of the ninth switching transistor is coupled to the cathode of the light-emitting device.

[0038] In some possible implementations provided in this disclosure, the third power supply terminal and the first power supply terminal are the same signal terminal.

[0039] In some possible implementations provided in this disclosure, a second capacitor and a third capacitor are also included;

[0040] The first terminal of the second capacitor is coupled to the first power supply terminal, and the second terminal of the second capacitor is coupled to the first terminal of the first capacitor.

[0041] The first terminal of the third capacitor is coupled to the first power supply terminal, and the second terminal of the third capacitor is coupled to the second terminal of the first capacitor.

[0042] Secondly, embodiments of this disclosure also provide a display panel including the pixel driving circuit of any of the above.

[0043] Thirdly, embodiments of this disclosure also provide a light emission control method applied to a pixel driving circuit according to any one of the above claims, comprising:

[0044] Initialization phase: In response to the signal from the initialization control terminal, the first switching transistor provides the signal from the third power supply terminal to the first terminal of the first capacitor; in response to the signal from the initialization control terminal, the second switching transistor provides the signal from the third power supply terminal to the first setting terminal; and in response to the signal from the first reset control terminal, the first reset sub-circuit provides the signal from the first reset signal terminal to the control terminal of the driving transistor.

[0045] Threshold voltage compensation stage: In response to the signal from the compensation control terminal, the compensation sub-circuit turns on the control terminal of the driving transistor and the second setting terminal, and writes the threshold voltage of the driving transistor to the control terminal of the driving transistor.

[0046] Data writing stage: In response to the signal at the scan signal terminal, the data writing sub-circuit provides the data voltage at the data signal terminal to the first terminal of the first capacitor;

[0047] Light emission stage: In response to the signal at the light emission control signal terminal, the third light emission control sub-circuit connects the first power supply terminal to the anode of the light emission device, the second light emission control sub-circuit connects the cathode of the light emission device to the first terminal of the driving transistor, and the first light emission control sub-circuit connects the second terminal of the driving transistor to the second power supply terminal.

[0048] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0049] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0050] Figure 1 is a schematic diagram of the pixel driving circuit in the related technology;

[0051] Figure 2 is a connection diagram of the first pixel driving circuit in an embodiment of this disclosure;

[0052] Figure 3 is a circuit connection diagram of the first pixel driving circuit in the embodiment of this disclosure;

[0053] Figure 4 is a connection diagram of the second pixel driving circuit in an embodiment of this disclosure;

[0054] Figure 5 is a first circuit connection diagram of the second pixel driving circuit in an embodiment of this disclosure;

[0055] Figure 6 is a second circuit connection diagram of the second pixel driving circuit in an embodiment of this disclosure;

[0056] Figure 7 is a third circuit connection diagram of the second pixel driving circuit in the embodiments of this disclosure;

[0057] Figure 8 is a connection diagram of the third pixel driving circuit in the embodiment of this disclosure;

[0058] Figure 9 is a circuit connection diagram of the third pixel driving circuit in the embodiments of this disclosure;

[0059] Figure 10 is a connection diagram of the fourth pixel driving circuit in the embodiment of this disclosure;

[0060] Figure 11 is a circuit connection diagram of the fourth pixel driving circuit in the embodiments of this disclosure;

[0061] Figure 12 is a connection diagram of the fifth pixel driving circuit in the embodiment of this disclosure;

[0062] Figure 13 is a first circuit connection diagram of the fifth pixel driving circuit in the embodiments of this disclosure;

[0063] Figure 14 is a second circuit connection diagram of the fifth pixel driving circuit in the embodiment of this disclosure;

[0064] Figure 15 is a third circuit connection diagram of the fifth pixel driving circuit in the embodiments of this disclosure;

[0065] Figure 16 is a connection diagram of the sixth pixel driving circuit in the embodiments of this disclosure;

[0066] Figure 17 is a first circuit connection diagram of the sixth pixel driving circuit in the embodiments of this disclosure;

[0067] Figure 18 is a second circuit connection diagram of the sixth pixel driving circuit in the embodiments of this disclosure;

[0068] Figure 19 is a third circuit connection diagram of the sixth pixel driving circuit in the embodiments of this disclosure;

[0069] Figure 20 is a timing diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0070] Figure 21 is a flowchart of a pixel driving circuit driving method according to an embodiment of the present disclosure. Detailed Implementation

[0071] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0072] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0073] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0074] In related technologies, referring to Figure 1, NMOS pixel circuits represented by 5T2C exhibit a problem of decreased brightness uniformity. This problem stems from a significant voltage difference caused by the relatively thin magnesium-silver alloy cathode. During the light-emitting phase, the LED is turned on, and current flows through the driving transistor, charging the anode of the light-emitting device. The anode voltage gradually increases until it exceeds a critical voltage, at which point the light-emitting device begins to emit light. The driving transistor has a capacitance Cst between its gate and source. Ideally, the voltage between the gate and source remains constant, meaning the change in source voltage equals the change in gate voltage. Even if sub-pixels with the same color and data voltage signal have different anode voltages (this difference can be caused by voltage non-uniformity of ELVSS), equal brightness can still be produced because the current is determined by the voltage Vgs. However, due to the presence of parasitic capacitance, the change in source (anode) voltage does not equal the change in gate voltage. The difference in anode voltage causes a difference in current, leading to a deterioration in brightness uniformity, failing to meet the conventional 85% uniformity requirement. The structure in the figure, in which the cathode of the light-emitting device is connected to the drain of the driving transistor, is called the OLED inverted structure. Since ELVSS can use a grid structure (metal layers such as gate layer and SD layer) in the BP film layer, it can greatly reduce the voltage difference, thereby improving the aforementioned problem of poor brightness uniformity.

[0075] The preferred embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0076] Referring to Figures 2 and 3, a pixel driving circuit proposed in this embodiment includes: a driving transistor DTFT, a first capacitor C1, a light-emitting device OLED, a first switching transistor T1, a second switching transistor T2, a data writing sub-circuit 10, and a first light-emitting control sub-circuit 20. The control terminals of the first switching transistor T1 and the second switching transistor T2 are coupled to the initialization control terminal GR(n). The anode of the light-emitting device OLED is coupled to the first power supply terminal U1, and the cathode of the light-emitting device OLED is coupled to the first terminal of the driving transistor DTFT. For example, the voltage of the first power supply terminal U1 is ELVDD, and the voltage of the second power supply terminal U2 mentioned below is ELVSS.

[0077] The first terminal of the first switching transistor T1 is coupled to the first terminal of the first capacitor C1, and the second terminal of the first switching transistor T1 is coupled to the third power supply terminal U3.

[0078] The first terminal of the second switching transistor T2 is coupled to the first setting terminal, and the second terminal of the second switching transistor T2 is coupled to the third power supply terminal U3. The first setting terminal is either the first or second terminal of the driving transistor DTFT, and the second terminal of the first capacitor C1 is coupled to the control terminal of the driving transistor DTFT.

[0079] The data writing sub-circuit 10 is coupled to the first terminal of the first capacitor C1. The data writing sub-circuit 10 is configured to provide the data voltage of the data signal terminal Vdata to the first terminal of the first capacitor C1 in response to the signal of the scan signal terminal GW(n).

[0080] The first light-emitting control sub-circuit 20 is coupled to the second terminal of the driving transistor DTFT and is configured to turn on the second terminal of the driving transistor DTFT and the second power supply terminal U2 in response to the signal of the light-emitting control signal terminal EM(n).

[0081] In this embodiment, the anode of the OLED is coupled to the first power supply terminal U1, and the cathode of the OLED is coupled to the first terminal of the driving transistor DTFT. That is, the OLED has an inverted structure. Based on this, the control terminals of the first switching transistor T1 and the second switching transistor T2 are coupled to the initialization control terminal GR(n). That is, the signal of the initialization control terminal GR(n) controls the switching on and off of the first switching transistor T1 and the second switching transistor T2 simultaneously. Compared with the method in which the first switching transistor T1 and the second switching transistor T2 are controlled by different control terminals, the wiring of the control terminals is effectively saved, which is conducive to the formation of a narrow bezel of the display panel.

[0082] It should also be noted that, in order to save on wiring, in one case, the third power supply terminal U3 and the first power supply terminal U1 are the same signal terminal.

[0083] That is, the second terminal of the first switching transistor T1, the second terminal of the second switching transistor T2, or both the second terminals of the first switching transistor T1 and the second terminal of the second switching transistor T2 can be connected to the first power supply terminal U1, i.e., ELVDD, thereby effectively saving wiring. It should also be noted that, for flexible wiring, the second terminal of the first switching transistor T1 can also be connected to the first terminal of the driving transistor DTFT, and the second terminal of the second switching transistor T2 can also be connected to the first terminal of the first capacitor C1, thereby effectively saving wiring.

[0084] Referring to Figure 4, the pixel driving circuit mentioned above also includes a compensation sub-circuit 30, which is coupled to the control terminal of the driving transistor DTFT.

[0085] The compensation sub-circuit 30 is configured to turn on the control terminal of the driving transistor DTFT and the second setting terminal in response to the signal of the compensation control terminal GC(n), wherein the second setting terminal is either the first terminal or the second terminal of the driving transistor DTFT.

[0086] During implementation, when the signal of the compensation control terminal GC(n) is valid, the control terminal of the driving transistor DTFT is connected to the second setting terminal through the compensation sub-circuit 30. That is, the control terminal of the driving transistor DTFT is connected to the first terminal of the driving transistor DTFT through the compensation sub-circuit 30, or the control terminal of the driving transistor DTFT is connected to the second terminal of the driving transistor DTFT through the compensation sub-circuit 30.

[0087] For example, referring to FIG5, the compensation sub-circuit 30 includes a third switching transistor T3.

[0088] The control terminal of the third switching transistor T3 is coupled to the compensation control terminal GC(n), the first terminal of the third switching transistor T3 is coupled to the control terminal of the driving transistor DTFT, and the second terminal of the third switching transistor T3 is coupled to the second setting terminal.

[0089] For example, the third switching transistor T3 can be turned on under the control of the effective level of the compensation control terminal GC(n), and turned off under the control of the ineffective level of the compensation control terminal GC(n). For example, if the third switching transistor T3 is set as an N-type transistor, then the effective level of the signal at the compensation control terminal GC(n) is a high level, and the ineffective level of the signal at the compensation control terminal GC(n) is a low level. Alternatively, if the third switching transistor T3 is set as a P-type transistor, then the effective level of the signal at the compensation control terminal GC(n) is a low level, and the ineffective level of the signal at the compensation control terminal GC(n) is a high level.

[0090] Referring to Figure 5, when the signal of the compensation control terminal GC(n) is high, the third switching transistor T3 is turned on, and the control terminal of the driving transistor DTFT is connected to the second setting terminal through the turned-on third switching transistor T3.

[0091] For example, the first setting terminal and the second setting terminal are the same signal terminal.

[0092] In one case, the first setting terminal and the second setting terminal are both the first terminals of the driving transistor DTFT. In this case, the first terminal of the second switching transistor T2 and the second terminal of the third switching transistor T3 are both connected to the first terminal of the driving transistor DTFT, as shown in Figure 6. In another case, the first setting terminal and the second setting terminal are both the second terminals of the driving transistor DTFT. In this case, the first terminal of the second switching transistor T2 and the second terminal of the third switching transistor T3 are both connected to the second terminal of the driving transistor DTFT.

[0093] Accordingly, the first setting terminal and the second setting terminal can be different signal terminals. For example, when the first setting terminal is the first terminal of the driving transistor DTFT and the second setting terminal is the second terminal of the driving transistor DTFT, the connection between the first terminal of the second switching transistor T2 and the third switching transistor T3 is shown in Figure 7.

[0094] In another embodiment, as shown in Figure 7, the compensation control terminal GC(n) and the initialization control terminal GR(n) are the same signal terminal.

[0095] Referring to Figure 7, the control terminals of the first switching transistor T1, the second switching transistor T2, and the third switching transistor T3 are all connected to the same control terminal. This connection can further save wiring, that is, the on / off state of the first switching transistor T1, the second switching transistor T2, and the third switching transistor T3 can be simultaneously controlled by the compensation control terminal GC(n) or the initialization control terminal GR(n).

[0096] Referring to Figure 7, the data writing sub-circuit 10 includes: a fourth switching transistor T4.

[0097] The control terminal of the fourth switching transistor T4 is coupled to the scan signal terminal GW(n), the first terminal of the fourth switching transistor T4 is coupled to the first terminal of the first capacitor C1, and the second terminal of the fourth switching transistor T4 is coupled to the data signal terminal Vdata.

[0098] For example, the fourth switching transistor T4 can be turned on under the control of the effective level of the scan signal terminal GW(n), and turned off under the control of the ineffective level of the scan signal terminal GW(n). For example, if the fourth switching transistor T4 is set as an N-type transistor, then the effective level of the signal at the scan signal terminal GW(n) is a high level, and the ineffective level of the signal at the scan signal terminal GW(n) is a low level. Alternatively, if the fourth switching transistor T4 is set as a P-type transistor, then the effective level of the signal at the scan signal terminal GW(n) is a low level, and the ineffective level of the signal at the scan signal terminal GW(n) is a high level.

[0099] Referring to Figure 7, during the implementation process, when the signal at the scanning signal terminal GW(n) is high, the fourth switching transistor T4 is turned on, and the data voltage at the data signal terminal Vdata is provided to the first terminal of the first capacitor C1 through the turned-on fourth switching transistor T4.

[0100] Referring to Figure 7, the first light-emitting control sub-circuit 20 includes: a fifth switching transistor T5.

[0101] The control terminal of the fifth switching transistor T5 is coupled to the light-emitting control signal terminal EM(n), the first terminal of the fifth switching transistor T5 is coupled to the second terminal of the driving transistor DTFT, and the second terminal of the fifth switching transistor T5 is coupled to the second power supply terminal U2.

[0102] For example, the fifth switching transistor T5 can be turned on under the control of the effective level of the light-emitting control signal terminal EM(n), and can be turned off under the control of the ineffective level of the light-emitting control signal terminal EM(n). For example, if the fifth switching transistor T5 is set as an N-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM(n) is a high level, and the ineffective level of the signal at the light-emitting control signal terminal EM(n) is a low level. Alternatively, if the fifth switching transistor T5 is set as a P-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM(n) is a low level, and the ineffective level of the signal at the light-emitting control signal terminal EM(n) is a high level.

[0103] Referring to Figure 7, during the implementation process, when the signal of the light emission control signal terminal EM(n) is high, the fifth switching transistor T5 is turned on, and the second terminal of the driving transistor DTFT is connected to the second power supply terminal U2 through the turned-on fifth switching transistor T5.

[0104] Referring to Figure 8, the pixel driving circuit mentioned above also includes a second light-emitting control sub-circuit 40, wherein the second light-emitting control sub-circuit 40 is coupled to the cathode of the light-emitting device OLED and the first end of the driving transistor DTFT.

[0105] The second light-emitting control sub-circuit 40 is configured to turn on the cathode of the light-emitting device OLED and the first terminal of the driving transistor DTFT in response to the signal of the light-emitting control signal terminal EM(n).

[0106] In this embodiment, in addition to the first light-emitting control sub-circuit 20 described above, a second light-emitting control sub-circuit 40 is also provided between the first power supply terminal U1 and the second power supply terminal U2. During implementation, when the signal of the light-emitting control signal terminal EM(n) is at an effective level, the second light-emitting control sub-circuit 40 connects the cathode of the light-emitting device OLED with the first terminal of the driving transistor DTFT.

[0107] Referring to Figure 9, the second light-emitting control sub-circuit 40 includes: a sixth switching transistor T6.

[0108] The control terminal of the sixth switching transistor T6 is coupled to the light-emitting control signal terminal EM(n), the first terminal of the sixth switching transistor T6 is coupled to the cathode of the light-emitting device OLED, and the second terminal of the sixth switching transistor T6 is coupled to the first terminal of the driving transistor DTFT.

[0109] For example, the sixth switching transistor T6 can be turned on under the control of the effective level of the light-emitting control signal terminal EM(n), and can be turned off under the control of the ineffective level of the light-emitting control signal terminal EM(n). For example, if the sixth switching transistor T6 is set as an N-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM(n) is a high level, and the ineffective level of the signal at the light-emitting control signal terminal EM(n) is a low level. Alternatively, if the sixth switching transistor T6 is set as a P-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM(n) is a low level, and the ineffective level of the signal at the light-emitting control signal terminal EM(n) is a high level.

[0110] Referring to Figure 9, during the implementation process, when the signal of the light emission control signal terminal EM(n) is high, the sixth switching transistor T6 is turned on, and the cathode of the light emission device OLED is connected to the first terminal of the driving transistor DTFT through the turned-on sixth switching transistor T6.

[0111] Referring to Figure 10, the pixel driving circuit also includes a third light emission control sub-circuit 50, wherein the third light emission control sub-circuit 50 is coupled to the first power supply terminal U1 and the anode of the light emission device OLED.

[0112] The third light-emitting control sub-circuit 50 is configured to connect the first power supply terminal U1 to the anode of the light-emitting device OLED in response to the signal of the light-emitting control signal terminal EM(n).

[0113] In this embodiment, in addition to the first light-emitting control sub-circuit 20 and the second light-emitting control sub-circuit 40, a third light-emitting control sub-circuit 50 is also provided between the first power supply terminal U1 and the second power supply terminal U2. During implementation, when the signal of the light-emitting control signal terminal EM(n) is at an effective level, the third light-emitting control sub-circuit 50 connects the first power supply terminal U1 to the anode of the light-emitting device OLED.

[0114] Referring to Figure 11, the third light-emitting control sub-circuit 50 includes: a seventh switching transistor T7.

[0115] The control terminal of the seventh switching transistor T7 is coupled to the light-emitting control signal terminal EM(n), the first terminal of the seventh switching transistor T7 is coupled to the first power supply terminal U1, and the second terminal of the seventh switching transistor T7 is coupled to the anode of the light-emitting device OLED.

[0116] For example, the seventh switching transistor T7 can be turned on under the control of the effective level of the light-emitting control signal terminal EM(n), and can be turned off under the control of the ineffective level of the light-emitting control signal terminal EM(n). For example, if the seventh switching transistor T7 is set as an N-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM(n) is a high level, and the ineffective level of the signal at the light-emitting control signal terminal EM(n) is a low level. Alternatively, if the seventh switching transistor T7 is set as a P-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM(n) is a low level, and the ineffective level of the signal at the light-emitting control signal terminal EM(n) is a high level.

[0117] Referring to Figure 11, during the implementation process, when the signal of the light emission control signal terminal EM(n) is high, the seventh switching transistor T7 is turned on, and the first power supply terminal U1 is connected to the anode of the light emission device OLED through the turned-on seventh switching transistor T7.

[0118] Referring to Figure 12, the pixel driving circuit also includes a first reset circuit 60, wherein the first reset circuit 60 is coupled to the control terminal of the driving transistor DTFT.

[0119] The first reset sub-circuit 60 is configured to provide the signal of the first reset signal terminal to the control terminal of the driving transistor DTFT in response to the signal of the first reset control terminal GI(n).

[0120] During implementation, when the signal of the first reset control terminal GI(n) is valid, the signal of the first reset signal terminal is provided to the control terminal of the driving transistor DTFT through the first reset sub-circuit 60, thereby resetting the control terminal of the driving transistor DTFT.

[0121] Referring to Figure 13, the first reset circuit 60 includes an eighth switching transistor T8.

[0122] The control terminal of the eighth switching transistor T8 is coupled to the first reset control terminal GI(n), the first terminal of the eighth switching transistor T8 is coupled to the first reset signal terminal, and the second terminal of the eighth switching transistor T8 is coupled to the control terminal of the driving transistor DTFT.

[0123] For example, the eighth switching transistor T8 can be turned on under the control of the effective level of the first reset control terminal GI(n), and can be turned off under the control of the ineffective level of the first reset control terminal GI(n). For example, if the eighth switching transistor T8 is set as an N-type transistor, then the effective level of the signal at the first reset control terminal GI(n) is a high level, and the ineffective level of the signal at the first reset control terminal GI(n) is a low level. Alternatively, if the eighth switching transistor T8 is set as a P-type transistor, then the effective level of the signal at the first reset control terminal GI(n) is a low level, and the ineffective level of the signal at the first reset control terminal GI(n) is a high level.

[0124] Referring to Figure 13, during the implementation process, when the signal of the first reset control terminal GI(n) is high, the eighth switching transistor T8 is turned on, and the signal of the first reset signal terminal is provided to the control terminal of the driving transistor DTFT through the turned-on eighth switching transistor T8.

[0125] It should also be noted that the aforementioned first reset signal terminal is the first power supply terminal U1, the cathode of the light-emitting device OLED, or the first terminal of the first capacitor C1.

[0126] Referring to Figure 13, the first reset signal terminal is the first power supply terminal U1. When the signal of the first reset control terminal GI(n) is high, the eighth switching transistor T8 is turned on. The signal of the first power supply terminal U1 is provided to the control terminal of the driving transistor DTFT through the turned-on eighth switching transistor T8, thereby resetting the control terminal of the driving transistor DTFT.

[0127] Referring to Figure 14, the first reset signal terminal is the cathode of the light-emitting device OLED. When the signal of the first reset control terminal GI(n) is high, the eighth switching transistor T8 is turned on. The signal of the cathode of the light-emitting device OLED is provided to the control terminal of the driving transistor DTFT through the turned-on eighth switching transistor T8, thereby resetting the control terminal of the driving transistor DTFT.

[0128] Referring to Figure 15, the first reset signal terminal is the first terminal of the first capacitor C1. When the signal of the first reset control terminal GI(n) is high, the eighth switching transistor T8 is turned on. The signal of the first terminal of the first capacitor C1 is provided to the control terminal of the driving transistor DTFT through the turned-on eighth switching transistor T8, thereby resetting the control terminal of the driving transistor DTFT.

[0129] It should be added that the voltage of the first power supply terminal U1 can also be a voltage value represented by Vint, Vref, and Vref1. Specifically, the voltage of the first power supply terminal U1 can be any one of Vint, Vref, and Vref1, and the magnitude of the voltage is not specifically limited. However, the magnitude of the voltage source connected to the second switching transistor T2 must be greater than the sum of the voltage source connected to the eighth switching transistor T8 and the threshold voltage of the driving transistor DTFT. In other words, the voltage source connected to the second switching transistor T2 cannot be the same as the voltage source connected to the eighth switching transistor T8.

[0130] In addition, the voltage range of ELVDD can be from 4 to 18V, and the voltage range of ELVSS can be from -10V to 5V. Of course, ELVDD must be at least 4V greater than ELVSS. The Vint voltage is generally close to that of ELVDD, and ELVDD-Vint ≤ 1V is acceptable.

[0131] Referring to Figure 16, the pixel driving circuit mentioned above also includes a second reset circuit 70, wherein the second reset circuit 70 is coupled to the cathode of the light-emitting device OLED.

[0132] The second reset sub-circuit 70 is configured to provide a signal from the second reset signal terminal to the cathode of the light-emitting device OLED in response to a signal from the second reset control terminal GB(n).

[0133] During implementation, when the signal of the second reset control terminal GB(n) is valid, the signal of the second reset signal terminal is provided to the cathode of the light-emitting device OLED through the second reset sub-circuit 70, thereby resetting the cathode of the light-emitting device OLED.

[0134] Referring to Figure 17, the second reset circuit 70 includes a ninth switching transistor T9.

[0135] The control terminal of the ninth switching transistor T9 is coupled to the second reset control terminal GB(n), the first terminal of the ninth switching transistor T9 is coupled to the second reset signal terminal, and the second terminal of the ninth switching transistor T9 is coupled to the cathode of the light-emitting device OLED.

[0136] For example, the ninth switching transistor T9 can be turned on under the control of the active level of the second reset control terminal GB(n), and turned off under the control of the inactive level of the second reset control terminal GB(n). For example, if the ninth switching transistor T9 is configured as an N-type transistor, then the active level of the signal at the second reset control terminal GB(n) is high, and the inactive level of the signal at the second reset control terminal GB(n) is low. Alternatively, if the ninth switching transistor T9 is configured as a P-type transistor, then the active level of the signal at the second reset control terminal GB(n) is low, and the inactive level of the signal at the second reset control terminal GB(n) is high.

[0137] Referring to Figure 17, during the implementation process, when the signal of the second reset control terminal GB(n) is high, the ninth switching transistor T9 is turned on, and the signal of the second reset signal terminal is provided to the cathode of the light-emitting device OLED through the turned-on ninth switching transistor T9, thereby resetting the cathode of the light-emitting device OLED.

[0138] It should be added that, for Figure 17, the eighth switching transistor T8 is connected to the cathode of the OLED, and the ninth switching transistor T9 can be turned on no later than the eighth switching transistor T8. Similarly, the first switching transistor T1 can also be connected to the cathode of the OLED, and the ninth switching transistor T9 can be turned on no later than the eighth switching transistor T8.

[0139] In addition, as shown in Figure 18, the pixel driving circuit also includes a second capacitor C2.

[0140] The first terminal of the second capacitor C2 is coupled to the first power supply terminal U1, and the second terminal of the second capacitor C2 is coupled to the first terminal of the first capacitor C1.

[0141] In this embodiment of the application, by setting the second capacitor C2, the voltage at the first end of the first capacitor C1 can be made more stable.

[0142] Referring to Figure 19, the pixel driving circuit described above also includes a third capacitor C3.

[0143] The first terminal of the third capacitor C3 is coupled to the first power supply terminal U1, and the second terminal of the third capacitor C3 is coupled to the second terminal of the first capacitor C1.

[0144] In this embodiment of the application, by setting the third capacitor C3, the voltage at the second end of the first capacitor C1 can be made more stable.

[0145] The operation of the pixel driving circuit in the embodiments of this application will be described in detail below with reference to Figures 19 and 20.

[0146] Timing T1 stage: GR(n) = 1, GI(n) = 1

[0147] When the initialization control terminal GR(n) is high, the first switching transistor T1 is turned on, and the signal from the third power supply terminal U3 is provided to the first terminal of the first capacitor C1 via the turned-on first switching transistor T1, thereby initializing the first terminal of the first capacitor C1. When the initialization control terminal GR(n) is high, the second switching transistor T2 is turned on, and the signal from the third power supply terminal U3 is provided to the second terminal of the first capacitor C1 via the turned-on second switching transistor T2, thereby initializing the second terminal of the first capacitor C1. When the first reset control terminal GI(n) is high, the eighth switching transistor T8 is turned on, and the signal from the first reset terminal is provided to the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8, thereby resetting the control terminal of the driving transistor DTFT.

[0148] Timing T2 stage: GR(n) = 1, GC(n) = 1, GB(n) = 1

[0149] When the initialization control terminal GR(n) is high, the first switching transistor T1 is turned on, and the signal from the third power supply terminal U3 is provided to the first terminal of the first capacitor C1 through the turned-on first switching transistor T1, thereby initializing the first terminal of the first capacitor C1. When the initialization control terminal GR(n) is high, the second switching transistor T2 is turned on, and the signal from the third power supply terminal U3 is provided to the second terminal of the first capacitor C1 through the turned-on second switching transistor T2, thereby initializing the second terminal of the first capacitor C1. When the compensation control terminal GC(n) is high, the third switching transistor T3 is turned on, and the second terminal of the third switching transistor T3 is connected to the second terminal of the driving transistor DTFT through the turned-on third switching transistor T3, and the threshold voltage of the driving transistor DTFT is written to the control terminal of the driving transistor DTFT. When the second reset control terminal GB(n) is high, the ninth switching transistor T9 is turned on, and the signal from the second reset signal terminal resets the cathode of the light-emitting device OLED.

[0150] Timing T3 stage: GW(n) = 1

[0151] When the signal at the scan signal terminal GW(n) is at a high potential, the fourth switching transistor T4 is turned on, and the data voltage at the data signal terminal Vdata is written to the first terminal of the first capacitor C1 through the turned-on fourth switching transistor T4.

[0152] Timing T4 stage: EM(n) = 1

[0153] When the signal at the light-emitting control signal terminal EM(n) is at an effective level, the sixth switching transistor T6 and the fifth switching transistor T5 are turned on. This completes the circuit consisting of the first power supply terminal U1, the light-emitting device OLED, the driving transistor DTFT, and the second power supply terminal U2, causing the OLED to emit light. The driving current of the OLED is Id = u × Cox × W / 2L × (Vgs - Vth). 2

[0154] Furthermore, Id = u × Cox × W / 2L × (Vdata + Vth - ELVSS - Vth) 2 =u×Cox×W / 2L×(Vdata-ELVSS) 2

[0155] In summary, 'μ' and 'Cox' can be constants, 'W' can be the channel width of T3, 'L' can be the channel length of T3, and 'Vgs' can refer to the differential voltage between the gate and source of T3. The driving current Id of the OLED light-emitting device is unaffected by the threshold voltage (Vth) of the driving transistor DTFT, and the brightness of the image output from the display panel can be maintained uniformly, independent of the threshold voltage of the driving transistor DTFT.

[0156] Based on the same inventive concept, this disclosure provides a display panel including any of the pixel driving circuits described above.

[0157] In this embodiment of the invention, the display panel can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0158] Based on the same inventive concept, this disclosure provides a light emission control method for a pixel driving circuit applied to any of the above claims, as shown in Figure 21, including:

[0159] Initialization phase: In response to the signal of the initialization control terminal GR(n), the first switching transistor T1 provides the signal of the third power supply terminal U3 to the first terminal of the first capacitor C1; in response to the signal of the initialization control terminal GR(n), the second switching transistor T2 provides the signal of the third power supply terminal U3 to the first setting terminal; and the first reset sub-circuit 60, in response to the signal of the first reset control terminal GI(n), provides the signal of the first reset signal terminal to the control terminal of the driving transistor DTFT.

[0160] During implementation, when the initialization control terminal GR(n) signal is at an active level, the signal from the third power supply terminal U3 is provided to the first terminal of the first capacitor C1 via the activated first switching transistor T1, thereby initializing the first terminal of the first capacitor C1. When the initialization control terminal GR(n) signal is at an active level, the signal from the third power supply terminal U3 is provided to either the first or second terminal of the driving transistor DTFT via the activated second switching transistor T2, thereby initializing either the first or second terminal of the driving transistor DTFT.

[0161] Simultaneously, when the signal of the first reset control terminal GI(n) is at an effective level, the first reset sub-circuit 60 is turned on, and the signal of the first reset signal terminal is provided to the control terminal of the driving transistor DTFT through the turned-on first reset sub-circuit 60, thereby resetting the control terminal of the driving transistor DTFT.

[0162] Threshold voltage compensation stage: In response to the signal of the compensation control terminal GC(n), the compensation sub-circuit 30 turns on the control terminal of the driving transistor DTFT and the second setting terminal, and writes the threshold voltage of the driving transistor DTFT to the control terminal of the driving transistor DTFT.

[0163] During implementation, when the signal of the compensation control terminal GC(n) is at an effective level, the compensation sub-circuit 30 is turned on, and the control terminal of the driving transistor DTFT is turned on through the turned-on compensation sub-circuit 30 and the second setting terminal is turned on, thereby writing the threshold voltage of the driving transistor DTFT to the control terminal of the driving transistor DTFT.

[0164] Data writing stage: In response to the signal of the scan signal terminal GW(n), the data writing sub-circuit 10 provides the data voltage of the data signal terminal Vdata to the first terminal of the first capacitor C1.

[0165] During implementation, when the signal at the scanning signal terminal GW(n) is at an effective level, the data writing sub-circuit 10 is turned on, and the data voltage at the data signal terminal Vdata is provided to the first terminal of the first capacitor C1 through the turned-on data writing sub-circuit 10, and then provided to the control terminal of the driving transistor DTFT.

[0166] Light emission stage: In response to the signal of the light emission control signal terminal EM(n), the third light emission control sub-circuit 50 connects the first power supply terminal U1 to the anode of the light emission device OLED, the second light emission control sub-circuit 40 connects the cathode of the light emission device OLED to the first terminal of the driving transistor DTFT, and the first light emission control sub-circuit 20 connects the second terminal of the driving transistor DTFT to the second power supply terminal U2.

[0167] During implementation, when the signal of the light emission control signal terminal EM(n) is at an effective level, the first light emission control sub-circuit 20, the second light emission control sub-circuit 40 and the third light emission control sub-circuit 50 are all turned on, thereby turning on the loop composed of the first power supply terminal U1, the anode of the light emission device OLED, the cathode of the light emission device OLED, the first terminal of the driving transistor DTFT, the second terminal of the driving transistor DTFT and the second power supply terminal U2, causing the light emission device OLED to emit light.

[0168] As described above, the pixel driving circuit, display panel, and light-emitting control method provided in this embodiment include: a driving transistor, a first capacitor, a light-emitting device, a first switching transistor, a second switching transistor, a data writing sub-circuit, and a first light-emitting control sub-circuit. The control terminals of the first and second switching transistors are coupled to an initialization control terminal. The anode of the light-emitting device is coupled to a first power supply terminal, and the cathode of the light-emitting device is coupled to a first terminal of the driving transistor. The first terminal of the first switching transistor is coupled to a first terminal of the first capacitor. The second terminal of the first switching transistor is coupled to a third power supply terminal U3. The first terminal of the second switching transistor is coupled to a first setting terminal. The second end of the body transistor is coupled to the third power supply terminal U3. The first setting terminal is either the first or second terminal of the driving transistor. The second terminal of the first capacitor is coupled to the control terminal of the driving transistor. The data writing sub-circuit is coupled to the first terminal of the first capacitor. The data writing sub-circuit is configured to provide the data voltage of the data signal terminal to the first terminal of the first capacitor in response to the signal of the scan signal terminal. The first light emission control sub-circuit is coupled to the second terminal of the driving transistor and is configured to turn on the second terminal of the driving transistor and the second power supply terminal in response to the signal of the light emission control signal terminal. The above-mentioned method of coupling the control terminals of the first and second switching transistors with the initialization control terminal optimizes the layout and wiring, which is beneficial to the formation of a narrow bezel.

[0169] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program product systems. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product system implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0170] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program product systems according to this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0171] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0172] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0173] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A pixel driving circuit, wherein, include: The system includes a driving transistor, a first capacitor, a light-emitting device, a first switching transistor, a second switching transistor, a data writing sub-circuit, and a first light-emitting control sub-circuit, wherein the control terminals of the first and second switching transistors are coupled to an initialization control terminal, the anode of the light-emitting device is coupled to a first power supply terminal, and the cathode of the light-emitting device is coupled to a first terminal of the driving transistor. The first terminal of the first switching transistor is coupled to the first terminal of the first capacitor, and the second terminal of the first switching transistor is coupled to the third power supply terminal. The first terminal of the second switching transistor is coupled to the first setting terminal, and the second terminal of the second switching transistor is coupled to the third power supply terminal. The first setting terminal is either the first terminal or the second terminal of the driving transistor, and the second terminal of the first capacitor is coupled to the control terminal of the driving transistor. The data writing sub-circuit is coupled to the first terminal of the first capacitor, and the data writing sub-circuit is configured to provide the data voltage of the data signal terminal to the first terminal of the first capacitor in response to the signal of the scan signal terminal. The first light-emitting control sub-circuit is coupled to the second terminal of the driving transistor and is configured to turn on the second terminal and the second power supply terminal of the driving transistor in response to a signal from the light-emitting control signal terminal.

2. The pixel driving circuit of claim 1, wherein, It also includes a compensation sub-circuit, which is coupled to the control terminal of the driving transistor; The compensation sub-circuit is configured to connect the control terminal of the driving transistor to the second setting terminal in response to a signal from the compensation control terminal, wherein the second setting terminal is either the first terminal or the second terminal of the driving transistor.

3. The pixel driving circuit of claim 2, wherein, The first setting terminal and the second setting terminal are the same signal terminal.

4. The pixel driving circuit of claim 2, wherein, The compensation sub-circuit includes: a third switching transistor; The control terminal of the third switching transistor is coupled to the compensation control terminal, the first terminal of the third switching transistor is coupled to the control terminal of the driving transistor, and the second terminal of the third switching transistor is coupled to the second setting terminal.

5. The pixel drive circuit according to any one of claims 2 to 4, wherein The compensation control terminal and the initialization control terminal are the same signal terminal.

6. The pixel driving circuit of claim 1, wherein, The data writing sub-circuit includes: a fourth switching transistor; The control terminal of the fourth switching transistor is coupled to the scan signal terminal, the first terminal of the fourth switching transistor is coupled to the first terminal of the first capacitor, and the second terminal of the fourth switching transistor is coupled to the data signal terminal.

7. The pixel driving circuit of claim 1, wherein, The first light-emitting control sub-circuit includes: a fifth switching transistor; The control terminal of the fifth switching transistor is coupled to the light-emitting control signal terminal, the first terminal of the fifth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the fifth switching transistor is coupled to the second power supply terminal.

8. The pixel driving circuit according to any one of claims 1 to 7, wherein It also includes a second light-emitting control sub-circuit, wherein the second light-emitting control sub-circuit is coupled to the cathode of the light-emitting device and the first terminal of the driving transistor; The second light-emitting control sub-circuit is configured to conduct the cathode of the light-emitting device to the first terminal of the driving transistor in response to a signal from the light-emitting control signal terminal.

9. The pixel driving circuit of claim 8, wherein, The second light-emitting control sub-circuit includes: a sixth switching transistor; The control terminal of the sixth switching transistor is coupled to the light-emitting control signal terminal, the first terminal of the sixth switching transistor is coupled to the cathode of the light-emitting device, and the second terminal of the sixth switching transistor is coupled to the first terminal of the driving transistor.

10. The pixel drive circuit according to any one of claims 1 to 7, wherein It also includes a third light-emitting control sub-circuit, wherein the third light-emitting control sub-circuit is coupled to the first power supply terminal and the anode of the light-emitting device; The third light-emitting control sub-circuit is configured to connect the first power supply terminal to the anode of the light-emitting device in response to a signal from the light-emitting control signal terminal.

11. The pixel driving circuit of claim 10, wherein, The third light-emitting control sub-circuit includes: a seventh switching transistor; The control terminal of the seventh switching transistor is coupled to the light-emitting control signal terminal, the first terminal of the seventh switching transistor is coupled to the first power supply terminal, and the second terminal of the seventh switching transistor is coupled to the anode of the light-emitting device.

12. The pixel drive circuit according to any one of claims 1 to 11, wherein It also includes a first reset circuit, wherein the first reset circuit is coupled to the control terminal of the driving transistor; The first reset sub-circuit is configured to provide a signal from the first reset signal terminal to the control terminal of the driving transistor in response to a signal from the first reset control terminal.

13. The pixel driving circuit of claim 12, wherein, The first reset circuit includes: an eighth switching transistor; The control terminal of the eighth switching transistor is coupled to the first reset control terminal, the first terminal of the eighth switching transistor is coupled to the first reset signal terminal, and the second terminal of the eighth switching transistor is coupled to the control terminal of the driving transistor.

14. The pixel drive circuit of claim 12 or 13, wherein, The first reset signal terminal is the first power supply terminal, the cathode of the light-emitting device, or the first terminal of the first capacitor.

15. The pixel drive circuit according to any one of claims 1 to 14, wherein It also includes a second reset circuit, wherein the second reset circuit is coupled to the cathode of the light-emitting device; The second reset sub-circuit is configured to provide a signal from the second reset signal terminal to the cathode of the light-emitting device in response to a signal from the second reset control terminal.

16. The pixel driving circuit of claim 15, wherein, The second reset circuit includes: a ninth switching transistor; The control terminal of the ninth switching transistor is coupled to the second reset control terminal, the first terminal of the ninth switching transistor is coupled to the second reset signal terminal, and the second terminal of the ninth switching transistor is coupled to the cathode of the light-emitting device.

17. The pixel driving circuit of claim 1, wherein, The third power supply terminal and the first power supply terminal are the same signal terminal.

18. The pixel drive circuit according to any one of claims 1 to 17, wherein It also includes: the second capacitor and the third capacitor; The first terminal of the second capacitor is coupled to the first power supply terminal, and the second terminal of the second capacitor is coupled to the first terminal of the first capacitor. The first terminal of the third capacitor is coupled to the first power supply terminal, and the second terminal of the third capacitor is coupled to the second terminal of the first capacitor.

19. A display panel, wherein, include: The pixel driving circuit as described in any one of claims 1 to 18.

20. A light emission control method applied to the pixel driving circuit according to any one of claims 1 to 18, wherein include: Initialization phase: In response to the signal from the initialization control terminal, the first switching transistor provides the signal from the third power supply terminal to the first terminal of the first capacitor; The second switching transistor responds to the signal at the initialization control terminal by providing the signal at the third power supply terminal to the first setting terminal; and the first reset sub-circuit responds to the signal at the first reset control terminal by providing the signal at the first reset signal terminal to the control terminal of the driving transistor. Threshold voltage compensation stage: In response to the signal from the compensation control terminal, the compensation sub-circuit connects the control terminal of the driving transistor to the second setting terminal and writes the threshold voltage of the driving transistor to the control terminal of the driving transistor. Data writing stage: The data writing sub-circuit responds to the signal at the scan signal terminal by providing the data voltage at the data signal terminal to the first terminal of the first capacitor; Light emission stage: In response to the signal at the light emission control signal terminal, the third light emission control sub-circuit will... The power supply terminal is connected to the anode of the light-emitting device, the second light-emitting control sub-circuit connects the cathode of the light-emitting device to the first terminal of the driving transistor, and the first light-emitting control sub-circuit connects the second terminal of the driving transistor to the second power supply terminal.

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