Display substrate and display device

Abstract

A display substrate, comprising a first display area (A1). The first display area (A1) comprises a plurality of sub-display areas (A11) extending in a first direction (D1) and arranged in a second direction (D2), and a plurality of light-transmitting areas (A13) located between adjacent sub-display areas (A11). The sub-display areas (A11) comprise: a substrate (100), and a plurality of first pixel circuits (11) and a plurality of first light-emitting elements (13) disposed on the substrate (100). A row of first pixel circuits in the sub-display areas (A11) are connected to a plurality of first signal lines extending in the first direction (D1). The distance between the orthographic projections of any two adjacent first signal lines among the plurality of first signal lines on the substrate (100) is less than the maximum length of one light-transmitting area (A13) in the second direction (D2).

Description

Display substrate and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate and a display device.

[0006] On one hand, this embodiment provides a display substrate, including: a first display area; the first display area includes: a plurality of sub-display areas extending along a first direction and arranged along a second direction, and a plurality of light-transmitting areas located between adjacent sub-display areas; the first direction intersects the second direction. The sub-display areas include: a substrate and a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on the substrate; at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements and configured to drive the at least one first light-emitting element to emit light. The orthographic projection of the at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element on the substrate. The plurality of first pixel circuits include multiple rows of first pixel circuits, and one row of first pixel circuits is connected to a plurality of first signal lines extending along the first direction; the row of first pixel circuits includes at least a portion of the plurality of first pixel circuits arranged sequentially along the first direction. The distance between the orthographic projections of any two adjacent first signal lines connected to the row of first pixel circuits on the substrate is less than the maximum length of one of the multiple light-transmitting areas along the second direction.

[0007] In some exemplary embodiments, the ratio of the maximum length of a row of first pixel circuits in the sub-display area projected onto the substrate along the second direction to the maximum length of a light-transmitting area along the second direction is greater than or equal to 1.

[0008] In some exemplary embodiments, in the second direction, a plurality of first pixel circuits in adjacent sub-display areas are connected by a plurality of signal connection lines; the first display area further includes a plurality of trace areas located between adjacent sub-display areas and spaced apart from the light-transmitting area along the first direction; at least one of the plurality of trace areas has a length along the first direction that is greater than the line width of at least one of the plurality of signal connection lines.

[0009] In some exemplary embodiments, the plurality of first signal lines include: a scan line, an emission control line, and a reset control line; the scan line, the emission control line, and the reset control line are located in the same conductive layer, the emission control line is located between the scan line and the reset control line in the second direction, and the minimum distance between the emission control line connected to the first pixel circuit in the same row and the reset control line is less than the minimum distance between the scan line and the emission control line.

[0010] In some exemplary embodiments, the plurality of first signal lines further includes: a reference signal line, a first initial signal line, and a second initial signal line. The reference signal line and the first initial signal line are located in the same conductive layer, and are located on the side of the conductive layer where the scan line is located away from the substrate; the second initial signal line is located in the conductive layer where the first initial signal line is away from the substrate.

[0011] In some exemplary embodiments, the first pixel circuit includes: a driving transistor, a capacitor, a first control transistor, and a second control transistor. The gate of the driving transistor is integrally formed with the first plate of the capacitor, and the second plate of the capacitor is connected to the second terminals of the first and second control transistors. The first terminals of the first and second control transistors are connected to the reference signal line. The gate of the first control transistor is connected to the reset control line, and the gate of the second control transistor is connected to the light emission control line. The gates of the first and second control transistors are offset along the first direction. The reference signal line is located on a conductive layer away from the substrate from the gates of the first and second control transistors. The orthographic projection of the reference signal line onto the substrate is a zigzag line extending along the first direction, and is located between the orthographic projections of the gates of the first and second control transistors onto the substrate.

[0012] In some exemplary embodiments, the active layer of the first control transistor and the active layer of the second control transistor are an integral structure, and the orthographic projection of the integral structure onto the substrate is a rectangular ring.

[0013] In some exemplary embodiments, the first pixel circuit further includes: a first compensation transistor, the gate of the first compensation transistor being integrally formed with the scan line, a first electrode of the first compensation transistor being connected to a second electrode of the driving transistor, and the second electrode of the first compensation transistor being connected to the gate of the driving transistor. The display substrate further includes: a shielding electrode; the conductive region between the orthographic projection of the shielding electrode onto the substrate and the orthographic projection of the channel region of the active layer of the first compensation transistor onto the substrate at least partially overlaps.

[0014] In some exemplary embodiments, the first pixel circuit further includes: a second compensation transistor, wherein the gate of the second compensation transistor is integrally formed with the light emission control line; the first electrode of the second compensation transistor is floating, and the second electrode of the second compensation transistor is connected to the second electrode of the first compensation transistor.

[0015] In some exemplary embodiments, the display substrate further includes a shielding layer located on the side of the plurality of first pixel circuits near the substrate. The shielding layer includes a first shielding structure and a first shielding connection electrode interconnected with each other. The orthographic projection of the first shielding structure onto the substrate covers the orthographic projection of the active layer of the transistors of the plurality of first pixel circuits onto the substrate. The first shielding connection electrode is connected to a first power line via a second shielding connection electrode located in a conductive layer away from the substrate, and the first power line is located in a conductive layer away from the substrate.

[0016] In some exemplary embodiments, the first light-emitting element includes an anode, an organic light-emitting layer, and a cathode stacked sequentially. The orthographic projection of the anode of the first light-emitting element onto the substrate does not overlap with the orthographic projections of the connection hole between the first shielding connection electrode and the second shielding connection electrode, and the connection hole between the second shielding connection electrode and the first power line onto the substrate.

[0017] In some exemplary embodiments, the corners of the conductive layer surrounding the light-transmitting area are rounded.

[0018] In some exemplary embodiments, the sub-display area includes: a plurality of sets of first light-emitting elements arranged along the first direction, each set of first light-emitting elements including: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light. The first light-emitting elements emitting the first color light and the first light-emitting elements emitting the second color light are arranged adjacent to each other along the second direction, and the first light-emitting element emitting the third color light is located on the same side of the first light-emitting elements emitting the first color light and the first light-emitting elements emitting the second color light in the first direction.

[0019] In some exemplary embodiments, the spacing between adjacent groups of first light-emitting elements along the first direction is less than the maximum length of the light-transmitting area along the second direction; or, the spacing between adjacent groups of first light-emitting elements along the first direction is less than the maximum length of the first pixel circuit along the second direction.

[0020] In some exemplary embodiments, the spacing between adjacent groups of first light-emitting elements along the first direction is equal to the spacing between adjacent first light-emitting elements in each group.

[0021] In some exemplary embodiments, the display substrate further includes a second display area located at least one side of the first display area. The second display area includes a substrate and a plurality of second pixel circuits and a plurality of second light-emitting elements disposed on the substrate; at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements and configured to drive the at least one second light-emitting element to emit light. The orthographic projection of the at least one second pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one second light-emitting element on the substrate. The maximum length of the orthographic projection of the second pixel circuit on the substrate along the second direction is greater than the maximum length of the orthographic projection of the first pixel circuit on the substrate along the second direction.

[0022] In some exemplary embodiments, the pixel density of the second display area is the same as that of the first display area.

[0023] On the other hand, this embodiment provides a display panel, including a display substrate as described above, and a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0024] On the other hand, this embodiment provides a display substrate, including: a first display area and a second display area located at least one side of the first display area; the first display area includes a plurality of sub-display areas extending along a first direction and arranged along a second direction, and a plurality of light-transmitting areas located between adjacent sub-display areas; the pixel density of the second display area is the same as the pixel density of the first display area; the first direction intersects the second direction. The sub-display areas include: a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on a substrate, at least one of the plurality of first pixel circuits being connected to at least one of the plurality of first light-emitting elements and configured to drive the at least one first light-emitting element to emit light. The orthographic projection of the at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element on the substrate. The second display area includes: a plurality of second pixel circuits and a plurality of second light-emitting elements disposed on the substrate, at least one of the plurality of second pixel circuits being connected to at least one of the plurality of second light-emitting elements and configured to drive the at least one second light-emitting element to emit light. The orthographic projection of the at least one second pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one second light-emitting element on the substrate. The maximum length of the orthographic projection of the second pixel circuit onto the substrate along the second direction is greater than the maximum length of the orthographic projection of the first pixel circuit onto the substrate along the second direction.

[0025] In some exemplary embodiments, the maximum length of the orthogonal projection of the second pixel circuit onto the substrate along the second direction is greater than the maximum length of one of the plurality of light-transmitting areas along the second direction.

[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0027] Overview of the attached figures

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0029] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0030] Figure 2 is a schematic diagram of the pixel circuit arrangement of the display area in at least one embodiment of the present disclosure;

[0031] Figure 3 is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0032] Figure 4A is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0033] Figure 4B is an example of the operating timing diagram of the pixel circuit shown in Figure 4A;

[0034] Figures 5 and 6 are partial top views of the first display area according to at least one embodiment of the present disclosure;

[0035] Figure 7A is a schematic diagram of the first display area after the shielding layer is formed in Figure 5;

[0036] Figure 7B is a schematic diagram of the first display area after the shielding layer is formed in Figure 6;

[0037] Figure 8A is a schematic diagram of the first display area after the semiconductor layer is formed in Figure 5;

[0038] Figure 8B is a schematic diagram of the shielding layer and semiconductor layer in Figure 6;

[0039] Figure 8C is a schematic diagram of the semiconductor layer in Figure 8B;

[0040] Figure 9A is a schematic diagram of the first display area after the first conductive layer is formed in Figure 5;

[0041] Figure 9B is a schematic diagram of the semiconductor layer and the first conductive layer in Figure 6;

[0042] Figure 9C is a schematic diagram of the first conductive layer in Figure 9B;

[0043] Figure 10A is a schematic diagram of the first display area after the second conductive layer is formed in Figure 5;

[0044] Figure 10B is a schematic diagram of the semiconductor layer, the first conductive layer and the second conductive layer in Figure 6;

[0045] Figure 10C is a schematic diagram of the second conductive layer in Figure 10B;

[0046] Figure 11A is a schematic diagram of the first display area after the fourth insulating layer is formed in Figure 5;

[0047] Figure 11B is a schematic diagram of the first display area after the fourth insulating layer is formed in Figure 6;

[0048] Figure 12A is a schematic diagram of the first display area after the third conductive layer is formed in Figure 5;

[0049] Figure 12B is a schematic diagram of the first display area after the third conductive layer is formed in Figure 6;

[0050] Figure 12C is a schematic diagram of the third conductive layer in Figure 12B;

[0051] Figure 13 is a schematic diagram of the first display area after the formation of the sixth insulating layer in Figure 6;

[0052] Figure 14A is a schematic diagram of the first display area after the fourth conductive layer is formed in Figure 5;

[0053] Figure 14B is a schematic diagram of the first display area after the fourth conductive layer is formed in Figure 6;

[0054] Figure 14C is a schematic diagram of the fourth conductive layer in Figure 14B;

[0055] Figure 14D is another schematic diagram of the fourth conductive layer according to at least one embodiment of the present disclosure;

[0056] Figure 15 is a schematic diagram of the first display area after the seventh insulating layer is formed in Figure 5;

[0057] Figure 16 is a schematic diagram of the anode layer in Figure 5;

[0058] Figure 17 is a schematic diagram of another arrangement of pixel circuits in the display area of ​​at least one embodiment of the present disclosure;

[0059] Figure 18 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0060] Detailed Explanation

[0061] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0062] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0063] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0064] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0065] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0066] In this specification, "connection" can include "electrical connection." "Electrical connection" includes situations where components are connected together by elements that have some electrical function. There are no particular limitations on the "elements that have some electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0067] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0068] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0069] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0070] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0071] In this disclosure, "light transmittance" refers to the ability of light to pass through a medium, and is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0072] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0073] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0074] With the continuous development of display technology, cameras are often installed on display devices to meet shooting or facial recognition needs. For example, display devices with facial recognition capabilities are widely used in automotive products. For the same facial recognition sensor, the facial recognition distance required for automotive display devices is typically greater than that required for mobile phones. Therefore, automotive display devices need a sufficiently large facial recognition area to improve facial recognition performance. Furthermore, automotive display devices have high lifespan requirements (usually over 10,000 hours), so the pixel aperture ratio of the facial recognition area cannot be too low; otherwise, it will be difficult to meet the lifespan requirements. Therefore, ensuring a long lifespan while providing sufficient light transmission space is a problem that needs to be solved for the facial recognition area of ​​automotive display devices.

[0075] This embodiment provides a display substrate, including: a first display area. The first display area includes: a plurality of sub-display areas extending along a first direction and arranged along a second direction, and a plurality of light-transmitting areas located between adjacent sub-display areas. The first direction intersects the second direction, for example, the first direction is perpendicular to the second direction. The sub-display areas include: a substrate and a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on the substrate; at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements and configured to drive the at least one first light-emitting element to emit light. The orthographic projection of at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of at least one first light-emitting element on the substrate. The plurality of first pixel circuits include multiple rows of first pixel circuits. One row of first pixel circuits in the multiple rows of first pixel circuits is connected to a plurality of first signal lines extending along the first direction; the row of first pixel circuits includes at least a portion of the plurality of first pixel circuits arranged sequentially along the first direction. The distance between the orthographic projections of any two adjacent first signal lines among the plurality of first signal lines connected to a row of first pixel circuits on the substrate is less than the maximum length of a light-transmitting area along the second direction.

[0076] In some examples, the spacing between any two adjacent first signal lines among multiple first signal lines connected to a row of first pixel circuits in the orthographic projection onto the substrate can be greater than 0. In other words, the orthographic projections of the multiple first signal lines onto the substrate may not overlap.

[0077] In some examples, the light-transmitting area can be a regular shape. For instance, when a light-transmitting area is rectangular or rounded, its maximum length along the second direction can be the side length of the rectangle in the second direction; when a light-transmitting area is circular or elliptical, its maximum length along the second direction can be the diameter of the circle or ellipse along the second direction. In other examples, the light-transmitting area can be an irregular shape. For example, the edge of a light-transmitting area can have irregular arc segments or curve segments, in which case the maximum length along the second direction can refer to the vertical distance between the farthest edges of the light-transmitting area in the second direction.

[0078] The display substrate provided in this embodiment increases the size of the light-transmitting area by compressing the space occupied by the first pixel circuit and the multiple first signal lines connected to it in the second direction, thereby improving the light transmittance of the display substrate. For example, the display substrate of this embodiment can meet the light transmittance requirements of automotive display devices and help extend the service life of automotive display devices.

[0079] In some exemplary embodiments, the ratio of the maximum length of the orthographic projection of a row of first pixel circuits in a sub-display area onto the substrate along the second direction to the maximum length of a light-transmitting area along the second direction can be greater than or equal to 1, for example, approximately 1.4 or 1.5. In some examples, the maximum length of the orthographic projection of the pixel circuit onto the substrate along the second direction refers to the vertical distance between the farthest edges of the pixel circuits along the second direction. For example, the light-transmitting area between adjacent sub-display areas can be obtained by compressing the size of the first pixel circuit along the second direction. The scaling setting in this example can simultaneously ensure the display effect and light transmittance of the first display area.

[0080] In some exemplary embodiments, in the second direction, multiple first pixel circuits within adjacent sub-display areas are connected by multiple signal connection lines. The first display area may further include multiple trace areas located between adjacent sub-display areas and spaced apart from multiple light-transmitting areas along the first direction; the length of at least one trace area along the first direction may be greater than the line width of at least one signal connection line. This example demonstrates that signal transmission between the first pixel circuits of adjacent sub-display areas can be achieved by setting trace areas. In other examples, the traces connecting the first pixel circuits of adjacent sub-display areas can be made of a transparent conductive material, eliminating the need for adjacent light-transmitting areas to be separated by trace areas, which can help improve the light transmittance of the display substrate.

[0081] In some exemplary embodiments, the multiple first signal lines connected to a row of first pixel circuits may include: scan lines, emission control lines, and reset control lines. The scan lines, emission control lines, and reset control lines may be located in the same conductive layer. The emission control lines may be located between the scan lines and reset control lines in the second direction. The minimum distance between the emission control lines and reset control lines connected to the same row of first pixel circuits may be less than the minimum distance between the scan lines and emission control lines. This example arrangement can reduce the space occupied by the first pixel circuits along the second direction, which is beneficial for increasing the size of the light-transmitting area.

[0082] In some exemplary embodiments, the multiple first signal lines connected to a row of first pixel circuits may further include: a reference signal line, a first initial signal line, and a second initial signal line. The reference signal line and the first initial signal line may be located in the same conductive layer, and on the side of the conductive layer where the scan line is located that is away from the substrate. The second initial signal line may be located in a conductive layer away from the substrate from which the first initial signal line is located. This example arranges the multiple first signal lines connected to a row of first pixel circuits on three different conductive layers, which can help save space occupied by the first pixel circuit in the second direction.

[0083] In some exemplary embodiments, the first pixel circuit may include: a driving transistor, a capacitor, a first control transistor, and a second control transistor. The gate of the driving transistor and the first plate of the capacitor may be an integral structure. The second plate of the capacitor is connected to the second electrode of the first control transistor and the second electrode of the second control transistor; the first electrode of the first control transistor and the first electrode of the second control transistor are connected to a reference signal line; the gate of the first control transistor is connected to a reset control line, and the gate of the second control transistor is connected to a light emission control line. The gates of the first control transistor and the second control transistor are offset along a first direction. The reference signal line may be located in a conductive layer away from the substrate from the gates of the first and second control transistors; the orthographic projection of the reference signal line onto the substrate may be a zigzag line extending along the first direction, and located between the orthographic projections of the gates of the first and second control transistors onto the substrate. In this example, the reference signal line is interlaced between the gates of the first and second control transistors, which helps to compress the space occupied by the first pixel circuit in the second direction.

[0084] In some exemplary embodiments, the first pixel circuit may further include a first compensation transistor. The gate of the first compensation transistor and the scan line may be an integral structure. The first electrode of the first compensation transistor is connected to the second electrode of the driving transistor, and the second electrode of the first compensation transistor is connected to the gate of the driving transistor. The display substrate may further include a shielding electrode; the orthographic projection of the shielding electrode onto the substrate and the orthographic projection of the conductive region between the channel region of the active layer of the first compensation transistor onto the substrate at least partially overlap. This example utilizes a shielding electrode to shield the conductive region between the channel regions of the active layer of the first compensation transistor, which is beneficial for ensuring the performance of the first compensation transistor. In some examples, the shielding electrode may be an integral structure with the second plate of the capacitor. In other examples, the shielding electrode may be connected to a first power line.

[0085] In some exemplary embodiments, the display substrate may further include a shielding layer located on the side of the plurality of first pixel circuits near the substrate. The shielding layer may include interconnected first shielding structures and first shielding connection electrodes. The orthographic projection of the first shielding structure onto the substrate may cover the orthographic projection of the active layer of the transistors of the plurality of first pixel circuits onto the substrate. The first shielding connection electrode is connected to a first power line via a second shielding connection electrode located in a conductive layer away from the substrate, and the first power line is located in a conductive layer away from the substrate. This example configures the shielding layer to access the first power signal provided by the first power line, which can reduce the influence of the shielding layer on other signal lines.

[0086] In some exemplary embodiments, the first light-emitting element may include an anode, an organic light-emitting layer, and a cathode stacked sequentially. The orthographic projection of the anode of the first light-emitting element onto the substrate does not overlap with the orthographic projection of the connection hole between the first and second shielding connection electrodes, or the connection hole between the second shielding connection electrode and the first power line onto the substrate. This arrangement in the example ensures the flatness of the anode of the first light-emitting element.

[0087] In some exemplary embodiments, the corners of the conductive layer surrounding the light-transmitting area may be rounded. In some examples, the conductive layer surrounding the light-transmitting area may include a conductive layer that defines the shape of the edge of the light-transmitting area. For example, the conductive layer surrounding the light-transmitting area may include at least one of the following: a shielding layer, a cathode layer, or a second source / drain metal layer. The arrangement in this example can reduce light diffraction.

[0088] In some exemplary embodiments, the display substrate may further include a second display area located at least one side of the first display area. The second display area may include a substrate and a plurality of second pixel circuits and a plurality of second light-emitting elements disposed on the substrate; at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements and configured to drive the at least one second light-emitting element to emit light. The orthographic projection of at least one second pixel circuit onto the substrate at least partially overlaps with the orthographic projection of at least one second light-emitting element onto the substrate. The maximum length of the orthographic projection of the second pixel circuit onto the substrate along a second direction is greater than the maximum length of the orthographic projection of the first pixel circuit onto the substrate along the second direction. In some examples, the pixel density of the second display area may be the same as the pixel density of the first display area. This example can guarantee the display effect of the first and second display areas and is beneficial for improving the light transmittance of the first display area.

[0089] The following examples illustrate the solution of this embodiment.

[0090] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate may include a display area AA and a peripheral area BB located around the display area AA. The display area AA of the display substrate may include at least a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited thereto. In other examples, the display area of ​​the display substrate may only include the first display area, and the peripheral area may surround the first display area.

[0091] In some examples, as shown in Figure 1, the first display area A1 may be located at the top center of the display area AA. The second display area A2 may surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 may be located at other positions such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 may surround at least one side of the first display area A1.

[0092] In some examples, as shown in Figure 1, the display area AA can be a rectangle, such as a rounded rectangle. The first display area A1 can be a rectangle, a circle, or an ellipse. However, this embodiment is not limited to this. For example, the first display area A1 can be a semicircle, a pentagon, or other shapes.

[0093] In some examples, as shown in Figure 1, the first display area A1 can be a light-transmitting display area, or it can also be called an under-display camera (FDC) area or a face recognition area. The second display area A2 can be called a normal display area. For example, the orthographic projection of a sensor (such as a camera, infrared sensor, or other hardware) onto the display substrate can be located within the first display area A1 of the display substrate. In some examples, as shown in Figure 1, the first display area A1 is rectangular, and the size of the orthographic projection of the sensor onto the display substrate can be less than or equal to the size of the inscribed circle of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 can be circular, and the size of the orthographic projection of the sensor onto the display substrate can be less than or equal to the size of the first display area A1.

[0094] In some examples, the display area AA can be provided with multiple sub-pixels. At least one sub-pixel can include pixel circuitry and a light-emitting element. The pixel circuitry can be configured to drive the connected light-emitting element. For example, the pixel circuitry can be configured to provide drive current to drive the light-emitting element to emit light. The pixel circuitry can include multiple transistors and at least one capacitor. For example, the pixel circuitry can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0095] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The emitted color of the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0096] In some examples, as shown in FIG1, the first display area A1 may include a plurality of first pixel circuits 11 and a plurality of first light-emitting elements 13; the second display area A2 may include a plurality of second pixel circuits 12 and a plurality of second light-emitting elements 14. At least one first pixel circuit 11 may be connected to at least one first light-emitting element 13 and configured to drive the connected at least one first light-emitting element 13 to emit light. At least one second pixel circuit 12 may be connected to at least one second light-emitting element 14 and configured to drive the connected at least one second light-emitting element 14 to emit light. For example, a first pixel circuit 11 may be connected to a first light-emitting element 13 and configured to drive the first light-emitting element 13; a second pixel circuit 12 may be connected to a second light-emitting element 14 and configured to drive the second light-emitting element 14. In other examples, a first pixel circuit may drive a plurality of first light-emitting elements, or a second pixel circuit may drive a plurality of second light-emitting elements. In this example, the first display area A1 is driven to emit light by a pixel circuit built-in method. This eliminates the need for long conductive connecting lines to connect the first pixel circuit and the first light-emitting element, thus avoiding display defects in the first display area caused by conductive connecting lines. Furthermore, the pixel circuit built-in method does not limit the size of the first display area and can support the realization of a large-size first display area.

[0097] In some examples, the orthographic projection of at least one first pixel circuit 11 onto the substrate at least partially overlaps with the orthographic projection of at least one first light-emitting element 13 onto the substrate. The orthographic projection of at least one second pixel circuit 12 onto the substrate at least partially overlaps with the orthographic projection of at least one second light-emitting element 14 onto the substrate.

[0098] Figure 2 is a schematic diagram of the pixel circuit arrangement of a display area according to at least one embodiment of the present disclosure. The number of sub-display areas and first pixel circuits in Figure 2 is for illustrative purposes only. In some examples, as shown in Figure 2, the multiple pixel circuits of the display area may include: multiple first pixel circuits 11 located in the first display area A1 and multiple second pixel circuits 12 located in the second display area A2. The multiple first pixel circuits 11 in the first display area A1 and the multiple second pixel circuits 12 in the second display area A2 can be arranged in an array along the first direction D1 and the second direction D2. The multiple pixel circuits arranged along the first direction D1 form a row of pixel circuits, and the multiple pixel circuits arranged along the second direction D2 form a column of pixel circuits. For example, the first direction D1 may be perpendicular to the second direction D2.

[0099] In some examples, as shown in Figure 2, the first display area A1 may include: multiple sub-display areas A11, multiple wiring areas A12, and multiple light-transmitting areas A13. The multiple sub-display areas A11 may be arranged at intervals along the second direction D2. The sub-display areas A11 may be generally rectangular. The length of the sub-display area A11 along the first direction D1 may be greater than its length along the second direction D2. The sub-display area A11 may include: at least one row of first pixel circuits disposed on the substrate and multiple groups of first light-emitting elements (not shown) arranged along the first direction D1. A row of first pixel circuits may include multiple first pixel circuits 11 aligned along the first direction D1. Each group of first light-emitting elements may include multiple first light-emitting elements, for example, three first light-emitting elements emitting different colors of light. For example, the orthographic projection of the multiple groups of first light-emitting elements arranged along the first direction D1 onto the substrate may be located within the orthographic projection range of a row of first pixel circuits onto the substrate.

[0100] In some examples, multiple pixel circuits in the display area can be connected to multiple first signal lines extending along the first direction D1 (illustrated as first signal line 15 in Figure 2) and multiple second signal lines extending along the second direction D2 (illustrated as second signal line 16 in Figure 2). The multiple first signal lines may include multiple gate lines, such as scan lines, light emission control lines, and reset control lines. The multiple second signal lines may include multiple data lines and first power lines. The first pixel circuits 11 in adjacent sub-display areas A11 can be connected via signal connection lines 17 to achieve signal transmission in the second direction D2. The multiple signal connection lines 17 can be centrally arranged within the wiring area A12.

[0101] In some examples, a first signal line 15 passing through the first display area A1 can be connected to a row of first pixel circuits 11 in the sub-display area A11 and a corresponding row of second pixel circuits 12 in the second display area A2. A second signal line 16 passing through the first display area A1 can be connected to a column of first pixel circuits 11 in multiple sub-display areas A11 and a corresponding column of second pixel circuits 12 in the second display area A2. A signal connection line 17 can be used to connect the same column of first pixel circuits 11 in adjacent sub-display areas A11.

[0102] In some examples, the maximum length of the first pixel circuit 11 along the second direction D2 can be less than the maximum length of the second pixel circuit 12 along the second direction D2. A column of first pixel circuits 11 in the sub-display area A11 can be aligned with a column of second pixel circuits 12 in the second display area A2. In this way, the pixel density (PPI, Pixels Per Inch) of the first display area A1 and the pixel density of the second display area A2 can be guaranteed to be the same. Taking an automotive display device as an example, since the pixel density of automotive display devices is relatively low, usually around 200 PPI, reducing the pixel density of the first display area will affect the display effect. Therefore, ensuring that the pixel density of the first display area A1 and the second display area A2 are the same can guarantee the display effect of the first display area A1.

[0103] In some examples, multiple trace areas A12 and multiple light-transmitting areas A13 are provided between adjacent sub-display areas A11. The trace areas A12 and the light-transmitting areas A13 can be arranged alternately along a first direction D1. For example, a light-transmitting area A13 can be surrounded by two adjacent trace areas A12 and two adjacent sub-display areas A11. The light-transmitting area A13 can be approximately rectangular, and its length along the first direction D1 can be greater than its length along the second direction D2. In other examples, the traces within the trace areas A12 can be made of a transparent conductive material, allowing the light-transmitting areas A13 separated by the trace areas A12 to be connected, thereby improving light transmittance.

[0104] In this example, compared to the second pixel circuit 12, by compressing the first pixel circuit 11 along the second direction D2, the horizontal space (i.e., the space along the first direction D1) in the first display area A1 can be fully utilized, and the vertical space (i.e., the space along the second direction D2) can be freed up as a light-transmitting area, thereby improving the light transmittance of the first display area A1 while ensuring the pixel density of the first display area A1.

[0105] Figure 3 is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure. Figure 3 illustrates the structure of a sub-pixel of the display area as an example. Figure 3 also illustrates the pixel circuit of each sub-pixel, which includes a transistor 21 and a capacitor 22 as an example. The transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor.

[0106] In some examples, as shown in Figure 3, the display area of ​​the display substrate may include at least: a substrate 100, and a circuit structure layer 120, a light-emitting structure layer 130, and an encapsulation structure layer 140 sequentially disposed on the substrate 100. The circuit structure layer 120 may include at least pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 130 may include at least light-emitting elements for multiple sub-pixels. In other examples, a touch structure layer may be disposed on the side of the encapsulation structure layer away from the substrate 100 to integrate touch functionality.

[0107] In some examples, the circuit structure layer 120 of the display area may include: a shielding layer 200 disposed on the substrate 100, a semiconductor layer, a first conductive layer (also referred to as a first gate metal layer), a second conductive layer (also referred to as a second gate metal layer), a third conductive layer (also referred to as a first source / drain metal layer) and a fourth conductive layer (also referred to as a second source / drain metal layer). A first insulating layer (also called a buffer layer) 101 may be disposed between the shielding layer 200 and the semiconductor layer; a second insulating layer (also called a first gate insulating layer) 102 may be disposed between the semiconductor layer and the first conductive layer; a third insulating layer (also called a second gate insulating layer) 103 may be disposed between the first conductive layer and the second conductive layer; a fourth insulating layer (also called an interlayer insulating layer) 104 may be disposed between the second conductive layer and the third conductive layer; a fifth insulating layer (also called a passivation layer) 105 and a sixth insulating layer (also called a first planarization layer) 106 may be disposed between the third conductive layer and the fourth conductive layer, wherein the sixth insulating layer 106 may be located on the side of the fifth insulating layer 105 away from the substrate 100; and a seventh insulating layer (also called a second planarization layer) 107 may be disposed on the side of the fourth conductive layer away from the substrate 100. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be inorganic insulating layers, while the sixth insulating layer 106 and the seventh insulating layer 107 can be organic insulating layers. However, this embodiment is not limited to these limitations. In other examples, the fifth insulating layer may be omitted between the third and fourth conductive layers, and only the sixth insulating layer may be provided between the third and fourth conductive layers.

[0108] In some examples, as shown in FIG3, the semiconductor layer of the display area may include: an active layer 210 of the transistor 21 of the pixel circuit. The active layer 210 of the transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first conductive layer may include: a first gate 213 of the transistor 21 and a first electrode 221 of the capacitor 22. The orthographic projection of the first gate 213 of the transistor 21 onto the substrate 100 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 100. The second conductive layer may include: a second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 100 may at least partially overlap, for example, they may coincide.

[0109] In some examples, as shown in Figure 3, the third conductive layer of the display area may include a first source 211 and a first drain 212 of transistor 21. The first source 211 of transistor 21 may be electrically connected to the first region 2101 of active layer 210, and the first drain 212 may be electrically connected to the second region 2102 of first active layer 210. The fourth conductive layer may include at least a first anode transition electrode 451. The first anode transition electrode 451 may be electrically connected to the first drain 212 of transistor 21 of pixel circuit through vias formed in fifth insulating layer 105 and sixth insulating layer 106. In this example, the first anode transition electrode 451 can be used to achieve the electrical connection between pixel circuit and light-emitting element.

[0110] In some examples, as shown in Figure 3, the light-emitting structure layer 130 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on a seventh insulating layer 107 and electrically connected to a first anode adapter electrode 451 through a via formed in the seventh insulating layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the seventh insulating layer 107, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0111] In some examples, the organic light-emitting layer 132 of the light-emitting element may include at least one emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0112] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0113] In some examples, as shown in Figure 3, the encapsulation structure layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density, which can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display substrate and relieve stress on the first and third encapsulation layers 141 and 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0114] Figure 4A is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit in this example is illustrated using a 9T1C structure. As shown in Figure 4A, the pixel circuit of this example may include nine transistors (i.e., first transistor T1 to ninth transistor T9) and a capacitor C. The first transistor T1 may also be called a data writing transistor, the second transistor T2 may also be called a first compensation transistor, the third transistor T3 may also be called a driving transistor, the fourth transistor T4 may also be called a first reset transistor, the fifth transistor T5 may also be called a first control transistor, the sixth transistor T6 may also be called a second control transistor, the seventh transistor T7 may also be called a light-emitting control transistor, the eighth transistor T8 may also be called a second reset transistor, and the ninth transistor T9 may also be called a second compensation transistor.

[0115] In some examples, the first transistor T1 through the ninth transistor T9 of the pixel circuit can all be P-type transistors, which can be low-temperature polycrystalline silicon (LTPS) thin-film transistors. In other examples, multiple transistors in the pixel circuit can all be N-type transistors, which can be oxide thin-film transistors; or they can include both P-type and N-type transistors, which can be both LTPS and oxide thin-film transistors. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide semiconductor. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate allows for the utilization of the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0116] In some examples, the pixel circuit can be electrically connected to the scan line GL, the emission control line EM, the reset control line RST, the data line DL, the first initial signal line INIT1, the second initial signal line INIT2, the reference signal line REF, the first power line VDD, and the second power line VSS. The first power line VDD can be configured to provide a constant first power signal to the pixel circuit, and the second power line VSS can be configured to provide a constant second power signal to the pixel circuit, wherein the first power signal can be greater than the second power signal. The scan line GL can be configured to provide a scan signal to the pixel circuit. The emission control line EM can be configured to provide an emission control signal to the pixel circuit. The reset control line RST can be configured to provide a reset control signal to the pixel circuit. The first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit; the first and second initial signals can be different. The reference signal line REF can be configured to provide a reference signal to the pixel circuit.

[0117] In this disclosure, the conduction level signal includes the level signal that turns on the transistor. For example, the conduction level signal that turns on a P-type transistor is a low-level signal, and the conduction level signal that turns on an N-type transistor is a high-level signal.

[0118] In some examples, the first electrode of the light-emitting element EL is connected to the fourth node N4, and the second electrode of the light-emitting element EL is connected to the second power line VSS. The first electrode of the capacitor C is connected to the first node N1, and the second electrode of the capacitor C is connected to the second node N2.

[0119] In some examples, the gate of the first transistor T1 is connected to the scan line GL, the first terminal of the first transistor T1 is connected to the data line DL, and the second terminal of the first transistor T1 is connected to the second node N2. When a conduction level signal is applied to the scan line GL, the first transistor T1 transmits the data signal provided by the data line DL to the second node N2.

[0120] In some examples, the gate of the second transistor T2 is connected to the scan line GL, the first terminal of the second transistor T2 is connected to the third node N3, and the second terminal of the second transistor T2 is connected to the first node N1. When a conduction level signal is applied to the scan line GL, the second transistor T2 can turn on the first node N1 and the third node N3 to write the threshold voltage of the third transistor T3 into the first node N1.

[0121] In some examples, the gate of the third transistor T3 is connected to the first node N1, the first terminal of the third transistor T3 is connected to the first power supply line VDD, and the second terminal of the third transistor T3 is connected to the third node N3. The third transistor T3 can determine the magnitude of the drive signal between the first power supply line VDD and the second power supply line VSS based on the voltage difference between its gate and the first terminal.

[0122] In some examples, the gate of the fourth transistor T4 is connected to the reset control line RST, the first terminal of the fourth transistor T4 is connected to the first initial signal line INIT1, and the second terminal of the fourth transistor T4 is connected to the first node N1. When a conduction level signal is applied to the reset control line RST, the fourth transistor T4 transmits the first initial signal line provided by the first initial signal line INIT1 to the first node N1 to initialize the first node N1.

[0123] In some examples, the gate of the fifth transistor T5 is connected to the reset control line RST, the first terminal of the fifth transistor T5 is connected to the reference signal line REF, and the second terminal of the fifth transistor T5 is connected to the second node N2. When a conduction level signal is applied to the reset control line RST, the fifth transistor T5 transmits the reference signal provided by the reference signal line REF to the second node N2 to initialize the second node N2.

[0124] In some examples, the gate of the sixth transistor T6 is connected to the light-emitting control line EM, the first terminal of the sixth transistor T6 is connected to the reference signal line REF, and the second terminal of the sixth transistor T6 is connected to the second node N2. When a conduction level signal is applied to the light-emitting control line EM, the sixth transistor T6 transmits the reference signal provided by the reference signal line REF to the second node N2, so that the data signal written to the second node N2 is coupled to the first node N1 through the capacitor C.

[0125] In some examples, the gate of the seventh transistor T7 is connected to the light-emitting control line EM, the first terminal of the seventh transistor T7 is connected to the third node N3, and the second terminal of the seventh transistor T7 is connected to the fourth node N4. When a conduction level signal is applied to the light-emitting control line EM, the seventh transistor T7 conducts the third node N3 and the fourth node N4, thereby forming a transmission path for the drive signal between the first power line VDD and the second power line VSS, causing the light-emitting element EL to emit light.

[0126] In some examples, the gate of the eighth transistor T8 is connected to the reset control line RST, the first electrode of the eighth transistor T8 is connected to the second initial signal line INIT2, and the second electrode of the eighth transistor T8 is connected to the fourth node N4. When a conduction level signal is applied to the reset control line RST, the eighth transistor T8 transmits the second initial signal provided by the second initial signal line INIT2 to the fourth node N4 to initialize or release the accumulated charge in the first electrode of the light-emitting element EL.

[0127] In some examples, the gate of the ninth transistor T9 is connected to the light-emitting control line EM, the first terminal of the ninth transistor T9 is left floating, and the second terminal of the ninth transistor T9 is connected to the first node N1. The ninth transistor T9 can be equivalently represented as a MIS (metal-insulator-semiconductor) channel capacitor that varies with bias voltage, with one end of the capacitor being the gate and the other end being the source or drain. Because the ninth transistor T9 has an equivalent capacitance, when the second transistor T2 is turned off, the charge released by the equivalent capacitance between the gate and the second terminal of the second transistor T2 will be entirely or partially absorbed by the equivalent capacitance of the ninth transistor T9. This maintains the accuracy and stability of the threshold voltage written to the first node N1, thus achieving a better threshold voltage compensation effect.

[0128] In some examples, the first node N1 can be the connection point of the first electrode of capacitor C, the gate of the third transistor T3, the second electrode of the second transistor T2, and the second electrode of the ninth transistor T9. The second node N2 can be the connection point of the second electrode of capacitor C, the second electrode of the first transistor T1, the second electrode of the fifth transistor T5, and the second electrode of the sixth transistor T6. The third node N3 can be the connection point of the first electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the seventh transistor T7. The fourth node N4 can be the connection point of the second electrode of the seventh transistor T7, the second electrode of the eighth transistor T8, and the first electrode of the light-emitting element EL.

[0129] Figure 4B is an example of the timing diagram for the pixel circuit shown in Figure 4A. The operation of the pixel circuit shown in Figure 4A will be explained below. The explanation will take the example where all the transistors in the pixel circuit shown in Figure 4A are P-type transistors. In some examples, the operation of the pixel circuit may include the following stages.

[0130] In the first stage S1, the reset control line RST provides a low-level reset control signal, turning on the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8. The turned-on fourth transistor T4 transmits the first initial signal line INIT1 to the first node N1, initializing node N1; the turned-on fifth transistor T5 transmits the reference signal line REF to the second node N2, initializing node N2; the turned-on eighth transistor T8 transmits the second initial signal line INIT2 to the fourth node N4, initializing or releasing the accumulated charge in the first electrode of the light-emitting element EL. The scan line GL provides a high-level scan signal, and both the first transistor T1 and the second transistor T2 are turned off. The light-emitting control line EM provides a high-level light-emitting control signal, and all transistors T6, T7, and T9 are turned off.

[0131] In the second stage S2, the scan line GL provides a low-level scan signal, turning on the first transistor T1 and the second transistor T2. The turned-on first transistor T1 transmits the data signal provided by the data line DL to the second node N2, where the voltage is the data voltage Vdata. The turned-on second transistor T2 enables the first node N1 and the third node N3 to conduct, writing the threshold voltage of the third transistor T3 into the first node N1. The voltage of the first node N1 is Vdd + Vth, where Vdd is the voltage of the first power supply signal provided by the first power supply line VDD, and Vth is the threshold voltage of the third transistor T3. The reset control line RST provides a high-level reset control signal, turning off the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8. The light emission control line EM provides a high-level light emission control signal, turning off the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9.

[0132] In the third stage (S3), the reset control line RST provides a high-level reset control signal, the scan line GL provides a high-level scan signal, and the light emission control line EM provides a low-level light emission control signal. The sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are all turned on. The turned-on sixth transistor T6 transmits the reference signal provided by the reference signal line REF to the second node N2. Due to the bootstrap effect of capacitor C, the voltage change at the first node N1 is Vref + Vdd + Vth - Vdata, where Vref is the voltage of the reference signal. The equivalent capacitance of the ninth transistor T9 can absorb all or part of the charge released by the equivalent capacitance between the gate and the second electrode of the second transistor T2, thereby maintaining the potential stability of the first node N1. The drive current can be provided to the light-emitting element EL through the third transistor T3 and the seventh transistor T7.

[0133] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and first terminal. Since the voltage of the first node N1 is Vref + Vdd + Vth - Vdata, the driving current of the third transistor T3 is:

[0134] I = K × (Vgs - Vth) 2 =K×(Vref+Vdd+Vth-Vdata-Vdd-Vth) 2 = K×(Vref-Vdata) 2 .

[0135] Where K is a constant, Vgs is the voltage difference between the gate and the first terminal of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage, Vref is the voltage of the reference signal, and Vdd is the voltage of the first power supply signal.

[0136] The pixel circuit in this embodiment can eliminate the influence of the threshold voltage of the driving transistor on the driving signal, thereby ensuring uniform display brightness and improving the display effect; moreover, it can help improve the compensation effect of the threshold voltage of the driving transistor, thereby helping to improve display performance.

[0137] Figures 5 and 6 are partial top views of the first display area according to at least one embodiment of the present disclosure. Figure 5 mainly illustrates two rows (row i and row i+1, where i is a positive integer) and six columns (columns j to j+5, where j is a positive integer) of first pixel circuits and corresponding connected first light-emitting elements. The first pixel circuit in row i is located in one sub-display area, and the first pixel circuit in row i+1 is located in another sub-display area. A light-transmitting area A13 and a wiring area A12 are provided between adjacent sub-display areas. The light-transmitting area A13 and the wiring area A12 can be arranged alternately along the first direction D1. Figure 6 is a partial schematic diagram of the first display area shown in Figure 5. Figure 6 mainly illustrates one row (e.g., row i) and three columns (e.g., columns j to j+2) of first pixel circuits and corresponding connected first light-emitting elements.

[0138] In some examples, as shown in Figures 5 and 6, a plurality of first light-emitting elements in a sub-display area may include: a plurality of first light-emitting elements EL1 emitting a first color light, a plurality of first light-emitting elements EL2 emitting a second color light, and a plurality of first light-emitting elements EL3 emitting a third color light. For example, the first color light may be red, the second color light may be green, and the third color light may be blue. The first light-emitting element EL1 may be a red light-emitting element, the first light-emitting element EL2 may be a green light-emitting element, and the third light-emitting element EL3 may be a blue light-emitting element. In this example, a group of first light-emitting elements may include one first light-emitting element EL1, one first light-emitting element EL2, and one first light-emitting element EL3. The first light-emitting elements EL1 and EL2 within a group of first light-emitting elements may be aligned along the second direction D2, and the first light-emitting element EL3 may be located on the same side of the first light-emitting elements EL1 and EL2 in the first direction D1.

[0139] In some examples, the orthographic projections of the first light-emitting elements EL1, EL2, and EL3 onto the substrate may partially overlap with the orthographic projections of the connected first pixel circuits onto the substrate. For instance, the first pixel circuit in the i-th row and j-th column is connected to a first light-emitting element EL2 and overlaps with the orthographic projection of that first light-emitting element EL2 onto the substrate; the first pixel circuit in the i-th row and (j+1)-th column is connected to a first light-emitting element EL3 and overlaps with the orthographic projection of that first light-emitting element EL3 onto the substrate; the first pixel circuit in the i-th row and (j+2)-th column is connected to a first light-emitting element EL1 and overlaps with the orthographic projection of that first light-emitting element EL1 onto the substrate; and the first pixel circuit in the i-th row and (j+3)-th column is connected to another first light-emitting element EL2. The first light-emitting elements EL1 connected to the first pixel circuit in the i-th row and (j+2)-th column and EL2 connected to the first pixel circuit in the i-th row and (j+3)-th column are aligned in the second direction D2.

[0140] The structure of a display substrate is illustrated below using an example of its fabrication process. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process.

[0141] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are at substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. The phrase "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The phrase "the shape of A" in this disclosure refers to the shape of the orthographic projection of A onto the substrate.

[0142] The following description uses a first pixel circuit within a sub-display area of ​​the first display area as an example to illustrate the film layers of the circuit structure. The connection relationship between the nine transistors and capacitors in the first pixel circuit can be seen in the equivalent circuit diagram shown in Figure 4A. The film layer sequence of the display substrate in this example can be seen in the structure shown in Figure 3, where capacitor 22 in Figure 3 can be equivalent to capacitor C in this example, and transistor 21 in Figure 3 can be equivalent to the seventh or eighth transistor in this example.

[0143] In some examples, the fabrication process of the display substrate may include the following operations.

[0144] (1) Providing a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, a rigid substrate can be, but is not limited to, one or more of glass and quartz; a flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0145] (2) Forming a shielding layer. In some examples, a shielding film is deposited on the substrate, and the shielding film is patterned by a patterning process to form a shielding layer disposed on the substrate. In some examples, the shielding layer may also be referred to as a bottom shielding metal (BSM).

[0146] Figure 7A is a schematic diagram of the first display area after the shielding layer is formed in Figure 5. Figure 7B is a schematic diagram of the first display area after the shielding layer is formed in Figure 6. In some examples, as shown in Figures 7A and 7B, the shielding layer of the first display area may include: a first shielding structure 201 extending along a first direction D1 and a second shielding structure 202 extending along a second direction D2. The first shielding structure 201 may be located within a sub-display area, and the second shielding structure 202 may be located within a wiring area. The orthographic projection of the shielding layer onto the substrate does not overlap with the light-transmitting area. The light-transmitting area may be located between adjacent second shielding structures 202 along the first direction D1, and between adjacent first shielding structures 201 along the second direction D2.

[0147] In some examples, adjacent first occlusion structures 201 can be connected by multiple second occlusion structures 202. Multiple first occlusion structures 201 and multiple second occlusion structures 202 can be connected to form a mesh structure. Multiple first occlusion structures 201 and multiple second occlusion structures 202 can be a single integrated structure.

[0148] In some examples, the orthographic projection of the second blocking structure 202 onto the substrate can be a strip extending along the second direction D2. The first blocking structure 201 can have multiple sets of cutouts arranged along the first direction D1, each set of cutouts including a first cutout 2011, a second cutout 2012, a third cutout 2013, a fourth cutout 2014, and a fifth cutout 2015. Each set of cutouts can correspond to a setting area of ​​a first pixel circuit.

[0149] In some examples, the first cutout portion 2011 and the third cutout portion 2013 can be arranged along the second direction D2, and the second cutout portion 2012, the fourth cutout portion 2014 and the fifth cutout portion 2015 can be arranged along the second direction D2 and are located on the same side of the first cutout portion 2011 and the third cutout portion 2013 along the first direction D1.

[0150] In some examples, the orthographic projection of the first cutout portion 2011 onto the substrate can be approximately a rectangle extending along the first direction D1; the orthographic projection of the second cutout portion 2012 onto the substrate can be approximately a rectangle extending along the second direction D2; the orthographic projection of the third cutout portion 2013 onto the substrate can be approximately L-shaped; the orthographic projection of the fourth cutout portion 2014 onto the substrate can be approximately rectangular, such as a rounded rectangle; and the fifth cutout portion 2015 can extend along the first direction D1, and its orthographic projection onto the substrate can be approximately P-shaped.

[0151] In some examples, the shielding layer may further include a plurality of first shielding connection electrodes 203 connected to the first shielding structure 201. The plurality of first shielding connection electrodes 203 and the first shielding structure 201 may be an integral structure. The first shielding connection electrodes 203 may be located on one side of the first shielding structure 201 along the second direction D2, and may be adjacent to the second cutout portion 2012 in the second direction D2. The orthographic projection of the first shielding connection electrode 201 onto the substrate may be approximately rectangular, such as a rounded rectangle. The first shielding connection electrodes 203 may be located between two adjacent second shielding structures 202 in the first direction D1.

[0152] This example demonstrates how setting a shielding layer can provide light-shielding for multiple transistors in the first pixel circuit. Furthermore, by setting a cutout in the shielding layer, it avoids the parasitic capacitance between large areas of metal and other metal film layers, which would affect the display effect.

[0153] In some examples, the shielding layer can be connected to a first power line located in the second source / drain metal layer via a first shielding connection electrode 203 to access a first power signal. In other examples, the shielding layer can extend to the surrounding area and connect to a first power supply line in the surrounding area to access a first power signal, thereby avoiding interference with other signal traces.

[0154] (3) Forming a semiconductor layer. In some examples, a first insulating film and a semiconductor film are deposited on the substrate on which the aforementioned pattern is formed, and the semiconductor film is patterned by a patterning process to form a first insulating layer and a semiconductor layer disposed on the substrate. In some examples, the material of the semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, or oxide semiconductor (e.g., IGZO).

[0155] Figure 8A is a schematic diagram of the first display area after the semiconductor layer is formed in Figure 5. Figure 8B is a schematic diagram of the shielding layer and semiconductor layer in Figure 6. Figure 8C is a schematic diagram of the semiconductor layer in Figure 8B.

[0156] In some examples, as shown in Figures 8A to 8C, the semiconductor layer of the first display area may include: an active layer of multiple transistors of multiple first pixel circuits, such as an active layer T10 of the first transistor, an active layer T20 of the second transistor, an active layer T30 of the third transistor, an active layer T40 of the fourth transistor, an active layer T50 of the fifth transistor, an active layer T60 of the sixth transistor, an active layer T70 of the seventh transistor, an active layer T80 of the eighth transistor, and an active layer T90 of the ninth transistor.

[0157] In some examples, the active layers T20 of the second transistor, T30 of the third transistor, T70 of the seventh transistor, and T80 of the eighth transistor in the same first pixel circuit can be a single integrated structure. The active layers T40 of the fourth transistor and T90 of the ninth transistor in the same first pixel circuit can be a single integrated structure, and the orthographic projection of this integrated structure onto the substrate can be approximately a cane shape extending along the second direction D2. The active layers T50 of the fifth transistor and T60 of the sixth transistor in the same first pixel circuit can be a single integrated structure, and the orthographic projection of this integrated structure onto the substrate can be approximately a rectangular ring.

[0158] In some examples, the integrated structure of the active layer T40 of the fourth transistor and the active layer T90 of the ninth transistor can be located in the first direction D1 between the integrated structure of the active layer T50 of the fifth transistor and the active layer T60 of the sixth transistor and the integrated structure of the active layer T70 of the seventh transistor and the active layer T80 of the eighth transistor.

[0159] In some examples, the active layers T50 of the fifth transistor, T60 of the sixth transistor, T40 of the fourth transistor, T90 of the ninth transistor, T70 of the seventh transistor, and T80 of the eighth transistor of a first pixel circuit can be located on the same side of the active layer T30 of the third transistor of the same first pixel circuit along the second direction D2; the active layers T10 of the first transistor and T20 of the second transistor can be located on the same side of the active layer T30 of the third transistor of the same first pixel circuit along the second direction D2. The active layers T10 of the first transistor and T20 of the second transistor can be adjacent in the first direction D1.

[0160] In some examples, the orthographic projection of the active layer T10 of the first transistor onto the substrate can be approximately L-shaped; the orthographic projection of the active layer T20 of the second transistor onto the substrate can be approximately L-shaped; and the orthographic projection of the active layer T30 of the third transistor onto the substrate can be approximately U-shaped. The orthographic projections of the active layers T70 of the seventh transistor and T80 of the eighth transistor onto the substrate can be approximately strip-shaped extending along the second direction D2.

[0161] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The semiconductor layer material may, for example, include polysilicon. The channel region may be undoped and possess semiconductor properties. The first and second regions may be doped regions on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0162] In some examples, the active layer T20 of the second transistor may include: a first channel region T200a, a second channel region T200b, a first region T20-1, a second region T20-2, and a third region (i.e., the conductive region between the aforementioned channel regions of the active layer of the second transistor) T20-3. The third region T20-3 of the active layer T20 of the second transistor may be located between the first channel region T200a and the second channel region T200b; the second region T20-2 is located on the side of the first channel region T200a away from the third region T20-3, and the first region T20-1 is located on the side of the second channel region T200b away from the third region T20-3. The first channel region T200a and the second region T20-2 may extend along a first direction D1, the second channel region T200b and the first region T20-1 may extend along a second direction D2, and the orthographic projection of the third region T20-3 onto the substrate may be approximately L-shaped.

[0163] In some examples, the first region T10-1 and the second region T10-2 of the active layer T10 of the first transistor, the second region T20-2 of the active layer T20 of the second transistor, the first region T30-1 of the active layer T30 of the third transistor, the first region T40-1 of the active layer T40 of the fourth transistor, and the first region T80-1 of the active layer T80 of the eighth transistor can be set individually.

[0164] In some examples, the first region T20-1 of the active layer T20 of the second transistor can simultaneously serve as the second region of the active layer T30 of the third transistor and the first region of the active layer T70 of the seventh transistor. The second region T80-2 of the active layer T80 of the eighth transistor can simultaneously serve as the second region of the active layer T70 of the seventh transistor. The second region T40-2 of the active layer T40 of the fourth transistor can simultaneously serve as the second region of the active layer T90 of the ninth transistor. The first region T50-1 of the active layer T50 of the fifth transistor can simultaneously serve as the first region T60-1 of the active layer T60 of the sixth transistor. The second region T50-2 of the active layer T50 of the fifth transistor can simultaneously serve as the second region of the active layer T60 of the sixth transistor.

[0165] In some examples, as shown in Figures 7A to 8B, the orthographic projection of the first occlusion structure 201 onto the substrate can cover the orthographic projection of the active layer of the nine transistors of the first pixel circuit onto the substrate. The orthographic projection of the first cutout portion 2011 of the first cutout structure 201 onto the substrate can be located on the side of the integrated structure of the active layers of the fifth transistor T5 and the sixth transistor T6 away from the active layer T30 of the third transistor along the second direction D2; the orthographic projection of the second cutout portion 2012 onto the substrate can be located between the active layer T40 of the fourth transistor and the active layer T80 of the eighth transistor; the orthographic projection of the third cutout portion 2013 onto the substrate can be located between the active layer T30 of the third transistor and the active layer T60 of the sixth transistor; the orthographic projection of the fourth cutout portion 2014 onto the substrate can be located between the active layer T90 of the ninth transistor and the active layer T70 of the seventh transistor; the orthographic projection of the fifth cutout portion 2015 onto the substrate can be surrounded by the active layer T30 of the third transistor, the active layer T10 of the first transistor, and the active layer T20 of the second transistor. This example demonstrates how setting a shielding layer to block the active layer of the transistor located in the semiconductor layer can prevent external light from affecting the transistors in the pixel circuit, thereby ensuring the performance of the transistors.

[0166] (4) Forming a first conductive layer. In some examples, a second insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed, and the first conductive film is patterned by a patterning process to form a second insulating layer and a first conductive layer disposed on the second insulating layer.

[0167] Figure 9A is a schematic diagram of the first display area after the formation of the first conductive layer in Figure 5. Figure 9B is a schematic diagram of the semiconductor layer and the first conductive layer in Figure 6. Figure 9C is a schematic diagram of the first conductive layer in Figure 9B.

[0168] In some examples, as shown in Figures 9A to 9C, the first conductive layer of the first display area may include: multiple scan lines (e.g., including scan lines GL(i) and GL(i+1)), multiple light emission control lines (e.g., including light emission control lines EM(i) and EM(i+1)), multiple reset control lines (e.g., including reset control lines RST(i) and RST(i+1)), and gates of transistors of multiple first pixel circuits (e.g., including: gate T11 of the first transistor T1, the first gate T21a and the second gate T21b of the second transistor T2, the gate T31 of the third transistor T3, the first gate T41a of the fourth transistor T4, the gate T51 of the fifth transistor T5, and the gate T61 of the sixth transistor T6).

[0169] In some examples, scan lines GL(i) and GL(i+1), light emission control lines EM(i) and EM(i+1), and reset control lines RST(i) and RST(i+1) can all be straight lines extending along the first direction D1. Within a sub-display area, the reset control line RST(i), light emission control line EM(i), and scan line GL(i) can be arranged sequentially along the second direction D2. The minimum distance L1 between the reset control line RST(i) and the light emission control line EM(i) in the second direction D2 can be less than the minimum distance L2 between the light emission control line EM(i) and the scan line GL(i) in the second direction D2.

[0170] In some examples, the gate T11 of the first transistor T1, the first gate T21a and the second gate T21b of the second transistor T2 in the first pixel circuit of the i-th row are integrally formed with the scan line GL(i). The gate T11 of the first transistor T1, the first gate T21a and the second gate T21b of the second transistor T2 can all be located on the side of the scan line GL(i) close to the gate T31 of the third transistor T3. The orthographic projection of the gate T11 of the first transistor T1 onto the substrate can be a strip extending along the second direction D2; the orthographic projection of the first gate T21a of the second transistor T2 onto the substrate can be a strip extending along the second direction D2; the orthographic projection of the second gate T21b of the second transistor T2 onto the substrate can be approximately L-shaped. The orthogonal projection of the first gate T21a of the second transistor T2 onto the substrate can cover the orthogonal projection of the first channel T200a of the active layer T20 of the second transistor T2 onto the substrate; the orthogonal projection of the second gate T21b of the second transistor T2 onto the substrate can cover the orthogonal projection of the second channel T200b of the active layer T20 of the second transistor T2 onto the substrate.

[0171] In some examples, the gate T31 of the third transistor T3 can be located between the light-emitting control line EM(i) and the scan line GL(i). The orthographic projection of the gate T31 of the third transistor T3 onto the substrate can be approximately rectangular, such as a rounded rectangle. The gate T31 of the third transistor T3 can also serve as the first plate C01 of the capacitor, and the first plate C01 of the capacitor can serve as the first electrode of the capacitor.

[0172] In some examples, the gate T51 of the fifth transistor T5 and the first gate T41a of the fourth transistor T4 in the first pixel circuit of the i-th row are integrated with the reset control line RST(i). The gate T51 of the fifth transistor T5 and the first gate T41a of the fourth transistor T4 can both be located on the side of the reset control line RST(i) closer to the light emission control line EM(i). The orthographic projection of the gate T51 of the fifth transistor T5 onto the substrate can be a strip extending along the second direction D2. The orthographic projection of the first gate T41a of the fourth transistor T4 onto the substrate can be approximately L-shaped. The overlapping portion of the reset control line RST(i) and the active layer T40 of the fourth transistor T4 can serve as the second gate of the fourth transistor T4; the overlapping portion of the reset control line RST(i) and the active layer T80 of the eighth transistor T8 can serve as the gate of the eighth transistor T8.

[0173] In some examples, the gate T61 of the sixth transistor T6 in the first pixel circuit of the i-th row is integrated with the light-emitting control line EM(i). The gate T61 of the sixth transistor T6 can be located on the side of the light-emitting control line EM(i) near the reset control line RST(i). The orthogonal projection of the gate T61 of the sixth transistor T6 onto the substrate can be a strip extending along the second direction D2. The gate T61 of the sixth transistor T6 and the gate T51 of the fifth transistor T5 are staggered in the second direction D2. The gate T61 of the sixth transistor T6 is located on the side of the gate T51 of the fifth transistor T5 near the first gate T41a of the fourth transistor T4 in the second direction D2. The overlapping portion of the light-emitting control line EM(i) and the active layer T70 of the seventh transistor T7 can serve as the gate of the seventh transistor T7; the overlapping portion of the light-emitting control line EM(i) and the active layer T90 of the ninth transistor T9 can serve as the gate of the ninth transistor T9.

[0174] This example demonstrates how setting the gates of the fifth transistor T5 and the sixth transistor T6 to be staggered in the second direction D2 can reserve routing space for the subsequent conductive layer formation, which is beneficial for compressing the size of the first pixel circuit along the second direction.

[0175] (5) Forming a second conductive layer. In some examples, a third insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed, and the second conductive film is patterned by a patterning process to form a third insulating layer and a second conductive layer disposed on the third insulating layer.

[0176] Figure 10A is a schematic diagram of the first display area after the formation of the second conductive layer in Figure 5. Figure 10B is a schematic diagram of the semiconductor layer, the first conductive layer, and the second conductive layer in Figure 6. Figure 10C is a schematic diagram of the second conductive layer in Figure 10B.

[0177] In some examples, as shown in Figures 10A to 10C, the second conductive layer of the first display area may include: multiple reference signal lines (e.g., including reference signal lines REF(i) and REF(i+1)), multiple first initial signal lines (e.g., including first initial signal lines INIT1(i) and INIT1(i+1)), the second plate CO2 of the capacitors of multiple first pixel circuits, and multiple shielding electrodes 25.

[0178] In some examples, the second plate C02 of the capacitor in the first pixel circuit of the i-th row can be located on the side of the reference signal line REF(i) away from the first initial connection segment 26 in the second direction D2. The orthographic projection of the second plate C02 of the capacitor onto the substrate can be approximately rectangular, such as a rounded rectangle. The orthographic projection of the second plate C02 of the capacitor onto the substrate can at least partially overlap with the orthographic projection of the first plate C01 of the capacitor onto the substrate. The second plate C02 of the capacitor can serve as the second electrode of the capacitor. The second plate C02 can have a plate cutout CK, the orthographic projection of the plate cutout CK onto the substrate can be approximately a rounded rectangle, and can be located on the upper left side of the second plate C02. The plate cutout CK can expose the third insulating layer covering the first plate C01 of the capacitor, and the orthographic projection of the plate cutout CK onto the substrate can be within the orthographic projection range of the first plate C01 of the capacitor onto the substrate.

[0179] In some examples, the second plate C02 of a capacitor and a shielding electrode 25 can be an integral structure. The shielding electrode 25 can be located at the lower right corner of the second plate C02 of the capacitor. The orthographic projection of the shielding electrode 25 onto the substrate can be approximately rectangular. The orthographic projection of the shielding electrode 25 onto the substrate can be adjacent to the orthographic projections of the first gate T21a and the third gate T21b of the second transistor T2 onto the substrate. The orthographic projection of the shielding electrode 25 onto the substrate can at least partially overlap with the orthographic projection of the third region T20-3 of the active layer T20 of the second transistor T2 onto the substrate. For example, the orthographic projection of the shielding electrode 25 onto the substrate can partially cover the orthographic projection of the third region T20-3 of the active layer T20 of the second transistor T2 onto the substrate. In this example, since the distance between the first gate and the second gate of the second transistor is increased, using the shielding electrode connected to the second plate of the capacitor to shield the third region of the active layer of the second transistor T2 can effectively shield the second transistor from interference, which is beneficial to ensuring the performance of the second transistor.

[0180] In some examples, the first initial signal line can be formed by connecting multiple first initial connection segments 26 aligned along the first direction D1. The orthographic projection of the first initial connection segment 26 onto the substrate can be a straight line extending along the first direction D1. For example, the orthographic projection of the first region T40-1 of the active layer T40 of the fourth transistor T4 in the i-th row of the first pixel circuit onto the substrate can be located between the orthographic projections of two adjacent first initial connection segments 26 onto the substrate. The first region T40-1 of the active layer of the fourth transistor in the i-th row of the first pixel circuit can be connected to the two adjacent first initial connection segments 26 through the connection electrode located in the third conductive layer, thereby providing the first initial signal to the fourth transistor.

[0181] In some examples, the orthographic projections of reference signal lines REF(i) and REF(i+1) onto the substrate can be zigzag lines extending along the first direction D1. The orthographic projection of reference signal line REF(i) onto the substrate can be located between the gate T51 of the fifth transistor T5 and the gate T61 of the sixth transistor T6 in the i-th row of the first pixel circuit. The orthographic projection of reference signal line REF(i) onto the substrate may not overlap with the orthographic projections of the gate T51 of the fifth transistor T5 and the gate T61 of the sixth transistor T6 onto the substrate. For example, reference signal line REF(i) may include a reference straight section 271 and a reference bent section 272. The reference straight section 271 and the reference bent section 272 can be connected at intervals along the first direction D1. The orthographic projection of the reference bent section 272 onto the substrate can be located on the side of the gate T61 of the sixth transistor T6 away from the light-emitting control line EM(i). The length of a single reference straight section 271 along the first direction D1 can be greater than the length of a single reference bent section 272 along the first direction D1. In this example, the reference signal lines are interspersed in the gaps between the orthographic projections of the first conductive layer onto the substrate, which can help to compress the size of the first pixel circuit along the second direction.

[0182] (6) Forming a fourth insulating layer. In some examples, a fourth insulating film is deposited on the substrate on which the aforementioned structure is formed, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer.

[0183] Figure 11A is a schematic diagram of the first display area after the fourth insulating layer is formed in Figure 5. Figure 11B is a schematic diagram of the first display area after the fourth insulating layer is formed in Figure 6.

[0184] In some examples, as shown in Figures 11A and 11B, the fourth insulating layer of the first display area can be provided with multiple vias, for example, including: first via V1 to sixteenth via V16. The fourth, third, and second insulating layers within the first via V1 to tenth via V10 can be removed, exposing a portion of the surface of the semiconductor layer. The fourth and third insulating layers within the eleventh via V11 can be removed, exposing a portion of the surface of the first conductive layer. The fourth insulating layer within the twelfth via V12 to fifteenth via V15 can be removed, exposing a portion of the surface of the second conductive layer. The fourth, third, second, and first insulating layers within the sixteenth via V16 can be removed, exposing a portion of the surface of the shielding layer. The orthographic projection of a sixteenth via V16 onto the substrate can lie within the orthographic projection range of a first shielding connection electrode 203 onto the substrate, exposing the surface of the first shielding connection electrode 203 away from the substrate.

[0185] In some examples, the multiple vias formed in the fourth insulating layer can be fabricated using multiple patterning processes. For instance, the first via V1 to the fifteenth via V15 can be formed using the same patterning process, while the sixteenth via V16 can be formed using a different patterning process. This embodiment is not limited to this.

[0186] (7) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate on which the aforementioned structure is formed, and the third conductive film is patterned by a patterning process to form a third conductive layer disposed on the fourth insulating layer.

[0187] Figure 12A is a schematic diagram of the first display area after the formation of the third conductive layer in Figure 5. Figure 12B is a schematic diagram of the first display area after the formation of the third conductive layer in Figure 6. Figure 12C is a schematic diagram of the third conductive layer in Figure 12B.

[0188] In some examples, as shown in Figures 12A to 12C, the third conductive layer of the first display area may include: a plurality of connection electrodes (e.g., including first connection electrodes 411a, 411b and 411c, second connection electrodes 412 to seventh connection electrodes 417, and second shielding connection electrode 204), a plurality of second initial signal lines (e.g., including second initial signal lines INIT2(i) and INIT2(i+1)), and a plurality of first data connection lines (e.g., including first data connection lines 421a, 421b and 421c).

[0189] In some examples, the orthographic projections of the first connecting electrodes 411a, 411b, and 411c onto the substrate can be approximately gourd-shaped. The first connecting electrode 411a can be connected to the first region of the active layer of the first transistor in the first pixel circuit of the i-th row and j-th column via a fifth via V5; the first connecting electrode 411b can be connected to the first region of the active layer of the first transistor in the first pixel circuit of the i-th row and j+1-th column via another fifth via V5; and the first connecting electrode 411c can be connected to the first region of the active layer of the first transistor in the first pixel circuit of the i-th row and j+2-th column via another fifth via V5.

[0190] In some examples, the first connecting electrode 411a and a first data connection line 421a can be an integral structure, the first connecting electrode 411b and a first data connection line 421b can be an integral structure, and the first connecting electrode 411c and a first data connection line 421c can be an integral structure. The orthographic projection of the first data connection line 421a onto the substrate can be approximately a straight line extending along the second direction Y; the orthographic projections of the first data connection lines 421b and 421c onto the substrate can be approximately U-shaped. Within a trace area, the first data connection lines 421c, 421a, and 421b can be arranged along the first direction D1, with the first data connection line 421a located between the first data connection lines 421b and 421c. For example, the first data connection line 421c connected to the first pixel circuit in row i-j-1, the first data connection line 421a connected to the first pixel circuit in row i-j-1, and the first data connection line 421b connected to the first pixel circuit in row i-j+1 can be located in the same routing area; the first data connection line 421c connected to the first pixel circuit in row i-j+2, the first data connection line connected to the first pixel circuit in row i-j+3, and the first data connection line connected to the first pixel circuit in row i-j+4 can be located in the same routing area. In some examples, within the routing area, the orthographic projection of the second shielding structure 202 of the shielding layer onto the substrate can cover the orthographic projection of the straight line segments of the three first data connection lines extending along the second direction D2 onto the substrate.

[0191] In some examples, the second connection electrode 412 can be located between the fourth connection electrode 414 and the third connection electrode 413 in the first direction D1, and the orthographic projection of the second connection electrode 412 onto the substrate can be approximately a broken line extending along the second direction D2. The first end of the second connection electrode 412 can be connected to the second region T10-2 of the active layer T10 of the first transistor through the sixth via V6, and the second end of the second connection electrode 412 can be connected to the second region T50-2 of the active layer T50 of the fifth transistor through the third via V3. The middle part of the second connection electrode 412 can be connected to the second plate C02 of the capacitor through the fifteenth via V15. Since the second region T50-2 of the active layer of the fifth transistor can also serve as the second region of the active layer of the sixth transistor, the second connection electrode 412 can serve as the second node N2, realizing the electrical connection between the second electrode of the fifth transistor, the second electrode of the sixth transistor, the second plate of the capacitor, and the second electrode of the first transistor.

[0192] In some examples, the third connection electrode 413 may be located between the second connection electrode 412 and the fifth connection electrode 415 in the first direction D1. The orthographic projection of the third connection electrode 413 onto the substrate may be approximately a broken line extending along the second direction D2. The first end of the third connection electrode 413 may be connected to the first region T20-1 of the active layer of the second transistor through the seventh via V7, the second end of the third connection electrode 413 may be connected to the second region T40-2 of the active layer of the fourth transistor through the eighth via V8, and the middle portion of the third connection electrode 413 may be connected to the gate T31 of the third transistor through the eleventh via V11. Since the second region T40-2 of the active layer of the fourth transistor can also serve as the second region of the active layer of the ninth transistor, and the gate of the third transistor can also serve as the first plate of the capacitor, the third connection electrode 413 can serve as the first node N1, realizing the electrical connection between the gate of the third transistor, the first plate of the capacitor, the second electrode of the fourth transistor, and the second electrode of the ninth transistor.

[0193] In some examples, the fourth connection electrode 414 may be located on the side of the second connection electrode 412 away from the third connection electrode 413 in the first direction D1. The orthographic projection of the fourth connection electrode 414 onto the substrate may be approximately rectangular. The fourth connection electrode 414 may be connected to the first region T30-1 of the active layer of the third transistor via the fourth via V4. The fourth connection electrode 414 may be connected to the subsequently formed first power line 51.

[0194] In some examples, the fifth connection electrode 415 may be located on the side of the third connection electrode 413 away from the second connection electrode 412 in the first direction D1. The orthographic projection of the fifth connection electrode 415 onto the substrate may be approximately rectangular. The fifth connection electrode 415 may be connected to the second region T80-2 of the active layer of the eighth transistor via the ninth via V9. Since the second region T80-2 of the active layer of the eighth transistor can also serve as the second region of the active layer of the seventh transistor, the fifth connection electrode 415 may serve as the second electrode of both the seventh and eighth transistors. The fifth connection electrode 415 may be connected to the subsequently formed first anode connection electrode.

[0195] In some examples, the sixth connection electrode 416 may be located on the side of the fourth connection electrode 414 away from the first connection electrode 411a in the second direction D2. The orthographic projection of the sixth connection electrode 416 onto the substrate may be approximately rectangular. The sixth connection electrode 416 can be connected to the first region T50-1 of the active layer of the fifth transistor through the second via V2, and can also be connected to the reference signal line REF(i) through the fourteenth via V14. Since the first region T50-1 of the active layer of the fifth transistor can also serve as the first region of the active layer of the sixth transistor, the sixth connection electrode 416 can realize the electrical connection between the reference signal line REF(i) and the first electrodes of both the fifth and sixth transistors.

[0196] In some examples, the seventh connection electrode 417 may be located on the side of the second initial signal line INIT2(i) away from the second connection electrode 412 in the second direction D2. The orthographic projection of the seventh connection electrode 417 onto the substrate may be approximately a strip extending along the first direction D1. The seventh connection electrode 417 may be connected to the first region T40-1 of the active layer of the fourth transistor via the first via V1, to a first initial connection segment 26 via the twelfth via V12, and to another first initial connection segment 26 via the thirteenth via V13. By connecting the adjacent first initial connection segments 26 and the first region of the active layer of the fourth transistor, the seventh connection electrode 417 enables the transmission of the first initial signal along the first direction D1.

[0197] In some examples, the orthographic projections of the second initial signal lines INIT2(i) and INIT2(i+1) onto the substrate can be approximately polygonal lines extending along the first direction D1. The orthographic projection of the second initial signal line INIT2(i) onto the substrate can lie between the orthographic projections of the first initial connection segment 26 and the reset control line RST(i) onto the substrate. The second initial signal line INIT2(i) can be connected to the first region T80-1 of the active layer of the eighth transistor via the tenth via V10.

[0198] In some examples, the second shielding connection electrode 204 may be located on the side of the seventh connection electrode 417 away from the second initial signal line (e.g., the second initial signal line INIT2(i)) in the second direction D2. The orthographic projection of the second shielding connection electrode 204 onto the substrate may be approximately a strip extending along the first direction D1. The second shielding connection electrode 204 may be connected to the first shielding connection electrode 203 via the sixteenth via V16. The second shielding connection electrode 204 may be connected to the subsequently formed first power line 51.

[0199] (8) Forming the fifth insulating layer and the sixth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the aforementioned structure is formed, and then a sixth insulating film is coated. The sixth insulating film and the fifth insulating film are patterned by a patterning process to form the fifth insulating layer and the sixth insulating layer disposed on the fifth insulating layer. In other examples, after depositing the fifth insulating film, the fifth insulating layer can be formed by a patterning process, and then the sixth insulating film can be coated, and the sixth insulating layer can be formed by a second patterning process. This embodiment is not limited to this.

[0200] Figure 13 is a schematic diagram of the first display area after the formation of the sixth insulating layer in Figure 6. In some examples, as shown in Figure 13, the sixth insulating layer of the first display area can be provided with multiple vias, such as: via 21 V21, via 22 V22, vias 23a, 23b and 23c, via 24 V24, via 25 V25, via 26 V26 and via 27 V27. The sixth and fifth insulating layers within vias 21 V21, 22 V22, 23a, 23b and 23c, 24 V24, 25 V25, 26 V26 and 27 V27 can be removed, exposing a portion of the surface of the third conductive layer.

[0201] (9) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned structure is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer disposed on the sixth insulating layer.

[0202] Figure 14A is a schematic diagram of the first display area after the fourth conductive layer is formed in Figure 5. Figure 14B is a schematic diagram of the first display area after the fourth conductive layer is formed in Figure 6. Figure 14C is a schematic diagram of the fourth conductive layer in Figure 14B.

[0203] In some examples, as shown in Figures 14A to 14C, the fourth conductive layer of the first display area may include: a first power line 51, a plurality of first anode connection electrodes (e.g., including first anode connection electrodes 451a, 451b and 451c), and a plurality of second data connection lines (e.g., including second data connection lines 422a, 422b and 422c).

[0204] In some examples, the first power line 51 can be a mesh structure. The first power line 51 may include: a first power extension 511, a second power extension 512, a third power extension 513, and a fourth power extension 514. The first power extension 511, the second power extension 512, and the third power extension 513 may be located in a sub-display area, and the fourth power extension 514 may be located in a wiring area. For example, a sub-display area may have one first power extension 511, one second power extension 512, and multiple third power extensions 513; a wiring area may have one fourth power extension 514. For example, the orthographic projection of the first power line 51 onto the substrate may cover the orthographic projection of the edge of the shielding layer onto the substrate. In this example, by setting the first power line to a mesh structure, the uniformity of the transmission of the first power signal can be guaranteed.

[0205] In some examples, the orthographic projections of the first power extension 511 and the second power extension 512 onto the substrate can both be straight lines extending along the first direction D1. A plurality of third power extensions 513 can be arranged along the first direction D1 and connected between the first power extensions 511 and the second power extensions 512. The orthographic projection of the third power extension 513 onto the substrate can be a broken line extending along the second direction D2. An anode connection electrode connected to a first pixel circuit and a second data connection line can be disposed between two adjacent third power extensions 513. A fourth power extension 514 can be connected between the first power extensions 511 and the second power extensions 512 on both sides of the light-transmitting area. The orthographic projection of the fourth power extension 514 onto the substrate can be a straight line extending along the second direction D2. For example, the orthographic projection of the fourth power extension 514 onto the substrate can cover the orthographic projection of the second shielding structure 202 onto the substrate. Within the trace area, the orthographic projection of the fourth power extension 514 onto the substrate can cover the orthographic projection of the straight segments of the three adjacent first data connection lines (e.g., including first data connection lines 421a, 421b and 421c) located on the third conductive layer extending along the second direction D2 onto the substrate.

[0206] In some examples, the first power extension 511 can be connected to the second shielding connection electrode 204 via the twenty-seventh via V27, thus achieving an electrical connection with the first shielding connection electrode 203. The first power line 51 can provide a first power signal to the shielding layer via the second shielding connection electrode 204 and the first shielding connection electrode 203. The third power extension 513 can be connected to the fourth connection electrode 414 via the twenty-first via V21, thus achieving a connection with the first electrode of the third transistor of the first pixel circuit.

[0207] In some examples, a first anode connection electrode and a second data connection line can be disposed within a single grid formed by the first power extension 511, the second power extension 512, and a plurality of third power extensions 513. The orthographic projection of the first anode connection electrode 451a onto the substrate can be a strip extending along the first direction D1, the orthographic projection of the first anode connection electrode 451b onto the substrate can be approximately rectangular, and the orthographic projection of the first anode connection electrode 451c onto the substrate can be approximately a strip extending along a direction intersecting the first direction D1 and the second direction D2. The orthographic projections of the second data connection lines 422a, 422b, and 422c onto the substrate can be straight lines extending along the second direction D2.

[0208] In some examples, the first anode connection electrode 451a can be connected to the fifth connection electrode 415 connected to the first pixel circuit in the i-th row and j-th column via the twenty-second via V22; the first anode connection electrode 451b can be connected to the first pixel circuit in the i-th row and j+1-th column; and the first anode connection electrode 451c can be connected to the first pixel circuit in the i-th row and j+2-th column.

[0209] In some examples, one end of the second data connection line 422a can be connected to the first connection electrode 411a through the twenty-third via V23a, thus connecting to a first data connection line 421a, and the other end can be connected to another first data connection line 421a through the twenty-fourth via V24. The second data connection line 422b can be connected to the first connection electrode 411b through the twenty-third via V23b, thus connecting to a first data connection line 421b, and the other end can be connected to another first data connection line 421b through the twenty-fifth via V25. The second data connection line 422c can be connected to the first connection electrode 411c through the twenty-third via V23c, thus connecting to a first data connection line 421c, and the other end can be connected to another first data connection line 421c through the twenty-sixth via V26. In this example, data signals can be transmitted along the second direction by alternately connecting the second data connection line located in the sub-display area and the first data connection line located in the trace area A12.

[0210] Figure 14D is another schematic diagram of the fourth conductive layer according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 14D, the shape of the light-transmitting area A13 can be a rounded rectangle. The corners of the light-transmitting area can be rounded. The edge shape of the light-transmitting area can be determined by the fourth conductive layer. The right-angled positions of the fourth conductive layer near the edge of the light-transmitting area can be rounded. For example, the connection position of the first power extension 511 and the fourth power extension 514 of the first power line 51 located on the fourth conductive layer near the edge of the light-transmitting area A13 can be an arc-shaped edge, and the connection position of the second power extension 512 and the fourth power extension 514 of the first power line 51 near the edge of the light-transmitting area A13 can be an arc-shaped edge.

[0211] In other examples, the edge shape of the light-transmitting area can be determined by a shielding layer that can cover the edge of the fourth conductive layer. The right-angle position of the shielding layer near the edge of the light-transmitting area can be connected by an arc-shaped edge. For example, the connection position of the first shielding structure and the second shielding structure of the shielding layer near the edge of the light-transmitting area can be an arc-shaped edge.

[0212] In other examples, the edge shape of the light-transmitting area can be determined by the cathode layer, which can cover the orthogonal projection of the shielding layer and the fourth conductive layer onto the substrate. The cathode layer can have cathode cutouts in the light-transmitting area, and the cathode cutouts can have rounded corners.

[0213] This example demonstrates how rounding the corners of the conductive layer surrounding the light-transmitting area can reduce optical diffraction and improve the light transmission of the first display area.

[0214] (10) Forming a seventh insulating layer. In some examples, a seventh insulating film is coated on the substrate on which the aforementioned structure is formed, and the seventh insulating film is patterned by a patterning process to form a seventh insulating layer.

[0215] Figure 15 is a schematic diagram of the first display area after the formation of the seventh insulating layer in Figure 5. In some examples, as shown in Figure 15, the seventh insulating layer of the first display area has multiple vias, such as multiple thirty-first vias V31a, V31b, and V31c. The seventh insulating layer within the multiple thirty-first vias V31a, V31b, and V31c can be removed, exposing a portion of the surface of the fourth conductive layer. The thirty-first via V31a can expose a portion of the surface of the anode connection electrode 451a, the thirty-first via V31b can expose a portion of the surface of the anode connection electrode 451b, and the thirty-first via V31c can expose a portion of the surface of the anode connection electrode 451c.

[0216] At this point, the circuit structure layer can be completed. The film structure of the circuit structure layer in the second display area is similar to that in the first display area, so it will not be described again here.

[0217] (11) Forming a light-emitting structure layer. In some examples, an anode thin film is deposited on the substrate on which the aforementioned pattern is formed, and the anode thin film is patterned by a patterning process to form an anode layer.

[0218] Figure 16 is a schematic diagram of the anode layer in Figure 5. In some examples, as shown in Figures 5 and 16, the anode layer of the first display area may include: a plurality of second anode connection electrodes (e.g., including second anode connection electrodes 134a, 134b and 134c) and anodes of a plurality of first light-emitting elements (e.g., including anodes 131a, 131b and 131c).

[0219] In some examples, anode 131a and second anode connecting electrode 134a are integrally formed, and the second anode connecting electrode 134a can be located along the second direction D2 on the side of anode 131a closer to anode 131b. Anode 131b and second anode connecting electrode 134b are integrally formed, and the second anode connecting electrode 134b can be located along the first direction D1 on one side of anode 131b. Anode 131c and second anode connecting electrode 134c are integrally formed, and the second anode connecting electrode 134c can be located along the first direction D1 on one side of anode 131c. The orthographic projections of the second anode connecting electrodes 134a, 134b, and 134c onto the substrate can be approximately trapezoidal. The orthographic projections of the anodes 131a, 131b, and 131c onto the substrate can be approximately rectangular. The orthographic projection area of ​​anode 131c onto the substrate can be larger than the orthographic projection area of ​​anode 131b onto the substrate, and the orthographic projection area of ​​anode 131b onto the substrate can be larger than the orthographic projection area of ​​anode 131a onto the substrate.

[0220] In some examples, the second anode connection electrode 134a can be connected to the first anode connection electrode 451c via the thirty-first via V31c, thereby achieving an electrical connection with the first pixel circuit in the i-th row and j+2-th column. The second anode connection electrode 134b can be connected to the first anode connection electrode 451a via the thirty-first via V31a, thereby achieving an electrical connection with the first pixel circuit in the i-th row and j+3-th column. The second anode connection electrode 134c can be connected to the first anode connection electrode 451b via the thirty-first via V31b, thereby achieving an electrical connection with the first pixel circuit in the i-th row and j+1-th column.

[0221] In some examples, a pixel definition film is coated on the substrate on which the aforementioned structure is formed, and the pixel definition film is patterned by a patterning process to form a pixel definition layer.

[0222] In some examples, as shown in Figures 5 and 6, the pixel definition layer of the first display area may have multiple first pixel openings (e.g., including first pixel openings OP1, OP2, and OP3). The pixel definition film within the first pixel openings can be removed, exposing a portion of the surface of the anode layer. The orthographic projection of the multiple first pixel openings onto the substrate can be approximately rectangular. The orthographic projection area of ​​first pixel opening OP1 onto the substrate can be smaller than the orthographic projection area of ​​first pixel opening OP2 onto the substrate, and the orthographic projection area of ​​first pixel opening OP2 onto the substrate can be smaller than the orthographic projection area of ​​first pixel opening OP3 onto the substrate.

[0223] In some examples, the light-emitting area of ​​a light-emitting element can be the portion of a pixel opening located in the pixel definition layer. For example, the light-emitting area of ​​the first light-emitting element EL1 corresponds to the first pixel opening OP1, the light-emitting area of ​​the first light-emitting element EL2 corresponds to the first pixel opening OP2, and the light-emitting area of ​​the first light-emitting element EL3 corresponds to the first pixel opening OP3. The light-emitting areas of the first light-emitting elements EL1, EL2, and EL3 can all be approximately rectangular. The length of the light-emitting area of ​​the first light-emitting element EL1 along the first direction D1 can be greater than its length along the second direction D2; the length of the light-emitting area of ​​the first light-emitting element EL2 along the first direction D1 can be greater than its length along the second direction D2; and the length of the light-emitting area of ​​the first light-emitting element EL3 along the first direction D1 can be less than its length along the second direction D2.

[0224] In some examples, the area of ​​the light-emitting region of the first light-emitting element EL1 may be smaller than the area of ​​the light-emitting region of the first light-emitting element EL2, and the area of ​​the light-emitting region of the first light-emitting element EL2 may be smaller than the area of ​​the light-emitting region of the first light-emitting element EL3.

[0225] In some examples, an organic functional layer is formed within the aforementioned first pixel opening, and the organic light-emitting layer contacts the anode layer exposed by the first pixel opening. Subsequently, a cathode film is deposited, and the cathode film is patterned using a patterning process to form a cathode layer, which can be connected to the organic light-emitting layer. The cathode layer may include the cathodes of multiple first light-emitting elements, and the cathodes of the multiple first light-emitting elements can be a single integrated structure.

[0226] In some examples, as shown in Figures 5 and 6, the light-transmitting area A13 can be roughly rectangular in shape, and multiple light-transmitting areas A13 can have roughly the same shape. The cathode film within the light-transmitting area A13 can be removed to improve the light transmittance of the light-transmitting area A13.

[0227] In some examples, as shown in Figures 5 and 6, the length of three adjacent first pixel circuits along the first direction D1 in a row of first pixel circuits within a sub-display area can be W2, and the maximum length of a row of first pixel circuits along the second direction D2 can be H2. The length of each first pixel circuit along the first direction D1 can be one-third of W2. The maximum length of a light-transmitting area A13 along the first direction D1 can be W1, and the maximum length along the second direction D2 can be H1. Taking a pixel density of 188 PPI in the first display area of ​​the display substrate as an example, the length W2 of three adjacent first pixel circuits along the first direction D1 can be greater than the maximum length W1 of the light-transmitting area A13 along the first direction D1; the maximum length H2 of a row of first pixel circuits along the second direction D2 can be greater than the maximum length H1 of the light-transmitting area A13 along the second direction D2. For example, the ratio of H2 to H1 can be greater than 1 and less than 2; for example, H2 can be approximately 79.2 micrometers (µm), and H1 can be approximately 55.7 micrometers. The ratio of W2 to W1 can be greater than or equal to 1. For example, W2 can be approximately 135 μm and W1 can be approximately 118 μm.

[0228] In some examples, the orthographic projection of the light-emitting areas of the plurality of first light-emitting elements in the sub-display area onto the substrate may lie within the orthographic projection range of the plurality of first pixel circuits onto the substrate. In this example, the maximum length of the light-emitting area of ​​the first light-emitting element along the second direction D2 may be less than the maximum length of the first pixel circuit along the second direction D2.

[0229] In some examples, a group of first light-emitting elements within a sub-display area may include: a first light-emitting element EL1 emitting a first color light, a first light-emitting element EL2 emitting a second color light, and a first light-emitting element EL3 emitting a third color light. As shown in Figures 5 and 6, the spacing W3 between adjacent groups of first light-emitting elements along the first direction D1 may be less than the maximum length H1 of a light-transmitting area A13 along the second direction D2. The spacing W3 between adjacent groups of first light-emitting elements along the first direction D1 may be less than the maximum length H2 of the first pixel circuit along the second direction D2. The spacing W3 between adjacent groups of first light-emitting elements along the first direction D1 may refer to the vertical distance between the closest anode edges of the two groups of first light-emitting elements.

[0230] In some examples, as shown in Figure 5, the spacing W4 between first light-emitting elements EL1 and EL3, the spacing W5 between first light-emitting elements EL2 and EL3, and the spacing W6 between first light-emitting elements EL1 and EL2 in a group of first light-emitting elements can be equal. The spacing W3 between adjacent groups of first light-emitting elements along the first direction D1 can be equal to the spacing between adjacent first light-emitting elements in each group. In other words, W3, W4, W5, and W6 can be the same. The spacing between adjacent first light-emitting elements in a group can refer to the vertical distance between the closest anode edges of adjacent first light-emitting elements.

[0231] In some examples, after fabricating the light-emitting structure layer, an encapsulation structure layer can be formed on the cathode. In some examples, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer may be disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0232] In some examples, the shielding layer, first conductive layer, second conductive layer, third conductive layer, and fourth conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, and fifth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON). These can be single-layer, multi-layer, or composite layers. The sixth and seventh insulating layers can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited in this regard.

[0233] The structure and fabrication process of the display substrate in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and added or reduced according to actual needs. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with existing fabrication processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0234] In this embodiment, the display substrate increases the size of the light-transmitting area by compressing the first pixel circuit of the first display area along the second direction. This allows for full utilization of the lateral space to accommodate the first pixel circuit and the first light-emitting element, thereby ensuring the pixel aperture ratio of the first display area. For example, when the display substrate is applied to an automotive display device, the pixel aperture ratio of the first display area can reach 35.7%, while meeting a lifespan of 10,000 hours.

[0235] Figure 17 is a schematic diagram of another arrangement of pixel circuits in a display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 17, the sub-display area A11 of the first display area A1 can be provided with two rows of first pixel circuits 11, and each row of first pixel circuits can correspond to a row of second pixel circuits in the second display area A2. Each column of first pixel circuits can correspond to a column of second pixel circuits in the second display area A2. Adjacent first pixel circuits 11 in the same column of first pixel circuits in adjacent sub-display areas A11 can achieve signal transmission along the second direction D2 through signal connection lines 17 of the wiring area A12 (e.g., including multiple first data connection lines located in the third conductive layer and a fourth power extension of the first power line located in the fourth conductive layer). In some examples, the maximum length of the light-transmitting area A13 along the second direction D2 can be greater than the maximum length of the first pixel circuit 11 along the second direction D2, and greater than the maximum length of the second pixel circuit 12 along the second direction D2. The arrangement of this example is advantageous for increasing the size of the light-transmitting area along the second direction. Further descriptions of the display substrate of this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0236] In other examples, the sub-display area A11 of the first display area A1 can be configured with three, four, or more rows of first pixel circuits. By concentrating the first pixel circuits along the second direction D2, it is advantageous to increase the size of the light-transmitting area along the second direction.

[0237] In other examples, the first direction can be a column direction, and the second direction can be a row direction. Multiple sub-display areas of the first display area can be arranged sequentially along the column direction, and multiple light-transmitting areas and multiple wiring areas located between adjacent sub-display areas can be spaced apart along the column direction. One or more columns of first pixel circuits can be set within a sub-display area. The light-transmitting areas can extend along the column direction.

[0238] This embodiment also provides a display substrate, including: a first display area and a second display area located on at least one side of the first display area; the first display area includes a plurality of sub-display areas extending along a first direction and arranged along a second direction, and a plurality of light-transmitting areas located between adjacent sub-display areas; the pixel density of the second display area is the same as the pixel density of the first display area; the first direction and the second direction intersect. Each sub-display area includes: a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on a substrate, at least one of the plurality of first pixel circuits being connected to at least one of the plurality of first light-emitting elements and configured to drive the at least one first light-emitting element to emit light. The orthographic projection of the at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element on the substrate. The second display area includes: a plurality of second pixel circuits and a plurality of second light-emitting elements disposed on the substrate, at least one of the plurality of second pixel circuits being connected to at least one of the plurality of second light-emitting elements and configured to drive the at least one second light-emitting element to emit light. The orthographic projection of the at least one second pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one second light-emitting element on the substrate. The maximum length of the orthographic projection of the second pixel circuit onto the substrate along the second direction is greater than the maximum length of the orthographic projection of the first pixel circuit onto the substrate along the second direction.

[0239] In some exemplary embodiments, the maximum length of the second pixel circuit projected onto the substrate along the second direction can be greater than the maximum length of a light-transmitting area along the second direction.

[0240] The display substrate provided in this embodiment increases the size of the light-transmitting area by compressing the space occupied by the first pixel circuit in the second direction, thereby improving the light transmittance of the display substrate. For a related description of this embodiment, please refer to the description of the foregoing embodiments; therefore, it will not be repeated here.

[0241] This embodiment also provides a display device, including a display substrate as described above, and a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor onto the display substrate at least partially overlaps with a first display area of ​​the display substrate. For example, the orthographic projection of the sensor onto the display substrate may be located within the first display area. The sensor may be a camera or an infrared sensor.

[0242] Figure 18 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 18, this embodiment provides a display device including: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 may be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 may be located within a first display area A1.

[0243] In some examples, the display substrate 91 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be a product with image (including still images or moving images, where the moving images can be video) display capabilities. For example, the display device can be any of the following: monitor, television set, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc. Furthermore, the display device can also be any of the following: microdisplay, VR device or AR device containing a microdisplay, etc.

[0244] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0245] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

A display substrate, comprising: First display area; The first display area includes: a plurality of sub-display areas extending along a first direction and arranged along a second direction, and a plurality of light-transmitting areas located between adjacent sub-display areas; the first direction intersects the second direction; The sub-display area includes: a substrate and a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on the substrate; at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements and configured to drive the at least one first light-emitting element to emit light; the orthographic projection of the at least one first pixel circuit on the substrate and the orthographic projection of the at least one first light-emitting element on the substrate at least partially overlap; The plurality of first pixel circuits include multiple rows of first pixel circuits, and one row of first pixel circuits in the plurality of rows of first pixel circuits is connected to multiple first signal lines extending along the first direction; the row of first pixel circuits includes at least a portion of the plurality of first pixel circuits arranged sequentially along the first direction. The distance between any two adjacent first signal lines among the plurality of first signal lines connected to the first pixel circuit of the row is less than the maximum length of one of the plurality of light-transmitting areas along the second direction. The display substrate according to claim 1, wherein, The ratio of the maximum length of the first pixel circuit in a row within the sub-display area projected onto the substrate along the second direction to the maximum length of the light-transmitting area along the second direction is greater than or equal to 1. The display substrate according to claim 1, wherein, In the second direction, multiple first pixel circuits in adjacent sub-display areas are connected by multiple signal connection lines; The first display area further includes: a plurality of trace areas located between adjacent sub-display areas and spaced apart from the plurality of light-transmitting areas along the first direction; at least one of the plurality of trace areas has a length along the first direction that is greater than the line width of at least one of the plurality of signal connection lines. The display substrate according to claim 1, wherein, The plurality of first signal lines include: a scan line, an emission control line, and a reset control line; the scan line, the emission control line, and the reset control line are located in the same conductive layer, the emission control line is located between the scan line and the reset control line in the second direction, and the minimum distance between the emission control line connected to the first pixel circuit in the same row and the reset control line is less than the minimum distance between the scan line and the emission control line. The display substrate according to claim 4, wherein, The plurality of first signal lines also include: a reference signal line, a first initial signal line, and a second initial signal line; The reference signal line and the first initial signal line are located in the same conductive layer, and are located on the side of the conductive layer where the scan line is located away from the substrate; the second initial signal line is located in the conductive layer where the first initial signal line is away from the substrate. According to claim 5, the display substrate, wherein, The first pixel circuit includes: a driving transistor, a capacitor, a first control transistor, and a second control transistor; The gate of the driving transistor is integral with the first plate of the capacitor. The second plate of the capacitor is connected to the second electrode of the first control transistor and the second control transistor. The first electrode of the first control transistor and the first electrode of the second control transistor are both connected to the reference signal line. The gate of the first control transistor is connected to the reset control line, and the gate of the second control transistor is connected to the light emission control line. The gates of the first control transistor and the second control transistor are offset along the first direction; The reference signal line is located on the conductive layer away from the substrate of the gates of the first control transistor and the second control transistor; the orthographic projection of the reference signal line on the substrate is a broken line extending along the first direction, and is located between the orthographic projections of the gates of the first control transistor and the gates of the second control transistor on the substrate. The display substrate according to claim 6, wherein, The active layer of the first control transistor and the active layer of the second control transistor are an integral structure, and the orthographic projection of the integral structure onto the substrate is a rectangular ring. The display substrate according to claim 6, wherein, The first pixel circuit further includes: a first compensation transistor, wherein the gate of the first compensation transistor is integral with the scan line, the first terminal of the first compensation transistor is connected to the second terminal of the driving transistor, and the second terminal of the first compensation transistor is connected to the gate of the driving transistor. The display substrate further includes: a shielding electrode; the orthographic projection of the shielding electrode onto the substrate and the orthographic projection of the conductive region between the active layer of the first compensation transistor and the substrate at least partially overlap. The display substrate according to claim 8, wherein, The first pixel circuit further includes: a second compensation transistor, the gate of the second compensation transistor being an integral structure with the light emission control line; the first electrode of the second compensation transistor being floating, and the second electrode of the second compensation transistor being connected to the second electrode of the first compensation transistor. The display substrate according to any one of claims 1 to 9 further comprises: A shielding layer located on the side of the plurality of first pixel circuits near the substrate, the shielding layer including a first shielding structure and a first shielding connection electrode connected to each other, the orthographic projection of the first shielding structure on the substrate covers the orthographic projection of the active layer of the transistors of the plurality of first pixel circuits on the substrate. The first shielding connection electrode is connected to the first power line through the second shielding connection electrode. The second shielding connection electrode is located in the conductive layer of the first shielding connection electrode away from the substrate, and the first power line is located in the conductive layer of the second shielding connection electrode away from the substrate. The display substrate according to claim 10, wherein, The first light-emitting element includes an anode, an organic light-emitting layer, and a cathode stacked sequentially; The orthographic projection of the anode of the first light-emitting element on the substrate does not overlap with the orthographic projection of the connection hole between the first shielding connection electrode and the second shielding connection electrode, or the connection hole between the second shielding connection electrode and the first power line on the substrate. The display substrate according to claim 1, wherein, The edges of the conductive layer surrounding the light-transmitting area are rounded. The display substrate according to claim 1, wherein, The sub-display area includes: multiple groups of first light-emitting elements arranged along the first direction, each group of first light-emitting elements including: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light; The first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light are arranged adjacent to each other along the second direction, and the first light-emitting element emitting the third color light is located on the same side of the first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light in the first direction. The display substrate according to claim 13, wherein, The spacing between adjacent groups of first light-emitting elements along the first direction is less than the maximum length of a light-transmitting area along the second direction; Alternatively, the spacing between adjacent groups of first light-emitting elements along the first direction is less than the maximum length of the first pixel circuit along the second direction. The display substrate according to claim 13, wherein, The spacing between adjacent groups of first light-emitting elements along the first direction is equal to the spacing between adjacent first light-emitting elements in each group. The display substrate according to any one of claims 1 to 15 further comprises: A second display area located on at least one side of the first display area; The second display area includes: the substrate and a plurality of second pixel circuits and a plurality of second light-emitting elements disposed on the substrate; at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements and configured to drive the at least one second light-emitting element to emit light; the orthographic projection of the at least one second pixel circuit on the substrate and the orthographic projection of the at least one second light-emitting element on the substrate at least partially overlap; The maximum length of the orthographic projection of the second pixel circuit onto the substrate along the second direction is greater than the maximum length of the orthographic projection of the first pixel circuit onto the substrate along the second direction. The display substrate according to claim 16, wherein, The pixel density of the second display area is the same as that of the first display area. A display device includes a display substrate as claimed in any one of claims 1 to 17, and a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor onto the display substrate at least partially overlaps with a first display area of ​​the display substrate. A display substrate, comprising: A first display area and a second display area located on at least one side of the first display area; the first display area includes a plurality of sub-display areas extending along a first direction and arranged along a second direction, and a plurality of light-transmitting areas located between adjacent sub-display areas; the pixel density of the second display area is the same as the pixel density of the first display area; the first direction and the second direction intersect; The sub-display area includes: a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on a substrate, wherein at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements and is configured to drive the at least one first light-emitting element to emit light; the orthographic projection of the at least one first pixel circuit on the substrate and the orthographic projection of the at least one first light-emitting element on the substrate at least partially overlap. The second display area includes: a plurality of second pixel circuits and a plurality of second light-emitting elements disposed on the substrate, wherein at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements and configured to drive the at least one second light-emitting element to emit light; the orthographic projection of the at least one second pixel circuit on the substrate and the orthographic projection of the at least one second light-emitting element on the substrate at least partially overlap; The maximum length of the orthographic projection of the second pixel circuit onto the substrate along the second direction is greater than the maximum length of the orthographic projection of the first pixel circuit onto the substrate along the second direction. The display substrate according to claim 19, wherein, The maximum length of the second pixel circuit's orthogonal projection onto the substrate along the second direction is greater than the maximum length of one of the plurality of light-transmitting areas along the second direction.

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