Display substrate and display apparatus

Abstract

Provided in the embodiments of the present disclosure are a display substrate and a display apparatus. The display substrate comprises: a plurality of sub-pixels, a plurality of data lines and a plurality of first signal lines, which are located in a display area; first signal provision line groups, which are electrically connected to the first signal lines, are located in first-type frame areas and extend to a binding area in a first frame area; and at least one first signal pin group and at least one integrated circuit pin group, which are located in the binding area, wherein in a first direction, the at least one first signal pin group is located on at least one side of the at least one integrated circuit pin group, each first signal pin group and a corresponding first signal provision line group are located on the same side of the at least one integrated circuit pin group, and first signal pins in the first signal pin group are configured to be electrically connected to first signal provision lines in the corresponding first signal provision line group.

Description

Display substrate, display device

[0001] This application claims priority to Chinese Patent Application No. 202411376292.9, filed on September 29, 2024, entitled “Display Substrate, Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide a display substrate, comprising:

[0006] The substrate includes a display area, a first border area, and a first type of border area; in a first direction, the first type of border area is located on at least one side of the display area; in a second direction, the first border area is located on one side of the display area, and the first border area is provided with a bonding area; the first direction intersects the second direction.

[0007] Multiple sub-pixels are located in the display area;

[0008] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels. The multiple data lines extend along the second direction and are arranged at intervals along the first direction.

[0009] Multiple first signal lines are located in the display area, extending along the first direction and arranged along the second direction, and the multiple first signal lines are electrically connected to the multiple sub-pixels;

[0010] At least one first signal providing line group is located in the first type of border area and extends to the binding area in the first border area, wherein the first signal providing line in the first signal providing line group is configured to be electrically connected to at least one of the plurality of first signal lines;

[0011] A plurality of bonded pin groups and at least one integrated circuit pin group are located in the bonded area. The plurality of bonded pin groups include at least one first signal pin group. At least a portion of the integrated circuit pins in the integrated circuit pin group are configured to be electrically connected to the plurality of data lines. In the first direction, the at least one first signal pin group is located on at least one side of the at least one integrated circuit pin group. The at least one first signal pin group corresponds one-to-one with the at least one first signal providing line group. The at least one first signal pin group and the corresponding first signal providing line group are located on the same side of the at least one integrated circuit pin group. At least a portion of the first signal pins in the at least one first signal group are configured to be electrically connected to at least a portion of the first signal providing line in the corresponding first signal providing line group.

[0012] In an exemplary embodiment, in the second direction, the plurality of bonding pin groups are located on the side of the integrated circuit pin group away from the display area;

[0013] The plurality of bonded pin groups further includes at least one drive pin group and at least one power pin group, wherein the at least one drive pin group corresponds one-to-one with the at least one integrated circuit pin group and is electrically connected to the corresponding integrated circuit pin group; in the first direction, at least one power pin group is provided between the at least one first signal pin group and the at least one drive pin group.

[0014] In an exemplary embodiment, the first type of bezel area is further provided with a plurality of gate drive circuit signal lines, which extend to the first bezel area. In the same first type of bezel area, in the first direction, the first signal providing line group is located on the side of the plurality of gate drive circuit signal lines away from the display area.

[0015] In an exemplary embodiment, the first type of border area includes a third border area and a fourth border area. In the first direction, the third border area is located on one side of the display area, and the fourth border area is located on the other side of the display area. The at least one first signal providing line group includes at least a first first signal providing line group and a second first signal providing line group. The first first signal providing line group is located in the third border area and extends to the first border area. The second first signal providing line group is located in the fourth border area and extends to the first border area.

[0016] The at least one first signal pin group includes a first first signal pin group and a second first signal pin group, wherein at least a portion of the first signal pins in the first first signal pin group are configured to be electrically connected to at least a portion of the first signal providing lines in the first first signal providing line group, and at least a portion of the first signal pins in the second first signal pin group are configured to be electrically connected to at least a portion of the first signal providing lines in the second first signal providing line group.

[0017] In the first direction, the first first signal pin group and the first first signal providing line group are located on the same side of the at least one drive pin group, and the second first signal pin group and the second first signal providing line group are located on the same side of the at least one drive pin group.

[0018] In an exemplary embodiment, the at least one power pin group includes at least a first power pin group and a second power pin group, and the bonding area further includes a first power signal supply line group and a second power signal supply line group. At least a portion of the power pins in the first power pin group are electrically connected to at least a portion of the power signal supply lines in the first power signal supply line group, and at least a portion of the power pins in the second power pin group are electrically connected to at least a portion of the power signal supply lines in the second power signal supply line group.

[0019] In the bonding area, in the first direction, the first power pin group and the second power pin group are located on opposite sides of the at least one drive pin group; the first power signal supply line group and the second power signal supply line group are located on opposite sides of the at least one drive pin group; the first power signal supply line group and the first power pin group are located on the same side of the at least one drive pin group; the second power signal supply line group and the second power pin group are located on the same side of the at least one drive pin group; the first first signal pin group is located on the side of the first power pin group away from the at least one drive pin group; the second first signal pin group is located on the side of the second power pin group and the second power signal supply line group away from the at least one drive pin group.

[0020] In an exemplary embodiment, the plurality of gate drive circuit signal lines include a plurality of first gate drive circuit signal lines and a plurality of second gate drive circuit signal lines. The plurality of first gate drive circuit signal lines are located in the third frame region and extend to the first frame region; the plurality of second gate drive circuit signal lines are located in the fourth frame region and extend to the first frame region.

[0021] In the bonding region, in the first direction, the first power signal supply line group and the plurality of first gate drive circuit signal lines are located on the same side of the at least one drive pin group, and the second power signal supply line group and the plurality of second gate drive circuit signal lines are located on the same side of the at least one drive pin group; the first first signal supply line group is located on the side of the plurality of first gate drive circuit signal lines away from the at least one integrated circuit pin group, and the second first signal supply line group is located on the side of the plurality of second gate drive circuit signal lines away from the at least one integrated circuit pin group.

[0022] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the plurality of sub-pixels are disposed on one side of the substrate. At least one of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element. The pixel driving circuit includes at least one thin-film transistor and a planarization layer. The planarization layer is located on the side of the thin-film transistor away from the substrate to cover the thin-film transistor. The light-emitting element is located on the side of the planarization layer away from the substrate. The planarization layer includes a first planarization layer via. The thin-film transistor includes an active layer on the substrate, a gate on the side of the active layer away from the substrate, a source and a drain on the side of the gate away from the substrate, and a transition electrode on the side of the source and the drain away from the substrate. In the same sub-pixel, one of the source and the drain of one of the thin-film transistors is electrically connected to the transition electrode through a via. The transition electrode is electrically connected to the light-emitting element through the first planarization layer via.

[0023] In the display area, the data line is disposed on the same layer as the transfer electrode, and the first signal line is disposed on the same layer as at least one of the active layer, the source and the drain, and the gate.

[0024] In the bonding area, the first signal supply line, the power signal supply line in the power signal supply line group, and at least one of the source, the drain, and the transition electrode are disposed on the same layer.

[0025] In an exemplary embodiment, the sub-pixel further includes at least one capacitor, the first plate of which is disposed in the same layer as the gate of the at least one thin-film transistor, and the second plate of which is located between the gate of the at least one thin-film transistor and the source and drain in a direction perpendicular to the plane of the substrate.

[0026] In the bonding region, the first signal providing line is a multilayer structure disposed on the same layer as the source, the drain, the transition electrode, the gate, and the second plate of the capacitor, and the multilayer structure is electrically connected.

[0027] In an exemplary embodiment, in the bonding region, the plurality of first gate drive circuit signal lines bend along the third border region in the direction pointing to the display region and are electrically connected to the integrated circuit pin group closest to the first power signal supply line group; the plurality of second gate drive circuit signal lines bend along the fourth border region in the direction pointing to the display region and are electrically connected to the integrated circuit pin group closest to the second power signal supply line group.

[0028] In the bonding region, at least a portion of the structure of the first gate drive circuit signal line at least partially overlaps with the orthographic projection of the power signal supply line in the first power signal supply line group on the substrate, and the first gate drive circuit signal line and the power signal supply line in the first power signal supply line group are located in different conductive layers in the overlapping region; at least a portion of the structure of the second gate drive circuit signal line at least partially overlaps with the orthographic projection of the power signal supply line in the second power signal supply line group on the substrate, and the plurality of second gate drive circuit signal lines and the power signal supply line in the second power signal supply line group are located in different conductive layers in the overlapping region.

[0029] In an exemplary embodiment, the plurality of bonded pin groups further includes a first gate drive circuit pin group and a second gate drive circuit pin group;

[0030] In the first direction, the first first signal pin group is located on the side of the first gate drive circuit pin group away from the first power supply pin group, and the second first signal pin group is located on the side of the second gate drive circuit pin group away from the second power supply pin group;

[0031] The first gate drive circuit signal line is configured to be electrically connected to the corresponding first gate drive circuit pin in the first gate drive circuit pin group, and the second gate drive circuit signal line is configured to be electrically connected to the corresponding second gate drive circuit pin in the second gate drive circuit pin group.

[0032] In the bonding region, at least a portion of the structure in at least a portion of the gate drive circuit signal lines has a non-overlapping area with the power signal supply lines in the power signal supply line group.

[0033] In an exemplary embodiment, in the bonding region, in the region where the gate drive circuit signal line overlaps with the power supply signal line, the gate drive circuit signal line is a multilayer structure disposed on the same layer as the gate and the second plate of the capacitor; in at least a portion of the region where the gate drive circuit signal line does not overlap with the power supply signal line, the gate drive circuit signal line is a multilayer structure disposed on the same layer as the source and drain, the transition electrode, the gate, and the second plate of the capacitor, and the multilayer structure is electrically connected.

[0034] In an exemplary embodiment, along the direction from the display area to the first border area, the first border area includes a first fan-out area, a bending area, a second fan-out area, and the binding area arranged sequentially.

[0035] In the first fan-out region, the first signal providing line, the plurality of first gate driving circuit signal lines, and the plurality of second gate driving circuit signal lines are a multi-layer structure disposed on the same layer as the gate and the second plate of the capacitor, and the multi-layer structure is electrically connected.

[0036] In the second fan-out region, the first signal supply line, the plurality of first gate drive circuit signal lines, the plurality of second gate drive circuit signal lines are disposed on the same layer as at least one of the gate, the second plate of the capacitor, the source and the drain, and the transition electrode. In the first direction, on the same side of the plurality of drive pin groups, the first signal supply line and the gate drive circuit signal lines are located on the side of the power supply signal supply line group away from the plurality of drive pin groups.

[0037] In an exemplary embodiment, the same power signal supply line group includes a first power signal supply line and a second power signal supply line. The first fan-out area is also provided with at least one first power connection line, at least one second power connection line, and a plurality of first data connection lines. The bending area is also provided with at least one first power connection structure, at least one second power connection structure, and a plurality of second data connection lines. The second fan-out area is also provided with a plurality of third data connection lines. The first power signal supply line and the second power signal supply line extend from the bonding area to the second fan-out area.

[0038] The first power connection structure is configured to electrically connect the first power connection line to the corresponding first power signal supply line, and the second power connection structure is configured to electrically connect the second power connection line to the corresponding second power signal supply line.

[0039] The plurality of data lines, the plurality of first data connection lines, the plurality of second data connection lines, and the plurality of third data connection lines correspond one-to-one. The data lines are electrically connected to the corresponding integrated circuit pins in the corresponding integrated circuit bonding pin groups through the corresponding first data connection lines, the corresponding second data connection lines, and the corresponding third data connection lines.

[0040] In an exemplary embodiment, in the first fan-out region, the plurality of first data connection lines are a multilayer structure disposed on the same layer as the gate and the second plate of the capacitor, and the first power connection line and the second power connection line are a multilayer structure disposed on the same layer as the source, the drain and the transition electrode, and the multilayer structure is electrically connected.

[0041] In the bending area, the third data connection line, the first power connection structure, the second power connection structure, the first signal supply line, and the gate drive circuit signal line are arranged on the same layer as the source and the drain, and different signal lines are spaced apart.

[0042] In the second fan-out region, the third data connection line is disposed on the same layer as at least one of the gate and the second plate of the capacitor.

[0043] In an exemplary embodiment, in the second fan-out region, the third data connection line is a multilayer structure disposed on the same layer as the gate and the second plate of the capacitor. The first signal providing line, the plurality of first gate driving circuit signal lines, and the plurality of second gate driving circuit signal lines are multilayer structures disposed on the same layer as the gate, the second plate of the capacitor, the source and the drain, and the transition electrode. The multilayer structures are electrically connected.

[0044] In an exemplary embodiment, the first fan-out area further includes at least one first signal connection structure; at least one first signal pin is included in the same first signal pin group; the types of the first signal providing line and the plurality of first signal lines include at least one; the types of the first signal providing line, the types of the first signal line, and the types of the first signal pin are in one-to-one correspondence; and the first signal providing line is electrically connected to the first signal line and the first signal pin of the corresponding type.

[0045] In the first border region, among at least one first signal providing line, the number of first signal providing lines of the same type is at least two. In the first fan-out region, at least two first signal providing lines of the same type are electrically connected through corresponding first signal connection structures. In the region where the first signal connection structure is connected to the corresponding first signal providing line, the first signal providing line is disposed on the same layer as one of the gate and the second plate of the capacitor, and the first signal connection structure is disposed on the same layer as the other of the gate and the second plate of the capacitor. The first signal connection structures corresponding to different types of first signal providing lines are spaced apart.

[0046] In an exemplary embodiment, the first signal pins in the two first signal pin groups are of the same type, the first signal providing lines in the first first signal providing line group and the second first signal providing line group are of the same type, and the same first signal line is electrically connected to the first signal providing line of the corresponding type in the first first signal providing line group and the second first signal providing line group.

[0047] In an exemplary embodiment, the display area is further provided with a plurality of first signal connection lines. The first signal connection lines are disposed on the same layer as the adapter electrode. The plurality of first signal connection lines are arranged at intervals along the first direction and extend along the second direction. The types of the plurality of first signal connection lines correspond one-to-one with the types of the plurality of first signal lines. The first signal connection lines are electrically connected to the plurality of first signal lines of the corresponding type through vias. The same first signal line is electrically connected to the plurality of first signal connection lines of the corresponding type through vias.

[0048] In an exemplary embodiment, the integrated circuit pins in the integrated circuit pin group and the bonding pins in the bonding pin group are multilayer structures disposed on the same layer as the source, the drain, and the transition electrode, and the multilayer structures are electrically connected.

[0049] In an exemplary embodiment, the third border region further includes a plurality of first gate driving circuits, and the fourth border region further includes a plurality of second gate driving circuits.

[0050] The plurality of first gate driving circuits are arranged along the direction extending from the third frame region, and the plurality of second gate driving circuits are arranged along the direction extending from the fourth frame region. The signal lines of the first gate driving circuits are also electrically connected to the plurality of first gate driving circuits, and the signal lines of the second gate driving circuits are also electrically connected to the plurality of second gate driving circuits.

[0051] In the first direction, in the third frame region, the at least one first signal providing line is located on the side of the plurality of first gate driving circuits away from the display area; in the fourth frame region, the at least one first signal providing line is located on the side of the plurality of second gate driving circuits away from the display area.

[0052] In an exemplary embodiment, the display area further includes a plurality of scanning signal lines, which extend along the first direction and are arranged along the second direction;

[0053] The first gate driving circuit and the second gate driving circuit are configured to be electrically connected to the corresponding scan signal line, and the scan signal line is disposed on the same layer as at least one of the gate and the second plate of the capacitor.

[0054] In an exemplary embodiment, the plurality of first signal lines include a plurality of initial signal lines, the at least one first signal providing line group includes at least one initial signal providing line group, the at least one first signal pin group includes at least one initial signal pin group, and the initial signal pin group includes at least one initial signal pin.

[0055] The same initial signal pin group includes at least one initial signal pin. The initial signal providing line in the at least one initial signal providing line group and the types of the plurality of initial signal lines include at least one. The types of initial signal providing lines, the types of initial signal lines, and the types of initial signal pins correspond one-to-one. The initial signal providing line is electrically connected to the corresponding type of initial signal line and the corresponding type of initial signal pin.

[0056] In a second aspect, embodiments of this disclosure provide a display substrate, comprising:

[0057] The substrate includes a display area, a first border area, and a first type of border area; in a first direction, the first type of border area is located on at least one side of the display area; in a second direction, the first border area is located on one side of the display area, and the first border area is provided with a bonding area; the first direction intersects the second direction.

[0058] Multiple sub-pixels are located in the display area;

[0059] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels. The multiple data lines extend along the second direction and are arranged at intervals along the first direction.

[0060] Multiple first signal lines are located in the display area, extending along the first direction and arranged along the second direction, and the multiple first signal lines are electrically connected to the multiple sub-pixels;

[0061] At least one first signal providing line group is located in the first type of border area and extends to the binding area in the first border area, wherein the first signal providing line in the first signal providing line group is configured to be electrically connected to at least one of the plurality of first signal lines;

[0062] At least one integrated circuit pin group is located in the bonding region, and at least a portion of the integrated circuit pins in the integrated circuit pin group are configured to be electrically connected to the plurality of data lines;

[0063] In the bonding region, in the first direction, the main body portion of the at least one first signal providing line group is located on at least one side of the at least one integrated circuit pin group, and at least a portion of the first signal providing line has a multilayer structure, the multilayer structure being electrically connected.

[0064] In an exemplary embodiment, the first type of frame area is further provided with a plurality of gate drive circuit signal lines, which extend to the bonding area in the first frame area.

[0065] In the bonding area, in the first direction, the main body portion of the gate drive circuit signal line is located on at least one side of the at least one integrated circuit pin group, on the same side of the first center line, the first signal providing line in the first signal providing line group, the gate drive circuit signal line and the integrated circuit pin group farthest from the first center line are electrically connected, and the first center line is the center line extending from the first border area along the second direction;

[0066] In the bonding region, at least a portion of the gate drive circuit signal lines have a multilayer structure, and the multilayer structure is electrically connected.

[0067] In an exemplary embodiment, the bonding area further includes at least one power signal supply line group, which is located on at least one side of the at least one integrated circuit pin group in the first direction;

[0068] In the bonding region, on the same side of the first center line in the first direction, the gate drive circuit signal line and the first signal providing line bend along the direction from the first type of bezel region toward the display region and are electrically connected to the integrated circuit pin group farthest from the first center line. At least a portion of the structure of the gate drive circuit signal line and the first signal providing line at least partially overlaps with the orthographic projection of the power signal providing line group on the substrate. The gate drive circuit signal line and the first signal providing line are located in different conductive layers from the power signal providing line in the overlapping region.

[0069] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the display substrate includes at least a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially disposed on one side of the substrate;

[0070] In the display area, the data line is located in the second source / drain metal layer, and the first signal line is located in at least one conductive layer of the first gate metal layer, the second gate metal layer, and the first source / drain metal layer;

[0071] In the bonding region, the first signal line and the gate drive circuit signal line are located in at least one conductive layer among the first gate metal layer, the second gate metal layer, and the first source / drain metal layer.

[0072] In an exemplary embodiment, along the direction from the display area to the first border area, the first border area includes a first fan-out area, a bending area, a second fan-out area, and the binding area arranged sequentially.

[0073] In the first fan-out region and the bonding region, in at least a portion of the area where the first signal providing line and the gate driving circuit signal line overlap with the power supply signal line, the first signal providing line and the gate driving circuit signal line are a multilayer structure located in the first gate metal layer and the second gate metal layer, and the multilayer structure is electrically connected.

[0074] In the second fan-out region and the bonding region, in at least a portion of the area where the first signal supply line and the gate drive circuit signal line do not overlap with the power supply signal line, the first signal supply line and the gate drive circuit signal line are a multilayer structure located in the first gate metal layer, the second gate metal layer, the first source drain metal layer and the second source drain metal layer, and the multilayer structure is electrically connected.

[0075] In an exemplary embodiment, the power signal supply line in the power signal supply line group extends from the bonding area to the second fan-out area;

[0076] In at least a portion of the second fan-out region and the bonding region, the power signal supply lines in the power signal supply line group are a multilayer structure located in the first source / drain metal layer and the second source / drain metal layer, and the multilayer structure is electrically connected.

[0077] Thirdly, this disclosure also provides a display device including the display substrate described in any of the above embodiments.

[0078] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0079] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0080] Figure 1 shows a schematic diagram of a display device;

[0081] Figure 2 shows a schematic diagram of a display substrate structure;

[0082] Figure 3 shows an enlarged structural diagram of the first border region;

[0083] Figure 4 is a schematic diagram of the structure of a display substrate;

[0084] Figure 5 shows a schematic diagram of a display substrate structure;

[0085] Figure 6a shows an equivalent circuit diagram of a pixel driving circuit.

[0086] Figure 6b shows an equivalent circuit diagram of a pixel driving circuit.

[0087] Figure 6c shows an equivalent circuit diagram of a pixel driving circuit.

[0088] Figure 7a is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0089] Figure 7b is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0090] Figure 7c shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0091] Figure 7d is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0092] Figure 8a shows an enlarged structural schematic diagram of position M1 in Figures 7a to 7d;

[0093] Figure 8b shows an enlarged structural schematic diagram of position M1 in Figures 7a to 7d;

[0094] Figure 8c shows an enlarged structural schematic diagram of position M1 in Figures 7a to 7d;

[0095] Figure 8d shows an enlarged structural schematic diagram of position M1 in Figures 7a to 7d;

[0096] Figure 8e shows a cross-sectional structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0097] Figure 9a shows a cross-sectional structural diagram of position C1-C1 in Figures 8a to 8d;

[0098] Figure 9b shows a cross-sectional structural diagram of position C1-C1 in Figures 8a to 8d;

[0099] Figure 9c shows a cross-sectional structural diagram of position C1-C1 in Figures 8a to 8d;

[0100] Figure 9d shows a cross-sectional structural diagram of position C2-C2 in Figures 8a to 8c and 8d.

[0101] Figure 9e shows a cross-sectional structural diagram of position C2-C2 in Figures 8a to 8c and 8d;

[0102] Figure 9f shows a cross-sectional structural diagram of position C2-C2 in Figures 8a to 8c and 8d;

[0103] Figure 9g shows a cross-sectional structural diagram of position C3-C3 in Figures 8a to 8d;

[0104] Figure 9h shows a schematic cross-sectional structure at position C3-C3 in Figures 8a to 8d;

[0105] Figure 9i shows a cross-sectional structure at position C4-C4 in Figure 8a;

[0106] Figure 9j shows a schematic diagram of a cross-sectional structure at position C5-C5 in Figure 8a;

[0107] Figure 9k shows a cross-sectional structural diagram of position C4-C4 in Figures 8b to 8d;

[0108] Figure 9L shows a cross-sectional structural diagram of position C5-C5 in Figures 8b to 8d;

[0109] Figure 9m shows a cross-sectional structural diagram of position C4-C4 in Figures 8b to 8d;

[0110] Figure 9n shows a schematic diagram of a cross-sectional structure at position C5-C5 in Figures 8b to 8d;

[0111] Figure 10a is an enlarged schematic diagram of the position of M2 in Figure 8c;

[0112] Figure 10b is an enlarged schematic diagram of the position of M2 in Figure 8c;

[0113] Figure 10c is a schematic cross-sectional view of the E1-E1 position in Figure 10a;

[0114] Figure 10d is a schematic diagram of the cross-sectional structure at position E1-E1 in Figure 10b;

[0115] Figure 11 is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0116] Figure 12 shows an enlarged structural diagram of position M1 in Figure 11;

[0117] Figure 13 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0118] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The embodiments of this disclosure can be implemented in many different forms. Those skilled in the art will readily understand that the implementation methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0119] In the accompanying drawings, the size of constituent elements, the thickness of layers, or areas may sometimes be exaggerated for clarity. Therefore, any implementation of this disclosure is not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and any implementation of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0120] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, rather than to limit the quantity.

[0121] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships when describing the positional relationships of constituent elements with reference to the accompanying drawings. This is solely for the purpose of facilitating the description of embodiments and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the orientation of the described constituent elements. Therefore, the use of terms not limited to those described herein can be appropriately replaced as appropriate.

[0122] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0123] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (or drain terminal, drain connection region, or drain electrode) and the source electrode (or source terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0124] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" can sometimes be interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged. In this disclosure, the control electrode can be the gate electrode.

[0125] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. The "component having a certain electrical function" can be, for example, an electrode or wiring, a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor.

[0126] Figure 1 shows a schematic diagram of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is connected to multiple data signal lines (D1 to Dn), the scan signal driving circuit is connected to multiple scan signal lines (G1 to Gm), and the light emission signal driving circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines (which may be referred to as data lines). In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driving circuit to the data signal driving circuit, clock signals, scan start signals, etc. of specifications suitable for the scan signal driving circuit to the scan signal driving circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driving circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driving circuit can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driving circuit can sequentially provide scan signals with conduction level pulses to scan signal lines G1 to Gm. For example, a scan signal driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A light-emitting signal driving circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, a light-emitting signal driving circuit can sequentially provide transmit signals with cutoff level pulses to light-emitting signal lines E1 to Eo. For example, a light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0127] Figure 2 shows a schematic diagram of a display panel structure. As shown in Figure 2, the display panel may include a display area AA and a border area BB surrounding the display area AA. In some examples, the border area BB may include: a first border area (lower border) B1 and a second border area (upper border) arranged opposite each other in the second direction Y, and a third border area (left border) B3 and a fourth border area (right border) B4 arranged opposite each other in the first direction X. The first border area B1 is connected to the third border area B3 and the fourth border area B4, and the second border area B2 is connected to the third border area B3 and the fourth border area B4. In some examples, the display area AA may include a first edge (lower edge) and a second edge (upper edge) arranged opposite each other in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) arranged opposite each other in the first direction X. The display area AA may include a plurality of regularly arranged sub-pixels Pxij. The sub-pixels may include pixel driving circuits and light-emitting devices. The first border area B1 may include a bonding circuit that connects signal lines to an external driving device. The third border area B3 and the fourth border area B4 may include gate driving circuits and a second power supply line VSS that transmits voltage signals to the plurality of sub-pixels.

[0128] Figure 3 shows a planar structural diagram of the first bezel region B1. In a plane parallel to the display substrate, the first bezel region B1 may include a first fan-out area 11, a bending area 12, a second fan-out area 13, and a bonding area 14 arranged sequentially along a direction away from the display region AA. The bonding area 14 may include a driver chip area 141, a third fan-out area 142, and a bonding electrode area 143 arranged sequentially along a direction away from the bending area 12 along the second fan-out area 13. The first fan-out area 11 may include data connection lines, a first power connection line, and a second power line. Multiple data connection lines are configured to connect to the display region AA in a fan-out routing manner. The first power line is configured to connect to the display region AA via a high-voltage power line (VDD), and the second power line is a low-voltage power line (VSS) located in the third bezel region B3 and the fourth bezel region B4. The bending area 12 may include a composite insulating layer with grooves, configured to bend the bonding area 14 to the back of the display region AA (as shown in Figure 4). The second fan-out area 13 includes multiple data connection lines led out in a fan-out routing manner. The driver chip area 141 may house an integrated circuit (IC) 20, configured to connect to the multiple data connection lines. The bonding electrode area 143 includes multiple bonding pads, configured to bond to a flexible printed circuit (FPC) 30. In an exemplary embodiment, the integrated circuit (IC) 20 may be bonded to the driver chip area 141, and the flexible printed circuit (FPC) 30 may be bonded to the bonding electrode area 143. In an exemplary embodiment, the integrated circuit 20 (which may be referred to as a data driving circuit or driving circuit) can generate driving signals required to drive sub-pixels and can provide these driving signals to the sub-pixel Pxij located in the display area AA. For example, the driving signal may be a data signal controlling the brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode area 143 may be provided with pads including multiple pins, and the flexible printed circuit 30 may be bonded to the pads.

[0129] In an exemplary embodiment, as shown in FIG4, the bending region 12 can reverse the surface of the bonding region 14, that is, the upward-facing surface of the bonding region 14 can be transformed to face downward by bending the bending region 12. In an exemplary embodiment, when the bending region 12 is bent, the bonding region 14 can overlap with the display region AA in the thickness direction of the display panel.

[0130] In exemplary embodiments, for large-size display substrates, multiple data driver ICs (also known as driver ICs or driver integrated circuits) and multiple FPCs can be provided. The multiple FPCs are respectively bound to and connected to the multiple data driver ICs. For example, n data driver ICs can be respectively bound to n FPCs, where n is a positive integer greater than or equal to 1, such as 4. This disclosure is not limited to four ICs and four FPCs; for example, two data driver ICs and two FPCs can be provided. For small-size display substrates, one or two data driver ICs can be provided. In this disclosure, the number of data driver ICs and FPCs can be set according to the size and functional requirements of the display substrate, and this disclosure does not limit this number.

[0131] In an exemplary embodiment, as shown in FIG5, a schematic diagram of a display substrate is provided. The display area AA may be provided with multiple scan signal lines SL, multiple initial signal lines Vinit, and multiple data signal lines D, including data lines DL0 (the same data signal line D may include the data line DL0 located in the display area AA and the data connection line DL located in the first border area B1). The multiple scan signal lines SL and multiple initial signal lines Vinit may extend along the first direction X and be arranged at intervals along the second direction Y. The multiple data lines DL0 may extend along the second direction Y and be arranged at intervals along the first direction X. Each scan signal line SL may be electrically connected to multiple sub-pixels Pxij in a row of sub-pixels, and each data line DL0 may be electrically connected to multiple sub-pixels in a column of sub-pixels. The third border area B3 and the fourth border area B4 may be provided with multiple gate driving circuits GOA (GOA is an abbreviation for array substrate row driving, and its full English name is Gate Driver on array). The data signal line D includes multiple initial signal supply lines Vinit0 and gate drive circuit signal lines (GOA signal lines). The GOA signal lines may include clock signal lines (e.g., CK signal lines, CB signal lines), start signal lines (e.g., STV signal lines), etc. The gate drive circuit GOA is electrically connected to the corresponding scan signal line SL and provides a scan signal to the corresponding scan signal line SL. The start signal line is configured to provide a start signal to the corresponding gate drive circuit GOA, the clock signal line is configured to provide a clock signal to the corresponding gate drive circuit GOA, and the initial signal line Vinit is configured to provide an initial signal to the corresponding sub-pixel. The data connection lines DL in the data signal line D may include a first data connection line DL1 located in the first fan-out region 11, a second data connection line DL2 located in the bend region 12, and a third data connection line DL3 located in the second fan-out region 13.

[0132] In an exemplary embodiment, as shown in FIG5, the first fan-out region 11 may include multiple first data connection lines DL1, first power connection lines PL11, and second power connection lines PL21. The multiple first data connection lines DL1 may be arranged at intervals approximately along the first direction X. The first power connection lines PL11 and second power connection lines PL21 are located on different conductive layers from the multiple first data connection lines DL1. The first power connection lines PL11 and second power connection lines PL21 may be located on the side of the multiple first data connection lines DL1 away from the substrate. The bending region 12 may include multiple second data connection lines DL2, first power connection structures PL12, and second power connection structures PL22. The multiple second data connection lines DL2, first power connection structures PL12, and second power connection structures PL22 are arranged at intervals along the first direction X. The second data connection lines DL2, first power connection structures PL12, and second power connection structures PL22 in the bending region 12 are usually located on the same conductive layer. Different signal lines need to be arranged at intervals to avoid signal short circuits. The second fan-out region 13 may include multiple third data connection lines DL3, first power signal supply lines VDD0, and second power signal supply lines VDD0. The power signal supply line VSS0, the first power signal supply line VDD0, and the second power signal supply line VSS0 can be located on the same conductive layer, while the third data connection line DL3 and the first power signal supply line VDD0 can be located on different conductive layers; the driver chip area 141 can be provided with an integrated circuit pin group 61, and the driver circuit 20 (e.g., a driver IC) can be bonded to the integrated circuit pin group 61. The end of the third data connection line DL3 away from the second data connection line DL2 can be electrically connected to the integrated circuit bonded pin in the integrated circuit pin group 61; the third fan-out area 142 can... The circuit has multiple pin connection lines 201; the bonding electrode area 143 may have multiple pads, which may include a first power pad 51, a second power pad 52, and a drive pad 53. The integrated circuit pin group 61 can be electrically connected to the drive pad 53 in the bonding electrode area 143 through the pin connection lines 201. The multiple drive pads 53 can be bonded to the flexible circuit board 30 (the flexible circuit board 30 is shown in Figure 4). The first power signal supply line VDD0 can be connected to the first power pad connection 51, and the second power signal supply line VSS0 can be connected to the second power pad 52.

[0133] In an exemplary embodiment, as shown in FIG5, the data line DL0, the first data connection line DL1, the second data connection line DL2, and the third data connection line DL3 can be connected one-to-one. The first power signal supply line VDD0 can be electrically connected to the first power connection line PL11 through the first power connection structure PL12. The second power signal supply line VSS0 can be electrically connected to the second power connection line PL21 through the second power connection structure PL22. The first power connection line PL11 can be connected to the first power line VDD located in the display area. The second power connection line PL21 can be connected to the second power line VSS located in the third border area and the fourth border area. The first power line VDD is electrically connected to multiple sub-pixels, and the second power line VSS is electrically connected to the cathode of the light-emitting element EL.

[0134] In an exemplary embodiment, as shown in FIG5, the gate drive circuit signal line may include a first gate drive circuit signal line 41 and a second gate drive circuit signal line 42. The first gate drive circuit signal line 41 extends from the third frame region B3 to the first frame region B1 and is connected to the first gate drive pad 541 and the gate drive circuit GOA located in the third frame region B3. The second gate drive circuit signal line 42 extends from the fourth frame region B4 to the first frame region B1 and is connected to the second gate drive pad 542 and the gate drive circuit GOA located in the fourth frame region B4. Alternatively, the gate drive circuit GOA may include a first gate drive circuit GOA1 disposed in the third frame region B3 and a second gate drive circuit GOA2 disposed in the fourth frame region B4. The first gate drive circuit GOA1 is configured to be electrically connected to the integrated circuit pin group 61 through the first gate drive circuit signal line 41, and the second gate drive circuit GOA2 is configured to be electrically connected to the integrated circuit pin group 61 through the second gate drive circuit signal line 42. The initial signal supply line Vinit0 located in the third border region B3 and the fourth border region B4 extends to the first border region B1 and is configured to be electrically connected to the integrated circuit pin group 61; the initial signal line Vinit located in the display region AA is connected to the initial signal supply line Vinit0 located in the third border region B3 and the fourth border region V4, and is configured to provide the initial signal from the initial signal supply line Vinit0 to the corresponding sub-pixel Pxij.

[0135] In an exemplary embodiment, at least one sub-pixel Pxij may include a pixel driving circuit and a light-emitting element. Within the same sub-pixel Pxij, the light-emitting element is electrically connected to the pixel driving circuit and configured to emit light under the drive of the pixel driving circuit. The pixel driving circuit may include, but is not limited to, the 7T1C circuit structure shown in FIG6a and the 8T1C circuit structure shown in FIG6b and 6c. The pixel driving circuit is described in detail below with reference to FIG6a to 6c:

[0136] Figure 6a shows an equivalent circuit diagram of a pixel driving circuit. In some examples, as shown in Figure 6a, the pixel driving circuit of this example may include seven transistors (i.e., first transistor T1 to seventh transistor T7) and a storage capacitor Cst. The gate of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 can also be called a driving transistor. The gate of the fourth transistor T4 is electrically connected to the first scan line GL, the first terminal of the fourth transistor T4 is electrically connected to the data signal line D, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the third transistor T3. The fourth transistor T4 can also be called a data writing transistor. The gate of the second transistor T2 is electrically connected to the first scan line GL, the first terminal of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3. The second transistor T2 can also be called a threshold compensation transistor. The gate of the fifth transistor T5 is electrically connected to the light-emitting control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the light-emitting control line EML, the first terminal of the sixth transistor T6 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 can also be referred to as light-emitting control transistors. The gate of the first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first terminal of the first transistor T1 is electrically connected to the first initial signal line Vinit1, and the second terminal of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first terminal of the seventh transistor T7 is electrically connected to the second initial signal line Vinit2, and the second terminal of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first transistor T1 and the seventh transistor T7 can also be referred to as reset control transistors. The first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the first power supply line VDD.

[0137] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0138] In some examples, the first transistor T1 through the seventh transistor T7 can be either P-type or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 through the seventh transistor T7 may include both P-type and N-type transistors.

[0139] In some examples, the first power line VDD can be configured to provide a constant first voltage signal to the pixel circuit, and the second power line VSS can be configured to provide a constant second voltage signal to the pixel circuit, wherein the first voltage signal can be greater than the second voltage signal. The first scan line GL can be configured to provide a scan signal SCAN to the pixel circuit, the data signal line D can be configured to provide a data signal DATA to the pixel circuit, the light emission control line EML can be configured to provide a light emission control signal EM to the pixel circuit, the first reset control line RST1 can be configured to provide a first reset control signal to the pixel circuit, and the second reset control line RST2 can be configured to provide a second reset control signal to the pixel circuit.

[0140] In some examples, the first initial signal line Vinit1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line Vinit2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first and second initial signals can be constant voltage signals, the magnitude of which may be, for example, between the first and second voltage signals, but is not limited thereto. In other examples, the first and second initial signals may be the same.

[0141] In an exemplary embodiment, the pixel driving circuit can also be as shown in Figures 6b and 6c; the difference between Figure 6b and Figure 6a is that an eighth transistor T8 is added, the gate of the eighth transistor T8 is connected to the second node N2, the first terminal of the eighth transistor T8 is connected to the third initial signal line Vinit3, and the gate of the eighth transistor T8 is connected to the third reset control line RST3. The difference between Figure 6c and Figure 6b is that the second terminal of the first transistor T1 is connected to the third node N3. In the pixel driving circuit structure shown in FIG6a, the scan signal line SL in FIG5 may include the first scan line GL, the first reset control line RST1, the second reset control line RST2, and the light emission control line EML in FIG6a. The initial signal line Vinit shown in FIG5 may include the first initial signal line Vinit1 and the second initial signal line Vinit2. In the pixel driving circuit structure shown in FIG6b and FIG6c, the scan signal line SL in FIG5 may include the first scan line GL, the first reset control line RST1, the second reset control line RST2, the third reset control line RST3, and the light emission control line EML in FIG6b and FIG6c. The initial signal line Vinit shown in FIG5 may include the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3.

[0142] In an exemplary embodiment, using different frequencies under different screens can improve power consumption to some extent. In high-precision frequency conversion technology, there are situations where multiple resets are required under one frame. The load (resistance) of the initial signal supply line Vinit0 at multiple reset positions is different, resulting in one or more horizontal lines appearing on the screen. Therefore, it is very important to reduce the load of the initial signal supply line Vinit0.

[0143] This disclosure provides a display substrate, which may include:

[0144] The substrate includes a display area, a first border area, and a first type of border area; in a first direction, the first type of border area is located on at least one side of the display area; in a second direction, the first border area is located on one side of the display area, and the first border area is provided with a bonding area; the first direction intersects the second direction.

[0145] Multiple sub-pixels are located in the display area;

[0146] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels. The multiple data lines extend along the second direction and are arranged at intervals along the first direction.

[0147] Multiple first signal lines are located in the display area, extending along the first direction and arranged along the second direction, and the multiple first signal lines are electrically connected to the multiple sub-pixels;

[0148] At least one first signal providing line group is located in the first type of border area and extends to the binding area in the first border area, wherein the first signal providing line in the first signal providing line group is configured to be electrically connected to at least one of the plurality of first signal lines;

[0149] A plurality of bonded pin groups and at least one integrated circuit pin group are located in the bonded area. The plurality of bonded pin groups include at least one first signal pin group. At least a portion of the integrated circuit pins in the integrated circuit pin group are configured to be electrically connected to the plurality of data lines. In the first direction, the at least one first signal pin group is located on at least one side of the at least one integrated circuit pin group. The at least one first signal pin group corresponds one-to-one with the at least one first signal providing line group. The at least one first signal pin group and the corresponding first signal providing line group are located on the same side of the at least one integrated circuit pin group. At least a portion of the first signal pins in the at least one first signal group are configured to be electrically connected to at least a portion of the first signal providing line in the corresponding first signal providing line group.

[0150] In the display substrate provided in this embodiment, a plurality of bonding pin groups and at least one integrated circuit pin group are provided in the bonding area, and at least one first signal providing line group is provided in the first type of frame area. The first signal providing line in the first type of signal providing line group extends to the bonding area. In a first direction, at least one first signal pin group is located on at least one side of at least one integrated circuit pin group. At least one first signal pin group corresponds one-to-one with at least one first signal providing line group. The first signal pin group and the corresponding first signal providing line group are located on the same side of at least one integrated circuit pin group. At least a portion of the first signal pins in the at least one first signal pin group are configured to be electrically connected to at least a portion of the first signal providing lines in the corresponding first signal providing line group. In the display substrate provided in this embodiment, the first signal providing line is electrically connected to the first signal pin group in the bonding pin group, which can reduce the resistance of the first signal providing line in the bonding area and solve, to a certain extent, the technical problem of horizontal lines appearing in the display area due to the high resistance of the first signal providing line.

[0151] In an exemplary embodiment, the first signal line and the data line are located in different conductive layers.

[0152] As shown in Figures 7a to 8d, Figures 7a to 7d are structural schematic diagrams of a display substrate provided in an embodiment of this disclosure. Figures 8a, 8b, and 8c are enlarged structural schematic diagrams of the M1 position in Figures 7a to 7c, and Figure 8d is an enlarged structural schematic diagram of the M1 position in Figure 7d. The display substrate may include:

[0153] The substrate includes a display area AA, a first border area B1, and a first type border area B01; in the first direction X, the first type border area B01 is located on at least one side of the display area AA; in the second direction Y, the first border area B1 is located on one side of the display area AA, and the first border area B1 is provided with a bonding area 14, and the first direction X intersects with the second direction Y.

[0154] Multiple sub-pixels Pxij are located in the display area AA;

[0155] Multiple data lines DL0 are located in the display area AA and are electrically connected to multiple sub-pixels Pxij. The multiple data lines DL0 extend along the second direction Y and are arranged at intervals along the first direction X.

[0156] Multiple first signal lines VL1 are located in the display area AA, extending along the first direction X and arranged along the second direction Y. The multiple first signal lines VL1 are electrically connected to multiple sub-pixels Pxij. The first signal lines VL1 and data lines DL0 are located in different conductive layers.

[0157] At least one first signal providing line group VL10 is located in the first type of border region B01 and extends to the binding region 14 in the first border region B1. The first signal providing line VL11 in the first signal providing line group VL10 is configured to be electrically connected to at least one of the plurality of first signal lines VL1.

[0158] Multiple bonded pin groups and at least one integrated circuit pin group 61 are located in the bonded region 14. The multiple bonded pin groups include at least one first signal pin group 54. At least a portion of the integrated circuit pins in the integrated circuit pin group 61 are configured to be electrically connected to multiple data lines DL0. In the first direction X, at least one first signal pin group 54 is located on at least one side of at least one integrated circuit pin group 61. At least one first signal pin group 54 corresponds one-to-one with at least one first signal providing line group VL10. At least one first signal pin group 54 and the corresponding first signal providing line group VL10 are located on the same side of at least one integrated circuit pin group 61. At least a portion of the first signal pins in the at least one first signal pin group 54 are configured to be electrically connected to at least a portion of the first signal providing lines VL11 in the corresponding first signal providing line group VL10.

[0159] In an exemplary embodiment, in the first direction X, at least one first signal pin group 54 may be located on at least one side of at least one integrated circuit pin group 61, that is, the first signal pin group 54 is located on the outermost side of the first frame region B1, which can minimize the length of the first signal providing line group VL10 in the bonding region 14 and reduce the resistance of the first signal providing line VL11.

[0160] In an exemplary embodiment, in the second direction Y, a plurality of bonded pin groups are located on the side of integrated circuit pin group 61 away from the display area AA;

[0161] Multiple bonding pin groups may also include at least one drive pin group 53 and at least one power pin group 50. At least one drive pin group 53 corresponds one-to-one with at least one integrated circuit pin group 61, and at least one drive pin group 53 is electrically connected to the corresponding integrated circuit pin group 61. In the first direction X, at least one power pin group 50 is provided between at least one first signal pin group 54 and at least one drive pin group 53. That is, the first signal pin group 54 is located at the outermost edge of the first frame area B1, which can minimize the length of the first signal providing line group VL10 in the bonding area 14 and reduce the resistance of the first signal providing line VL11.

[0162] In an exemplary embodiment, the first type of bezel area B01 is further provided with a plurality of gate drive circuit signal lines 40. The plurality of gate drive circuit signal lines 40 extend to the first bezel area B1. In the same first type of bezel area B01, in the first direction X, the first signal providing line group VL10 is located on the side of the plurality of gate drive circuit signal lines 40 away from the display area AA. That is, the first signal providing line group VL10 is located on the outermost side of the first type of bezel area B01, and the first signal pin group 54 is located on the outermost side of the first bezel area B1. This reduces the distance between the first signal providing line group VL10 and the first signal pin group 54 to a certain extent. This can reduce the routing length of the first signal providing line VL11 in the first signal providing line group VL10 in the bonding area 14, reduce the resistance of the first signal providing line VL11, and to a certain extent overcome the technical problem of horizontal stripes appearing in the display area due to the large resistance of the first signal providing line VL11.

[0163] In an exemplary embodiment, as shown in Figures 7a to 7d, the first type of border region B01 may include a third border region B3 and a fourth border region B4. In the first direction X, the third border region B3 is located on one side of the display region AA, and the fourth border region B4 is located on the other side of the display region AA. At least one first signal providing line group VL10 may include at least a first first signal providing line group VL101 and a second first signal providing line group VL102. The first first signal providing line group VL101 is located in the third border region B3 and extends to the first border region B1. The second first signal providing line group VL102 is located in the fourth border region B4 and extends to the first border region B1.

[0164] At least one first signal pin group 54 may include a first first signal pin group 541 and a second first signal pin group 542, wherein at least a portion of the first signal pins in the first first signal pin group 541 are configured to be electrically connected to at least a portion of the first signal providing lines VL11 in the first first signal providing line group VL101, and at least a portion of the first signal pins in the second first signal pin group 542 are configured to be electrically connected to at least a portion of the first signal providing lines VL11 in the second first signal providing line group VL102;

[0165] In the first direction X, the first first signal pin group 541 and the first first signal providing line group VL101 are located on the same side of at least one drive pin group 53, and the second first signal pin group 542 and the second first signal providing line group VL102 are located on the same side of at least one drive pin group 53.

[0166] In an exemplary embodiment, at least one power pin group 50 includes at least a first power pin group 501 and a second power pin group 502. The bonding region 14 may also include a plurality of voltage signal supply line groups VD. The plurality of voltage signal supply line groups VD may include a first power signal supply line group VD1 and a second power signal supply line group VD2. At least some of the power pins in the first power pin group 501 are electrically connected to at least some of the power signal supply lines in the first power signal supply line group VD1, and at least some of the power pins in the second power pin group 502 are electrically connected to at least some of the power signal supply lines in the second power signal supply line group.

[0167] In the bonding region 14, in the first direction X, a first power pin group 501 and a second power pin group 502 are located on both sides of at least one drive pin group 53, a first power signal supply line group VD1 and a second power signal supply line group VD2 are located on both sides of at least one drive pin group 53, the first power signal supply line group VD1 and the first power pin group 501 are located on the same side of at least one drive pin group 53, and the second power signal supply line group VD2 and the second power pin group 502 are located on the same side of at least one drive pin group 53; a first first signal pin group 54 is located on the side of the first power pin group 501 away from at least one drive pin group 53, and a second first signal pin group 54 is located on the side of the second power pin group 502 away from at least one drive pin group 53.

[0168] In an exemplary embodiment, the plurality of gate drive circuit signal lines 40 may include a plurality of first gate drive circuit signal lines 41 and a plurality of second gate drive circuit signal lines 42. The plurality of first gate drive circuit signal lines 41 are located in the third frame region B3 and extend to the first frame region B1; the plurality of second gate drive circuit signal lines 42 are located in the fourth frame region B4 and extend to the first frame region B1.

[0169] In the bonding region 14, in the first direction X, the first power signal supply line group VD1 and a plurality of first gate drive circuit signal lines 41 are located on the same side of at least one drive pin group 53, and the second power signal supply line group VD2 and a plurality of second gate drive circuit signal lines 42 are located on the same side of at least one drive pin group 53; the first first signal supply line group VL101 is located on the side of the plurality of first gate drive circuit signal lines 41 away from at least one integrated circuit pin group 61, and the second first signal supply line group VL10 is located on the side of the plurality of second gate drive circuit signal lines 42 away from at least one integrated circuit pin group 61, which can reduce the distance between the first signal supply line group VL10 and the corresponding first signal pin group 54, and reduce the resistance of the first signal supply line VL11 in the bonding region.

[0170] In an exemplary embodiment, a plurality of sub-pixels Pxij are disposed on one side of the substrate in a direction perpendicular to the plane of the substrate. At least one of the plurality of sub-pixels Pxij includes a pixel driving circuit and a light-emitting element. The pixel driving circuit includes at least one thin-film transistor and a planarization layer. The planarization layer is located on the side of the thin-film transistor away from the substrate to cover the thin-film transistor. The light-emitting element is located on the side of the planarization layer away from the substrate. The planarization layer includes a first planarization layer via. The thin-film transistor includes an active layer on the substrate, a gate on the side of the active layer away from the substrate, a source and a drain on the side of the gate away from the substrate, and a transition electrode on the side of the source and drain away from the substrate. In the same sub-pixel Pxij, one of the source and drain of one of the thin-film transistors is electrically connected to the transition electrode through a via. The transition electrode is electrically connected to the light-emitting element through the first planarization layer via.

[0171] In the display area AA, the data line DL0 is disposed on the same layer as the transfer electrode, and the first signal line VL1 is disposed on the same layer as at least one of the active layer, source and drain, and gate.

[0172] In the bonding area 14, the power signal supply line in the first signal supply line VL11 and the power signal supply line group VD is disposed in the same layer as at least one of the source and drain electrodes and the transition electrode.

[0173] In an exemplary embodiment, the sub-pixel Pxij may further include at least one capacitor, the first plate of which is disposed in the same layer as the gate of at least one thin-film transistor, and the second plate of which is located between the gate, source and drain of at least one thin-film transistor in a direction perpendicular to the plane of the substrate.

[0174] In the bonding region 14, the first signal supply line VL11 is a multi-layer structure disposed on the same layer as the source and drain, the transition electrode, the gate, and the second plate of the capacitor, and the multi-layer structure is electrically connected.

[0175] In an exemplary embodiment, FIG8e shows a cross-sectional structure of a sub-pixel in pixel region AA. The cross-sectional structure shows a transistor 21 and a capacitor 22 in the pixel driving circuit of the sub-pixel, as well as a light-emitting element connected to the pixel driving circuit. The transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor.

[0176] In some examples, as shown in Figure 8e, in the direction Z perpendicular to the display substrate, the display area AA of the display substrate may include at least: a substrate 100, and a circuit structure layer 120, a light-emitting structure layer 130, and an encapsulation structure layer 140 sequentially disposed on the substrate 100. The circuit structure layer 120 may include at least: pixel circuits for multiple sub-pixels, and the pixel circuit for each sub-pixel may include multiple transistors and at least one capacitor. The light-emitting structure layer 130 may include at least: light-emitting elements for multiple sub-pixels. In other examples, a touch structure layer may be disposed on the side of the encapsulation structure layer away from the substrate 100 to integrate touch functionality.

[0177] In some examples, the circuit structure layer 120 of the display area may include: a shielding layer 200 disposed on the substrate 100, a semiconductor layer, a first conductive layer (also referred to as a first gate metal layer), a second conductive layer (also referred to as a second gate metal layer), a third conductive layer (also referred to as a first source / drain metal layer) and a fourth conductive layer (also referred to as a second source / drain metal layer). A first insulating layer (also called a buffer layer) 101 may be disposed between the shielding layer 200 and the semiconductor layer; a second insulating layer (also called a first gate insulating layer) 102 may be disposed between the semiconductor layer and the first conductive layer; a third insulating layer (also called a second gate insulating layer) 103 may be disposed between the first conductive layer and the second conductive layer; a fourth insulating layer (also called an interlayer insulating layer) 104 may be disposed between the second conductive layer and the third conductive layer; a fifth insulating layer (also called a passivation layer) 105 and a sixth insulating layer (also called a first planarization layer) 106 may be disposed between the third conductive layer and the fourth conductive layer, wherein the sixth insulating layer 106 may be located on the side of the fifth insulating layer 105 away from the substrate 100; and a seventh insulating layer (also called a second planarization layer) 107 may be disposed on the side of the fourth conductive layer away from the substrate 100. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be inorganic insulating layers, while the sixth insulating layer 106 and the seventh insulating layer 107 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, the fifth insulating layer may be omitted between the third and fourth conductive layers, and only the sixth insulating layer may be provided between the third and fourth conductive layers. In an exemplary embodiment, the active layer may be located on the semiconductor layer, the gate and the first electrode of the capacitor may be located on the first conductive layer, the second electrode of the capacitor may be located on the second conductive layer, the source and drain may be located on the third conductive layer, and the transition electrode may be located on the fourth conductive layer.

[0178] In some examples, as shown in FIG8e, the semiconductor layer of the display area may include: the active layer 210 of transistor 21 in the pixel driving circuit. The active layer 210 of transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first conductive layer may include: a first gate 213 of transistor 21 and a first electrode 221 of capacitor 22. The orthographic projection of the first gate 213 of transistor 21 onto the substrate 100 may cover the orthographic projection of the channel region 2100 of active layer 210 onto the substrate 100. The second conductive layer may include: a second electrode 222 of capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of capacitor 22 onto the substrate 100 may at least partially overlap, for example, they may coincide.

[0179] In some examples, as shown in Figure 8e, the third conductive layer of the display area may include a source 211 and a drain 212 of transistor 21. The source 211 of transistor 21 may be electrically connected to the first region 2101 of active layer 210, and the drain 212 may be electrically connected to the second region 2102 of first active layer 210. The fourth conductive layer may include at least a transition electrode 241. The transition electrode 241 may be electrically connected to the drain 212 of transistor 21 of pixel driving circuit through vias formed in fifth insulating layer 105 and sixth insulating layer 106. In this example, the transition electrode 241 enables the electrical connection between pixel driving circuit and light-emitting element.

[0180] In some examples, as shown in Figure 8e, the light-emitting structure layer 130 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131 (which may be referred to as an anode), an organic light-emitting layer 132, and a second electrode 133 (which may be referred to as a cathode). The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on a seventh insulating layer 107 and electrically connected to a transition electrode 241 through a via formed in the seventh insulating layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the seventh insulating layer 107, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0181] In some examples, the organic light-emitting layer 132 of the light-emitting element may include at least one emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0182] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0183] In some examples, as shown in Figure 8e, the encapsulation structure layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density, which can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display substrate and relieve stress on the first and third encapsulation layers 141 and 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0184] In an exemplary embodiment, the difference between FIG8a and FIG8b is that in FIG8a, the first power signal supply line VDD0 and the second power signal supply line VSS0 are arranged on the same layer as the source and drain, while in FIG8b, the first power signal supply line VDD0 and the second power signal supply line VSS0 are arranged on the same layer as the source, drain, and transition electrode.

[0185] In an exemplary embodiment, in Figures 8a to 8d:

[0186] In the first region A1: the first signal supply line VL11 can be a multilayer structure disposed on the same layer as the gate and the second plate of the second capacitor. The multilayer structure can be electrically connected through vias or electrically connected by overlapping. The second power supply connection line PL21 can be disposed on the same layer as at least one of the source, drain, and transition electrodes, as shown in Figure 9a, which is a cross-sectional structural diagram of the C1-C1 position. The second power supply connection line PL21 can be disposed on the same layer as the source and drain. Figure 9b shows another cross-sectional structural diagram of the C1-C1 position. The second power supply connection line PL21 can be a multilayer structure disposed on the same layer as the source, drain, and transition electrodes. The multilayer structure can be electrically connected through vias. Figure 9c shows another cross-sectional structural diagram of the C1-C1 position. The second power supply connection line PL21 can be a multilayer structure disposed on the same layer as the source, drain, and transition electrodes. The multilayer structure is electrically connected by overlapping.

[0187] In the second region A2 and the third region A3 (regions where the gate drive circuit signal line 40 and the power signal supply line group 50 do not overlap): the gate drive circuit signal line 40 and the first signal supply line VL11 can be a single-layer or multi-layer structure disposed on the same layer as at least one of the gate, the second plate of the capacitor, the source and drain, and the transition electrode. The multi-layer structure can be electrically connected by vias or by overlapping. Figures 9d to 9f show several cross-sectional structural diagrams of the C2-C2 position in Figures 8a to 8b and Figure 8d, and Figures 9g and 9h show several cross-sectional structural diagrams of the C3-C3 position in Figures 8a to 8d. As shown in Figures 9d and 9g, the gate drive circuit signal line 40 can be disposed on the same layer as the gate, the second plate of the capacitor, the source and drain, and the transition electrode. The second electrode plate is disposed in the same layer as the multilayer structure; as shown in Figures 9e and 9h, the gate drive circuit signal line 40 can be a multilayer structure disposed in the same layer as the gate, the second electrode plate of the capacitor, the source and the drain; as shown in Figure 9f, the gate drive circuit signal line 40 can be a multilayer structure disposed in the same layer as the gate, the second electrode plate of the capacitor, the source and the drain, and the transition electrode; as shown in Figure 9d, the first signal supply line VL11 can be a single-layer structure disposed in the same layer as the source and the drain; as shown in Figure 9e, the first signal supply line VL11 can be a multilayer structure disposed in the same layer as the gate, the second electrode plate of the capacitor, the source and the drain; as shown in Figure 9f, the first signal supply line VL11 can be a multilayer structure disposed in the same layer as the gate, the second electrode plate of the capacitor, the source and the drain, and the transition electrode;

[0188] In the region where the gate drive circuit signal line 40 overlaps with the power signal supply line in the power signal supply line group 50: Figure 9i shows a cross-sectional view of position C4-C4 in Figure 8a, and Figure 9j shows a cross-sectional view of position C5-C5 in Figure 8a. The gate drive circuit signal line 40 can be a multi-layer structure (the multi-layer structure can be connected through vias) disposed on the same layer as the gate and the second plate of the capacitor. The first power signal supply line VDD0 and the second power signal supply line VSS0 in the power signal supply line group 50 can be a single-layer structure disposed on the same layer as the source and drain. Figure 9k shows a cross-sectional view of position C4-C4 in Figures 8b to 8d, and Figure 9L shows a cross-sectional view of position C5-C5 in Figures 8b to 8d. The gate drive circuit signal line 40 can be on the same layer as the gate and the second plate of the capacitor. The multi-layer structure is configured (the multi-layer structure can be connected via vias). The first power signal supply line VDD0 and the second power signal supply line VSS0 in the power signal supply line group 50 can be multi-layer structures configured on the same layer as the source, drain, and transition electrodes (the multi-layer structure can be electrically connected vias). Figure 9m shows another cross-sectional structure at position C4-C4 in Figures 8b to 8d, and Figure 9n shows another cross-sectional structure at position C5-C5 in Figures 8b to 8d. The gate drive circuit signal line 40 can be a multi-layer structure configured on the same layer as the gate and the second plate of the capacitor (the multi-layer structure can be connected vias). The first power signal supply line VDD0 and the second power signal supply line VSS0 in the power signal supply line group 50 can be multi-layer structures configured on the same layer as the source, drain, and transition electrodes (the multi-layer structure can be electrically connected vias).

[0189] In an exemplary embodiment, the bonding area 14 may include a driver chip area 141, a third fan-out area 142, and a bonding electrode area 143 arranged sequentially along the display area AA to the first border area B1. The integrated circuit pin group 61 is located in the driver chip area 141, the bonding pin group is located in the bonding electrode area 143, and the third fan-out area 142 is provided with a plurality of pin connection lines 201. The integrated circuit pins in the integrated circuit pin group 61 are electrically connected to the driving pins in the driver pin group 53 through the pin connection lines 201.

[0190] In an exemplary embodiment, in the structures shown in Figures 7a to 7c and 8a to 8c, in the bonding region 14, a plurality of first gate drive circuit signal lines 41 bend along the third border region B3 in the direction pointing to the display region AA, and are electrically connected to the integrated circuit pin group 61 closest to the first power signal supply line group VD1; a plurality of second gate drive circuit signal lines 42 bend along the fourth border region B4 in the direction pointing to the display region AA, and are electrically connected to the integrated circuit pin group 61 closest to the second power signal supply line group VD2;

[0191] In the bonding region 14, at least a portion of the structure of the first gate drive circuit signal line 41 at least partially overlaps with the orthographic projection of the power signal supply line in the first power signal supply line group VD1 onto the substrate, and the first gate drive circuit signal line 41 and the power signal supply line in the first power signal supply line group VD1 are located in different conductive layers in the overlapping region; at least a portion of the structure of the second gate drive circuit signal line 42 at least partially overlaps with the orthographic projection of the power signal supply line in the second power signal supply line group VD2 onto the substrate, and the plurality of second gate drive circuit signal lines 42 and the power signal supply lines in the second power signal supply line group VD2 are located in different conductive layers in the overlapping region.

[0192] In an exemplary embodiment, as shown in FIG8c, at least a portion of the structure between the first gate drive circuit signal line 41 at the bend position M3 and the integrated circuit pin group 61 to which it is connected at least partially overlaps with the orthographic projection of the power signal supply line in the first power signal supply line group VD1 onto the substrate. The first gate drive circuit signal line 41 and the power signal supply line in the first power signal supply line group VD1 are located in different conductive layers in the overlapping region. At least a portion of the structure between the second gate drive circuit signal line 42 at the bend position M3 and the corresponding integrated circuit pin group 61 at least partially overlaps with the orthographic projection of the power signal supply line in the second power signal supply line group VD2 onto the substrate. The plurality of second gate drive circuit signal lines 42 and the power signal supply lines in the second power signal supply line group VD2 are located in different conductive layers in the overlapping region.

[0193] In an exemplary embodiment, in the structure shown in FIG7d and FIG8d, the plurality of bonded pin groups may further include at least one gate drive circuit pin group 56, and the at least one gate drive circuit pin group 56 may include a first gate drive circuit pin group 561 and a second gate drive circuit pin group 562.

[0194] In the first direction X, the first first signal pin group 541 is located on the side of the first gate drive circuit pin group 561 away from the first power supply pin group 501, and the second first signal pin group 542 is located on the side of the second gate drive circuit pin group 562 away from the second power supply pin group 502.

[0195] The first gate drive circuit signal line 41 is configured to be electrically connected to the corresponding first gate drive circuit pin in the first gate drive circuit pin group 561, and the second gate drive circuit signal line 42 is configured to be electrically connected to the corresponding second gate drive circuit pin in the second gate drive circuit pin group 562. This can reduce the routing distance between the gate drive circuit signal line 40 and the gate drive circuit pin group 56, and reduce the resistance of the gate drive circuit signal line 40.

[0196] In the bonding region 14, at least a portion of the structure in at least a portion of the gate drive circuit signal line 40 has a non-overlapping area with the power signal supply line in the power signal supply line group AD.

[0197] In an exemplary embodiment, in the bonding region 14, in the area where the gate drive circuit signal line 40 overlaps with the power supply signal line, the gate drive circuit signal line 40 can be a multilayer structure disposed on the same layer as the gate and the second plate of the capacitor, as shown in Figures 9i to 9n; in at least a portion of the area where the gate drive circuit signal line 40 does not overlap with the power supply signal line, the gate drive circuit signal line 40 can be a multilayer structure disposed on the same layer as the source and drain, the transition electrode, the gate, and the second plate of the capacitor (the structure of the gate drive circuit signal line 40 can be as shown in Figure 9f). The multilayer structure can be electrically connected. Setting the gate drive circuit signal line 40 as a multilayer structure can reduce resistance and improve the display effect of the display substrate.

[0198] In an exemplary embodiment, along the direction from the display area AA to the first border area B1, the first border area B1 includes a first fan-out area 11, a bending area 12, a second fan-out area 13, and a binding area 14 arranged sequentially.

[0199] In the first fan-out region 11, the first signal supply line VL11, the multiple first gate drive circuit signal lines 41, and the multiple second gate drive circuit signal lines 42 are a multi-layer structure disposed on the same layer as the gate and the second plate of the capacitor, and the multi-layer structure is electrically connected; as shown in Figures 9a to 9c.

[0200] In the second fan-out region 13, the first signal supply line, a plurality of first gate drive circuit signal lines 41, a plurality of second gate drive circuit signal lines 42 are disposed on the same layer as at least one of the gate, the second plate of the capacitor, the source and drain, and the transition electrode (as shown in Figures 9d to 9f). In the first direction X, on the same side of the plurality of drive pin groups 53, the first signal supply line VL11 and the gate drive circuit signal line 40 are located on the side of the power supply signal supply line group 50 away from the plurality of drive pin groups 53.

[0201] In an exemplary embodiment, the same power signal supply line group 50 may include a first power signal supply line VDD0 and a second power signal supply line VSS0. The first fan-out area 11 is also provided with at least one first power connection line PL11, at least one second power connection line PL21, and a plurality of first data connection lines DL1. The bending area 12 is also provided with at least one first power connection structure PL12, at least one second power connection structure PL22, and a plurality of second data connection lines DL2. The second fan-out area 13 is also provided with a plurality of third data connection lines DL3. The first power signal supply line VDD0 and the second power signal supply line VSS0 extend from the bonding area 14 to the second fan-out area 13.

[0202] The first power connection structure PL12 is configured to electrically connect the first power connection line PL11 to the corresponding first power signal supply line VDD0, and the second power connection structure PL22 is configured to electrically connect the second power connection line PL21 to the corresponding second power signal supply line VSS0.

[0203] Multiple data lines DL0, multiple first data connection lines DL1, multiple second data connection lines DL2, and multiple third data connection lines DL3 are corresponding one-to-one. Data line DL0 is electrically connected to the corresponding integrated circuit pin in the corresponding integrated circuit bonding pin group 61 through the corresponding first data connection line DL1, the corresponding second data connection line DL2, and the corresponding third data connection line DL3.

[0204] In an exemplary embodiment, in the first fan-out region 11, a plurality of first data connection lines DL1 are multi-layer structures disposed on the same layer as the gate and the second plate of the capacitor, and the first power connection line PL11 and the second power connection line PL21 are multi-layer structures disposed on the same layer as the source, drain and transition electrode, and the multi-layer structures are electrically connected, as shown in Figures 9b and 9c.

[0205] In the bending area 12, the third data connection line DL3, the first power connection structure PL12, the second power connection structure PL22, the first signal supply line VL11, and the gate drive circuit signal line 40 are arranged on the same layer as the source and drain, and different signal lines are spaced apart.

[0206] In the second fan-out area 13, the third data connection line DL3 is disposed on the same layer as at least one of the gate and the second plate of the capacitor.

[0207] In an exemplary embodiment, in the structures shown in Figures 7a, 7c to 7d, in the bending region 12, the dimension of the first power connection structure PL12 along the first direction X is the same as the dimension of the third data connection line DL3 along the first direction X, and the first power connection structure PL12 and the third data connection line DL3 can be arranged alternately; in the structure shown in Figure 7b, in the bending region 12, the dimensions of multiple first power connection structures PL12 along the first direction X are greater than the dimensions of the third data connection line DL3 along the first direction X.

[0208] In an exemplary embodiment, in the structure shown in FIG7c, each drive pin group 53 has two power signal supply line groups 50 on both sides. In the first fan-out area 11, a first power connection line PL11 corresponds to one of the drive pin groups 53 and the first power signal supply lines VDD0 on both sides of the drive pin group 53, and is electrically connected to the corresponding first power signal supply lines VDD0, but is not connected to the first power signal supply lines VDD0 on both sides of other drive pin groups 53. In the structure shown in FIG7d, the first frame area B1 is provided with only two power signal supply line groups 50 (the first power signal supply line group 501 and the second power signal supply line group 502). In the first fan-out area 11, the first power connection line PL11 is electrically connected to the first power signal supply line VDD0 in the first power signal supply line group 501 and the second power signal supply line group.

[0209] In an exemplary embodiment, in the second fan-out region 13, the third data connection line DL3 can be a multi-layer structure disposed on the same layer as the gate and the second plate of the capacitor. The first signal providing line VL11, the multiple first gate drive circuit signal lines 41, and the multiple second gate drive circuit signal lines 42 can be multi-layer structures disposed on the same layer as the gate, the second plate of the capacitor, the source and drain, and the transition electrode (as shown in Figure 9f). The multi-layer structure is electrically connected.

[0210] In an exemplary embodiment, the first signal pins in the two first signal pin groups 54 are of the same type, the first signal providing line VL11 in the first first signal providing line group VL101 and the second first signal providing line group VL102 are of the same type, and the same first signal line VL1 is electrically connected to the corresponding first signal providing line VL11 in the first first signal providing line group VL101 and the second first signal providing line group VL102.

[0211] In an exemplary embodiment, the plurality of first signal lines VL1 may include a plurality of initial signal lines Vinit, at least one first signal providing line group VL10 includes at least one initial signal providing line group Vinit0, and at least one first signal pin group 54 includes at least one initial signal pin group, which includes at least one initial signal pin.

[0212] The same initial signal pin group includes at least one initial signal pin, and the initial signal providing line in at least one initial signal providing line group Vinit0 and the multiple initial signal lines Vinit include at least one type. The types of initial signal providing lines, initial signal lines, and initial signal pins are in one-to-one correspondence, and the initial signal providing lines are electrically connected to the corresponding types of initial signal lines and initial signal pins.

[0213] In an exemplary embodiment, the types of initial signal providing lines and initial signal lines Vinit in the initial signal providing line group Vinit0 may include n, where n is a positive integer greater than or equal to 1. As shown in FIG10a, the types of initial signal providing lines in the initial signal providing line group Vinit0 may include a first initial signal providing line Vinit01, a second initial signal providing line Vinit02, and a third initial signal providing line Vinit03.

[0214] In an exemplary embodiment, as shown in Figures 10a to 10c, the first fan-out area 11 may further include at least one first signal connection structure L1; the same first signal pin group 54 includes at least one first signal pin, the first signal providing line VL11 and the types of multiple first signal lines VL1 include at least one, the types of first signal providing line VL11, the types of first signal lines VL1, and the types of first signal pins correspond one-to-one, and the first signal providing line VL11 is electrically connected to the corresponding type of first signal line VL1 and the corresponding type of first signal pin;

[0215] In the first border region B1, among at least one first signal providing line VL11, the number of first signal providing lines VL11 of the same type is at least two. In the first fan-out region 11, at least two first signal providing lines VL11 of the same type are electrically connected through corresponding first signal connection structures L1. In the region where the first signal connection structure L1 is connected to the corresponding first signal providing line VL11, the first signal providing line is disposed on the same layer as one of the second plates of the gate and the capacitor, and the first signal connection structure L1 is disposed on the same layer as the other of the second plates of the gate and the capacitor. The first signal connection structures L1 corresponding to different types of first signal providing lines VL11 are spaced apart.

[0216] Figures 10a and 10b show an enlarged structural diagram of position M2 in Figure 8c. The first signal providing line VL11 may include a first initial signal providing line Vinit01, a second initial signal providing line Vinit02, and a third initial signal providing line Vinit03. In the first border area B1, there are two of each of the first initial signal providing lines Vinit01, Vinit02, and Vinit03. Correspondingly, the first signal connection structure L1 may include a first initial signal connection structure Vinit01L, a second initial signal connection structure Vinit02L, and a third initial signal connection structure Vinit03L. The two first initial signal providing lines Vinit01 are connected in parallel through the first initial signal connection structure Vinit01L. Two second initial signal providing lines Vinit02 are connected in parallel through a second initial signal connection structure Vinit02L, and two third initial signal providing lines Vinit03 are connected in parallel through a third initial signal connection structure Vinit03L. The first initial signal connection structure Vinit01L can be electrically connected to the two first initial signal providing lines Vinit01 through a via VM, the second initial signal connection structure Vinit02L can be electrically connected to the two second initial signal providing lines Vinit02 through a via VM, and the third initial signal connection structure Vinit03L can be electrically connected to the two third initial signal providing lines Vinit03 through a via VM. Figure 10c shows a cross-sectional view of the structure at position E1-E1 in Figure 10a, and Figure 10d shows a cross-sectional view of the structure at position E1-E1 in Figure 10b.

[0217] In an exemplary embodiment, the first signal providing lines VL11 of the same type in the border area are configured as at least two parallel structures, which can reduce the resistance of the first signal providing lines VL11.

[0218] In the structure shown in Figure 10a, there are two of the same type of first signal providing lines VL11 in both the first type of border region B01 (which may include the third border region B3 and the fourth border region B4) and the first border region B1; in the structure shown in Figure 10b, there is one of the same type of first signal providing lines VL11 in the first type of border region B01 (which may include the third border region B3 and the fourth border region B4) and two in the first border region B1, which can save space in the first type of border region B01.

[0219] The first signal providing line VL11 shown in Figures 10b to 10d includes the first initial signal providing line Vinit01, the second initial signal providing line Vinit02, and the third initial signal providing line Vinit03. Correspondingly, the first signal line VL1 in the display area AA may include the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 (i.e., the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 shown in Figures 6b and 6c). The first initial signal providing line Vinit01 can be electrically connected to multiple first initial signal lines Vinit1, the second initial signal providing line Vinit02 can be electrically connected to multiple second initial signal lines Vinit2, and the third initial signal providing line Vinit03 can be electrically connected to multiple third initial signal lines Vinit3.

[0220] In an exemplary embodiment, the pixel driving circuits of multiple sub-pixels can form multiple rows and multiple columns, each first signal line VL1 can be electrically connected to at least a portion of the pixel driving circuits in at least one row of pixel driving circuits, and each data line DL0 can be electrically connected to at least a portion of the pixel driving circuits in at least one column of pixel driving circuits.

[0221] In an exemplary embodiment, as shown in FIG7a, the display area AA is further provided with a plurality of first signal connection lines SVL1. The first signal connection lines SVL1 are disposed on the same layer as the adapter electrode. The plurality of first signal connection lines SVL1 are arranged at intervals along the first direction X and extend along the second direction Y. The types of the plurality of first signal connection lines SVL1 correspond one-to-one with the types of the plurality of first signal lines VL1. The first signal connection lines SVL1 are electrically connected to the plurality of first signal lines VL1 of the corresponding type through vias. The same first signal line VL1 is electrically connected to the plurality of first signal connection lines SVL1 of the corresponding type through vias, so that the plurality of first signal connection lines SVL1 of the same type and the plurality of first signal connection lines SVL1 in the display area AA are interconnected to form a grid structure, thereby reducing the voltage drop of the first signal lines VL1 and improving the display uniformity.

[0222] In an exemplary embodiment, the integrated circuit pins in the integrated circuit pin group 61 and the bonding pins in the bonding pin group can be multi-layer structures disposed on the same layer as the source, drain, and transition electrodes. The multi-layer structure is electrically connected, which can reduce the resistance of the integrated circuit pins and the bonding pins.

[0223] In an exemplary embodiment, the third border region B3 may further include a plurality of first gate driving circuits GOA1, and the fourth border region B4 may further include a plurality of second gate driving circuits GOA2.

[0224] Multiple first gate drive circuits GOA1 can be arranged along the direction of extension of the third frame region B3, and multiple second gate drive circuits GOA2 can be arranged along the direction of extension of the fourth frame region B4. The first gate drive circuit signal line 41 is also electrically connected to the multiple first gate drive circuits GOA1, and the second gate drive circuit signal line 42 is also electrically connected to the multiple second gate drive circuits GOA2.

[0225] In the first direction X, in the third frame region B3, at least one first signal providing line VL11 is located on the side of the plurality of first gate driving circuits GOA1 away from the display region AA; in the fourth frame region B4, at least one first signal providing line VL11 is located on the side of the plurality of second gate driving circuits GOA2 away from the display region AA.

[0226] In an exemplary embodiment, the display area AA further includes multiple scan signal lines SL, which extend along a first direction X and are arranged along a second direction Y;

[0227] The first gate drive circuit GOA1 and the second gate drive circuit GOA2 are configured to be electrically connected to the corresponding scan signal line SL. The scan signal line SL can be disposed on the same layer as at least one of the gate and the second plate of the capacitor.

[0228] In an exemplary embodiment, the multiple scan signal lines SL may include a first reset control line RST1, a second reset control line RST2, an emission control line EML, a first scan line GL as shown in Figures 6a to 6c, and a third reset control line RST3 as shown in Figure 6b. In the first type of frame region B01, each gate drive circuit GOA may be configured to provide a signal to one of the first reset control line RST1, the second reset control line RST2, the emission control line EML, the first scan line GL, and the third reset control line RST3.

[0229] In an exemplary embodiment, the gate drive circuit signal line 40 may include a clock signal line (e.g., a CK signal line and a CB signal line) and a start signal line (e.g., an STV signal line), and the gate drive circuit signal line 40 is configured to provide a signal to the gate drive circuit GOA.

[0230] This disclosure also provides a display substrate, as shown in Figures 11 and 12. Figure 12 is an enlarged schematic diagram of the position M1 in Figure 11. The display substrate may include:

[0231] The substrate includes a display area AA, a first border area B1, and a first type border area B01; in the first direction X, the first type border area B01 is located on at least one side of the display area AA; in the second direction Y, the first border area B1 is located on one side of the display area AA, and the first border area B1 is provided with a bonding area 14, and the first direction X intersects with the second direction Y.

[0232] Multiple sub-pixels Pxij are located in the display area AA;

[0233] Multiple data lines DL0 are located in the display area AA and are electrically connected to multiple sub-pixels Pxij. The multiple data lines DL0 extend along the second direction Y and are arranged at intervals along the first direction X.

[0234] Multiple first signal lines VL1 are located in the display area AA, extending along the first direction X and arranged along the second direction Y. The multiple first signal lines VL1 are electrically connected to multiple sub-pixels Pxij. In an exemplary embodiment, the first signal lines VL1 and the data lines DL0 can be located in different conductive layers.

[0235] At least one first signal providing line group VL10 is located in the first type of border region B01 and extends to the binding region 14 in the first border region B1. The first signal providing line VL11 in the first signal providing line group VL10 is configured to be electrically connected to at least one of the plurality of first signal lines VL1.

[0236] At least one integrated circuit pin group 61 is located in the bonding region 14, and at least a portion of the integrated circuit pins in the integrated circuit pin group 61 are configured to be electrically connected to a plurality of data lines DL0;

[0237] In the bonding region 14, in the first direction X, the main body of at least one first signal providing line group VL10 is located on at least one side of at least one integrated circuit pin group 61, and at least a portion of the first signal providing line VL11 has a multilayer structure that can be electrically connected.

[0238] In an exemplary embodiment, at least a portion of the structure of the first signal providing line VL11 is an electrically connected multilayer structure, which can reduce the resistance of the first signal providing line VL11 and prevent horizontal stripes from appearing in the display area due to the high resistance of the first signal providing line VL11.

[0239] In an exemplary embodiment, the first type of frame region B01 is further provided with a plurality of gate drive circuit signal lines 40, which extend to the bonding region 14 in the first frame region B1.

[0240] In the bonding region 14, in the first direction X, the main body of the gate drive circuit signal line 40 is located on at least one side of at least one integrated circuit pin group 61, on the same side of the first center line O1-O1. The first signal providing line VL11 in the first signal providing line group VL10 and the gate drive circuit signal line are electrically connected to the integrated circuit pin group 61 farthest from the first center line. The first center line O1-O1 is the center line extending from the first border region B1 along the second direction Y.

[0241] In the bonding region 14, at least a portion of the gate drive circuit signal lines 40 have a multilayer structure, and the multilayer structure can be electrically connected.

[0242] In an exemplary embodiment, in the bonding region 14, at least a portion of the gate drive circuit signal line 40 has a multilayer structure located between the source / drain metal layer and the gate metal layer, which can reduce the resistance of the gate drive circuit signal line 40.

[0243] In an exemplary embodiment, the bonding region 14 further includes at least one power signal supply line group 50, which is located on at least one side of at least one integrated circuit pin group 61 in the first direction X.

[0244] In the bonding region 14, on the same side of the first center line O1-O1 in the first direction X, the gate drive circuit signal line 40 and the first signal supply line VL11 are bent along the direction from the first type of frame region B01 toward the display region AA, and are electrically connected to the integrated circuit pin group 61 farthest from the first center line O1-O1. At least a portion of the structure of the gate drive circuit signal line 40 and the first signal supply line VL11 (for example, it can be at least a portion of the structure between the gate drive circuit signal line 40 and the first signal supply line VL11 at the bending position M3 and the integrated circuit pin group 61 to which they are connected, as shown in FIG. 12) at least partially overlaps with the orthographic projection of the power signal supply line group 50 on the substrate. The gate drive circuit signal line 40 and the first signal supply line VL11 and the power signal supply line in the power signal supply line group 50 are located in different conductive layers in the overlapping region.

[0245] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the display substrate includes at least a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially disposed on one side of the substrate;

[0246] In the display area AA, the data line DL0 is located in the second source-drain metal layer, and the first signal line VL1 can be located in at least one conductive layer of the first gate metal layer, the second gate metal layer, and the first source-drain metal layer.

[0247] In the bonding region 14, the first signal line VL1 and the gate drive circuit signal line 40 can be located in at least one conductive layer among the first gate metal layer, the second gate metal layer, and the first source / drain metal layer.

[0248] In an exemplary embodiment, at least a portion of the gate of the transistor may be located in the first gate metal layer, the second plate of the capacitor may be located in the second gate metal layer, the source and drain may be located in the first source-drain metal layer, and the transition electrode may be located in the second source-drain metal layer. In an exemplary embodiment, the display substrate may further include a third gate metal layer and a third source-drain metal layer. In a direction perpendicular to the plane of the substrate, the third gate metal layer may be located between the second gate metal layer and the first source-drain metal layer. The third source-drain metal layer may be located on the side of the second source-drain metal layer away from the substrate, and the third source-drain metal layer may have at least a portion of the transistor's gate.

[0249] In an exemplary embodiment, in 12, the cross-sectional structural schematic diagram at position C1-C1 can be shown in Figures 9a and 9c, the cross-sectional structural schematic diagram at position C2-C2 can be shown in Figures 9d to 9f, the cross-sectional structural schematic diagram at position C3-C3 can be shown in Figures 9g to 9h, the cross-sectional structural schematic diagram at position C4-C4 can be shown in Figures 9k and 9m, and the cross-sectional structural schematic diagram at position C5-C5 can be shown in Figures 9L and 9n.

[0250] In an exemplary embodiment, along the direction from the display area AA to the first border area B1, the first border area B1 may include a first fan-out area 11, a bending area 12, a second fan-out area 13 and a binding area 14 arranged sequentially.

[0251] In the first fan-out region 11 and the bonding region 14, at least a portion of the first signal supply line VL11 and the gate drive circuit signal line 40 overlap with the power supply signal supply line. The first signal supply line VL11 and the gate drive circuit signal line 40 are multilayer structures located in the first gate metal layer and the second gate metal layer. The multilayer structures can be electrically connected, as shown in Figures 9a to 9c and Figures 9k to 9n.

[0252] In the second fan-out region 13 and the bonding region 14, in at least a portion of the area where the first signal supply line VL11 and the gate drive circuit signal line 40 do not overlap with the power supply signal supply line, the first signal supply line VL11 and the gate drive circuit signal line 40 are multi-layer structures located in the first gate metal layer, the second gate metal layer, the first source drain metal layer and the second source drain metal layer. The multi-layer structures can be electrically connected, as shown in Figure 9f.

[0253] In an exemplary embodiment, the power signal supply line in the power signal supply line group 50 extends from the bonding region 14 to the second fan-out region 13;

[0254] In at least a portion of the second fan-out region 13 and the bonding region 14, the power signal supply lines in the power signal supply line group 50 can be a multilayer structure located in the first source / drain metal layer and the second source / drain metal layer, and the multilayer structure can be electrically connected, as shown in Figures 9k to 9n.

[0255] In an exemplary embodiment, the power signal supply line in the power signal supply line group 50 can be a three-layer structure located in the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer.

[0256] In an exemplary embodiment, in the first fan-out region 11 and the bonding region 14, at least a portion of the area where the first signal supply line VL11 and the gate drive circuit signal line 40 overlap with the power supply signal line can be a multilayer structure located in the first gate metal layer, the second gate metal layer, and the third gate metal layer, and the multilayer structure can be electrically connected.

[0257] In an exemplary embodiment, in the second fan-out region 13 and the bonding region 14, in at least a portion of the area where the first signal supply line VL11 and the gate drive circuit signal line 40 do not overlap with the power supply signal supply line, the first signal supply line VL11 and the gate drive circuit signal line 40 can be a multilayer structure located in the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source drain metal layer, the second source drain metal layer, and the third gate metal layer, and the multilayer structure can be electrically connected.

[0258] In an exemplary embodiment, the electrical connection between the multi-layer structures can be achieved by the multi-layer structures being electrically connected through vias, or by the multi-layer structures being electrically connected by overlapping.

[0259] In an exemplary embodiment, the first region A1, the second region A2, and the third region A3 in FIG12 have the same structure as the first region A1, the second region A2, and the third region A3 shown in FIG8a to FIG8d above, and will not be described again here.

[0260] In an exemplary embodiment, the first signal supply line VL11 may be the initial signal supply line Vinit0, or other constant voltage signal lines, such as the second power supply line VSS.

[0261] In an exemplary embodiment, the power supply pin group 50 may include a first power supply pin 51 and a second power supply pin 52. The first power supply pin 51 is configured to be connected to a first power signal supply line VDD0, and the second power supply pin 52 is configured to be connected to a second power signal supply line VSS0.

[0262] In an exemplary embodiment, as shown in Figures 8a to 8d and Figure 12, the bonding pin group may further include a test pin group 55, and the driver chip area 141 may also be provided with a test circuit 71. The test circuit 71 may be electrically connected to the corresponding test pin in the test pin group 55 through test leads 81. At least a portion of the gate drive circuit signal lines 40 may also be electrically connected to the corresponding test pin in the test pin group 55 through test leads 81.

[0263] In an exemplary embodiment, the display substrate may be a symmetrical structure relative to O1-O1 (it may be approximately symmetrical).

[0264] This disclosure also provides a display device, as shown in FIG13, which may include a display substrate.

[0265] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0266] In one exemplary embodiment, the display device can be a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED), or a Light Emitting Diode (LED) display device. The display device can be any product or component with display functionality, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0267] The display substrate and display device provided in this disclosure have multiple bonding pin groups and at least one integrated circuit pin group in the bonding area, and at least one first signal providing line group in the first type of bezel area. The first signal providing line in the first type of signal providing line group extends to the bonding area. In a first direction, at least one first signal pin group is located on at least one side of at least one integrated circuit pin group. At least one first signal pin group corresponds one-to-one with at least one first signal providing line group. The first signal pin group and the corresponding first signal providing line group are located on the same side of at least one integrated circuit pin group. At least a portion of the first signal pins in the at least one first signal pin group are configured to be electrically connected to at least a portion of the first signal providing lines in the corresponding first signal providing line group. In the display substrate provided in this disclosure, the first signal providing line is directly electrically connected to the first signal pin group, which can reduce the resistance of the first signal providing line in the bonding area and solve, to a certain extent, the technical problem of horizontal lines appearing in the display area due to the high resistance of the first signal providing line.

[0268] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0269] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0270] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit them. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The substrate includes a display area, a first border area, and a first type of border area; In a first direction, the first type of border area is located on at least one side of the display area; In the second direction, the first border area is located on one side of the display area, the first border area is provided with a binding area, and the first direction intersects with the second direction; Multiple sub-pixels are located in the display area; Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels. The multiple data lines extend along the second direction and are arranged at intervals along the first direction. Multiple first signal lines are located in the display area, extending along the first direction and arranged along the second direction, and the multiple first signal lines are electrically connected to the multiple sub-pixels; At least one first signal providing line group is located in the first type of border area and extends to the binding area in the first border area, wherein the first signal providing line in the first signal providing line group is configured to be electrically connected to at least one of the plurality of first signal lines; A plurality of bonded pin groups and at least one integrated circuit pin group are located in the bonded area. The plurality of bonded pin groups include at least one first signal pin group. At least a portion of the integrated circuit pins in the integrated circuit pin group are configured to be electrically connected to the plurality of data lines. In the first direction, the at least one first signal pin group is located on at least one side of the at least one integrated circuit pin group. The at least one first signal pin group corresponds one-to-one with the at least one first signal providing line group. The at least one first signal pin group and the corresponding first signal providing line group are located on the same side of the at least one integrated circuit pin group. At least a portion of the first signal pins in the at least one first signal group are configured to be electrically connected to at least a portion of the first signal providing line in the corresponding first signal providing line group.

2. The display substrate according to claim 1, wherein, in the second direction, the plurality of bonding pin groups are located on the side of the integrated circuit pin group away from the display area; The plurality of bonded pin groups further includes at least one drive pin group and at least one power pin group, wherein the at least one drive pin group corresponds one-to-one with the at least one integrated circuit pin group and is electrically connected to the corresponding integrated circuit pin group; in the first direction, at least one power pin group is provided between the at least one first signal pin group and the at least one drive pin group.

3. The display substrate according to claim 2, wherein the first type of bezel area is further provided with a plurality of gate driving circuit signal lines, the plurality of gate driving circuit signal lines extending to the first bezel area, and in the same first type of bezel area, in the first direction, the first signal providing line group is located on the side of the plurality of gate driving circuit signal lines away from the display area.

4. The display substrate according to claim 3, wherein the first type of border region includes a third border region and a fourth border region, wherein in the first direction, the third border region is located on one side of the display region, and the fourth border region is located on the other side of the display region; the at least one first signal providing line group includes at least a first first signal providing line group and a second first signal providing line group, wherein the first first signal providing line group is located in the third border region and extends to the first border region; and the second first signal providing line group is located in the fourth border region and extends to the first border region. The at least one first signal pin group includes a first first signal pin group and a second first signal pin group, wherein at least a portion of the first signal pins in the first first signal pin group are configured to be electrically connected to at least a portion of the first signal providing lines in the first first signal providing line group, and at least a portion of the first signal pins in the second first signal pin group are configured to be electrically connected to at least a portion of the first signal providing lines in the second first signal providing line group. In the first direction, the first first signal pin group and the first first signal providing line group are located on the same side of the at least one drive pin group, and the second first signal pin group and the second first signal providing line group are located on the same side of the at least one drive pin group.

5. The display substrate according to claim 4, wherein the at least one power pin group includes at least a first power pin group and a second power pin group, and the bonding area further includes a first power signal supply line group and a second power signal supply line group, wherein at least a portion of the power pins in the first power pin group are electrically connected to at least a portion of the power signal supply lines in the first power signal supply line group, and at least a portion of the power pins in the second power pin group are electrically connected to at least a portion of the power signal supply lines in the second power signal supply line group; In the bonding area, in the first direction, the first power pin group and the second power pin group are located on opposite sides of the at least one drive pin group; the first power signal supply line group and the second power signal supply line group are located on opposite sides of the at least one drive pin group; the first power signal supply line group and the first power pin group are located on the same side of the at least one drive pin group; the second power signal supply line group and the second power pin group are located on the same side of the at least one drive pin group; the first first signal pin group is located on the side of the first power pin group away from the at least one drive pin group; the second first signal pin group is located on the side of the second power pin group and the second power signal supply line group away from the at least one drive pin group.

6. The display substrate according to claim 5, wherein the plurality of gate driving circuit signal lines include a plurality of first gate driving circuit signal lines and a plurality of second gate driving circuit signal lines, the plurality of first gate driving circuit signal lines being located in the third frame region and extending to the first frame region; the plurality of second gate driving circuit signal lines being located in the fourth frame region and extending to the first frame region; In the bonding region, in the first direction, the first power signal supply line group and the plurality of first gate drive circuit signal lines are located on the same side of the at least one drive pin group, and the second power signal supply line group and the plurality of second gate drive circuit signal lines are located on the same side of the at least one drive pin group; the first first signal supply line group is located on the side of the plurality of first gate drive circuit signal lines away from the at least one integrated circuit pin group, and the second first signal supply line group is located on the side of the plurality of second gate drive circuit signal lines away from the at least one integrated circuit pin group.

7. The display substrate according to claim 6, wherein in a direction perpendicular to the plane of the substrate, the plurality of sub-pixels are disposed on one side of the substrate, at least one of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element, the pixel driving circuit includes at least one thin-film transistor and a planarization layer, the planarization layer being located on the side of the thin-film transistor away from the substrate to cover the thin-film transistor, the light-emitting element being located on the side of the planarization layer away from the substrate, the planarization layer including a first planarization layer via, the thin-film transistor including an active layer on the substrate, a gate on the side of the active layer away from the substrate, a source and a drain on the side of the gate away from the substrate, and a transition electrode on the side of the source and the drain away from the substrate, wherein in the same sub-pixel, one of the source and the drain of one of the thin-film transistors is electrically connected to the transition electrode through a via, and the transition electrode is electrically connected to the light-emitting element through the first planarization layer via; In the display area, the data line is disposed on the same layer as the transfer electrode, and the first signal line is disposed on the same layer as at least one of the active layer, the source and the drain, and the gate. In the bonding area, the first signal supply line, the power signal supply line in the power signal supply line group, and at least one of the source, the drain, and the transition electrode are disposed on the same layer.

8. The display substrate according to claim 7, wherein the sub-pixel further comprises at least one capacitor, wherein a first plate of the capacitor is disposed in the same layer as the gate of the at least one thin film transistor, and a second plate of the capacitor is located between the gate of the at least one thin film transistor and the source and the drain in a direction perpendicular to the plane of the substrate; In the bonding region, the first signal providing line is a multilayer structure disposed on the same layer as the source, the drain, the transition electrode, the gate, and the second plate of the capacitor, and the multilayer structure is electrically connected.

9. The display substrate according to claim 8, wherein in the bonding region, the plurality of first gate drive circuit signal lines are bent along the third frame region in a direction pointing to the display region and electrically connected to the integrated circuit pin group closest to the first power signal supply line group; the plurality of second gate drive circuit signal lines are bent along the fourth frame region in a direction pointing to the display region and electrically connected to the integrated circuit pin group closest to the second power signal supply line group. In the bonding region, at least a portion of the structure of the first gate drive circuit signal line at least partially overlaps with the orthographic projection of the power signal supply line in the first power signal supply line group on the substrate, and the first gate drive circuit signal line and the power signal supply line in the first power signal supply line group are located in different conductive layers in the overlapping region; at least a portion of the structure of the second gate drive circuit signal line at least partially overlaps with the orthographic projection of the power signal supply line in the second power signal supply line group on the substrate, and the plurality of second gate drive circuit signal lines and the power signal supply line in the second power signal supply line group are located in different conductive layers in the overlapping region.

10. The display substrate according to claim 8, wherein the plurality of bonding pin groups further includes a first gate drive circuit pin group and a second gate drive circuit pin group; In the first direction, the first first signal pin group is located on the side of the first gate drive circuit pin group away from the first power supply pin group, and the second first signal pin group is located on the side of the second gate drive circuit pin group away from the second power supply pin group; The first gate drive circuit signal line is configured to be electrically connected to the corresponding first gate drive circuit pin in the first gate drive circuit pin group, and the second gate drive circuit signal line is configured to be electrically connected to the corresponding second gate drive circuit pin in the second gate drive circuit pin group. In the bonding region, at least a portion of the structure in at least a portion of the gate drive circuit signal lines has a non-overlapping area with the power signal supply lines in the power signal supply line group.

11. The display substrate according to claim 9 or 10, wherein in the bonding region, in the region where the gate drive circuit signal line overlaps with the power supply signal line, the gate drive circuit signal line is a multilayer structure disposed on the same layer as the gate and the second plate of the capacitor; in at least a portion of the region where the gate drive circuit signal line does not overlap with the power supply signal line, the gate drive circuit signal line is a multilayer structure disposed on the same layer as the source and the drain, the transition electrode, the gate, and the second plate of the capacitor, wherein the multilayer structure is electrically connected.

12. The display substrate according to any one of claims 8 to 10, wherein along the direction from the display area to the first frame area, the first frame area includes a first fan-out area, a bending area, a second fan-out area, and the bonding area disposed sequentially; In the first fan-out region, the first signal providing line, the plurality of first gate driving circuit signal lines, and the plurality of second gate driving circuit signal lines are a multi-layer structure disposed on the same layer as the gate and the second plate of the capacitor, and the multi-layer structure is electrically connected. In the second fan-out region, the first signal supply line, the plurality of first gate drive circuit signal lines, the plurality of second gate drive circuit signal lines are disposed on the same layer as at least one of the gate, the second plate of the capacitor, the source and the drain, and the transition electrode. In the first direction, on the same side of the plurality of drive pin groups, the first signal supply line and the gate drive circuit signal lines are located on the side of the power supply signal supply line group away from the plurality of drive pin groups.

13. The display substrate according to claim 12, wherein the same power signal supply line group includes a first power signal supply line and a second power signal supply line, the first fan-out area is further provided with at least one first power connection line, at least one second power connection line, and a plurality of first data connection lines, the bending area is further provided with at least one first power connection structure, at least one second power connection structure, and a plurality of second data connection lines, the second fan-out area is further provided with a plurality of third data connection lines, and the first power signal supply line and the second power signal supply line extend from the bonding area to the second fan-out area; The first power connection structure is configured to electrically connect the first power connection line to the corresponding first power signal supply line, and the second power connection structure is configured to electrically connect the second power connection line to the corresponding second power signal supply line. The plurality of data lines, the plurality of first data connection lines, the plurality of second data connection lines, and the plurality of third data connection lines correspond one-to-one. The data lines are electrically connected to the corresponding integrated circuit pins in the corresponding integrated circuit bonding pin groups through the corresponding first data connection lines, the corresponding second data connection lines, and the corresponding third data connection lines.

14. The display substrate according to claim 13, wherein in the first fan-out area, the plurality of first data connection lines are a multilayer structure disposed on the same layer as the gate and the second electrode plate of the capacitor, the first power connection line and the second power connection line are a multilayer structure disposed on the same layer as the source, the drain and the transition electrode, and the multilayer structure is electrically connected; In the bending area, the third data connection line, the first power connection structure, the second power connection structure, the first signal supply line, and the gate drive circuit signal line are arranged on the same layer as the source and the drain, and different signal lines are spaced apart. In the second fan-out region, the third data connection line is disposed on the same layer as at least one of the gate and the second plate of the capacitor.

15. The display substrate according to claim 12, in the second fan-out area, the third data connection line is a multilayer structure disposed on the same layer as the gate and the second plate of the capacitor, the first signal providing line, the plurality of first gate driving circuit signal lines, and the plurality of second gate driving circuit signal lines are multilayer structures disposed on the same layer as the gate, the second plate of the capacitor, the source and the drain, and the transition electrode, and the multilayer structure is electrically connected.

16. The display substrate according to claim 12, wherein the first fan-out area further includes at least one first signal connection structure; at least one first signal pin is included in the same first signal pin group, the types of the first signal providing line and the plurality of first signal lines include at least one, the types of the first signal providing line, the types of the first signal line, and the types of the first signal pin are in one-to-one correspondence, and the first signal providing line is electrically connected to the first signal line of the corresponding type and the first signal pin of the corresponding type. In the first border region, among at least one first signal providing line, the number of first signal providing lines of the same type is at least two. In the first fan-out region, at least two first signal providing lines of the same type are electrically connected through corresponding first signal connection structures. In the region where the first signal connection structure is connected to the corresponding first signal providing line, the first signal providing line is disposed on the same layer as one of the gate and the second plate of the capacitor, and the first signal connection structure is disposed on the same layer as the other of the gate and the second plate of the capacitor. The first signal connection structures corresponding to different types of first signal providing lines are spaced apart.

17. The display substrate according to claim 16, wherein the first signal pins in the two first signal pin groups are of the same type, the first signal providing lines in the first first signal providing line group and the second first signal providing line group are of the same type, and the same first signal line is electrically connected to the first signal providing line of the corresponding type in the first first signal providing line group and the second first signal providing line group.

18. The display substrate according to claim 16, wherein the display area is further provided with a plurality of first signal connection lines, the first signal connection lines are disposed on the same layer as the adapter electrode, the plurality of first signal connection lines are arranged at intervals along the first direction and extend along the second direction, the types of the plurality of first signal connection lines correspond one-to-one with the types of the plurality of first signal lines, the first signal connection lines are electrically connected to the plurality of first signal lines of the corresponding type through vias, and the same first signal line is electrically connected to the plurality of first signal connection lines of the corresponding type through vias.

19. The display substrate according to claim 7 or 8, wherein the integrated circuit pins in the integrated circuit pin group and the bonding pins in the bonding pin group are multilayer structures disposed on the same layer as the source, the drain, and the transition electrode, and the multilayer structures are electrically connected.

20. The display substrate according to claim 8, wherein the third frame region further includes a plurality of first gate driving circuits, and the fourth frame region further includes a plurality of second gate driving circuits; The plurality of first gate driving circuits are arranged along the direction extending from the third frame region, and the plurality of second gate driving circuits are arranged along the direction extending from the fourth frame region. The signal lines of the first gate driving circuits are also electrically connected to the plurality of first gate driving circuits, and the signal lines of the second gate driving circuits are also electrically connected to the plurality of second gate driving circuits. In the first direction, in the third frame region, the at least one first signal providing line is located on the side of the plurality of first gate driving circuits away from the display area; in the fourth frame region, the at least one first signal providing line is located on the side of the plurality of second gate driving circuits away from the display area.

21. The display substrate according to claim 20, wherein the display area further includes a plurality of scanning signal lines, the plurality of scanning signal lines extending along the first direction and arranged along the second direction; The first gate driving circuit and the second gate driving circuit are configured to be electrically connected to the corresponding scan signal line, and the scan signal line is disposed on the same layer as at least one of the gate and the second plate of the capacitor.

22. The display substrate according to any one of claims 1 to 10, wherein the plurality of first signal lines include a plurality of initial signal lines, the at least one first signal providing line group includes at least one initial signal providing line group, the at least one first signal pin group includes at least one initial signal pin group, and the initial signal pin group includes at least one initial signal pin; The same initial signal pin group includes at least one initial signal pin. The initial signal providing line in the at least one initial signal providing line group and the types of the plurality of initial signal lines include at least one. The types of initial signal providing lines, the types of initial signal lines, and the types of initial signal pins are in one-to-one correspondence. The initial signal providing line is electrically connected to the corresponding type of initial signal line and the corresponding type of initial signal pin.

23. A display substrate, comprising: The substrate includes a display area, a first border area, and a first type of border area; In a first direction, the first type of border area is located on at least one side of the display area; In the second direction, the first border area is located on one side of the display area, the first border area is provided with a binding area, and the first direction intersects with the second direction; Multiple sub-pixels are located in the display area; Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels. The multiple data lines extend along the second direction and are arranged at intervals along the first direction. Multiple first signal lines are located in the display area, extending along the first direction and arranged along the second direction, and the multiple first signal lines are electrically connected to the multiple sub-pixels; At least one first signal providing line group is located in the first type of border area and extends to the binding area in the first border area, wherein the first signal providing line in the first signal providing line group is configured to be electrically connected to at least one of the plurality of first signal lines; At least one integrated circuit pin group is located in the bonding region, and at least a portion of the integrated circuit pins in the integrated circuit pin group are configured to be electrically connected to the plurality of data lines; In the bonding region, in the first direction, the main body portion of the at least one first signal providing line group is located on at least one side of the at least one integrated circuit pin group, and at least a portion of the first signal providing line has a multilayer structure, the multilayer structure being electrically connected.

24. The display substrate according to claim 23, wherein the first type of frame area is further provided with a plurality of gate driving circuit signal lines, the plurality of gate driving circuit signal lines extending to the bonding area in the first frame area; In the bonding area, in the first direction, the main body portion of the gate drive circuit signal line is located on at least one side of the at least one integrated circuit pin group, on the same side of the first center line, the first signal providing line in the first signal providing line group, the gate drive circuit signal line and the integrated circuit pin group farthest from the first center line are electrically connected, and the first center line is the center line extending from the first border area along the second direction; In the bonding region, at least a portion of the gate drive circuit signal lines have a multilayer structure, and the multilayer structure is electrically connected.

25. The display substrate of claim 24, wherein the bonding region further comprises at least one power signal supply line group, wherein in the first direction, the at least one power signal supply line group is located on at least one side of the at least one integrated circuit pin group; In the bonding region, on the same side of the first center line in the first direction, the gate drive circuit signal line and the first signal providing line bend along the direction from the first type of bezel region toward the display region and are electrically connected to the integrated circuit pin group farthest from the first center line. At least a portion of the structure of the gate drive circuit signal line and the first signal providing line at least partially overlaps with the orthographic projection of the power signal providing line group on the substrate. The gate drive circuit signal line and the first signal providing line are located in different conductive layers from the power signal providing line in the overlapping region.

26. The display substrate according to claim 25, wherein, in a direction perpendicular to the plane of the substrate, the display substrate includes at least a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially disposed on one side of the substrate; In the display area, the data line is located in the second source / drain metal layer, and the first signal line is located in at least one conductive layer of the first gate metal layer, the second gate metal layer, and the first source / drain metal layer; In the bonding region, the first signal line and the gate drive circuit signal line are located in at least one conductive layer among the first gate metal layer, the second gate metal layer, and the first source / drain metal layer.

27. The display substrate according to claim 26, wherein along the direction from the display area to the first frame area, the first frame area includes a first fan-out area, a bending area, a second fan-out area, and the bonding area arranged sequentially; In the first fan-out region and the bonding region, in at least a portion of the area where the first signal providing line and the gate driving circuit signal line overlap with the power supply signal line, the first signal providing line and the gate driving circuit signal line are a multilayer structure located in the first gate metal layer and the second gate metal layer, and the multilayer structure is electrically connected. In the second fan-out region and the bonding region, in at least a portion of the area where the first signal supply line and the gate drive circuit signal line do not overlap with the power supply signal line, the first signal supply line and the gate drive circuit signal line are a multilayer structure located in the first gate metal layer, the second gate metal layer, the first source drain metal layer and the second source drain metal layer, and the multilayer structure is electrically connected.

28. The display substrate according to claim 26 or 27, wherein the power signal supply line in the power signal supply line group extends from the bonding region to the second fan-out region; In at least a portion of the second fan-out region and the bonding region, the power signal supply lines in the power signal supply line group are a multilayer structure located in the first source / drain metal layer and the second source / drain metal layer, and the multilayer structure is electrically connected.

29. A display device comprising a display substrate as described in any one of claims 1 to 22, or comprising a display substrate as described in any one of claims 23 to 28.

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