Shift register and driving method therefor, gate driving circuit and display apparatus

Abstract

A shift register and a driving method therefor, a gate driving circuit and a display apparatus. The shift register comprises: a control sub-circuit and an output sub-circuit; the control sub-circuit is configured to provide a signal to a first node (ND1) and a second node (ND2) under signal control of a signal input terminal (IN), a clock signal terminal (CLK), at least one low-level power supply terminal (VN1), at least one high-level power supply terminal (VN2) and a third node (N3); the output sub-circuit is configured to provide a signal (Gn) to the third node (ND3) and at least one output signal terminal under signal control of the at least one high-level power supply terminal (VN2), the at least one low-level power supply terminal (VN1), the first node (ND1) and the second node (ND2).

Description

Shift registers and their driving methods, gate driving circuits and display devices

[0001] This application claims priority to Chinese Patent Application No. PCT / CN2024 / 122662, filed on September 30, 2024, entitled "Shift Register and Driving Method Thereof, Gate Driving Circuit and Display Device", the contents of which are to be construed as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, display technology, and particularly to a shift register and its driving method, gate driving circuit, and display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a shift register and its driving method, a gate driving circuit, and a display device.

[0006] In a first aspect, this disclosure provides a shift register, including: a control sub-circuit and an output sub-circuit;

[0007] The control sub-circuit is electrically connected to the signal input terminal, the clock signal terminal, at least one low-level power supply terminal, at least one high-level power supply terminal, the first node, the second node, and the third node, respectively, and is configured to provide signals to the first node and the second node under the control of the signals from the signal input terminal, the clock signal terminal, at least one low-level power supply terminal, at least one high-level power supply terminal, and the third node;

[0008] The output sub-circuit is electrically connected to at least one output signal terminal, at least one high-level power supply terminal, at least one low-level power supply terminal, a first node, a second node, and a third node, respectively, and is configured to provide signals to the third node and at least one output signal terminal under the control of signals from at least one high-level power supply terminal, at least one low-level power supply terminal, the first node, and the second node.

[0009] Secondly, this disclosure also provides a gate drive circuit, including: a plurality of cascaded shift registers as described above.

[0010] Thirdly, this disclosure also provides a display device having a display area and a non-display area, wherein the display area is provided with an array of pixel driving circuits, and the non-display area is provided with the aforementioned gate driving circuit.

[0011] Fourthly, this disclosure also provides a method for driving a shift register, configured to drive the aforementioned shift register, the method comprising:

[0012] The control sub-circuit provides signals to the first and second nodes under the control of the signal input terminal, the clock signal terminal, at least one low-level power supply terminal, at least one high-level power supply terminal and the third node;

[0013] The output sub-circuit provides signals to the third node and at least one output signal terminal under the control of signals from at least one high-level power supply terminal, at least one low-level power supply terminal, the first node, and the second node.

[0014] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0015] Overview of the attached figures

[0016] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0017] Figure 1 is a schematic diagram of the structure of a shift register provided in an example embodiment of this disclosure;

[0018] Figure 2 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment;

[0019] Figure 3 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment;

[0020] Figure 4 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment;

[0021] Figure 5 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment;

[0022] Figure 6 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment;

[0023] Figure 7 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment;

[0024] Figure 8 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment;

[0025] Figure 9A is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment;

[0026] Figure 9B is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment;

[0027] Figure 10 is an equivalent circuit diagram of an output sub-circuit provided in an exemplary embodiment;

[0028] Figure 11 is an equivalent circuit diagram of an output sub-circuit provided in an exemplary embodiment;

[0029] Figure 12 is an equivalent circuit diagram of an output sub-circuit provided in an exemplary embodiment;

[0030] Figure 13 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0031] Figure 14 is the timing diagram of the shift register provided in Figure 13;

[0032] Figure 15 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0033] Figure 16A is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0034] Figure 16B is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0035] Figure 17A is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0036] Figure 17B is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0037] Figure 18 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0038] Figure 19 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0039] Figure 20A is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0040] Figure 20B is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0041] Figure 21A is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0042] Figure 21B is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0043] Figure 22 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0044] Figure 23A is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0045] Figure 23B is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0046] Figure 24 is an equivalent circuit diagram of a reset sub-circuit provided in an exemplary embodiment;

[0047] Figure 25 is a structural circuit diagram of a display device provided in an exemplary embodiment;

[0048] Figure 26 is an output timing diagram of a multi-stage shift register provided in an exemplary embodiment;

[0049] Figure 27 is a structural circuit diagram of a display device provided in an exemplary embodiment;

[0050] Figure 28 is an output timing diagram of a multi-stage shift register provided in an exemplary embodiment;

[0051] Figure 29 is a schematic diagram of the structure of the shift register provided in an embodiment of this disclosure;

[0052] Figure 30 is a schematic diagram of the structure of a shift register provided in an exemplary embodiment;

[0053] Figure 31 is a schematic diagram of the connection of the shift register provided in Figure 30;

[0054] Figure 32 is the equivalent circuit diagram of the first node control sub-circuit in the shift register provided in Figure 31;

[0055] Figure 33 is an equivalent circuit diagram of the second node control sub-circuit in the shift register provided in Figure 31;

[0056] Figure 34 is an equivalent circuit diagram of the first output control sub-circuit in the shift register provided in Figure 31;

[0057] Figure 35 is the second equivalent circuit diagram of the first output control sub-circuit in the shift register provided in Figure 31;

[0058] Figure 36 is the equivalent circuit diagram of the first output control sub-circuit in the shift register provided in Figure 31.

[0059] Figure 37 is an equivalent circuit diagram of the second output control sub-circuit in the shift register provided in Figure 31;

[0060] Figure 38 is the equivalent circuit diagram of the second output control sub-circuit in the shift register provided in Figure 31.

[0061] Figure 39 is the equivalent circuit diagram of the second output control sub-circuit in the shift register provided in Figure 31.

[0062] Figure 40 is the equivalent circuit diagram of the second output control sub-circuit in the shift register provided in Figure 31;

[0063] Figure 41 is the equivalent circuit diagram of the second output control sub-circuit in the shift register provided in Figure 31.

[0064] Figure 42 is a second connection diagram of the shift register provided in Figure 30;

[0065] Figure 43 is the equivalent circuit diagram of the first node control sub-circuit in the shift register provided in Figure 42;

[0066] Figure 44 is the equivalent circuit diagram of the second node control sub-circuit in the shift register provided in Figure 42;

[0067] Figure 45 is the equivalent circuit diagram of the first output control sub-circuit in the shift register provided in Figure 42;

[0068] Figure 46 is an equivalent circuit diagram of the second output control sub-circuit in the shift register provided in Figure 42;

[0069] Figure 47 is the equivalent circuit diagram of the second output control sub-circuit in the shift register provided in Figure 42;

[0070] Figure 48 is another schematic diagram of the shift register provided in Figure 29;

[0071] Figure 49 is the equivalent circuit diagram of the power-on control sub-circuit;

[0072] Figure 50 is the equivalent circuit diagram of the shift register provided in Figure 31.

[0073] Figure 51 is the timing diagram of the shift register provided in Figure 50 during the refresh frame.

[0074] Figure 52 is the second equivalent circuit diagram of the shift register provided in Figure 31;

[0075] Figure 53 is the equivalent circuit diagram of the shift register provided in Figure 31.

[0076] Figure 54 is the equivalent circuit diagram of the shift register provided in Figure 31.

[0077] Figure 55 is the equivalent circuit diagram of the shift register provided in Figure 31.

[0078] Figure 56 is the equivalent circuit diagram of the shift register provided in Figure 31.

[0079] Figure 57 is the equivalent circuit diagram of the shift register provided in Figure 31.

[0080] Figure 58 is the equivalent circuit diagram of the shift register provided in Figure 31.

[0081] Figure 59 is the equivalent circuit diagram of the shift register provided in Figure 31.

[0082] Figure 60 is the equivalent circuit diagram of the shift register provided in Figure 31;

[0083] Figure 61 is the equivalent circuit diagram of the shift register provided in Figure 42;

[0084] Figure 62 is the second equivalent circuit diagram of the shift register provided in Figure 42;

[0085] Figure 63 is a flowchart of the shift register driving method;

[0086] Figure 64 is a schematic diagram of multiple shift registers cascaded together;

[0087] Figure 65 is a schematic diagram of multiple shift registers cascaded (II).

[0088] Figure 66 is a schematic diagram of the structure of the display device provided in an embodiment of this disclosure;

[0089] Figure 67 shows the timing diagram of the clock signal terminal during refresh and hold frames.

[0090] Detailed Explanation

[0091] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0092] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0093] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0094] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0095] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0096] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0097] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0098] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0099] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0100] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0101] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0102] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0103] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0104] Current display devices use cascaded drive circuits to generate scanning signals, but the output methods of current cascaded drive circuits are relatively simple and cannot meet display requirements.

[0105] Figure 1 is a schematic diagram of the structure of a shift register provided in an example embodiment of this disclosure. As shown in Figure 1, the shift register may include a control sub-circuit and an output sub-circuit.

[0106] The control sub-circuit is electrically connected to the signal input terminal IN, the first clock signal terminal CLK1, the first node N1, and the second node N2, respectively, and is configured to provide signals to the first node N1 or the second node N2 under the control of the signals from the signal input terminal IN and the first clock signal terminal CLK1.

[0107] The output sub-circuit is electrically connected to the first node N1, the second node N2, at least one power supply signal terminal Vn, and at least one output signal terminal Gn, respectively. It is configured to provide a signal to at least one output signal terminal Gn under the control of the signals of the first node N1, the second node N2, and at least one power supply signal terminal Vn. The duration of the effective level signal provided by the output sub-circuit is longer than the period duration of the signal provided by the first clock signal terminal.

[0108] The effective level signal provided by the output sub-circuit refers to the high-level signal output by the shift register during one working process, which includes stages P1 to P4. Referring to the timing diagram shown in Figure 14 below, the high-level signal provided by the output sub-circuit to the signal output terminal OUT during stages P2 and P3 can be considered the effective level signal provided by the output sub-circuit. The duration of one cycle (1H) of the signal provided by the first clock terminal can be the sum of the duration of a high-level signal and the duration of an adjacent low-level signal. The effective level signal duration shown in Figure 14 is approximately 3 cycles (3H), the effective level signal duration shown in Figure 26 is approximately 1.5 cycles (1.5H), and the effective level signal duration shown in Figure 28 is approximately 3 cycles (3H).

[0109] In one exemplary embodiment, the signal at the first clock signal terminal CLK1 can be a periodic pulse signal.

[0110] In one exemplary embodiment, as shown in FIG1, the shift register may further include a reset sub-circuit, which is electrically connected to the reset signal terminal RST, the first node N1 and the seventh power supply terminal V7 respectively, and is configured to provide the signal of the seventh power supply terminal V7 to the first node N1 under the control of the signal of the reset signal terminal RST.

[0111] In one exemplary embodiment, the signal of the seventh power supply terminal V7 is a low-level signal. Under the control of the signal of the reset signal terminal RST, the reset sub-circuit provides the signal of the seventh power supply terminal V7 to the first node N1, which can initialize the first node N1.

[0112] In this embodiment, the control subcircuit can provide signals to the first node or the second node under the control of the signals at the signal input terminal and the first clock signal terminal. The reset subcircuit, under the control of the reset signal terminal, provides a signal at the seventh power supply terminal to the first node. The output subcircuit, under the control of the signals at the first node, the second node, and at least one power supply signal terminal, provides signals to at least one output signal terminal. By providing signals to at least one output signal terminal under the control of the signals at the signal input terminal and the first clock signal terminal, the signal output of the shift register is realized. Furthermore, the sign of the pulse of the signal at the signal input terminal can determine the sign of the pulse of the output signal of the shift register.

[0113] In one exemplary embodiment, the control sub-circuit may include: a first control sub-circuit, which is also electrically connected to a first power supply terminal V1 and a second power supply terminal V2.

[0114] Figure 2 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment. As shown in Figure 2, the first control sub-circuit is also electrically connected to the first power supply terminal V1 and the second power supply terminal V2. The first control sub-circuit may include: a third transistor T3, a fifth crystal T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3.

[0115] In one exemplary embodiment, as shown in FIG2, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V2. 1. Electrical connections: The control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; The control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; The third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected to the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3.

[0116] In one exemplary embodiment, as shown in FIG2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors.

[0117] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0118] Figure 2 shows an exemplary structure of the control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the control sub-circuit is not limited to this.

[0119] Figure 3 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment. As shown in Figure 3, the first control sub-circuit is also electrically connected to the first power supply terminal V1 and the second power supply terminal V2. The first control sub-circuit may include: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.

[0120] In one exemplary embodiment, as shown in FIG3, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal N2. Terminal V1 is electrically connected; the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the control electrode of the ninth transistor T9 is electrically connected to the first clock signal terminal CLK1, the first electrode of the ninth transistor T9 is electrically connected to the fifth node N5, and the second electrode of the ninth transistor T9 is connected to the sixth node N6.

[0121] In one exemplary embodiment, as shown in FIG3, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are P-type transistors.

[0122] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0123] Figure 3 illustrates an exemplary structure of the control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the control sub-circuit is not limited to this.

[0124] In one exemplary embodiment, the control sub-circuit may include a third control sub-circuit, which is also electrically connected to the first power supply terminal V1.

[0125] Figure 4 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment. As shown in Figure 4, the third control sub-circuit is also electrically connected to the first power supply terminal V1. The third control sub-circuit may include: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3.

[0126] In one exemplary embodiment, as shown in FIG4, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal CLK1, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply. Terminal V1 is electrically connected; the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected to the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3.

[0127] In one exemplary embodiment, as shown in FIG4, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors.

[0128] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal.

[0129] Figure 4 shows an exemplary structure of the control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the control sub-circuit is not limited to this.

[0130] Figure 5 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment. As shown in Figure 5, the third control sub-circuit is also electrically connected to the first power supply terminal V1. The third control sub-circuit may include: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.

[0131] In one exemplary embodiment, as shown in FIG5, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal CLK1, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first clock signal terminal CLK1. Power supply terminal V1 is electrically connected; the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the control electrode of the ninth transistor T9 is electrically connected to the first clock signal terminal CLK1, the first electrode of the ninth transistor T9 is electrically connected to the fifth node N5, and the second electrode of the ninth transistor T9 is connected to the sixth node N6.

[0132] In one exemplary embodiment, as shown in FIG5, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are P-type transistors.

[0133] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal.

[0134] Figure 5 shows an exemplary structure of the control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the control sub-circuit is not limited to this.

[0135] Figure 6 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment. As shown in Figure 6, the first control sub-circuit is also electrically connected to the first power supply terminal V1 and the second power supply terminal V2. The first control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8.

[0136] In one exemplary embodiment, as shown in FIG6, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1.

[0137] In one exemplary embodiment, as shown in FIG6, the fifth transistor T5 is an N-type transistor, and the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are P-type transistors.

[0138] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0139] Figure 6 shows an exemplary structure of the control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the control sub-circuit is not limited to this.

[0140] In one exemplary embodiment, the control sub-circuit may include a second control sub-circuit, which is also electrically connected to a first power supply terminal V1, a second power supply terminal V2, and a third power supply terminal V3.

[0141] Figure 7 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment. As shown in Figure 7, the second control sub-circuit is also electrically connected to the first power supply terminal V1, the second power supply terminal V2 and the third power supply terminal V3. The second control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8. The fifth transistor T5 is a dual-gate transistor and includes a first control electrode and a second control electrode.

[0142] In one exemplary embodiment, as shown in FIG7, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the first control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the second control electrode of the fifth transistor T5 is electrically connected to the third power supply terminal V3, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1.

[0143] In one exemplary embodiment, as shown in FIG7, the fifth transistor T5 is an N-type transistor, and the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are P-type transistors.

[0144] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, the signal at the second power supply terminal V2 is a low-level signal, and the signal at the third power supply terminal V3 is a low-level signal.

[0145] In one exemplary embodiment, the voltage value of the third power supply terminal V3 is less than or equal to the voltage value of the second power supply terminal V2.

[0146] Figure 7 shows an exemplary structure of the control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the control sub-circuit is not limited to this.

[0147] Figure 8 is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment. As shown in Figure 8, the first control sub-circuit is also electrically connected to the first power supply terminal V1 and the second power supply terminal V2. The first control sub-circuit may include: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3.

[0148] In one exemplary embodiment, as shown in FIG8, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the first node N1, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected to the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3.

[0149] In one exemplary embodiment, as shown in FIG8, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors.

[0150] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0151] Figure 8 shows an exemplary structure of the control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the control sub-circuit is not limited to this.

[0152] In one exemplary embodiment, the control sub-circuit is also electrically connected to the second clock signal terminal CLK2 and the first power supply terminal V1, and is configured to provide the signal of the first power supply terminal V1 to the second node N2 under the control of the signals of the first node N1 and the second clock signal terminal CLK2.

[0153] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal.

[0154] In this embodiment of the disclosure, the control sub-circuit can provide the signal of the first power supply terminal V1 to the second node N2 under the control of the signals of the first node N1 and the second clock signal terminal CLK2, thereby increasing the noise immunity of the second node N2.

[0155] Figure 9A is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment, and Figure 9B is an equivalent circuit diagram of a control sub-circuit provided in an exemplary embodiment. As shown in Figures 9A and 9B, the control sub-circuit may further include a tenth transistor T10 and an eleventh transistor T11.

[0156] In one exemplary embodiment, as shown in FIG9A, the control electrode of the tenth transistor T10 is electrically connected to the first node N1, the first electrode of the tenth transistor T10 is electrically connected to the first power supply terminal V1, and the second electrode of the tenth transistor T10 is electrically connected to the seventh node N7; the control electrode of the eleventh transistor T11 is electrically connected to the second clock signal terminal CLK2, the first electrode of the eleventh transistor T11 is electrically connected to the seventh node N7, and the second electrode of the eleventh transistor T11 is electrically connected to the second node N2.

[0157] In one exemplary embodiment, as shown in FIG9B, the control electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CLK2, the first electrode of the tenth transistor T10 is electrically connected to the first node N1, and the second electrode of the tenth transistor T10 is electrically connected to the seventh node N7; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the seventh node N7, and the second electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal V1.

[0158] In one exemplary embodiment, as shown in Figures 9A and 9B, the tenth transistor T10 and the eleventh transistor T11 are P-type transistors.

[0159] In this embodiment of the disclosure, a noise immunity circuit is formed by the tenth transistor T10 and the eleventh transistor T11 to increase the noise immunity of the second node N2.

[0160] In this embodiment of the disclosure, only the formation of a noise suppression circuit using the tenth transistor T10 and the eleventh transistor T11 based on the control sub-circuit shown in FIG2 is illustrated. The implementation of the noise suppression circuit using the tenth transistor T10 and the eleventh transistor T11 based on the control sub-circuit shown in FIG3 to FIG8 is the same or similar. This embodiment of the disclosure is not limited or described in detail here.

[0161] Figures 9A and 9B illustrate an exemplary structure of the control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the control sub-circuit is not limited to this.

[0162] In one exemplary embodiment, at least one power signal terminal may include: a fourth power terminal V4 and a fifth power terminal V5, and at least one output signal terminal may include: a signal output terminal OUT; and an output sub-circuit configured to provide the signal of the fourth power terminal V4 or the fifth power terminal V5 to the signal output terminal OUT under the control of the signals of the first node N1 and the second node N2.

[0163] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, and the signal at the fifth power supply terminal V5 is a low-level signal.

[0164] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0165] Figure 10 is an equivalent circuit diagram of an output sub-circuit provided in an exemplary embodiment. As shown in Figure 10, the output sub-circuit may include: a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0166] In one exemplary embodiment, as shown in FIG10, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the first power supply terminal V1.

[0167] In one exemplary embodiment, as shown in FIG10, the first transistor T1, the second transistor T2, and the fourth transistor T4 are P-type transistors.

[0168] Figure 10 shows an exemplary structure of the output sub-circuit. It will be readily understood by those skilled in the art that the implementation of the output sub-circuit is not limited to this.

[0169] In one exemplary embodiment, at least one power signal terminal includes: a fourth power terminal V4, a fifth power terminal V5, a sixth power terminal V6, and an eighth power terminal V8; at least one output signal terminal includes: a signal output terminal OUT and a cascaded output terminal CR; and an output sub-circuit is configured to, under the control of the signals of the first node N1 and the second node N2, provide the signal of the sixth power terminal V6 or the eighth power terminal V8 to the signal output terminal OUT, and provide the signal of the fourth power terminal V4 or the fifth power terminal V5 to the cascaded output terminal CR.

[0170] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, the signal at the fifth power supply terminal V5 is a low-level signal, the signal at the sixth power supply terminal V6 is a high-level signal, and the signal at the eighth power supply terminal V8 is a low-level signal.

[0171] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0172] Figure 11 is an equivalent circuit diagram of an output sub-circuit provided in an exemplary embodiment. As shown in Figure 11, the output sub-circuit may include: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0173] In one exemplary embodiment, as shown in FIG11, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the control electrode of the twelfth transistor T12 is electrically connected to the first node N1, and the first electrode of the twelfth transistor T12 is electrically connected to the cascaded output terminal CR. The first capacitor C1 is electrically connected to the sixth power supply terminal V6, and the second terminal of the twelfth transistor T12 is electrically connected to the signal output terminal OUT. The control terminal of the thirteenth transistor T13 is electrically connected to the eighth node N8, the first terminal of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT, and the second terminal of the thirteenth transistor T13 is electrically connected to the eighth power supply terminal V8. The first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR. The second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4.

[0174] In one exemplary embodiment, as shown in FIG11, the first transistor T1, the second transistor T2, the fourth transistor T4, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0175] Figure 11 shows an exemplary structure of the output sub-circuit. It will be readily understood by those skilled in the art that the implementation of the output sub-circuit is not limited to this.

[0176] Figure 12 is an equivalent circuit diagram of an output sub-circuit provided in an exemplary embodiment. As shown in Figure 12, the output sub-circuit may include: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0177] In one exemplary embodiment, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second terminal of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first terminal of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the second terminal of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first terminal of the fourth transistor T4 is electrically connected to the second node N2, and the second terminal of the fourth transistor T4 is electrically connected to the eighth node N8; the control electrode of the twelfth transistor T12 is electrically connected to the ninth node N9, the first terminal of the twelfth transistor T12 is electrically connected to the sixth power supply terminal V6, and the second terminal of the twelfth transistor T12 is electrically connected to the signal output terminal OUT; the control electrode of the thirteenth transistor T13 is electrically connected to the second node N2, and the first terminal of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT; The thirteenth transistor T13 is electrically connected to the signal output terminal OUT. The second terminal of the thirteenth transistor T13 is electrically connected to the eighth power supply terminal V8. The control terminal of the fourteenth transistor T14 is electrically connected to the fifth power supply terminal V5. The first terminal of the fourteenth transistor T14 is electrically connected to the first node N1. The second terminal of the fourteenth transistor T14 is electrically connected to the ninth node N9. The first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the eighth node N8. The second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR. The second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the first node N1. The second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4. The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 of the fourth capacitor is electrically connected to the ninth node N9. The second plate C42 of the fourth capacitor is electrically connected to the signal output terminal OUT.

[0178] In one exemplary embodiment, as shown in FIG12, the first transistor T1, the second transistor T2, the fourth transistor T4, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are P-type transistors.

[0179] Figure 12 shows an exemplary structure of the output sub-circuit. It will be readily understood by those skilled in the art that the implementation of the output sub-circuit is not limited to this.

[0180] Figure 13 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 13, at least one power supply signal terminal includes: a fourth power supply terminal V4 and a fifth power supply terminal V5; at least one output signal terminal includes: a signal output terminal OUT; the control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3; and the output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0181] In an exemplary embodiment, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second terminal of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first terminal of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second terminal of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first terminal of the third transistor T3 is electrically connected to the signal input terminal IN, and the second terminal of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first terminal of the fourth transistor T4 is electrically connected to the second node N2, and the second terminal of the fourth transistor T4 is electrically connected to the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first terminal of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first terminal of the sixth transistor T6 is electrically connected to the signal output terminal OUT, and the second terminal of the sixth transistor T6 is electrically connected to the fifth power supply terminal V5; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first terminal of the sixth transistor T6 is electrically connected to the signal output terminal OUT, and the second terminal of the sixth transistor T6 is electrically connected to the fifth power supply terminal V4; the control electrode of the sixth transistor T6 is electrically connected to the signal output ... OUT The fourth node N4 is electrically connected; the second terminal of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN; the first terminal of the seventh transistor T7 is electrically connected to the third node N3; and the second terminal of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control terminal of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1; the first terminal of the eighth transistor T8 is electrically connected to the fourth node N4; and the second terminal of the eighth transistor T8 is electrically connected to the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected to the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3.

[0182] In one exemplary embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors.

[0183] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0184] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, and the signal at the fifth power supply terminal V5 is a low-level signal.

[0185] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0186] Figure 13 illustrates an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0187] Figure 14 is a timing diagram of the shift register shown in Figure 13. The following describes an exemplary embodiment of this disclosure using the operation of the first-stage shift register exemplified in Figure 13. The signal input IN of the first-stage shift register exemplified in Figure 13 is the signal of the initial signal line STV. The operation of the shift register may include:

[0188] In the first stage P1: the signal input terminal IN is a high-level signal, the first clock signal terminal CLK1 is a high-level signal, the third node N3 maintains a high-level signal, the second node N2 and the eighth node N8 maintain a low-level signal, the fourth node N4 and the first node N1 maintain a high-level signal, and the signal output terminal OUT maintains a low-voltage signal.

[0189] In the second stage (P2), when the signal input terminal IN is high, transistors T7 and T6 are off, and the voltage of node N3 changes with the signal of the first clock signal terminal CLK1. When the signal of the first clock signal terminal CLK1 is low, the voltage of node N3 is reduced by the signal of the first clock signal terminal CLK1, transistor T5 is turned on, and the low voltage signal of the second power supply terminal V2 is written to node N4. Transistor T8 is turned on, and the signals of node N4 and node N1 change from high to low. Transistor T1 is turned on, and the high-level signal of the fourth power supply terminal V4 is written to the signal output terminal OUT, which outputs a high-level signal. When the signal of the first clock signal terminal CLK1 is high, the voltage of node N3 is reduced by the signal of the first clock signal terminal CLK1, transistor T5 is off, and transistor T8 is off. Under the action of the second capacitor C2, node N1 maintains a low-level signal, transistor T1 is turned on, and the high-level signal of the fourth power supply terminal V4 is written to the signal output terminal OUT, which outputs a high-level signal.

[0190] In the third stage (P3), the signal at the input terminal IN is low, turning on the seventh transistor T7 and the sixth transistor T6. The signal at the first power supply terminal V1 is written to the third node N3 and charges the third capacitor C3. The signal at the first power supply terminal V1 is also written to the fourth node N4. Since the first power supply terminal V1 is high, the signals at the third node N3 and the fourth node N4 are both high. The signal at the first clock signal terminal CLK1 is high, turning off the eighth transistor T8. Under the action of the second capacitor C2, the first node N1 remains low, and the first transistor T1 turns on, writing the high-level signal at the fourth power supply terminal V4 to the signal output terminal OUT. The signal output terminal OUT outputs a high-level signal.

[0191] In the fourth stage (P4), the signal at the input terminal IN is low, turning on the sixth transistor T6 and the seventh transistor T7. The signals at the third node N3 and the fourth node N4 remain high. The signal at the first clock signal terminal CLK1 is low, turning on the eighth transistor T8. The high-level signal at the fourth node N4 is written to the first node N1, causing N1 to change from low to high, and the first transistor T1 turns off. The third transistor T3 turns on. Since the fifth power supply terminal V5 is low, the fourth transistor T4 turns on, and the low-level signal at the input terminal IN is written to the second node N2 and the eighth node N8. The eighth node N8 is low, turning on the second transistor T2. The signal at the fifth power supply terminal V5 is written to the signal output terminal OUT. Since the fifth power supply terminal V5 is low, the signal output terminal OUT outputs a low-level signal. As the signal output terminal OUT changes from a high-level signal to a low-level signal, the eighth node N8 is continuously pulled low during this stage through the coupling effect of the first capacitor C1, and the voltage is lower than the voltage of the fifth power supply terminal V5. At this time, the fourth transistor T4 enters the cut-off state to maintain the low voltage of the eighth node N8, so as to ensure that the second transistor T2 remains on, thus achieving stepless output at the signal output terminal OUT.

[0192] The operation of the shift register is similar in the following embodiments, and will not be described again in the following embodiments.

[0193] Figure 15 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 15, at least one power supply signal terminal includes: a fourth power supply terminal V4 and a fifth power supply terminal V5; at least one output signal terminal includes: a signal output terminal OUT; the control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9; and the output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0194] In one exemplary embodiment, as shown in FIG15, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, and the first electrode of the third transistor T3 is electrically connected to the signal input terminal V5. The control terminal of the fourth transistor T4 is connected to the fifth power supply terminal V5, the first terminal of the fourth transistor T4 is connected to the second node N2, and the second terminal of the fourth transistor T4 is connected to the eighth node N8; the control terminal of the fifth transistor T5 is connected to the fifth node N5, the first terminal of the fifth transistor T5 is connected to the first clock signal terminal CLK1 or the second power supply terminal V2, and the second terminal of the fifth transistor T5 is connected to the fourth node N4; the control terminal of the sixth transistor T6 is connected to the signal input terminal IN. The first terminal of the sixth transistor T6 is electrically connected to the fourth node N4, and the second terminal of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first terminal of the seventh transistor T7 is electrically connected to the sixth node N6, and the second terminal of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control terminal of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first terminal of the eighth transistor T8 is electrically connected to the fourth node N4, and the second terminal of the eighth transistor T8 is electrically connected to the first node N1; the control terminal of the ninth transistor T9 is electrically connected to the first… The clock signal terminal CLK1 is electrically connected; the first terminal of the ninth transistor T9 is electrically connected to the fifth node N5; the second terminal of the ninth transistor T9 is connected to the sixth node N6; the first capacitor C1 includes a first plate C11 and a second plate C12; the first plate C11 of the first capacitor is electrically connected to the eighth node N8; the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22; the first plate C21 of the second capacitor is electrically connected to the first node N1; the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4.

[0195] In one exemplary embodiment, as shown in FIG15, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are P-type transistors.

[0196] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0197] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, and the signal at the fifth power supply terminal V5 is a low-level signal.

[0198] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0199] Figure 15 illustrates an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0200] Figure 16A is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 16A, at least one power supply signal terminal includes: a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8. At least one output signal terminal includes: a signal output terminal OUT and a cascaded output terminal CR. The control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3. The output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0201] In one exemplary embodiment, as shown in FIG16A, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the second clock signal terminal CLK1 ... clock signal terminal CLK1; the control electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the second clock signal terminal CLK1, and the The first terminal of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5; the first terminal of the fourth transistor T4 is electrically connected to the second node N2; the second terminal of the fourth transistor T4 is electrically connected to the eighth node N8; the control terminal of the fifth transistor T5 is electrically connected to the third node N3; the first terminal of the fifth transistor T5 is electrically connected to the first clock signal terminal CLK1 or the second power supply terminal V2; the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; the control terminal of the sixth transistor T6 is electrically connected to the signal input terminal IN; the first terminal of the sixth transistor T6 is electrically connected to the fourth node N4; the second terminal of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN; the first ... The control electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1; the control electrode of the twelfth transistor T12 is electrically connected to the first node N1, the first electrode of the twelfth transistor T12 is electrically connected to the sixth power supply terminal V6, and the second electrode of the twelfth transistor T12 is electrically connected to the signal output terminal OUT; the control electrode of the thirteenth transistor T13 is electrically connected to the eighth node N8, and the first electrode of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT. The second terminal of transistor T13 is electrically connected to the eighth power supply terminal V8; the first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR; the second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4; the third capacitor C3 includes a first plate C31 and a second plate C32. The first plate C31 of the third capacitor is electrically connected to the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3.

[0202] In one exemplary embodiment, as shown in FIG16A, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0203] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0204] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, the signal at the fifth power supply terminal V5 is a low-level signal, the signal at the sixth power supply terminal V6 is a high-level signal, and the signal at the eighth power supply terminal V8 is a low-level signal.

[0205] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0206] Figure 16A illustrates an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0207] Figure 16B is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 16B, at least one power supply signal terminal includes: a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8. At least one output signal terminal includes: a signal output terminal OUT and a cascaded output terminal CR. The control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3. The output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0208] In one exemplary embodiment, as shown in FIG16B, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the second clock signal terminal CLK1 ... clock signal terminal CLK1; the control electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the second clock signal terminal CLK1, and the The first terminal of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5; the first terminal of the fourth transistor T4 is electrically connected to the second node N2; the second terminal of the fourth transistor T4 is electrically connected to the eighth node N8; the control terminal of the fifth transistor T5 is electrically connected to the third node N3; the first terminal of the fifth transistor T5 is electrically connected to the first clock signal terminal CLK1 or the second power supply terminal V2; the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; the control terminal of the sixth transistor T6 is electrically connected to the signal input terminal IN; the first terminal of the sixth transistor T6 is electrically connected to the fourth node N4; the second terminal of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN; the first terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN; the second terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN; the second terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN; the second terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN; the second terminal of the seventh transistor T7 is electrically connected to the signal input terminal N2; the second terminal of the seventh transistor T7 is electrically connected to the signal input terminal N2; the third ... The first terminal of transistor T7 is electrically connected to the third node N3; the second terminal of transistor T7 is electrically connected to the first power supply terminal V1; the control terminal of transistor T8 is electrically connected to the first clock signal terminal CLK1; the first terminal of transistor T8 is electrically connected to the fourth node N4; the second terminal of transistor T8 is electrically connected to the first node N1; the control terminal of transistor T12 is electrically connected to the ninth node N9; the first terminal of transistor T12 is electrically connected to the sixth power supply terminal V6; the second terminal of transistor T12 is electrically connected to the signal output terminal OUT; the control terminal of transistor T13 is electrically connected to the second node N2; the first terminal of transistor T13 is electrically connected to the signal output terminal OUT; the thirteenth transistor... The second terminal of transistor T13 is electrically connected to the eighth power supply terminal V8; the control terminal of the fourteenth transistor T14 is electrically connected to the fifth power supply terminal V5, the first terminal of the fourteenth transistor T14 is electrically connected to the first node N1, and the second terminal of the fourteenth transistor T14 is electrically connected to the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4;The third capacitor C3 includes a first plate C31 and a second plate C32. The first plate C31 is electrically connected to the first clock signal terminal CLK1, and the second plate C32 is electrically connected to the third node N3. The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 is electrically connected to the ninth node N9, and the second plate C42 is electrically connected to the signal output terminal OUT.

[0209] In one exemplary embodiment, as shown in FIG16B, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are P-type transistors.

[0210] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0211] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, the signal at the fifth power supply terminal V5 is a low-level signal, the signal at the sixth power supply terminal V6 is a high-level signal, and the signal at the eighth power supply terminal V8 is a low-level signal.

[0212] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0213] Figure 16B illustrates an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0214] Figure 17A is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 17A, at least one power supply signal terminal includes: a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8. At least one output signal terminal includes: a signal output terminal OUT and a cascaded output terminal CR. The control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0215] In one exemplary embodiment, as shown in FIG17A, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second terminal of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first terminal of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the fifth power supply terminal V5 of the second transistor T2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first terminal of the third transistor T3 is electrically connected to the signal input terminal IN, and the second terminal of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 ... second clock signal terminal CLK1, and the second terminal of the third transistor T3 is electrically connected to the second clock signal terminal CLK1; the control electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CLK1, the first terminal of the third transistor T3 is electrically connected to the second clock signal terminal CLK1, and the second terminal of the third transistor T3 is electrically connected The fifth power supply terminal V5 is electrically connected; the first terminal of the fourth transistor T4 is electrically connected to the second node N2; the second terminal of the fourth transistor T4 is electrically connected to the eighth node N8; the control terminal of the fifth transistor T5 is electrically connected to the fifth node N5; the first terminal of the fifth transistor T5 is electrically connected to the first clock signal terminal CLK1 or the second power supply terminal V2; the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; the control terminal of the sixth transistor T6 is electrically connected to the signal input terminal IN; the first terminal of the sixth transistor T4 is electrically connected to the fourth node N4; the second terminal of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN; the first terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN; the second terminal of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN; the second terminal of the seventh transistor T7 is electrically connected to the signal input terminal N2 ... The first terminal of transistor T7 is electrically connected to the sixth node N6; the second terminal of transistor T7 is electrically connected to the first power supply terminal V1; the control terminal of transistor T8 is electrically connected to the first clock signal terminal CLK1; the first terminal of transistor T8 is electrically connected to the fourth node N4; the second terminal of transistor T8 is electrically connected to the first node N1; the control terminal of transistor T9 is electrically connected to the first clock signal terminal CLK1; the first terminal of transistor T9 is electrically connected to the fifth node N5; the second terminal of transistor T9 is connected to the sixth node N6; the control terminal of transistor T12 is electrically connected to the first node N1; the first terminal of transistor T12 is electrically connected to the sixth power supply terminal V6; the second terminal of transistor T12 is electrically connected to the sixth node N6; the second terminal of transistor T12 is electrically connected to the sixth node N1; the second terminal of transistor T12 is electrically connected to the sixth power supply terminal V6; the second terminal of transistor T12 is electrically connected to the sixth node N ... The second terminal of transistor 2 is electrically connected to the signal output terminal OUT; the control terminal of the thirteenth transistor T13 is electrically connected to the eighth node N8, the first terminal of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT, and the second terminal of the thirteenth transistor T13 is electrically connected to the eighth power supply terminal V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4.

[0216] In one exemplary embodiment, as shown in FIG17A, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0217] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0218] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, the signal at the fifth power supply terminal V5 is a low-level signal, the signal at the sixth power supply terminal V6 is a high-level signal, and the signal at the eighth power supply terminal V8 is a low-level signal.

[0219] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0220] Figure 17A shows an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0221] Figure 17B is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 17B, at least one power supply signal terminal includes: a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8. At least one output signal terminal includes: a signal output terminal OUT and a cascaded output terminal CR. The control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0222] In one exemplary embodiment, as shown in FIG17B, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second terminal of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first terminal of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the fifth power supply terminal V5 of the second transistor T2 is electrically connected; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first terminal of the third transistor T3 is electrically connected to the signal input terminal IN, and the second terminal of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 ... second clock signal terminal CLK1, and the second terminal of the third transistor T3 is electrically connected to the second clock signal terminal CLK1; the control electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CLK1, the first terminal of the third transistor T3 is electrically connected to the second clock signal terminal CLK1, and the second terminal of the third transistor T3 The fifth power supply terminal V5 is electrically connected; the first terminal of the fourth transistor T4 is electrically connected to the second node N2; the second terminal of the fourth transistor T4 is electrically connected to the eighth node N8; the control terminal of the fifth transistor T5 is electrically connected to the fifth node N5; the first terminal of the fifth transistor T5 is electrically connected to the first clock signal terminal CLK1 or the second power supply terminal V2; the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; the control terminal of the sixth transistor T6 is electrically connected to the signal input terminal IN; the first terminal of the sixth transistor T4 is electrically connected to the fourth node N4; the second terminal of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control terminal of the seventh transistor T7 is electrically connected to the signal input terminal IN; the first terminal of the seventh transistor T7... The control electrode of the seventh transistor T7 is electrically connected to the sixth node N6; the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1; the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the control electrode of the ninth transistor T9 is electrically connected to the first clock signal terminal CLK1; the first electrode of the ninth transistor T9 is electrically connected to the fifth node N5; the second electrode of the ninth transistor T9 is connected to the sixth node N6; the control electrode of the twelfth transistor T12 is electrically connected to the ninth node N9; the first electrode of the twelfth transistor T12 is electrically connected to the sixth power supply terminal V6; the second electrode of the twelfth transistor T12... The second terminal is electrically connected to the signal output terminal OUT; the control terminal of the thirteenth transistor T13 is electrically connected to the second node N2, the first terminal of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT, and the second terminal of the thirteenth transistor T13 is electrically connected to the eighth power supply terminal V8; the control terminal of the fourteenth transistor T14 is electrically connected to the fifth power supply terminal V5, the first terminal of the fourteenth transistor T14 is electrically connected to the first node N1, and the second terminal of the fourteenth transistor T14 is electrically connected to the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR;The second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 is electrically connected to the first node N1, and the second plate C22 is electrically connected to the fourth power supply terminal V4. The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 is electrically connected to the ninth node N9, and the second plate C42 is electrically connected to the signal output terminal OUT.

[0223] In one exemplary embodiment, as shown in FIG17B, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are P-type transistors.

[0224] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0225] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, the signal at the fifth power supply terminal V5 is a low-level signal, the signal at the sixth power supply terminal V6 is a high-level signal, and the signal at the eighth power supply terminal V8 is a low-level signal.

[0226] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0227] Figure 17B shows an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0228] Figure 18 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 18, at least one power supply signal terminal includes: a fourth power supply terminal V4 and a fifth power supply terminal V5; at least one output signal terminal includes: a signal output terminal OUT; the control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8; and the output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0229] In one exemplary embodiment, as shown in FIG18, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second terminal of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first terminal of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second terminal of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first terminal of the third transistor T3 is electrically connected to the signal input terminal IN, and the second terminal of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first terminal of the fourth transistor T4 is electrically connected to the second node N2, and the second terminal of the fourth transistor T4 is electrically connected to the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, and the fifth... The first terminal of transistor T5 is electrically connected to the second power supply terminal V2, and the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; the control terminal of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first terminal of the sixth transistor T6 is electrically connected to the fourth node N4, and the second terminal of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control terminal of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first terminal of the eighth transistor T8 is electrically connected to the fourth node N4, and the second terminal of the eighth transistor T8 is electrically connected to the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate of the second capacitor is electrically connected to the first node N1, and the second plate of the second capacitor is electrically connected to the fourth power supply terminal V4.

[0230] In one exemplary embodiment, as shown in FIG18, the fifth transistor T5 is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the eighth transistor T8 are P-type transistors.

[0231] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0232] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, and the signal at the fifth power supply terminal V5 is a low-level signal.

[0233] Figure 18 illustrates an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0234] Figure 19 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 19, at least one power supply signal terminal includes: a fourth power supply terminal V4 and a fifth power supply terminal V5; at least one output signal terminal includes: a signal output terminal OUT; the control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8; and the output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0235] In one exemplary embodiment, as shown in FIG19, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second terminal of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first terminal of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second terminal of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first terminal of the third transistor T3 is electrically connected to the signal input terminal IN, and the second terminal of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first terminal of the fourth transistor T4 is electrically connected to the second node N2, and the second terminal of the fourth transistor T4 is electrically connected to the eighth node N8; the fifth transistor T5 is a dual-gate transistor and includes a first control electrode and a second control electrode, the first control electrode of the fifth transistor T5 being connected to the signal input terminal... The fifth transistor T5 is electrically connected to the IN terminal, the second control terminal of the fifth transistor T5 is electrically connected to the third power supply terminal V3, the first terminal of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second terminal of the fifth transistor T5 is electrically connected to the fourth node; the control terminal of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first terminal of the sixth transistor T6 is electrically connected to the fourth node N4, and the second terminal of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control terminal of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first terminal of the eighth transistor T8 is electrically connected to the fourth node N4, and the second terminal of the eighth transistor T8 is electrically connected to the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate of the second capacitor is electrically connected to the first node N1, and the second plate of the second capacitor is electrically connected to the fourth power supply terminal V4.

[0236] In one exemplary embodiment, as shown in FIG18, the fifth transistor T5 is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the eighth transistor T8 are P-type transistors.

[0237] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, the signal at the second power supply terminal V2 is a low-level signal, and the signal at the third power supply terminal V3 is a low-level signal.

[0238] In one exemplary embodiment, the voltage value of the third power supply terminal V3 is less than or equal to the voltage value of the second power supply terminal V2.

[0239] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, and the signal at the fifth power supply terminal V5 is a low-level signal.

[0240] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0241] Figure 19 illustrates an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0242] Figure 20A is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 20A, at least one power supply signal terminal includes: a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8. At least one output signal terminal includes: a signal output terminal OUT and a cascaded output terminal CR. The control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8. The output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0243] In one exemplary embodiment, as shown in FIG20A, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, and the first electrode of the third transistor T3 is electrically connected to the signal input terminal. The control terminal of the fourth transistor T4 is connected to the fifth power supply terminal V5, the first terminal of the fourth transistor T4 is connected to the second node N2, and the second terminal of the fourth transistor T4 is connected to the eighth node N8; the control terminal of the fifth transistor T5 is connected to the signal input terminal IN, the first terminal of the fifth transistor T5 is connected to the second power supply terminal V2, and the second terminal of the fifth transistor T5 is connected to the fourth node N4; the control terminal of the sixth transistor T6 is connected to the signal input terminal IN, and the first terminal of the sixth transistor T6 is connected to the signal input terminal IN. The fourth node N4 is electrically connected; the second terminal of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control terminal of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1; the first terminal of the eighth transistor T8 is electrically connected to the fourth node N4; the second terminal of the eighth transistor T8 is electrically connected to the first node N1; the control terminal of the twelfth transistor T12 is electrically connected to the first node N1; the first terminal of the twelfth transistor T12 is electrically connected to the sixth power supply terminal V6; the second terminal of the twelfth transistor T12 is electrically connected to the signal output terminal OUT; the control terminal of the thirteenth transistor T13 is electrically connected to the eighth node N4. 8. Electrical connections: The first terminal of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT, and the second terminal of the thirteenth transistor T13 is electrically connected to the eighth power supply terminal V8; The first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR; The second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4.

[0244] In one exemplary embodiment, as shown in FIG20A, the fifth transistor is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0245] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0246] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, the signal at the fifth power supply terminal V5 is a low-level signal, the signal at the sixth power supply terminal V6 is a high-level signal, and the signal at the eighth power supply terminal V8 is a low-level signal.

[0247] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0248] Figure 20A illustrates an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0249] Figure 20B is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 20B, at least one power supply signal terminal includes: a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8. At least one output signal terminal includes: a signal output terminal OUT and a cascaded output terminal CR. The control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8. The output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0250] In one exemplary embodiment, as shown in FIG20B, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the fourth transistor T4... The control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5; the first electrode of the fourth transistor T4 is electrically connected to the second node N2; the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8. The control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN; the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2; the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. The control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN; the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4; the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1. The control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1; the first electrode of the eighth transistor T8 is electrically connected to the signal input terminal IN ... The fourth node N4 is electrically connected; the second terminal of the eighth transistor T8 is electrically connected to the first node N1; the control terminal of the twelfth transistor T12 is electrically connected to the ninth node N9; the first terminal of the twelfth transistor T12 is electrically connected to the sixth power supply terminal V6; the second terminal of the twelfth transistor T12 is electrically connected to the signal output terminal OUT; the control terminal of the thirteenth transistor T13 is electrically connected to the second node N2; the first terminal of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT; the second terminal of the thirteenth transistor T13 is electrically connected to the eighth power supply terminal V8; the control terminal of the fourteenth transistor T14 is electrically connected to the fifth power supply terminal V5; the first terminal of the fourteenth transistor T14 is electrically connected to the first node N1; the fourteenth... The second terminal of transistor T14 is electrically connected to the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4; the fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected to the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected to the signal output terminal OUT.

[0251] In one exemplary embodiment, as shown in FIG20B, the fifth transistor is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 are P-type transistors.

[0252] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0253] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, the signal at the fifth power supply terminal V5 is a low-level signal, the signal at the sixth power supply terminal V6 is a high-level signal, and the signal at the eighth power supply terminal V8 is a low-level signal.

[0254] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0255] Figure 20B illustrates an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0256] Figure 21A is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 21A, at least one power supply signal terminal includes: a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8. At least one output signal terminal includes: a signal output terminal OUT and a cascaded output terminal CR. The control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8. The output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0257] In one exemplary embodiment, as shown in FIG21A, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, and the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN. The second terminal of transistor T3 is electrically connected to the second node N2; the control terminal of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first terminal of the fourth transistor T4 is electrically connected to the second node N2, and the second terminal of the fourth transistor T4 is electrically connected to the eighth node N8; the fifth transistor T5 is a dual-gate transistor, the first control terminal of the fifth transistor T5 is electrically connected to the signal input terminal IN, the second control terminal of the fifth transistor T5 is electrically connected to the third power supply terminal V3, the first terminal of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; the control terminal of the sixth transistor T6 is electrically connected to the signal input terminal IN. The input terminal IN is electrically connected; the first terminal of the sixth transistor T6 is electrically connected to the fourth node N4; the second terminal of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control terminal of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1; the first terminal of the eighth transistor T8 is electrically connected to the fourth node N4; the second terminal of the eighth transistor T8 is electrically connected to the first node N1; the control terminal of the twelfth transistor T12 is electrically connected to the first node N1; the first terminal of the twelfth transistor T12 is electrically connected to the sixth power supply terminal V6; the second terminal of the twelfth transistor T12 is electrically connected to the signal output terminal OUT; the thirteenth transistor T1... The control electrode of transistor 3 is electrically connected to the eighth node N8. The first electrode of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT, and the second electrode of the thirteenth transistor T13 is electrically connected to the eighth power supply terminal V8. The first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR. The second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4.

[0258] In one exemplary embodiment, as shown in FIG21A, the fifth transistor is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0259] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, the signal at the second power supply terminal V2 is a low-level signal, and the signal at the third power supply terminal V3 is a low-level signal.

[0260] In one exemplary embodiment, the voltage value of the third power supply terminal V3 is less than or equal to the voltage value of the second power supply terminal V2.

[0261] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, the signal at the fifth power supply terminal V5 is a low-level signal, the signal at the sixth power supply terminal V6 is a high-level signal, and the signal at the eighth power supply terminal V8 is a low-level signal.

[0262] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0263] Figure 21A shows an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0264] Figure 21B is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 21B, at least one power supply signal terminal includes: a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8. At least one output signal terminal includes: a signal output terminal OUT and a cascaded output terminal CR. The control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8. The output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0265] In one exemplary embodiment, as shown in FIG21B, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second terminal of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first terminal of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the second terminal of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first terminal of the third transistor T3 is electrically connected to the signal input terminal IN, and the second terminal of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5. 5. Electrical connections: The first terminal of the fourth transistor T4 is electrically connected to the second node N2, and the second terminal of the fourth transistor T4 is electrically connected to the eighth node N8; The fifth transistor T5 is a dual-gate transistor, with its first control terminal electrically connected to the signal input IN, its second control terminal electrically connected to the third power supply V3, its first terminal electrically connected to the second power supply V2, and its second terminal electrically connected to the fourth node N4; The control terminal of the sixth transistor T6 is electrically connected to the signal input IN, its first terminal electrically connected to the fourth node N4, and its second terminal electrically connected to the first power supply V1; The control terminal of the eighth transistor T8 is connected to the first clock signal terminal. CLK1 is electrically connected; the first terminal of the eighth transistor T8 is electrically connected to the fourth node N4, and the second terminal of the eighth transistor T8 is electrically connected to the first node N1; the control terminal of the twelfth transistor T12 is electrically connected to the ninth node N9, the first terminal of the twelfth transistor T12 is electrically connected to the sixth power supply terminal V6, and the second terminal of the twelfth transistor T12 is electrically connected to the signal output terminal OUT; the control terminal of the thirteenth transistor T13 is electrically connected to the second node N2, the first terminal of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT, and the second terminal of the thirteenth transistor T13 is electrically connected to the eighth power supply terminal V8; the control terminal of the fourteenth transistor T14 is electrically connected to the fifth power supply terminal V5, and the first terminal of the fourteenth transistor T14 is electrically connected to the first node N1. Point N1 is electrically connected, and the second terminal of the fourteenth transistor T14 is electrically connected to the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR; the second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4; the fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 of the fourth capacitor is electrically connected to the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected to the signal output terminal OUT.

[0266] In one exemplary embodiment, as shown in FIG21B, the fifth transistor is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 are P-type transistors.

[0267] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, the signal at the second power supply terminal V2 is a low-level signal, and the signal at the third power supply terminal V3 is a low-level signal.

[0268] In one exemplary embodiment, the voltage value of the third power supply terminal V3 is less than or equal to the voltage value of the second power supply terminal V2.

[0269] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, the signal at the fifth power supply terminal V5 is a low-level signal, the signal at the sixth power supply terminal V6 is a high-level signal, and the signal at the eighth power supply terminal V8 is a low-level signal.

[0270] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0271] Figure 21B shows an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0272] Figure 22 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 22, at least one power supply signal terminal includes: a fourth power supply terminal V4 and a fifth power supply terminal V5; at least one output signal terminal includes: a signal output terminal OUT; the control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a third capacitor C3; and the output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0273] In one exemplary embodiment, as shown in FIG22, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second terminal of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first terminal of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second terminal of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first terminal of the third transistor T3 is electrically connected to the signal input terminal IN, and the second terminal of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first terminal of the fourth transistor T4 is electrically connected to the second node N2, and the second terminal of the fourth transistor T4 is electrically connected to the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first terminal of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second terminal of the fifth transistor T5 is electrically connected to the first node N1. Electrical connections: The control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the first node N1, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; The control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; The first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; The second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4; The third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected to the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3.

[0274] In one exemplary embodiment, as shown in FIG22, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors.

[0275] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0276] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, and the signal at the fifth power supply terminal V5 is a low-level signal.

[0277] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0278] Figure 22 illustrates an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0279] Figure 23A is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 23A, at least one power supply signal terminal includes: a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8. At least one output signal terminal includes: a signal output terminal OUT and a cascaded output terminal CR. The control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3. The output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0280] In one exemplary embodiment, as shown in FIG23A, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the fifth power supply terminal V5. The control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the first node N1, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the seventh crystal... The control electrode of transistor T7 is electrically connected to the signal input terminal IN; the first electrode of the seventh transistor T7 is electrically connected to the third node N3; and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1. The control electrode of the twelfth transistor T12 is electrically connected to the first node N1; the first electrode of the twelfth transistor T12 is electrically connected to the sixth power supply terminal V6; and the second electrode of the twelfth transistor T12 is electrically connected to the signal output terminal OUT. The control electrode of the thirteenth transistor T13 is electrically connected to the eighth node N8; the first electrode of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT; and the second electrode of the thirteenth transistor T13 is electrically connected to the eighth power supply terminal V8. A capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR. A second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4. A third capacitor C3 includes a first plate C31 and a second plate C32. The first plate C31 of the third capacitor is electrically connected to the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3.

[0281] In one exemplary embodiment, as shown in FIG23A, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0282] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0283] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, the signal at the fifth power supply terminal V5 is a low-level signal, the signal at the sixth power supply terminal V6 is a high-level signal, and the signal at the eighth power supply terminal V8 is a low-level signal.

[0284] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0285] Figure 23A shows an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0286] Figure 23B is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figure 23B, at least one power supply signal terminal includes: a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8. At least one output signal terminal includes: a signal output terminal OUT and a cascaded output terminal CR. The control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3. The output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0287] In one exemplary embodiment, as shown in FIG23B, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the cascaded output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the cascaded output terminal CR, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the fourth transistor T4... The control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5; the first electrode of the fourth transistor T4 is electrically connected to the second node N2; the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected to the third node N3; the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2; the second electrode of the fifth transistor T5 is electrically connected to the first node N1; the control electrode of the sixth transistor T6 is electrically connected to the second node N2; the first electrode of the sixth transistor T6 is electrically connected to the first node N1; the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN; the first electrode of the seventh transistor T7 is electrically connected to the third node N8; the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN; the first electrode of the seventh transistor T7 is electrically connected to the third node N8; the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN; the first electrode of the seventh transistor T7 is electrically connected to the signal input terminal N2; the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal N1; the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal N2; the first electrode of the seventh transistor T7 is electrically connected to the signal input terminal N2 ... 3. Electrical connections: The second terminal of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control terminal of the twelfth transistor T12 is electrically connected to the ninth node N9, the first terminal of the twelfth transistor T12 is electrically connected to the sixth power supply terminal V6, and the second terminal of the twelfth transistor T12 is electrically connected to the signal output terminal OUT; the control terminal of the thirteenth transistor T13 is electrically connected to the second node N2, the first terminal of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT, and the second terminal of the thirteenth transistor T13 is electrically connected to the eighth power supply terminal V8; the control terminal of the fourteenth transistor T14 is electrically connected to the fifth power supply terminal V5, the first terminal of the fourteenth transistor T14 is electrically connected to the first node N1, and the fourteenth transistor T14... The second terminal of capacitor 14 is electrically connected to the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascaded output terminal CR; the second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4; the third capacitor C3 includes a first plate C31 and a second plate C32. The first plate C31 of the third capacitor is electrically connected to the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3;The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 is electrically connected to the ninth node N9, and the second plate C42 is electrically connected to the signal output terminal OUT.

[0288] In one exemplary embodiment, as shown in FIG23B, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are P-type transistors.

[0289] In one exemplary embodiment, the signal at the first power supply terminal V1 is a high-level signal, and the signal at the second power supply terminal V2 is a low-level signal.

[0290] In one exemplary embodiment, the signal at the fourth power supply terminal V4 is a high-level signal, the signal at the fifth power supply terminal V5 is a low-level signal, the signal at the sixth power supply terminal V6 is a high-level signal, and the signal at the eighth power supply terminal V8 is a low-level signal.

[0291] In one exemplary embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0292] Figure 23B illustrates an exemplary structure of a shift register. It will be readily understood by those skilled in the art that the implementation of a shift register is not limited to this.

[0293] Figure 24 is an equivalent circuit diagram of a reset sub-circuit provided in an exemplary embodiment. As shown in Figure 24, the reset sub-circuit includes: a fifteenth transistor T15.

[0294] In one exemplary embodiment, as shown in FIG24, the control terminal of the fifteenth transistor T15 is electrically connected to the reset signal terminal RST, the first terminal of the fifteenth transistor T15 is electrically connected to the seventh power supply terminal V7, and the second terminal of the fifteenth transistor T15 is electrically connected to the first node N1.

[0295] In one exemplary embodiment, the signal at the seventh power supply terminal V7 is a low-level signal.

[0296] Figure 24 shows an exemplary structure of the reset sub-circuit. It will be readily understood by those skilled in the art that the implementation of the reset sub-circuit is not limited to this.

[0297] This disclosure also provides a gate driving circuit, including: a plurality of cascaded shift registers, wherein at least one output signal terminal of at least one shift register includes: a signal output terminal;

[0298] The signal output terminal of the i-th stage shift register is electrically connected to the signal input terminal of the (i+L)-th stage shift register, 1≤i≤ML, M is the total number of stages of the shift register, M≥1, and L is a positive integer greater than or equal to 1.

[0299] The shift register is the shift register provided in any of the foregoing embodiments, and its implementation principle and effect are similar, so it will not be described again here.

[0300] This disclosure also provides a display device, including a display area and a non-display area. The display area is provided with an array of pixel driving circuits, and the non-display area is provided with a gate driving circuit. The pixel driving circuit includes at least one light-emitting control transistor. At least one shift register in the gate driving circuit is electrically connected to at least one light-emitting control transistor in at least one row of the pixel driving circuit.

[0301] The gate drive circuit is the same as the gate drive circuit provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0302] Figure 25 is a structural circuit diagram of a display device provided in an exemplary embodiment. As shown in Figure 25, the control sub-circuit is electrically connected to the signal input terminal IN and the first clock signal terminal CLK1, respectively. The display device also includes: an initial signal line STV, a first clock signal line CK1, and a second clock signal line CK2. The signal input terminal IN of at least one shift register is electrically connected to the initial signal line STV, and the first clock signal terminal CLK1 is electrically connected to one of the first clock signal lines CK1 and CK2. The first clock signal terminals CLK1 of adjacent shift registers are connected to different signal lines.

[0303] Figure 26 is an output timing diagram of a multi-stage shift register provided in an exemplary embodiment. As shown in Figure 26, the signal input terminal IN of the first-stage shift register is electrically connected to the initial signal line STV, the signal output terminal of the i-th-stage shift register is electrically connected to the signal input terminal of the (i+1)-th-stage shift register, and the first clock signal terminal CLK1 of at least one stage shift register is electrically connected to one of the first clock signal lines CK1 and the second clock signal line CK2. The timing diagram shown in Figure 26 can be output to realize the shifting of the output signal.

[0304] Figure 27 is a structural circuit diagram of a display device provided in an exemplary embodiment. As shown in Figure 27, the control sub-circuit is electrically connected to the signal input terminal IN and the first clock signal terminal CLK1, respectively. The display device also includes: an initial signal line STV, a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK4; the signal input terminal IN of at least one shift register is electrically connected to the initial signal line STV; the first clock signal terminal CLK1 of the 4M-3th stage shift register is electrically connected to the first clock signal line CK1, the first clock signal terminal CLK1 of the 4M-2nd stage shift register is electrically connected to the second clock signal line CK2, the first clock signal terminal CLK1 of the 4M-1st stage shift register is electrically connected to the third clock signal line CK3, and the first clock signal terminal CLK1 of the 4Mth stage shift register is electrically connected to the fourth clock signal line CK4; wherein, M is the total number of stages of the shift register, and M≥1.

[0305] Figure 28 is an output timing diagram of a multi-stage shift register provided in an exemplary embodiment. As shown in Figure 28, the signal input terminal IN of the first-stage shift register is electrically connected to the initial signal line STV. The signal output terminal of the i-th stage shift register is electrically connected to the signal input terminal of the (i+2)-th stage shift register. The first clock signal terminal CLK1 of the 4M-3-th stage shift register is electrically connected to the first clock signal line CK1. The first clock signal terminal CLK1 of the 4M-2-th stage shift register is electrically connected to the second clock signal line CK2. The first clock signal terminal CLK1 of the 4M-1-th stage shift register is electrically connected to the third clock signal line CK3. The first clock signal terminal CLK1 of the 4M-th stage shift register is electrically connected to the fourth clock signal line CK4. The timing diagram shown in Figure 28 can be output to realize the shifting of the output signal.

[0306] This disclosure also provides a method for driving a shift register, configured to drive the shift register. The method for driving the shift register may include:

[0307] The control sub-circuit provides signals to the first node or the second node under the control of the signals at the signal input terminal and the first clock signal terminal;

[0308] The output sub-circuit provides a signal to at least one output signal terminal under the control of the signals of the first node, the second node, and at least one power signal terminal;

[0309] The duration of the effective level signal provided by the output sub-circuit is longer than the period duration of the signal provided by the first clock signal terminal.

[0310] The shift register is the shift register provided in any of the foregoing embodiments, and its implementation principle and effect are similar, so it will not be described again here.

[0311] Figure 29 is a schematic diagram of the structure of the shift register provided in the embodiment of this disclosure. As shown in Figure 29, the shift register provided in the embodiment of this disclosure may include a control sub-circuit and an output sub-circuit.

[0312] As shown in Figure 29, the control sub-circuit is electrically connected to the signal input terminal IN, the clock signal terminal CK, at least one low-level power supply terminal VN1, at least one high-level power supply terminal VN2, the first node ND1, the second node ND2, and the third node ND3, respectively. It is configured to provide signals to the first node ND1 and the second node ND2 under the control of the signals from the signal input terminal IN, the clock signal terminal CK, at least one low-level power supply terminal VN1, at least one high-level power supply terminal VN2, and the third node ND3, respectively. The output sub-circuit is electrically connected to at least one output signal terminal Gn, at least one high-level power supply terminal VN2, at least one low-level power supply terminal VN1, the first node ND1, the second node ND2, and the third node ND3, respectively. It is configured to provide signals to the third node ND3 and at least one output signal terminal Gn under the control of the signals from at least one high-level power supply terminal VN2, at least one low-level power supply terminal VN1, the first node ND1, and the second node ND2, respectively.

[0313] Figure 30 is a schematic diagram of the shift register provided in an exemplary embodiment. As shown in Figure 30, the control subcircuit includes a first node control subcircuit and a second node control subcircuit, and the output subcircuit includes a first output control subcircuit and a second output control subcircuit.

[0314] As shown in Figure 30, the first node control sub-circuit is electrically connected to the signal input terminal IN, the clock signal terminal CK, at least one high-level power supply terminal VN2, the first node ND1, and the second node ND2, respectively. It is configured to provide at least one high-level power supply terminal VN2 signal to the first node ND1 and the signal input terminal IN signal to the second node ND2 under the control of the signal from at least one of the signal input terminals IN and CK. The second node control sub-circuit is electrically connected to at least one low-level power supply terminal VN1, the first node ND1, and the third node ND3, respectively. It is configured to provide at least one low-level power supply terminal VN1 signal to the first node ND1 under the control of the signal from the third node ND3.

[0315] As shown in Figure 30, the first output control sub-circuit is electrically connected to at least one signal terminal of at least one high-level power supply terminal VN2 and at least one low-level power supply terminal VN1, the second node ND2, and the third node ND3, and is configured to provide the signal of the second node ND2 to the third node ND3 under the control of the signal of at least one signal terminal of at least one high-level power supply terminal VN2 and at least one low-level power supply terminal VN1; the second output control sub-circuit is electrically connected to at least one high-level power supply terminal VN2, at least one low-level power supply terminal VN1, at least one output signal terminal Gn, the first node ND1, and the third node ND3, and is configured to provide the signal of at least one signal terminal of at least one high-level power supply terminal VN2 and at least one low-level power supply terminal VN2 to at least one output signal terminal Gn under the control of the signal of the first node ND1 and the third node ND3.

[0316] Figure 31 is a schematic diagram of the connection of the shift register provided in Figure 30. As shown in Figure 31, at least one output signal terminal Gn includes: a cascaded output terminal CR and a signal output terminal OUT. At least one high-level power supply terminal connected to the output sub-circuit includes: a first high-level power supply terminal VH1 and a second high-level power supply terminal VH2. At least one low-level power supply terminal connected to the output sub-circuit includes: a first low-level power supply terminal VL1 and a second low-level power supply terminal VL2. At least one high-level power supply terminal connected to the control sub-circuit includes: a second high-level power supply terminal VH2. At least one low-level power supply terminal connected to the control sub-circuit includes: at least one signal terminal among the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2.

[0317] At least one output signal terminal Gn in this disclosure includes a cascaded output terminal CR and a signal output terminal OUT. The cascaded output terminal CR can provide cascaded signals to the signal input terminals of other stages of the shift register, which is beneficial for the transmission of cascaded signals. The signal output terminal OUT can provide drive signals to the pixel driving circuit located in the display area. This disclosure uses different signal terminals for the cascaded signals and drive signals, which not only facilitates the transmission of cascaded signals but also reduces the load on the signal output terminals, making the shift register suitable for display products capable of high-frequency driving.

[0318] Figure 32 is an equivalent circuit diagram of the first node control sub-circuit in the shift register provided in Figure 31. As shown in Figure 32, the first node control sub-circuit includes: a first transistor T1, a second transistor T2, and a third transistor T3. Specifically, the control electrode of the first transistor T1 is electrically connected to the clock signal terminal CK, its first electrode is electrically connected to the signal input terminal IN, and its second electrode is electrically connected to the second node ND2; the control electrode of the second transistor T2 is electrically connected to the signal input terminal IN, its first electrode is electrically connected to the second high-level power supply terminal VH2, and its second electrode is electrically connected to the fourth node ND4; the control electrode of the third transistor T3 is electrically connected to the clock signal terminal CK, its first electrode is electrically connected to the fourth node ND4, and its second electrode is electrically connected to the first node ND1.

[0319] In an exemplary embodiment, at least one of the first transistor T1 to the third transistor T3 is a P-type transistor.

[0320] Figure 33 is an equivalent circuit diagram of the second node control sub-circuit in the shift register provided in Figure 31. As shown in Figure 33, the second node control sub-circuit includes a fourth transistor T4. The fourth transistor T4 has a single-gate structure, or the control electrode of the fourth transistor T4 includes a first control electrode and a second control electrode. The shift register is disposed on the substrate, and the second control electrode is disposed on the side of the first control electrode close to the substrate. Wherein, when the fourth transistor T4 has a single-gate structure, the control electrode of the fourth transistor T4 is electrically connected to the third node ND3, the first electrode of the fourth transistor T4 is electrically connected to one of the signal terminals of the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2, and the second electrode of the fourth transistor T4 is electrically connected to the first node ND1. When the control electrode of the fourth transistor T4 includes a first control electrode and a second control electrode, the first control electrode of the fourth transistor T4 is electrically connected to the third node ND3, the second control electrode of the fourth transistor T4 is electrically connected to one of the signal terminals of the first low-level power supply terminal VL1, the second low-level power supply terminal VL2 and the third low-level power supply terminal VL3, the first electrode of the fourth transistor T4 is electrically connected to one of the signal terminals of the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2, and the second electrode of the fourth transistor T4 is electrically connected to the first node ND1.

[0321] When the control electrode of the fourth transistor T4 includes a first control electrode and a second control electrode, this disclosure provides that the control electrode of the fourth transistor includes a first control electrode and a second control electrode electrically connected to one of the signal terminals of the first low-level power supply terminal VL1, the second low-level power supply terminal VL2, and the third low-level power supply terminal VL3. This can ensure the stability of the threshold voltage of the fourth transistor T4 and reduce the deviation of the threshold voltage of the fourth transistor after being biased.

[0322] In an exemplary embodiment, the fourth transistor T4 is an N-type transistor. Since the first terminal of the fourth transistor T4 is connected to a low-level power supply, this disclosure reduces the power consumption of the shift register by making the fourth transistor an N-type transistor.

[0323] In an exemplary embodiment, the voltage value of the signal at the third low-level power supply terminal VL3 is higher than the voltage value of the signal at at least one of the signal terminals at the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2.

[0324] In an exemplary embodiment, FIG34 is an equivalent circuit diagram of the first output control sub-circuit in the shift register provided in FIG31. As shown in FIG34, the first output control sub-circuit includes a fifth transistor T5. The control terminal of the fifth transistor T5 is electrically connected to one of the signal terminals of the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2, the first terminal of the fifth transistor T5 is electrically connected to the second node ND2, and the second terminal of the fifth transistor T5 is electrically connected to the third node ND3.

[0325] In an exemplary embodiment, FIG35 is a second equivalent circuit diagram of the first output control sub-circuit in the shift register provided in FIG31. As shown in FIG35, the first output control sub-circuit includes a fifth transistor T5. The control terminal of the fifth transistor T5 is electrically connected to the third low-level power supply terminal VL3, the first terminal of the fifth transistor T5 is electrically connected to the second node ND2, and the second terminal of the fifth transistor T5 is electrically connected to the third node ND3.

[0326] In an exemplary embodiment, the difference between the voltage value of the signal at the third low-level power supply terminal VL3 and the voltage value of the signal at the second low-level power supply terminal VL2 is greater than the threshold voltage of the fifth transistor.

[0327] In an exemplary embodiment, since the signal input terminal IN receives a signal from the second low-level power supply terminal VL2 for a portion of the time, the control electrode of the fifth transistor T5 is electrically connected to the third low-level power supply terminal VL3, and the difference between the voltage value of the signal from the third low-level power supply terminal VL3 and the voltage value of the signal from the second low-level power supply terminal VL2 is greater than the threshold voltage of the fifth transistor, the fifth transistor T5 will disconnect when the signal from the first electrode of the fifth transistor is the signal from at least one signal terminal of the second low-level power supply terminal VL2. This can improve the leakage current of the fifth transistor T5, enhance the stability of the signal from the second node N2, improve the display abnormalities and flickering problems when the display product is displayed at a low refresh rate, and improve the display effect of the display product.

[0328] In the exemplary embodiment, in the shift register provided in Figures 34 and 35, the fifth transistor T5 is a P-type transistor. Since the control electrode of the fifth transistor T5 is electrically connected to one of the signal terminals of the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2, the fifth transistor T5 is always in the on state.

[0329] In an exemplary embodiment, Figure 36 is an equivalent circuit diagram of the first output control sub-circuit in the shift register provided in Figure 31. As shown in Figure 36, the first output control sub-circuit includes a fifth transistor T5. The control terminal of the fifth transistor T5 is electrically connected to one of the signal terminals of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2. The first terminal of the fifth transistor T5 is electrically connected to the second node ND2, and the second terminal of the fifth transistor T5 is electrically connected to the third node ND3.

[0330] In an exemplary embodiment, the fifth transistor T5 in the shift register shown in FIG36 is an N-type transistor. The fact that the fifth transistor T5 is an N-type transistor can reduce leakage current, improve display abnormalities and flickering issues when the display product is used at low refresh rates, and enhance the display effect of the display product.

[0331] In an exemplary embodiment, in the shift register provided in FIG36, the fifth transistor T5 is an N-type transistor. Since the control electrode of the fifth transistor T5 is electrically connected to one of the signal terminals of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2, the fifth transistor T5 is always in the on state.

[0332] In an exemplary embodiment, Figure 37 is an equivalent circuit diagram of the second output control sub-circuit in the shift register provided in Figure 31, and Figure 38 is an equivalent circuit diagram of the second output control sub-circuit in the shift register provided in Figure 31. As shown in Figures 37 and 38, the second output control sub-circuit includes: a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2. At least one of the first capacitor C1 and the second capacitor C2 includes: a first plate and a second plate. Specifically, the control electrode of the sixth transistor T6 is electrically connected to the first node ND1, the first electrode of the sixth transistor T6 is electrically connected to the second high-level power supply terminal VH2, and the second electrode of the sixth transistor T6 is electrically connected to the cascaded output terminal CR; the control electrode of the seventh transistor T7 is electrically connected to the third node ND3, the first electrode of the seventh transistor T7 is electrically connected to the second low-level power supply terminal VL2, and the second electrode of the seventh transistor T7 is electrically connected to the cascaded output terminal CR; the control electrode of the eighth transistor T8 is electrically connected to the first node ND1, the first electrode of the eighth transistor T8 is electrically connected to the first high-level power supply terminal VH1, and the second electrode of the eighth transistor T8 is electrically connected to the cascaded output terminal CR. The second electrode is electrically connected to the signal output terminal OUT; the control electrode of the ninth transistor T9 is electrically connected to the third node ND3, the first electrode of the ninth transistor T9 is electrically connected to the first low-level power supply terminal VL1, and the second electrode of the ninth transistor T9 is electrically connected to the signal output terminal OUT; the first plate of the first capacitor C1 is electrically connected to the first node ND1, and the second plate of the first capacitor C1 is electrically connected to one of the signal terminals of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2; the first plate of the second capacitor C2 is electrically connected to the third node ND3, and the second plate of the second capacitor C2 is electrically connected to the cascaded output terminal CR. Figure 37 illustrates the case where the second plate of the first capacitor C1 is electrically connected to the second high-level power supply terminal VH2, and Figure 38 illustrates the case where the second plate of the first capacitor C1 is electrically connected to the first high-level power supply terminal VH1.

[0333] In an exemplary embodiment, as shown in Figures 37 and 38, at least one of the sixth transistor T6 to the ninth transistor T9 is a P-type transistor.

[0334] In an exemplary embodiment, Figure 39 is an equivalent circuit diagram three of the second output control sub-circuit in the shift register provided in Figure 31, Figure 40 is an equivalent circuit diagram four of the second output control sub-circuit in the shift register provided in Figure 31, and Figure 41 is an equivalent circuit diagram five of the second output control sub-circuit in the shift register provided in Figure 31. The difference between the second output control sub-circuit provided in Figures 39 to 41 and the second output control sub-circuit provided in Figure 37 is that the second output control sub-circuit in Figures 39 to 41 further includes at least one of the tenth transistor T10 and the eleventh transistor T11; at least one of the tenth transistor T10 and the eleventh transistor T11 has a single-gate structure, or the control electrode of at least one of the tenth transistor T10 and the eleventh transistor T11 includes a first control electrode and a second control electrode, the shift register is disposed on the substrate, and the second control electrode is disposed on the side of the first control electrode close to the substrate.

[0335] In an exemplary embodiment, when the tenth transistor T10 has a single-gate structure, the control electrode of the tenth transistor T10 is electrically connected to the first node ND1, the first electrode of the tenth transistor T10 is electrically connected to the second low-level power supply terminal VL2, and the second electrode of the tenth transistor T10 is electrically connected to the cascaded output terminal CR. When the control electrode of the tenth transistor T10 includes both a first control electrode and a second control electrode, the first control electrode of the tenth transistor T10 is electrically connected to the first node ND1, the second control electrode of the tenth transistor T10 is electrically connected to at least one signal terminal among the first low-level power supply terminal VL1, the second low-level power supply terminal VL2, and the third low-level power supply terminal VL3, the first electrode of the tenth transistor T10 is electrically connected to the second low-level power supply terminal VL2, and the second electrode of the tenth transistor T10 is electrically connected to the cascaded output terminal CR.

[0336] In an exemplary embodiment, when the eleventh transistor T11 has a single-gate structure, the control electrode of the eleventh transistor T11 is electrically connected to the first node ND1, the first electrode of the eleventh transistor T11 is electrically connected to the first low-level power supply terminal VL1, and the second electrode of the eleventh transistor T11 is electrically connected to the signal output terminal OUT. When the control electrode of the eleventh transistor T11 includes both a first control electrode and a second control electrode, the first control electrode of the eleventh transistor T11 is electrically connected to the first node ND1, the second control electrode of the eleventh transistor T11 is electrically connected to at least one of the first low-level power supply terminals VL1, VL2, and VL3, the first electrode of the eleventh transistor T11 is electrically connected to the first low-level power supply terminal VL1, and the second electrode of the eleventh transistor T11 is electrically connected to the signal output terminal OUT.

[0337] Figure 39 illustrates the second output control sub-circuit as having only the tenth transistor T10, Figure 40 illustrates the second output control sub-circuit as having only the eleventh transistor T11, and Figure 41 illustrates the second output control sub-circuit as having both the tenth transistor T10 and the eleventh transistor T11.

[0338] In an exemplary embodiment, at least one of the tenth transistor T10 and the eleventh transistor T11 is an N-type transistor.

[0339] The tenth transistor T10 in this disclosure can output a signal to the cascaded output terminal together with the seventh transistor T7, which can reduce the duration of the falling edge of the output signal at the cascaded output terminal and ensure the stability of the signal at the cascaded output terminal, thereby making the shift register suitable for high-frequency driven display devices.

[0340] The eleventh transistor T11 in this disclosure can output a signal to the signal output terminal together with the ninth transistor T9, which can reduce the duration of the falling edge of the output signal at the signal output terminal and ensure the stability of the signal at the signal output terminal, thereby making the shift register suitable for high-frequency driven display devices.

[0341] In an exemplary embodiment, the signal received by the first high-level power supply terminal VH1 is the same as the signal received by the second high-level power supply terminal VH2, or the signal received by the first low-level power supply terminal VL1 is the same as the signal received by the second low-level signal terminal.

[0342] In an exemplary embodiment, Figure 42 is a second connection diagram of the shift register provided in Figure 30. As shown in Figure 42, at least one output signal terminal Gn includes: a signal output terminal OUT; at least one high-level power supply terminal connected to the output sub-circuit includes: a high-level power supply terminal VH; at least one low-level power supply terminal connected to the output sub-circuit includes: a first low-level power supply terminal VL1; at least one high-level power supply terminal connected to the control sub-circuit includes: a high-level power supply terminal VH; at least one low-level power supply terminal connected to the control sub-circuit includes: a first low-level power supply terminal VL1.

[0343] Figure 43 is an equivalent circuit diagram of the first node control sub-circuit in the shift register provided in Figure 42. As shown in Figure 43, the first node control sub-circuit includes: a first transistor T1, a second transistor T2, and a third transistor T3. Specifically, the control electrode of the first transistor T1 is electrically connected to the clock signal terminal CK, its first electrode is electrically connected to the signal input terminal IN, and its second electrode is electrically connected to the second node ND2. Similarly, the control electrode of the second transistor T2 is electrically connected to the signal input terminal IN, its first electrode is electrically connected to the high-level power supply terminal, and its second electrode is electrically connected to the fourth node ND4. Finally, the control electrode of the third transistor T3 is electrically connected to the clock signal terminal CK, its first electrode is electrically connected to the fourth node ND4, and its second electrode is electrically connected to the first node ND1.

[0344] In an exemplary embodiment, as shown in FIG43, at least one of the first transistor T1 to the third transistor T3 is a P-type transistor.

[0345] Figure 44 is an equivalent circuit diagram of the second node control sub-circuit in the shift register provided in Figure 42. As shown in Figure 43, the second node control sub-circuit includes: a fourth transistor T4, which is a single-gate structure; or, the control electrode of the fourth transistor T4 includes: a first control electrode and a second control electrode. The shift register is disposed on the substrate, and the second control electrode is disposed on the side of the first control electrode close to the substrate.

[0346] In an exemplary embodiment, when the fourth transistor T4 has a single-gate structure, the control electrode of the fourth transistor T4 is electrically connected to the third node ND3, the first electrode of the fourth transistor T4 is electrically connected to the first low-level power supply terminal VL1, and the second electrode of the fourth transistor T4 is electrically connected to the first node ND1.

[0347] In an exemplary embodiment, when the control electrode of the fourth transistor T4 includes a first control electrode and a second control electrode, the first control electrode of the fourth transistor T4 is electrically connected to the third node ND3, the second control electrode of the fourth transistor T4 is electrically connected to at least one of the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2, the first electrode of the fourth transistor T4 is electrically connected to the first low-level power supply terminal VL1, and the second electrode of the fourth transistor T4 is electrically connected to the first node ND1.

[0348] In an exemplary embodiment, when the control electrode of the fourth transistor T4 includes a first control electrode and a second control electrode, this disclosure ensures the stability of the threshold voltage of the fourth transistor T4 and reduces the deviation of the threshold voltage of the fourth transistor after being biased by including the first control electrode and the second control electrode as being electrically connected to one of the signal terminals of the first low-level power supply terminal VL1, the second low-level power supply terminal VL2 and the third low-level power supply terminal VL3.

[0349] In an exemplary embodiment, the fourth transistor T4 is an N-type transistor. Since the first terminal of the fourth transistor T4 is connected to a low-level power supply, this disclosure reduces the power consumption of the shift register by making the fourth transistor an N-type transistor.

[0350] Figure 45 is an equivalent circuit diagram of the first output control sub-circuit in the shift register provided in Figure 42. As shown in Figure 45, the first output control sub-circuit includes a fifth transistor T5. The control terminal of the fifth transistor T5 is electrically connected to the first low-level power supply terminal VL1, the first terminal of the fifth transistor T5 is electrically connected to the second node ND2, and the second terminal of the fifth transistor T5 is electrically connected to the third node ND3.

[0351] In an exemplary embodiment, the fifth transistor T5 is a P-type transistor. Since the control electrode of the fifth transistor T5 is electrically connected to the first low-level power supply terminal VL1, the fifth transistor T5 is always in the on state.

[0352] Figure 46 is an equivalent circuit diagram of the second output control sub-circuit in the shift register provided in Figure 42. As shown in Figure 46, the second output control sub-circuit includes: a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2. At least one of the first capacitors C1 and C2 includes a first plate and a second plate. Specifically, the control electrode of the sixth transistor T6 is electrically connected to the first node ND1, the first electrode of the sixth transistor T6 is electrically connected to the high-level power supply terminal, and the second electrode of the sixth transistor T6 is electrically connected to the signal output terminal OUT. The control electrode of the seventh transistor T7 is electrically connected to the third node ND3, the first electrode of the seventh transistor T7 is electrically connected to the first low-level power supply terminal VL1, and the second electrode of the seventh transistor T7 is electrically connected to the signal output terminal OUT. The first plate of the first capacitor C1 is electrically connected to the first node ND1, and the second plate of the first capacitor C1 is electrically connected to the high-level power supply terminal. The first plate of the second capacitor C2 is electrically connected to the third node ND3, and the second plate of the second capacitor C2 is electrically connected to the signal output terminal OUT.

[0353] In an exemplary embodiment, at least one of the sixth transistor T6 and the seventh transistor T7 is a P-type transistor.

[0354] Figure 47 is an equivalent circuit diagram of the second output control sub-circuit in the shift register provided in Figure 42. The second output control sub-circuit provided in Figure 47 differs from the second output control sub-circuit provided in Figure 46 in that it further includes a twelfth transistor T12, which is a single-gate structure. Alternatively, the control electrode of the twelfth transistor T12 includes a first control electrode and a second control electrode. The shift register is mounted on the substrate, and the second control electrode is located on the side of the first control electrode closer to the substrate. When the twelfth transistor T12 has a single-gate structure, its control electrode is electrically connected to the first node ND1, its first electrode is electrically connected to the signal output terminal OUT, and its second electrode is electrically connected to the first low-level power supply terminal VL1. When the control electrode of the twelfth transistor T12 includes both a first control electrode and a second control electrode, the first control electrode of the twelfth transistor T12 is electrically connected to the first node ND1, the second control electrode of the twelfth transistor T12 is electrically connected to one of the signal terminals of the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2, the first electrode of the twelfth transistor T12 is electrically connected to the signal output terminal OUT, and the second electrode of the twelfth transistor T12 is electrically connected to the first low-level power supply terminal VL1.

[0355] In an exemplary embodiment, the twelfth transistor T12 is an N-type transistor.

[0356] The twelfth transistor T12 in this disclosure can output a signal to the signal output terminal together with the seventh transistor T7, which can ensure the stability of the signal at the signal output terminal.

[0357] Figure 48 is another structural schematic diagram of the shift register provided in Figure 29. As shown in Figure 48, the shift register further includes a power-on control sub-circuit. This power-on control sub-circuit is electrically connected to the power-on control signal terminal CX, at least one high-level power supply terminal VN2, and the first node ND1, and is configured to provide at least one high-level power supply terminal VN2 signal to the first node ND1 under the control of the signal from the power-on control signal terminal CX.

[0358] Figure 49 is the equivalent circuit diagram of the power-on control sub-circuit. As shown in Figure 49, the power-on control sub-circuit includes a thirteenth transistor T13. The control terminal of the thirteenth transistor T13 is electrically connected to the power-on control signal terminal CX, the first terminal of the thirteenth transistor T13 is electrically connected to at least one high-level power supply terminal VN2, and the second terminal of the thirteenth transistor T13 is electrically connected to the first node ND1.

[0359] In an exemplary embodiment, the power-on control signal terminal CX is an active level signal during the power-on phase and an inactive level signal during the display phase. An active level signal at the signal terminal refers to a signal that turns on the transistor connected to the signal terminal, while an inactive level signal at the signal terminal refers to a signal that turns off the transistor connected to the signal terminal.

[0360] In an exemplary embodiment, the power-on control subcircuit can prevent screen flickering upon power-on of the display device and improve the reliability of the shift register.

[0361] Figure 50 is an equivalent circuit diagram of the shift register provided in Figure 31. As shown in Figure 50, at least one output signal terminal includes a cascaded output terminal CR and a signal output terminal OUT. The shift register may also include a control sub-circuit and an output sub-circuit, or a control sub-circuit, an output sub-circuit, and a power-on control sub-circuit. The power-on control sub-circuit includes a first transistor to a fourth transistor, and the output transistors include a fifth transistor T5 to a ninth transistor T9, a first capacitor C1, and a second capacitor C2. The power-on control sub-circuit also includes a thirteenth transistor T13. The fourth transistor T4 has a single-gate structure, or the control electrode of the fourth transistor T4 includes a first control electrode and a second control electrode. Specifically, the control electrode of the first transistor T1 is electrically connected to the clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the second node ND2; the control electrode of the second transistor T2 is electrically connected to the signal input terminal IN, the first electrode of the second transistor T2 is electrically connected to the second high-level power supply terminal VH2, and the second electrode of the second transistor T2 is electrically connected to the fourth node ND4; the control electrode of the third transistor T3 is electrically connected to the clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the fourth node ND4, and the second electrode of the third transistor T3 is electrically connected to the first node ND1; when the fourth transistor T4 is a single-gate structure, the control electrode of the fourth transistor T4 is electrically connected to the third node ND3, the first electrode of the fourth transistor T4 is electrically connected to one of the signal terminals of the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2, and the second electrode of the fourth transistor T4 is electrically connected to the first node ND1.The control electrode of the fourth transistor T4 includes: when the first control electrode and the second control electrode are present, the first control electrode of the fourth transistor T4 is electrically connected to the third node ND3, and the second control electrode of the fourth transistor T4 is electrically connected to one of the signal terminals of the first low-level power supply terminal VL1, the second low-level power supply terminal VL2, and the third low-level power supply terminal VL3; the first electrode of the fourth transistor T4 is electrically connected to one of the signal terminals of the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2, and the second electrode of the fourth transistor T4 is electrically connected to the first node ND1. The control electrode of the fifth transistor T5 is electrically connected to one of the signal terminals of the first low-level power supply terminal VL1, the second low-level power supply terminal VL2, and the third low-level power supply terminal VL3; the first electrode of the fifth transistor T5 is electrically connected to the second node ND2, and the second electrode of the fifth transistor T5 is electrically connected to the third node ND3. The control electrode of the sixth transistor T6 is electrically connected to the first node ND1, and the first electrode of the sixth transistor T6 is electrically connected to the second high-level power supply terminal VH2. The second terminal of the sixth transistor T6 is electrically connected to the cascaded output terminal CR; the control terminal of the seventh transistor T7 is electrically connected to the third node ND3, the first terminal of the seventh transistor T7 is electrically connected to the second low-level power supply terminal VL2, and the second terminal of the seventh transistor T7 is electrically connected to the cascaded output terminal CR; the control terminal of the eighth transistor T8 is electrically connected to the first node ND1, the first terminal of the eighth transistor T8 is electrically connected to the first high-level power supply terminal VH1, and the second terminal of the eighth transistor T8 is electrically connected to the signal output terminal OUT; the control terminal of the ninth transistor T9 is electrically connected to the third node ND3, the first terminal of the ninth transistor T9 is electrically connected to the first low-level power supply terminal VL1, and the second terminal of the ninth transistor T9 is electrically connected to the signal output terminal OUT; the first plate of the first capacitor C1 is electrically connected to the first node ND1, and the second plate of the first capacitor C1 is electrically connected to the second high-level power supply terminal VH2; the first plate of the second capacitor C2 is electrically connected to the third node ND3, and the second plate of the second capacitor C2 is electrically connected to the cascaded output terminal CR.

[0362] In an exemplary embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 in the shift register provided in FIG50 are P-type transistors. The fourth transistor T4 is an N-type transistor.

[0363] In an exemplary embodiment, a shift register is disposed in the display device. The operation of the display device includes a power-on stage and a display stage. During the display stage, the display device displays content, and the displayed content includes multiple display frames. The driving modes of the display device include a first driving mode and a second driving mode. The refresh rate of the display device in the first driving mode is lower than the refresh rate of the display device in the second driving mode. For example, the refresh rate of the first driving mode can be 1Hz-60Hz, and the refresh rate of the second driving mode can be 60Hz-480Hz. The content displayed on the display substrate includes multiple display frames. In the second driving mode, at least one display frame includes a refresh frame. In the first driving mode, at least one display frame includes a refresh frame and at least one hold frame.

[0364] During the display phase, the power-on control signal terminal CX is at an invalid level. The thirteenth transistor T13 remains off. The signals at the first low-level power supply terminal VL1, the second low-level power supply terminal VL2, and the third low-level power supply terminal VL3 are all at a low level. The fifth transistor T5 remains on.

[0365] Figure 51 is a timing diagram of the shift register provided in Figure 50 during the refresh frame. As shown in Figure 51, the exemplary embodiments of this disclosure will be described below through the operation of the shift register provided in Figure 50.

[0366] In the first stage, the signals at P1, the signal input terminal IN, and the clock signal terminal CK are all low-level signals. The first transistor T1, the second transistor T2, and the third transistor T3 are turned on.

[0367] The first transistor T1 is turned on, and the low-level signal at the signal input terminal IN is written to the second node ND2 and the third node N3 through the turned-on first transistor T1 and the turned-on fifth transistor T5. The signal at the third node N3 is a low-level signal, the fourth transistor T4 is turned off, and the seventh transistor T7 and the ninth transistor T9 are turned on. The seventh transistor T7 is turned on, and the signal at the second low-level power supply terminal VL2 is written to the cascaded output terminal CR. The ninth transistor T9 is turned on, and the signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT. The second transistor T2 and the third transistor T3 are turned on, and the signal at the second high-level power supply terminal VH2 is written to the fourth node ND4 and the first node ND1 through the turned-on second transistor T2 and the turned-on third transistor T3. The signal at the first node ND1 is a high-level signal, and the sixth transistor T6 and the eighth transistor T8 are turned off.

[0368] During this stage, the cascaded output terminal CR and the signal output terminal OUT output low-level signals.

[0369] In the second stage, the signals at P2, the signal input terminal IN, and the clock signal terminal CK are high-level signals. The first transistor T1, the second transistor T2, and the third transistor T3 are disconnected.

[0370] Under the influence of the first capacitor C1, the signal at the first node ND1 remains the same as in the previous stage. Under the influence of the second capacitor C2, the signal at the third node ND3 remains at the low level of the previous stage. The fourth transistor T4 is off, while the seventh transistor T7 and the ninth transistor T9 are on. When the seventh transistor T7 is on, the signal at the second low-level power supply terminal VL2 is written to the cascaded output terminal CR. When the ninth transistor T9 is on, the signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT.

[0371] During this stage, the cascaded output terminal CR and the signal output terminal OUT output low-level signals.

[0372] In the third stage, the signal at P3 and the signal input terminal IN is a high-level signal, and the signal at the clock signal terminal CK is a low-level signal. The first transistor T1 and the third transistor T3 are turned on, and the second transistor T2 is turned off.

[0373] The first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is written to the second node ND2 and the third node N3 through the turned-on first transistor T1 and the turned-on fifth transistor T5. The signal at the third node N3 is a high-level signal, the fourth transistor T4 is turned on, and the seventh transistor T7 and the eighth transistor T8 are turned off. The fourth transistor T4 is turned on, and the signal at at least one of the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2 is written to the first node ND1, and the sixth transistor T6 and the eighth transistor T8 are turned on. The sixth transistor T6 is turned on, and the signal at the second high-level power supply terminal VH2 is written to the cascaded output terminal CR, and the eighth transistor T8 is turned on, and the signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT. The third transistor T3 is turned on, and the low-level signal at the first node ND1 is written to the third node ND3.

[0374] During this stage, the cascaded output terminal CR and the signal output terminal OUT output high-level signals.

[0375] In the fourth stage, the signals at P4, the signal input terminal IN, and the clock signal terminal CK are high-level signals. The first transistor T1, the second transistor T2, and the third transistor T3 are disconnected.

[0376] Under the influence of the first capacitor C1, the signal at the first node ND1 remains the same as in the previous stage, and the sixth transistor T6 and the eighth transistor T8 remain on. With the sixth transistor T6 on, the signal at the second high-level power supply terminal VH2 is written to the cascaded output terminal CR, and with the eighth transistor T8 on, the signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT. Under the influence of the second capacitor C2, the signal at the third node ND3 remains the high-level signal from the previous stage.

[0377] During this stage, the cascaded output terminal CR and the signal output terminal OUT output high-level signals.

[0378] The working process of the fifth stage, P5, is the same as that of the third stage, P3, and will not be described again here.

[0379] In the sixth stage, the signal at the P6 input terminal IN is a low-level signal, and the signal at the clock signal terminal CK is a high-level signal. The first transistor T1 and the third transistor T3 are disconnected, and the second transistor T2 is turned on.

[0380] The first transistor T1 is off, preventing the low-level signal at the input terminal IN from being written to the second node ND2 and the third node ND3. Under the influence of the second capacitor C2, the signal at the third node ND3 remains at the high-level signal of the previous stage, and the fourth transistor T4 is on. The second transistor T2 is on, and the signal at the second high-level power supply terminal VH2 is written to the fourth node ND4. The fourth transistor T4 is on, and the signal at at least one of the first low-level power supply terminals VL1 and VL2 is written to the first node ND1. The sixth transistor T6 and the eighth transistor T8 are on. The sixth transistor T6 is on, and the signal at the second high-level power supply terminal VH2 is written to the cascaded output terminal CR. The eighth transistor T8 is on, and the signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT.

[0381] During this stage, the cascaded output terminal CR and the signal output terminal OUT output high-level signals.

[0382] The working process of the seventh stage, P7, is the same as that of the first stage, P1, and will not be described again here.

[0383] In the eighth stage, the signal at the P8 input terminal IN is a low-level signal, and the signal at the clock signal terminal CK is a high-level signal. The first transistor T1 and the third transistor T3 are off, and the second transistor T2 is on.

[0384] The first transistor T1 is off, preventing the low-level signal at the signal input terminal IN from being written to the second node ND2 and the third node ND3. Under the influence of the second capacitor C2, the signal at the third node ND3 remains at the low level of the previous stage. The fourth transistor T4 is off, while the seventh transistor T7 and the ninth transistor T9 are on. When the seventh transistor T7 is on, the signal at the second low-level power supply terminal VL2 is written to the cascaded output terminal CR. When the ninth transistor T9 is on, the signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT. The second transistor T2 is on, and the signal at the second high-level power supply terminal VH2 is written to the fourth node ND4. Under the influence of the first capacitor C1, the first node ND1 maintains the high-level signal of the previous stage, and the sixth transistor T6 and the eighth transistor T8 are off.

[0385] During this stage, the cascaded output terminal CR and the signal output terminal OUT output low-level signals.

[0386] Figure 52 is a second equivalent circuit diagram of the shift register provided in Figure 31. The shift register provided in Figure 52 differs from the shift register provided in Figure 50 in the connection method of the second plate of the first capacitor. In the shift register provided in Figure 52, the second plate of the first capacitor C1 is electrically connected to the first high-level power supply terminal VH1.

[0387] The driving timing of the shift register provided in Figure 51 can be applied to the shift register provided in Figure 52. The operation of the shift register provided in Figure 52 under the driving timing provided in Figure 51 is the same as the operation of the shift register provided in Figure 50 under the driving timing provided in Figure 51, and will not be described again here.

[0388] Figure 53 is the equivalent circuit diagram of the shift register provided in Figure 31. The shift register in Figure 53 differs from the shift register in Figure 50 in that it further includes a tenth transistor T10. The tenth transistor T10 has a single-gate structure, or its control electrode includes a first control electrode and a second control electrode. When the tenth transistor T10 has a single-gate structure, its control electrode is electrically connected to the first node ND1, its first electrode is electrically connected to the second low-level power supply terminal VL2, and its second electrode is electrically connected to the cascaded output terminal CR. When the control electrode of the tenth transistor T10 includes a first control electrode and a second control electrode, the first control electrode of the tenth transistor T10 is electrically connected to the first node ND1, the second control electrode of the tenth transistor T10 is electrically connected to at least one of the first low-level power supply terminal VL1, the second low-level power supply terminal VL2 and the third low-level power supply terminal VL3, the first electrode of the tenth transistor T10 is electrically connected to the second low-level power supply terminal VL2, and the second electrode of the tenth transistor T10 is electrically connected to the cascaded output terminal CR.

[0389] In an exemplary embodiment, the tenth transistor T10 is an N-type transistor.

[0390] The driving timing of the shift register provided in Figure 51 can be applied to the shift register provided in Figure 53. The operation of the first transistor T1 to the ninth transistor T9 in the shift register provided in Figure 53 under the driving timing provided in Figure 51 is the same as the operation of the first transistor T1 to the ninth transistor T9 in the shift register provided in Figure 50 under the driving timing provided in Figure 51, and will not be described again here.

[0391] In the shift register shown in Figure 53, since the first node ND1 is a high-level signal in stages P1, P2, P7, and P8, the tenth transistor T10 is turned on in stages P1, P2, P7, and P8. The signal of the second low-level power supply terminal VL2 is written to the cascaded output terminal CR through the tenth transistor T10. At this time, the seventh transistor T7 is also turned on, and the signal of the second low-level power supply terminal VL2 is written to the cascaded output terminal CR through the seventh transistor T7. Since ND1 is a low-level signal in stages P3, P4, P5, and P6, the tenth transistor T10 is turned off, and the second low-level power supply terminal VL2 cannot be written to the cascaded output terminal CR. This ensures that the signal of the cascaded output terminal CR is a high-level signal in stages P3, P4, P5, and P6.

[0392] Figure 54 is the equivalent circuit diagram of the shift register provided in Figure 31. The shift register in Figure 54 differs from the shift register in Figure 50 in that it further includes an eleventh transistor, T11. The eleventh transistor T11 has a single-gate structure, or its control electrode includes a first control electrode and a second control electrode. When the eleventh transistor T11 has a single-gate structure, its control electrode is electrically connected to the first node ND1, its first electrode is electrically connected to the first low-level power supply terminal VL1, and its second electrode is electrically connected to the signal output terminal OUT. When the control electrode of the eleventh transistor T11 includes a first control electrode and a second control electrode, the first control electrode of the eleventh transistor T11 is electrically connected to the first node ND1, the second control electrode of the eleventh transistor T11 is electrically connected to at least one of the first low-level power supply terminal VL1, the second low-level power supply terminal VL2 and the third low-level power supply terminal VL3, the first electrode of the eleventh transistor T11 is electrically connected to the first low-level power supply terminal VL1, and the second electrode of the eleventh transistor T11 is electrically connected to the signal output terminal OUT.

[0393] In an exemplary embodiment, the eleventh transistor T11 is an N-type transistor.

[0394] The driving timing of the shift register provided in Figure 51 can be applied to the shift register provided in Figure 54. The operation of the first transistor T1 to the ninth transistor T9 in the shift register provided in Figure 54 under the driving timing provided in Figure 51 is the same as the operation of the first transistor T1 to the ninth transistor T9 in the shift register provided in Figure 50 under the driving timing provided in Figure 51, and will not be described again here.

[0395] In the shift register shown in Figure 54, since the first node ND1 is a high-level signal in stages P1, P2, P7, and P8, the eleventh transistor T11 is turned on in stages P1, P2, P7, and P8. The signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT through the turned-on eleventh transistor T11. At the same time, the ninth transistor T9 is also turned on, and the signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT through the turned-on ninth transistor T9. Since ND1 is a low-level signal in stages P3, P4, P5, and P6, the eleventh transistor T11 is turned off, and the first low-level power supply terminal VL1 cannot be written to the signal output terminal OUT. This ensures that the signal at the signal output terminal OUT is a high-level signal in stages P3, P4, P5, and P6.

[0396] Figure 55 is the equivalent circuit diagram of the shift register provided in Figure 31. The shift register in Figure 55 differs from the shift register in Figure 50 in that it also includes a tenth transistor T10 and an eleventh transistor T11. The tenth transistor T10 in Figure 55 is the same as the tenth transistor T10 in Figure 53, and will not be described further. The eleventh transistor T11 in Figure 55 is the same as the eleventh transistor T11 in Figure 54, and will not be described further.

[0397] The driving timing of the shift register shown in Figure 51 can be applied to the shift register shown in Figure 55. The operation of the first transistor T1 to the ninth transistor T9 in the shift register shown in Figure 55 under the driving timing shown in Figure 51 is the same as the operation of the first transistor T1 to the ninth transistor T9 in the shift register shown in Figure 50 under the driving timing shown in Figure 51, and will not be repeated here. The operation of the tenth transistor T10 in the shift register shown in Figure 55 under the driving timing shown in Figure 51 is the same as the operation of the tenth transistor T10 in the shift register shown in Figure 53 under the driving timing shown in Figure 51, and will not be repeated here. The operation of the eleventh transistor T11 in the shift register shown in Figure 55 under the driving timing shown in Figure 51 is the same as the operation of the eleventh transistor T11 in the shift register shown in Figure 54 under the driving timing shown in Figure 51, and will not be repeated here.

[0398] Figure 56 is the equivalent circuit diagram of the shift register provided in Figure 31. The shift register provided in Figure 56 differs from the shift register provided in Figure 50 in the transistor type of the fifth transistor and the connection method of the control electrode of the fifth transistor. In the shift register provided in Figure 55, the fifth transistor T5 is an N-type transistor, and the control electrode of the fifth transistor T5 is electrically connected to at least one of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2, which will not be elaborated further here.

[0399] The driving timing of the shift register provided in Figure 51 can be applied to the shift register provided in Figure 56. The operation of the first transistor T1 to the ninth transistor T9 in the shift register provided in Figure 56 under the driving timing provided in Figure 51 is the same as the operation of the first transistor T1 to the ninth transistor T9 in the shift register provided in Figure 50 under the driving timing provided in Figure 51, and will not be described again here.

[0400] Figure 57 is the equivalent circuit diagram of the shift register provided in Figure 31. The shift register provided in Figure 57 differs from the shift register provided in Figure 52 in the transistor type of the fifth transistor and the connection method of the control electrode of the fifth transistor. In the shift register provided in Figure 57, the fifth transistor T5 is an N-type transistor, and the control electrode of the fifth transistor T5 is electrically connected to at least one of the signal terminals of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2, which will not be described in detail here.

[0401] The driving timing of the shift register provided in Figure 51 can be applied to the shift register provided in Figure 57. The operation of the first transistor T1 to the ninth transistor T9 in the shift register provided in Figure 57 under the driving timing provided in Figure 51 is the same as the operation of the first transistor T1 to the ninth transistor T9 in the shift register provided in Figure 52 under the driving timing provided in Figure 51, and will not be described again here.

[0402] Figure 58 is the equivalent circuit diagram of the shift register provided in Figure 31. The shift register provided in Figure 58 differs from the shift register provided in Figure 53 in the transistor type of the fifth transistor and the connection method of the control electrode of the fifth transistor. In the shift register provided in Figure 58, the fifth transistor T5 is an N-type transistor, and the control electrode of the fifth transistor T5 is electrically connected to at least one of the signal terminals of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2, which will not be elaborated further here.

[0403] The driving timing of the shift register provided in Figure 51 can be applied to the shift register provided in Figure 58. The operation of the first transistor T1 to the tenth transistor T10 in the shift register provided in Figure 58 under the driving timing provided in Figure 51 is the same as the operation of the first transistor T1 to the tenth transistor T10 in the shift register provided in Figure 53 under the driving timing provided in Figure 51, and will not be described again here.

[0404] Figure 59 is the equivalent circuit diagram of the shift register provided in Figure 31. The shift register provided in Figure 59 differs from the shift register provided in Figure 54 in the transistor type of the fifth transistor and the connection method of the control electrode of the fifth transistor. In the shift register provided in Figure 59, the fifth transistor T5 is an N-type transistor, and the control electrode of the fifth transistor T5 is electrically connected to at least one of the signal terminals of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2, which will not be elaborated further here.

[0405] The driving timing of the shift register provided in Figure 51 can be applied to the shift register provided in Figure 59. The operation of the first transistor T1 to the ninth transistor T9 and the eleventh transistor T11 in the shift register provided in Figure 59 under the driving timing provided in Figure 51 is the same as the operation of the first transistor T1 to the ninth transistor T9 and the eleventh transistor T11 in the shift register provided in Figure 54 under the driving timing provided in Figure 51, and will not be described again here.

[0406] Figure 60 is the equivalent circuit diagram of the shift register provided in Figure 31. The shift register provided in Figure 60 differs from the shift register provided in Figure 55 in the transistor type of the fifth transistor and the connection method of the control electrode of the fifth transistor. In the shift register provided in Figure 60, the fifth transistor T5 is an N-type transistor, and the control electrode of the fifth transistor T5 is electrically connected to at least one of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2, which will not be elaborated further here.

[0407] The driving timing of the shift register provided in Figure 51 can be applied to the shift register provided in Figure 60. The operation of the first transistor T1 to the eleventh transistor T11 in the shift register provided in Figure 60 under the driving timing provided in Figure 51 is the same as the operation of the first transistor T1 to the eleventh transistor T11 in the shift register provided in Figure 55 under the driving timing provided in Figure 51, and will not be described again here.

[0408] Figure 61 is an equivalent circuit diagram of the shift register provided in Figure 42. As shown in Figure 61, at least one output signal terminal includes a signal output terminal OUT. The shift register may also include a control sub-circuit and an output sub-circuit, or a control sub-circuit, an output sub-circuit, and a power-on control sub-circuit. The power-on control sub-circuit includes: first transistor T1 to fourth transistor T4; the output transistors include: fifth transistor T5 to seventh transistor T7, first capacitor C1, and second capacitor C2; and the power-on control sub-circuit includes: a thirteenth transistor T13. The fourth transistor T4 has a single-gate structure, or the control electrode of the fourth transistor T4 includes: a first control electrode and a second control electrode. Specifically, the control electrode of the first transistor T1 is electrically connected to the clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the second node ND2; the control electrode of the second transistor T2 is electrically connected to the signal input terminal IN, the first electrode of the second transistor T2 is electrically connected to the high-level power supply terminal VH, and the second electrode of the second transistor T2 is electrically connected to the fourth node ND4; the control electrode of the third transistor T3 is electrically connected to the clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the fourth node ND4, and the second electrode of the third transistor T3 is electrically connected to the first node ND1; when the fourth transistor T4 is a single-gate structure, the control electrode of the fourth transistor T4 is electrically connected to the third node ND3, the first electrode of the fourth transistor T4 is electrically connected to the first low-level power supply terminal VL1, and the second electrode of the fourth transistor T4 is electrically connected to the first node ND1. The control electrode of the fourth transistor T4 includes: when the first control electrode and the second control electrode are present, the first control electrode of the fourth transistor T4 is electrically connected to the third node ND3, and the second control electrode of the fourth transistor T4 is electrically connected to one of the signal terminals of the first low-level power supply terminal VL1 and the second low-level power supply terminal VL2. The first electrode of the fourth transistor T4 is electrically connected to the first low-level power supply terminal VL1, and the second electrode of the fourth transistor T4 is electrically connected to the first node ND1. The control electrode of the fifth transistor T5 is electrically connected to the first low-level power supply terminal VL1, the first electrode of the fifth transistor T5 is electrically connected to the second node ND2, and the second electrode of the fifth transistor T5 is electrically connected to the third node ND3. The sixth transistor T6... The control electrode of the sixth transistor T6 is electrically connected to the first node ND1; the first electrode of the sixth transistor T6 is electrically connected to the high-level power supply terminal VH; and the second electrode of the sixth transistor T6 is electrically connected to the signal output terminal OUT. The control electrode of the seventh transistor T7 is electrically connected to the third node ND3; the first electrode of the seventh transistor T7 is electrically connected to the first low-level power supply terminal VL1; and the second electrode of the seventh transistor T7 is electrically connected to the signal output terminal OUT. The first plate of the first capacitor C1 is electrically connected to the first node ND1; and the second plate of the first capacitor C1 is electrically connected to the high-level power supply terminal VH. The first plate of the second capacitor C2 is electrically connected to the third node ND3; and the second plate of the second capacitor C2 is electrically connected to the signal output terminal OUT.

[0409] In an exemplary embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 in the shift register shown in FIG61 are P-type transistors. The fourth transistor T4 is an N-type transistor.

[0410] The driving timing of the shift register provided in Figure 51 can be applied to the shift register provided in Figure 61.

[0411] The exemplary embodiments of this disclosure are illustrated below with reference to the operation of the shift register shown in Figure 61.

[0412] In the first stage, the signals at P1, the signal input terminal IN, and the clock signal terminal CK are all low-level signals. The first transistor T1, the second transistor T2, and the third transistor T3 are turned on.

[0413] The first transistor T1 is turned on, and the low-level signal at the signal input terminal IN is written to the second node ND2 and the third node N3 through the turned-on first transistor T1 and the turned-on fifth transistor T5. The signal at the third node N3 is a low-level signal, the fourth transistor T4 is turned off, and the seventh transistor T7 is turned on. The seventh transistor T7 is turned on, and the signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT. The second transistor T2 and the third transistor T3 are turned on, and the signal at the high-level power supply terminal VH is written to the fourth node ND4 and the first node ND1 through the turned-on second transistor T2 and the turned-on third transistor T3. The signal at the first node ND1 is a high-level signal, and the sixth transistor T6 is turned off.

[0414] During this stage, the signal output terminal OUT outputs a low-level signal.

[0415] In the second stage, the signals at P2, the signal input terminal IN, and the clock signal terminal CK are high-level signals. The first transistor T1, the second transistor T2, and the third transistor T3 are disconnected.

[0416] Under the influence of the first capacitor C1, the signal at the first node ND1 remains the same as in the previous stage. Under the influence of the second capacitor C2, the signal at the third node ND3 remains at the low level of the previous stage. The fourth transistor T4 is turned off, and the seventh transistor T7 is turned on. With the seventh transistor T7 on, the signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT.

[0417] During this stage, the signal output terminal OUT outputs a low-level signal.

[0418] In the third stage, the signal at P3 and the signal input terminal IN is a high-level signal, and the signal at the clock signal terminal CK is a low-level signal. The first transistor T1 and the third transistor T3 are turned on, and the second transistor T2 is turned off.

[0419] The first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is written to the second node ND2 and the third node N3 through the turned-on first transistor T1 and the turned-on fifth transistor T5. The signal at the third node N3 is a high-level signal, the fourth transistor T4 is turned on, and the seventh transistor T7 is turned off. The fourth transistor T4 is turned on, and the signal at the first low-level power supply terminal VL1 is written to the first node ND1, and the sixth transistor T6 and the eighth transistor T8 are turned on. The sixth transistor T6 is turned on, and the signal at the high-level power supply terminal VH is written to the signal output terminal OUT. The third transistor T3 is turned on, and the low-level signal at the first node ND1 is written to the third node ND3.

[0420] During this stage, the signal output terminal OUT outputs a high-level signal.

[0421] In the fourth stage, the signals at P4, the signal input terminal IN, and the clock signal terminal CK are high-level signals. The first transistor T1, the second transistor T2, and the third transistor T3 are disconnected.

[0422] Under the influence of the first capacitor C1, the signal at the first node ND1 remains the same as in the previous stage, and the sixth transistor T6 and the eighth transistor T8 remain on. With the sixth transistor T6 on, the high-level power supply terminal VH is written to the signal output terminal OUT. Under the influence of the second capacitor C2, the signal at the third node ND3 remains the high-level signal from the previous stage.

[0423] During this stage, the signal output terminal OUT outputs a high-level signal.

[0424] The working process of the fifth stage, P5, is the same as that of the third stage, P3, and will not be described again here.

[0425] In the sixth stage, the signal at the P6 input terminal IN is a low-level signal, and the signal at the clock signal terminal CK is a high-level signal. The first transistor T1 and the third transistor T3 are disconnected, and the second transistor T2 is turned on.

[0426] The first transistor T1 is off, preventing the low-level signal at the input terminal IN from being written to the second node ND2 and the third node ND3. Furthermore, due to the action of the second capacitor C2, the signal at the third node ND3 remains at the high-level signal of the previous stage, and the fourth transistor T4 is on. The second transistor T2 is on, allowing the high-level power supply terminal VH to be written to the fourth node ND4. The fourth transistor T4 is on, allowing the signal at the first low-level power supply terminal VL1 and at least one of its signal terminals to be written to the first node ND1, and the sixth transistor T6 is on. The sixth transistor T6 is on, allowing the high-level power supply terminal VH to be written to the signal output terminal OUT.

[0427] During this stage, the signal output terminal OUT outputs a high-level signal.

[0428] The working process of the seventh stage, P7, is the same as that of the first stage, P1, and will not be described again here.

[0429] In the eighth stage, the signal at the P8 input terminal IN is a low-level signal, and the signal at the clock signal terminal CK is a high-level signal. The first transistor T1 and the third transistor T3 are off, and the second transistor T2 is on.

[0430] The first transistor T1 is off, preventing the low-level signal at the input terminal IN from being written to the second node ND2 and the third node ND3. Under the influence of the second capacitor C2, the signal at the third node ND3 remains at the low level of the previous stage. The fourth transistor T4 is off, and the seventh transistor T7 is on. With the seventh transistor T7 on, the signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT. The second transistor T2 is on, and the high-level power supply terminal VH is written to the fourth node ND4. Under the influence of the first capacitor C1, the first node ND1 maintains the high-level signal of the previous stage, and the sixth transistor T6 is off.

[0431] During this stage, the signal output terminal OUT outputs a low-level signal.

[0432] Figure 62 is the equivalent circuit diagram of the shift register provided in Figure 42. The shift register provided in Figure 62 differs from the shift register provided in Figure 61 in that it further includes a twelfth transistor T12. The twelfth transistor T12 has a single-gate structure, or its control electrode includes a first control electrode and a second control electrode. When the twelfth transistor T12 has a single-gate structure, its control electrode is electrically connected to the first node ND1, its first electrode is electrically connected to the first low-level power supply terminal VL1, and its second electrode is electrically connected to the signal output terminal OUT. When the control electrode of the twelfth transistor T12 includes a first control electrode and a second control electrode, the first control electrode of the twelfth transistor T12 is electrically connected to the first node ND1, the second control electrode of the twelfth transistor T12 is electrically connected to at least one of the first low-level power supply terminal VL1, the second low-level power supply terminal VL2 and the third low-level power supply terminal VL3, the first electrode of the twelfth transistor T12 is electrically connected to the first low-level power supply terminal VL1, and the second electrode of the twelfth transistor T12 is electrically connected to the signal output terminal OUT.

[0433] In an exemplary embodiment, the twelfth transistor T12 is an N-type transistor.

[0434] The driving timing of the shift register provided in Figure 51 can be applied to the shift register provided in Figure 62. The operation of the first transistor T1 to the seventh transistor T7 in the shift register provided in Figure 62 under the driving timing provided in Figure 51 is the same as that of the first transistor T1 to the seventh transistor T7 in the shift register provided in Figure 61 under the driving timing provided in Figure 51, and will not be described again here.

[0435] In the shift register shown in Figure 62, since the first node ND1 is a high-level signal in stages P1, P2, P7, and P8, the twelfth transistor T12 is turned on in stages P1, P2, P7, and P8. The signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT through the turned-on twelfth transistor T12. At the same time, the ninth transistor T9 is also turned on, and the signal at the first low-level power supply terminal VL1 is written to the signal output terminal OUT through the turned-on ninth transistor T9. Since ND1 is a low-level signal in stages P3, P4, P5, and P6, the twelfth transistor T12 is turned off, and the first low-level power supply terminal VL1 cannot be written to the signal output terminal OUT. This ensures that the signal at the signal output terminal OUT is a high-level signal in stages P3, P4, P5, and P6.

[0436] The shift registers shown in Figures 61 and 62 contain fewer transistors than those shown in Figures 50, 52 to 60, which reduces the area occupied by the shift register and facilitates the implementation of a narrow bezel.

[0437] This disclosure also provides a method for driving a shift register, configured to drive the shift register provided in any of the embodiments of Figures 50, 52 to 62. Figure 63 is a flowchart of the method for driving the shift register. As shown in Figure 63, the method for driving the shift register provided in this disclosure may include the following steps:

[0438] Step S100: Under the control of the signal input terminal, clock signal terminal, at least one low-level power supply terminal, at least one high-level power supply terminal and the third node, the control sub-circuit provides signals to the first node and the second node.

[0439] Step S200: The output sub-circuit provides signals to the third node and at least one output signal terminal under the control of at least one high-level power supply terminal, at least one low-level power supply terminal, the first node and the second node.

[0440] This disclosure also provides a gate drive circuit, including: a plurality of cascaded shift registers provided in any of the foregoing embodiments.

[0441] Figure 64 is a schematic diagram of multiple cascaded shift registers. As shown in Figure 64, at least one output signal terminal includes a signal output terminal OUT, and the signal output terminal OUT of at least one shift register GOA is electrically connected to the signal input terminal IN of at least one shift register GOA. GOA(i) refers to the i-th shift register.

[0442] Figure 65 is a schematic diagram of multiple cascaded shift registers. As shown in Figure 65, at least one output signal terminal includes a cascaded output terminal CR and a signal output terminal OUT. The cascaded output terminal CR of at least one shift register GOA is electrically connected to the signal input terminal IN of at least one shift register GOA.

[0443] This disclosure also provides a display device. FIG66 is a schematic diagram of the structure of the display device provided in this disclosure embodiment. As shown in FIG66, the display device provided in this disclosure embodiment has a display area AA and a non-display area BB, wherein the display area AA is provided with an array of pixel driving circuits 100, and the non-display area BB is provided with a gate driving circuit 200 as provided in any of the foregoing embodiments.

[0444] In an exemplary embodiment, the gate driving circuit 200 may be located on at least one of the first and second sides of the display area that are relatively disposed therebetween.

[0445] In an exemplary embodiment, FIG67 is a timing diagram of the clock signal terminal in the refresh frame and the hold frame. As shown in FIG67, the clock signal terminal CK connected to at least one shift register in the gate drive circuit is a constant voltage signal in at least one hold frame.

[0446] In the gate drive circuit of this disclosure, the clock signal terminal connected to at least one shift register is a constant voltage signal in at least one holding frame, which can save the power consumption of the shift register without affecting the output signal of the shift register.

[0447] In exemplary embodiments, the display device can be any device that displays images, whether moving (e.g., video) or stationary (e.g., still images), and whether text or pictures. More specifically, it is contemplated that embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, etc., and this application does not limit the scope of the embodiments.

[0448] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0449] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0450] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A shift register, comprising: Control sub-circuit and output sub-circuit; The control sub-circuit is electrically connected to the signal input terminal, the clock signal terminal, at least one low-level power supply terminal, at least one high-level power supply terminal, the first node, the second node, and the third node, respectively, and is configured to provide signals to the first node and the second node under the control of the signals from the signal input terminal, the clock signal terminal, at least one low-level power supply terminal, at least one high-level power supply terminal, and the third node; The output sub-circuit is electrically connected to at least one output signal terminal, at least one high-level power supply terminal, at least one low-level power supply terminal, a first node, a second node, and a third node, respectively, and is configured to provide signals to the third node and at least one output signal terminal under the control of signals from at least one high-level power supply terminal, at least one low-level power supply terminal, the first node, and the second node.

2. The shift register according to claim 1, wherein, The control sub-circuit includes: a first node control sub-circuit and a second node control sub-circuit; The first node control sub-circuit is electrically connected to the signal input terminal, the clock signal terminal, at least one high-level power supply terminal, the first node, and the second node, respectively. It is configured to provide the first node with a signal from at least one high-level power supply terminal and the second node with a signal from the signal input terminal under the control of the signal from at least one of the signal input terminal and the clock signal terminal. The second node control sub-circuit is electrically connected to at least one low-level power supply terminal, the first node, and the third node, respectively, and is configured to provide a signal from at least one low-level power supply terminal to the first node under the control of the signal from the third node.

3. The shift register according to claim 2, wherein, The output sub-circuit includes: a first output control sub-circuit and a second output control sub-circuit; The first output control sub-circuit is electrically connected to at least one signal terminal of at least one high-level power supply terminal and at least one low-level power supply terminal, the second node and the third node, respectively, and is configured to provide the signal of the second node to the third node under the control of the signal of at least one signal terminal of at least one high-level power supply terminal and at least one low-level power supply terminal; The second output control sub-circuit is electrically connected to at least one high-level power supply terminal, at least one low-level power supply terminal, at least one output signal terminal, a first node, and a third node, respectively, and is configured to provide a signal from one of the signal terminals, at least one high-level power supply terminal and at least one low-level power supply terminal, to at least one output signal terminal under the control of the signals from the first node and the third node.

4. The shift register according to claim 3, wherein, At least one output signal terminal includes: a cascaded output terminal and a signal output terminal; at least one high-level power supply terminal connected to the output sub-circuit includes: a first high-level power supply terminal and a second high-level power supply terminal; at least one low-level power supply terminal connected to the output sub-circuit includes: a first low-level power supply terminal and a second low-level power supply terminal; at least one high-level power supply terminal connected to the control sub-circuit includes: a second high-level power supply terminal; at least one low-level power supply terminal connected to the control sub-circuit includes: at least one signal terminal among the first low-level power supply terminal and the second low-level power supply terminal.

5. The shift register according to claim 4, wherein, The first node control sub-circuit includes: a first transistor, a second transistor, and a third transistor; The control electrode of the first transistor is electrically connected to the clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the second node. The control electrode of the second transistor is electrically connected to the signal input terminal, the first electrode of the second transistor is electrically connected to the second high-level power supply terminal, and the second electrode of the second transistor is electrically connected to the fourth node. The control electrode of the third transistor is electrically connected to the clock signal terminal, the first electrode of the third transistor is electrically connected to the fourth node, and the second electrode of the third transistor is electrically connected to the first node. At least one of the first to the third transistors is a P-type transistor.

6. The shift register according to claim 5, wherein, The second node control sub-circuit includes: a fourth transistor, the fourth transistor being a single-gate structure, or the control electrode of the fourth transistor including: a first control electrode and a second control electrode, the shift register being disposed on the substrate, and the second control electrode being disposed on the side of the first control electrode closer to the substrate; When the fourth transistor is a single-gate structure, the control electrode of the fourth transistor is electrically connected to the third node, the first electrode of the fourth transistor is electrically connected to one of the signal terminals of the first low-level power supply terminal and the second low-level power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first node. When the control electrode of the fourth transistor includes a first control electrode and a second control electrode, the first control electrode of the fourth transistor is electrically connected to the third node, the second control electrode of the fourth transistor is electrically connected to one of the signal terminals of the first low-level power supply terminal, the second low-level power supply terminal and the third low-level power supply terminal, the first electrode of the fourth transistor is electrically connected to one of the signal terminals of the first low-level power supply terminal and the second low-level power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first node. The fourth transistor is an N-type transistor; The voltage value of the signal at the third low-level power supply terminal is higher than the voltage value of the signal at at least one of the signal terminals of the first low-level power supply terminal and the second low-level power supply terminal.

7. The shift register according to claim 4, wherein, The first output control sub-circuit includes: a fifth transistor; The control electrode of the fifth transistor is electrically connected to one of the signal terminals of the first low-level power supply terminal and the second low-level power supply terminal; the first electrode of the fifth transistor is electrically connected to the second node; and the second electrode of the fifth transistor is electrically connected to the third node. The fifth transistor is a P-type transistor.

8. The shift register according to claim 4, wherein, The first output control sub-circuit includes: a fifth transistor; The control electrode of the fifth transistor is electrically connected to the third low-level power supply terminal, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the third node. The fifth transistor is a P-type transistor; The difference between the voltage value of the signal at the third low-level power supply terminal and the voltage value of the signal at the second low-level power supply terminal is greater than the threshold voltage of the fifth transistor.

9. The shift register according to claim 4, wherein, The first output control sub-circuit includes: a fifth transistor; The control electrode of the fifth transistor is electrically connected to one of the signal terminals of the first high-level power supply terminal and the second high-level power supply terminal; the first electrode of the fifth transistor is electrically connected to the second node; and the second electrode of the fifth transistor is electrically connected to the third node. The fifth transistor is an N-type transistor.

10. The shift register according to claim 4, wherein, The second output control sub-circuit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, and a second capacitor, wherein at least one of the first capacitor and the second capacitor includes: a first electrode and a second electrode. The control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second high-level power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascaded output terminal. The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second low-level power supply terminal, and the second electrode of the seventh transistor is electrically connected to the cascaded output terminal. The control electrode of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the first high-level power supply terminal, and the second electrode of the eighth transistor is electrically connected to the signal output terminal. The control electrode of the ninth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the first low-level power supply terminal, and the second electrode of the ninth transistor is electrically connected to the signal output terminal. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to one of the signal terminals of the first high-level power supply terminal and the second high-level power supply terminal. The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the cascaded output terminal. At least one of the sixth to ninth transistors is a P-type transistor.

11. The shift register according to claim 10, wherein, The second output control sub-circuit further includes: at least one of the tenth transistor and the eleventh transistor; at least one of the tenth transistor and the eleventh transistor has a single-gate structure, or the control electrode of at least one of the tenth transistor and the eleventh transistor includes: a first control electrode and a second control electrode, the shift register is disposed on the substrate, and the second control electrode is disposed on the side of the first control electrode close to the substrate; When the tenth transistor is a single-gate structure, the control electrode of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the second low-level power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascaded output terminal. When the control electrode of the tenth transistor includes a first control electrode and a second control electrode, the first control electrode of the tenth transistor is electrically connected to the first node, the second control electrode of the tenth transistor is electrically connected to at least one of the first low-level power supply terminal, the second low-level power supply terminal and the third low-level power supply terminal, the first electrode of the tenth transistor is electrically connected to the second low-level power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascaded output terminal. When the eleventh transistor is a single-gate structure, the control electrode of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the first low-level power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the signal output terminal. When the control electrode of the eleventh transistor includes a first control electrode and a second control electrode, the first control electrode of the eleventh transistor is electrically connected to the first node, the second control electrode of the eleventh transistor is electrically connected to at least one signal terminal among the first low-level power supply terminal, the second low-level power supply terminal and the third low-level power supply terminal, the first electrode of the eleventh transistor is electrically connected to the first low-level power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the signal output terminal. At least one of the tenth and eleventh transistors is an N-type transistor.

12. The shift register according to claim 4, wherein, The signal received by the first high-level power supply terminal is the same as the signal received by the second high-level power supply terminal, or the signal received by the first low-level power supply terminal is the same as the signal received by the second low-level signal terminal.

13. The shift register according to claim 3, wherein, At least one output signal terminal includes: a signal output terminal; at least one high-level power supply terminal connected to the output sub-circuit includes: a high-level power supply terminal; at least one low-level power supply terminal connected to the output sub-circuit includes: a first low-level power supply terminal; at least one high-level power supply terminal connected to the control sub-circuit includes: a high-level power supply terminal; at least one low-level power supply terminal connected to the control sub-circuit includes: a first low-level power supply terminal.

14. The shift register according to claim 13, wherein, The first node control sub-circuit includes: a first transistor, a second transistor, and a third transistor; The control electrode of the first transistor is electrically connected to the clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the second node. The control electrode of the second transistor is electrically connected to the signal input terminal, the first electrode of the second transistor is electrically connected to the high-level power supply terminal, and the second electrode of the second transistor is electrically connected to the fourth node. The control electrode of the third transistor is electrically connected to the clock signal terminal, the first electrode of the third transistor is electrically connected to the fourth node, and the second electrode of the third transistor is electrically connected to the first node. At least one of the first to the third transistors is a P-type transistor.

15. The shift register according to claim 14, wherein, The second node control sub-circuit includes: a fourth transistor, the fourth transistor being a single-gate structure, or the control electrode of the fourth transistor including: a first control electrode and a second control electrode, the shift register being disposed on the substrate, and the second control electrode being disposed on the side of the first control electrode closer to the substrate; When the fourth transistor is a single-gate structure, the control electrode of the fourth transistor is electrically connected to the third node, the first electrode of the fourth transistor is electrically connected to the first low-level power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first node. When the control electrode of the fourth transistor includes a first control electrode and a second control electrode, the first control electrode of the fourth transistor is electrically connected to the third node, the second control electrode of the fourth transistor is electrically connected to at least one signal terminal of the first low-level power supply terminal and the second low-level power supply terminal, the first electrode of the fourth transistor is electrically connected to the first low-level power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first node. The fourth transistor is an N-type transistor.

16. The shift register according to claim 13, wherein, The first output control sub-circuit includes: a fifth transistor; The control electrode of the fifth transistor is electrically connected to the first low-level power supply terminal, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the third node. The fifth transistor is a P-type transistor.

17. The shift register according to claim 13, wherein, The second output control sub-circuit includes: a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor, wherein at least one of the first capacitor and the second capacitor includes: a first electrode and a second electrode. The control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the high-level power supply terminal, and the second electrode of the sixth transistor is electrically connected to the signal output terminal. The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the first low-level power supply terminal, and the second electrode of the seventh transistor is electrically connected to the signal output terminal. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the high-level power supply terminal. The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the signal output terminal. At least one of the sixth and seventh transistors is a P-type transistor.

18. The shift register according to claim 17, wherein, The second output control sub-circuit further includes: a twelfth transistor, the twelfth transistor having a single-gate structure, or the control electrode of the twelfth transistor including: a first control electrode and a second control electrode, the shift register being disposed on the substrate, and the second control electrode being disposed on the side of the first control electrode closer to the substrate; When the twelfth transistor is a single-gate structure, the control electrode of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the signal output terminal, and the second electrode of the twelfth transistor is electrically connected to the first low-level power supply terminal. When the control electrode of the twelfth transistor includes a first control electrode and a second control electrode, the first control electrode of the twelfth transistor is electrically connected to the first node, the second control electrode of the twelfth transistor is electrically connected to one of the signal terminals of the first low-level power supply terminal and the second low-level power supply terminal, the first electrode of the twelfth transistor is electrically connected to the signal output terminal, and the second electrode of the twelfth transistor is electrically connected to the first low-level power supply terminal. The twelfth transistor is an N-type transistor.

19. The shift register according to claim 1, further comprising: Power-on control sub-circuit; The power-on control sub-circuit is electrically connected to the power-on control signal terminal, at least one high-level power supply terminal, and the first node, and is configured to provide the first node with a signal from at least one high-level power supply terminal under the control of the signal from the power-on control signal terminal.

20. The shift register according to claim 19, wherein, The power-on control sub-circuit includes: a thirteenth transistor; The control terminal of the thirteenth transistor is electrically connected to the power-on control signal terminal, the first terminal of the thirteenth transistor is electrically connected to at least one high-level power supply terminal, and the second terminal of the thirteenth transistor is electrically connected to the first node.

21. A gate driving circuit, comprising: Multiple cascaded shift registers as described in any one of claims 1 to 20.

22. The gate driving circuit according to claim 21, wherein, At least one output signal terminal includes: a cascaded output terminal and a signal output terminal, wherein the cascaded output terminal of at least one shift register is electrically connected to the signal input terminal of at least one shift register; At least one output signal terminal includes: a signal output terminal, wherein the signal output terminal of at least one shift register is electrically connected to the signal input terminal of at least one shift register.

23. A display device having a display area and a non-display area, wherein, The display area is provided with an array of pixel driving circuits, and the non-display area is provided with a gate driving circuit as described in claim 21 or 22.

24. The display device according to claim 23, wherein, The content displayed by the display device includes multiple display frames. The driving mode of the display device includes a first driving mode and a second driving mode. The refresh rate of the display device in the first driving mode is less than the refresh rate of the display device in the second driving mode. In the first driving mode, at least one display frame includes: at least one holding frame, wherein the clock signal terminal connected to at least one shift register in the gate driving circuit is a constant voltage signal in at least one holding frame.

25. A method for driving a shift register, configured to drive a shift register as claimed in any one of claims 1 to 20, the method comprising: The control sub-circuit provides signals to the first and second nodes under the control of the signal input terminal, the clock signal terminal, at least one low-level power supply terminal, at least one high-level power supply terminal and the third node; The output sub-circuit provides signals to the third node and at least one output signal terminal under the control of signals from at least one high-level power supply terminal, at least one low-level power supply terminal, the first node, and the second node.

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