Display driving circuit and display apparatus

Abstract

The present disclosure relates to the technical field of display, and provides a display driving circuit and a display apparatus. The display driving circuit of the present disclosure comprises a timing controller and a plurality of source drivers. The timing controller comprises at least one first output end and a plurality of second output ends. One first output end is electrically connected to at least one of the source drivers. The second output ends are connected to the source drivers in one-to-one correspondence. The timing controller is configured to output a first clock signal by means of the first output end, and output a first data signal by means of the second output ends. The source drivers are configured to sample the first data signal by using the first clock signal, and output sampled display data.

Description

A display driving circuit and a display device Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display driving circuit and a display device. Background Technology

[0002] As consumers increasingly demand higher display quality, high-resolution, high-refresh-rate display products are becoming more and more popular. Currently, 4K and even 8K resolution LCD displays are available on the market, and refresh rates have been increased to 500Hz or even higher.

[0003] Higher refresh rates and resolutions result in smoother, more stable images, reducing flicker and artifacts. Higher resolutions and color depths provide more detail and richer colors, making images more realistic and detailed. However, as refresh rates and resolutions increase, the amount of displayed data also grows exponentially, placing higher demands on the data transmission rate and quality of the display driver circuitry.

[0004] Summary of the Invention

[0005] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a display driving circuit and a display device.

[0006] Firstly, the technical solution adopted to solve the technical problem of this disclosure is a display driving circuit, which includes a timing controller and a plurality of source drivers; the timing controller includes at least one first output terminal and a plurality of second output terminals; one first output terminal is electrically connected to at least one of the source drivers; the second output terminals are connected to the source drivers one by one;

[0007] The timing controller is configured to output a first clock signal through the first output terminal and a first data signal through the second output terminal;

[0008] The source driver is configured to sample the first data signal using the first clock signal and output the sampled display data.

[0009] In some embodiments, the display driving circuit further includes a phase compensation sub-circuit;

[0010] The phase compensation sub-circuit is configured to determine the phase offset between the first clock signal and the first data signal based on the received first clock signal and the first data signal; and to perform phase compensation on the currently received first clock signal or the first data signal using the phase offset.

[0011] In some embodiments, the phase compensation sub-circuit is integrated within the source driver, and the source driver further includes a clock signal receiving sub-circuit, a data signal receiving sub-circuit, a data sampling sub-circuit, and a data output sub-circuit;

[0012] The clock signal receiving sub-circuit is configured to transmit the received first clock signal to the phase compensation sub-circuit.

[0013] The data signal receiving sub-circuit is configured to transmit the received first data signal to the data sampling sub-circuit and the phase compensation sub-circuit;

[0014] The phase compensation sub-circuit is configured to calculate the phase offset between the first clock signal and the first data signal; and to perform phase compensation on the first clock signal using the phase offset to obtain the second clock signal.

[0015] The data sampling sub-circuit is configured to sample the first data signal according to the second clock signal to obtain display data;

[0016] The data output sub-circuit is configured to output the display data.

[0017] In some embodiments, the data sampling sub-circuit is further configured to send a feedback signal to the phase compensation sub-circuit in response to receiving the second clock signal;

[0018] The phase compensation sub-circuit is also configured to stop receiving the first data signal in response to receiving a feedback signal.

[0019] In some embodiments, the phase compensation sub-circuit calculates the phase offset between the first clock signal and the first data signal, specifically including:

[0020] Obtain the initial sampling point of the first clock signal, and the initial and final positions of the first data signal during the active level phase;

[0021] Calculate the first phase step size from the initial sampling point to the initial position point;

[0022] Calculate the second phase step size from the initial sampling point to the termination position point;

[0023] Based on the first phase step and the second phase step, the phase offset between the initial sampling point and the effective level center position is determined; the effective level center position is the optimal sampling position of the first clock signal for the first data signal during the effective level phase.

[0024] In some embodiments, the display driving circuit further includes a phase compensation sub-circuit; the phase compensation sub-circuit includes a phase offset detection unit and a phase calibration unit, wherein the phase offset detection unit is integrated within the source driver and the phase calibration unit is integrated within the timing controller; the source driver further includes a clock signal receiving sub-circuit, a data signal receiving sub-circuit, a data sampling sub-circuit, and a data output sub-circuit; the timing controller further includes a clock signal transmitting sub-circuit and a data signal transmitting sub-circuit.

[0025] The clock signal transmitting sub-circuit is configured to transmit the first clock signal to the clock signal receiving sub-circuit through the first output terminal;

[0026] The data signal transmitting sub-circuit is configured to transmit a phase calibration signal to the data signal receiving sub-circuit through the second output terminal; and to transmit the received second data signal to the data signal receiving sub-circuit through the second output terminal.

[0027] The clock signal receiving sub-circuit is configured to transmit the received first clock signal to the phase offset detection unit;

[0028] The data signal receiving sub-circuit is configured to transmit the received phase calibration signal to the phase offset detection unit; and to send the received second data signal to the data sampling sub-circuit.

[0029] The phase offset detection unit is configured to calculate the phase offset between the first clock signal and the phase calibration signal, and send the phase offset to the phase calibration unit;

[0030] The phase calibration unit is configured to perform phase compensation on the first data signal using the phase offset to obtain a second data signal; and to transmit the second data signal to the data signal transmitting sub-circuit.

[0031] The data sampling sub-circuit is configured to sample the second data signal according to the received first clock signal to obtain display data;

[0032] The data output sub-circuit is configured to output the display data.

[0033] In some embodiments, the phase offset detection unit is further configured to send the received first clock signal to the data sampling sub-circuit; and, in response to receiving a feedback signal, to stop receiving the second data signal; the data sampling sub-circuit is further configured to send a feedback signal to the phase offset detection unit in response to receiving the first clock signal; or...

[0034] The data sampling sub-circuit is further configured to send a feedback signal to the phase offset detection unit in response to receiving the first clock signal sent by the clock signal receiving sub-circuit; the phase offset detection unit is further configured to stop receiving the second data signal and the first clock signal in response to receiving the feedback signal.

[0035] In some embodiments, the phase offset detection unit is specifically configured to acquire the initial sampling point of the first clock signal, the initial position point and the termination position point of the first data signal in the effective level phase; calculate the third phase step from the initial position point to the initial sampling point; calculate the fourth phase step from the termination position point to the initial sampling point; and determine the phase offset between the effective level center position and the initial sampling point based on the third phase step and the fourth phase step; wherein the effective level center position is the optimal sampling position of the first clock signal for the first data signal in the effective level phase.

[0036] In some embodiments, the phase calibration signal is the first data signal; or, the first data signal includes a first sub-signal and a second sub-signal; the timing controller transmits the first sub-signal before transmitting the second sub-signal, and the second sub-signal includes a signal representing the display data; the first sub-signal is the phase calibration signal.

[0037] In some embodiments, the timing controller includes a clock signal transmitting subcircuit and a data signal transmitting subcircuit;

[0038] The clock signal transmitting sub-circuit is configured to transmit the first clock signal to the source driver through the first output terminal;

[0039] The data signal transmitting sub-circuit is configured to perform phase compensation on the first data signal using a preset phase offset to obtain a second data signal; and to send the second data signal to the source driver through the second output terminal.

[0040] In some embodiments, the timing controller includes a clock signal transmitting subcircuit, a phase compensation subcircuit, and a data signal transmitting subcircuit;

[0041] The clock signal transmitting sub-circuit is configured to transmit the first clock signal to the source driver through the first output terminal;

[0042] The phase compensation sub-circuit is configured to determine the phase offset between the first clock signal and the first data signal based on the received first clock signal and the first data signal; and to perform phase compensation on the currently received first data signal using the phase offset to obtain a second data signal.

[0043] The data signal transmitting sub-circuit is configured to send the received second data signal to the source driver through the second output terminal.

[0044] In some embodiments, the timing controller further includes a third output terminal;

[0045] The timing controller is also configured to output control command signals to each of the source drivers through the third output terminal;

[0046] The source driver is further configured to control the output of the display data according to the received target clock signal, target data signal and control command signal;

[0047] The target clock signal is a first clock signal, and the target data signal is a second data signal; or, the target clock signal is a second clock signal, and the target data signal is a first data signal; or, the target clock signal is the first clock signal, and the target data signal is the first data signal.

[0048] In some embodiments, the source driver includes a data sampling sub-circuit and a data processing sub-circuit;

[0049] The data sampling sub-circuit is configured to sequentially sample the target data signal using the target clock signal;

[0050] The data processing sub-circuit is configured to, when the sampling result is a first frame control instruction, retrieve first output strategy information of each frame of display data in response to the control instruction signal being a second level signal; when the sampling result is a first line control instruction, retrieve second output strategy information of one line of display data in response to the control instruction signal being a first level signal; and when the sampling result is the display data, control the output of the display data according to the first output strategy information and the second output strategy information in response to the control instruction signal being a second level signal.

[0051] In some embodiments, the data processing sub-circuit is further configured to, in response to the control command signal being a first level signal, disable the receiving function of the first data signal and / or the sending function of the display data when the sampling result is a second frame control command within the frame waiting period; the frame waiting period represents an idle period from the output of the display data in the current frame to the output of the display data in the next frame.

[0052] In some embodiments, the data processing sub-circuit is further configured to enable the receiving function of the first data signal and / or the sending function of the display data in response to the control command signal being a first level signal, when the receiving function of the first data signal and / or the sending function of the display data are currently disabled.

[0053] In some embodiments, the data processing sub-circuit is further configured to, during the frame waiting period, in response to the control command signal being a first level signal, acquire the sampling result as a second line control command and a preset grayscale voltage, adjust the driving voltage of the display data corresponding to the current frame to the preset grayscale voltage and output it, so as to maintain the voltage on the data line during the frame waiting period, wherein the data line is used to electrically connect the source driver and the pixel driving circuit; the preset grayscale voltage has the opposite polarity to the driving voltage.

[0054] In some embodiments, the data processing sub-circuit is further configured to continue sampling to obtain the preset grayscale voltage in response to the control command signal being a second level signal, provided that the sampling result is a second line control command within the frame waiting period.

[0055] In some embodiments, the driving voltage of the display data corresponding to the current frame is less than the preset grayscale voltage, and the preset grayscale voltage is less than the driving voltage of the display data corresponding to the next frame; or, the driving voltage of the display data corresponding to the current frame is greater than the preset grayscale voltage, and the preset grayscale voltage is greater than the driving voltage of the display data corresponding to the next frame.

[0056] In some embodiments, both the first clock signal and the first data signal are low-voltage differential signals.

[0057] Secondly, embodiments of this disclosure also provide a display device, which includes a display driving circuit as described in any one of the first aspects. Attached Figure Description

[0058] Figure 1 shows the transmission line diagram of the existing Mini-LVDS signal sampling multi-Drop architecture;

[0059] Figure 2 shows the eye diagram of the Mini-LVDS signal on the vertical voltage axis under the architecture shown in Figure 1.

[0060] Figure 3 shows the eye diagram of the Mini-LVDS signal on the horizontal time axis under the architecture in Figure 1.

[0061] Figure 4 is a schematic diagram of a display device provided in an embodiment of this disclosure;

[0062] Figure 5 is a circuit architecture diagram of a display driving circuit provided in an embodiment of this disclosure;

[0063] Figure 6 is a schematic diagram of the clock signal phase delay under the architecture shown in Figure 5;

[0064] Figure 7 is a schematic diagram of the phase compensation sub-circuit provided in an embodiment of this disclosure;

[0065] Figure 8 is a schematic diagram of a display driving circuit according to an example provided in an embodiment of this disclosure;

[0066] Figure 9 is a schematic diagram of a display driving circuit under another example provided in the embodiments of this disclosure;

[0067] Figure 10 is a schematic diagram of a display driving circuit according to another example provided in the embodiments of this disclosure;

[0068] Figure 11 is a schematic diagram of a display driving circuit according to another example provided in the embodiments of this disclosure;

[0069] Figure 12 is a schematic diagram of the first clock signal before and after phase adjustment according to an embodiment of this disclosure;

[0070] Figures 13a to 13c are signal transmission structure diagrams of different examples of the display driving circuit provided in the embodiments of this disclosure;

[0071] Figure 14 is a structural diagram of an exemplary first data signal provided in an embodiment of this disclosure;

[0072] Figure 15 is a schematic diagram of the first data signal before and after phase adjustment according to an embodiment of this disclosure;

[0073] Figure 16 is a schematic diagram of a timing controller according to an example provided in an embodiment of this disclosure;

[0074] Figure 17 is a schematic diagram of the eye diagram before and after the improvement of the first data signal provided in the embodiment of this disclosure;

[0075] Figure 18 is a schematic diagram of a timing controller under another example provided in the embodiments of this disclosure;

[0076] Figure 19 is a schematic diagram of the eye diagram before and after the improvement of the first clock signal provided in the embodiments of this disclosure;

[0077] Figure 20 is a circuit architecture diagram of another display driving circuit provided in an embodiment of this disclosure;

[0078] Figure 21 is a timing diagram of the segmented transmission of target data signals by control command signals according to an embodiment of this disclosure;

[0079] Figure 22 is a schematic diagram of an exemplary source driver provided in an embodiment of this disclosure;

[0080] Figure 23 is a schematic diagram of a specific instruction for a frame waiting period under an example provided in an embodiment of this disclosure;

[0081] Figure 24 is a schematic diagram of the specific instructions for the frame wait period under another example provided in the embodiments of this disclosure. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0083] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0084] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0085] Before introducing the contents of this disclosure, the special terms involved in this invention will be explained.

[0086] Mini-LVDS is a data transmission technology used in displays and a high-speed data transmission interface protocol. It is an optimization and upgrade of the traditional Low Voltage Differential Signaling (LVDS) technology. Mini-LVDS uses low-voltage differential signals for data transmission and employs a high-speed differential transmission method with both edges of the transmit clock. This technology can flexibly allocate the number of data transmission channels according to the resolution and refresh rate of the display screen, thereby ensuring efficient and stable data transmission.

[0087] Multi-Drop architecture is a network architecture that allows multiple devices to be connected to a single interface. This architecture simplifies the connection and communication process by enabling a host to communicate with multiple devices using fewer lines. In this embodiment, a multi-Drop architecture is used to transmit differential clock signals between the clock driver and the source driver.

[0088] Point-to-point (PTP) architecture is a peer-to-peer architecture that can be understood as a single structure connecting to a single device. Through point-to-peer transmission protocols, highly reliable and stable data transmission can be achieved.

[0089] In related technologies, Mini-LVDS technology is commonly used for data transmission. Compared to traditional LVDS technology, Mini-LVDS offers a several-fold increase in data transmission bit rate. However, with the continuous improvement of resolution and refresh rate, both the clock differential signal (CLK) and data differential signal (Data) in Mini-LVDS employ a multi-Drop architecture to achieve multi-point parallel transmission, as shown in Figure 1. The timing controller TCON sends the data signal Data to the source drivers SD1 and SD2 through the same pair of differential lines. When the two source drivers SD1 and SD2 receive the data signal Data, the different line lengths and impedance mismatch cause reflected noise. Especially at high speeds, the signal reflection is strong, which can no longer meet the needs of higher-speed data transmission, such as speeds exceeding 1.2Gbps.

[0090] Both the clock signal CLK and the digital signal Data are differential signals (including differential pairs). Eye diagrams are typically used to measure the quality of differential signals. An eye diagram is a graphical representation used in digital communication systems to measure signal integrity and transmission quality. The eye diagram can be used to display the waveform of a signal through statistical graphs on an oscilloscope, helping testers assess the stability and reliability of the signal. By observing parameters such as the eye opening size and crossover point position, the performance of the digital signal can be evaluated and optimized. Typically, the eye diagram reflects voltage noise and time-domain jitter in digital signals. Figures 2 and 3 show the eye diagrams obtained using an oscilloscope for transmitting the clock signal CLK and digital signal Data using a multi-Drop architecture. These diagrams demonstrate voltage noise and time-domain jitter. Specifically, for the data signal Data, due to the superposition of multiple signals, the signal lines in the eye diagram become thicker (as shown in the boxed area in Figure 2), resulting in blurring. This is reflected on the vertical voltage axis as voltage noise. This is reflected on the horizontal time axis as time-domain jitter. Therefore, the higher the data signal rate (Data), the more pronounced this reflection phenomenon becomes, severely impacting signal transmission quality and consequently affecting image display. Thus, due to the limitations of mini-LVDS signal quality integrity, it is difficult to increase the data signal transmission rate (Data).

[0091] Based on the aforementioned issue of the limited speed of the Mini-LVDS transmission interface protocol, this disclosure provides a display driver circuit and a display device that employ a new data transmission architecture (which can also be understood as a new transmission interface protocol), which can support higher-speed signal transmission compared to the Mini-LVDS protocol in related technologies.

[0092] Figure 4 is a schematic diagram of a display device provided in an embodiment of this disclosure. As shown in Figure 4, the display device includes a display driving circuit 10 and a display panel 20. The display panel 20 includes pixel units (not shown in the figure) and a pixel driving circuit (not shown in the figure). The display driving circuit 10 is electrically connected to the pixel driving circuit via a data line 30 and is configured to output a driving voltage corresponding to the display data to the pixel driving circuit. The pixel driving circuit is configured to drive the pixel units to display an image according to the received driving voltage.

[0093] Figure 5 is a circuit architecture diagram of a display driving circuit provided in an embodiment of this disclosure. As shown in Figure 5, the display driving circuit 10 includes a timing controller 101 and a plurality of source drivers 102. The timing controller 101 is used to transmit clock signals CLK (including a first clock signal and a second clock signal) and data signals Data (including a first data signal and a second data signal) to each source driver 102. For the transmission of clock signals CLK, this disclosure adopts a multi-Drop architecture; for the transmission of data signals Data, this disclosure adopts a PTP architecture.

[0094] Specifically, the timing controller 101 includes at least one first output terminal 1011 and a plurality of second output terminals 1012; one first output terminal 1011 is electrically connected to at least one source driver 102; and each second output terminal 1012 is connected to a corresponding source driver 102. The first output terminal 1011 is an interface for transmitting clock signals CLK (including a first clock signal and a second clock signal). The second output terminals 1012 are interfaces for transmitting data signals Data (including a first data signal and a second data signal).

[0095] Optionally, the timing controller 101 includes at least one first output terminal 1011, each first output terminal 1011 being electrically connected to at least two source drivers 102. For example, the display driving circuit 10 includes m source drivers 102; m is a positive integer greater than or equal to 4. Taking an even number of m as an example, the timing controller 101 includes two first output terminals 1011, one of which is electrically connected to 1 to m / 2 source drivers 102, and the other first output terminal 1011 is electrically connected to the remaining m / 2+1 to m source drivers 102.

[0096] The timing controller 101 is configured to output a first clock signal through a first output terminal 1011 and a first data signal through a second output terminal 1012. The first clock signal output through the same first output terminal 1011 passes through different transmission branches during transmission and is sent to different source drivers 102; the first data signals output through different second output terminals 1012 pass through a unique transmission path and are sent to a unique corresponding source driver 102.

[0097] The first clock signal is a low-voltage differential signal. The first data signal is a low-voltage differential signal.

[0098] For any source driver 102, it is configured to sample a first data signal using a first clock signal and output the sampled display data. Specifically, if the sampled display data is a digital signal, the digital signal can be converted into an analog signal, i.e., a driving voltage, and transmitted to the pixel driving circuit.

[0099] In the display driver circuit 10 provided in this embodiment, the timing controller 101 is configured to output a first clock signal through a one-to-many first output terminal 1011 and a first data signal through a one-to-one second output terminal 1012. Since the signal transmission paths are not interconnected, reflection noise is avoided, thus preventing signal integrity and improving signal transmission quality. This effectively avoids reflection noise generated in the cascaded sharing of multiple source drivers 102. Therefore, compared to the limitations of the multi-Drop architecture, the transmission rate of the first data signal and the first clock signal can be higher in this disclosure.

[0100] In the display driver circuit 10 provided in this embodiment, the timing controller 101 is configured to output a first clock signal through a one-to-many first output terminal 1011 and a first data signal through a one-to-one second output terminal 1012. As shown in Figures 2 and 3, for the clock signal CLK, in actual transmission, since the transmission of the clock differential pair is a fixed 1 / 0 signal alternating transmission, the voltage noise generated by the clock signal CLK is smaller than the voltage noise generated by the data signal Data. If a clock recovery circuit is added to the source driver 102 to completely eliminate the weak noise during the transmission of the clock signal CLK, it will result in higher costs. Based on this, this embodiment adopts a multi-Drop architecture to transmit the first clock signal, which ensures that no large reflection phenomenon is generated under high-speed transmission (or that no noise sufficient to seriously affect high-speed transmission) and also achieves lower costs. Furthermore, this embodiment employs a point-to-point (PTP) architecture to transmit the first data signal. When the timing controller 101 simultaneously transmits the first data signal to multiple source drivers 102, since the paths for transmitting different first data signals are not interconnected, the first data signal output by one second output terminal 1012 is only sent to one source driver 102. This prevents reflection noise from affecting the integrity of the first data signal, thereby improving signal transmission quality and effectively avoiding reflection noise generated in the cascaded sharing method of multiple source drivers 102. Therefore, compared to the limitations of the multi-Drop architecture on the transmitted data signal, this disclosure can achieve a higher transmission rate for the output first data signal.

[0101] It should be noted that after adopting a point-to-point PTP architecture, the data signal Data (differential pair) shows almost no phase jitter when observed using the eye diagram. However, due to the use of a mutual-drop structure for the high-speed transmission of the clock signal CLK (differential pair), although the voltage noise on the vertical voltage axis is already very small, the cascaded use of multiple source drivers 102 still causes significant phase jitter on the horizontal time axis, affecting subsequent data sampling and normal screen display. As shown in Figure 6, the phase of the data signal Data of source driver SD1 is the same as that of the data signal Data of source driver SD2, mainly manifested in the fact that their effective level center positions are the same. The effective level center position refers to the optimal sampling position of the clock signal CLK for the data signal Data. The center position of the rising or falling edge of the clock signal CLK is the initial sampling point. Observing the simplified eye diagram, it can be seen that a phase difference exists between the initial sampling points of the clock signals CLK of source drivers SD1 and SD2. As shown in Figure 6, the source driver SD1 displays the clock signal CLK and the data signal Data. The alignment of the initial sampling point of the clock signal CLK with the optimal sampling position of the data signal Data can be understood as eliminating phase jitter. Further observation reveals that the phase jitter between the optimal sampling position of the data signal Data and the initial sampling point of the clock signal CLK, as shown in the source driver SD2, increases. This causes the eye diagram received by the source driver SD2 to be non-compliant. Under high-speed transmission, the display data sampled by the source driver SD2 is prone to misinterpretation, potentially resulting in image abnormalities. Therefore, this embodiment of the present disclosure adds a phase compensation sub-circuit 103 to compensate for the phase of the first clock signal or the first data signal.

[0102] Figure 7 is a schematic diagram of a phase compensation sub-circuit provided in an embodiment of this disclosure. In some embodiments, as shown in Figure 7, the display driving circuit 10 further includes a phase compensation sub-circuit 103. The phase compensation sub-circuit 103 includes a phase offset detection unit 1031 and a phase calibration unit 1032. The phase offset detection unit 1031 is configured to determine the phase offset between the first clock signal and the first data signal based on the received first clock signal and first data signal; the phase calibration unit 1032 is configured to perform phase compensation on the currently received first clock signal or first data signal using the phase offset.

[0103] Figure 8 is a schematic diagram of a display driving circuit according to an example provided in this disclosure. In one possible implementation, as shown in Figure 8, the phase compensation sub-circuit 103 is integrated in the source driver 102, which further includes a clock signal receiving sub-circuit 21 and a data signal receiving sub-circuit 22. The clock signal receiving sub-circuit 21 is configured to transmit a received first clock signal to the phase offset detection unit 1031; the data signal receiving sub-circuit 22 is configured to transmit a received first data signal to the phase offset detection unit 1031. The phase offset detection unit 1031 is configured to determine the phase offset between the first clock signal and the first data signal based on the received first clock signal and first data signal; the phase calibration unit 1032 is configured to perform phase compensation on the currently received first clock signal using the phase offset, so that the initial sampling point of the compensated first clock signal (i.e., the second clock signal hereinafter) is aligned with the optimal sampling position of the first data signal, thereby improving the integrity of subsequent sampling of the first data signal and ensuring normal display of the screen.

[0104] Figure 9 is a schematic diagram of a display driving circuit according to another example provided in this embodiment. In another possible implementation, as shown in Figure 9, the phase compensation sub-circuit 103 includes a phase offset detection unit 1031 and a phase calibration unit 1032. The phase offset detection unit 1031 is integrated in the source driver 102, and the phase calibration unit 1032 is integrated in the timing controller 101. The phase offset detection unit 1031 receives a first clock signal sent by the clock signal receiving sub-circuit 21 and a first data signal sent by the data signal receiving sub-circuit 22. The phase offset detection unit 1031 sends the calculated phase offset to the phase calibration unit 1032. The phase offset detection unit 1031 is configured to determine the phase offset between the first clock signal and the first data signal based on the received first clock signal and the first data signal; the phase calibration unit 1032 is configured to use the phase offset to perform phase compensation on the currently received first data signal, so that the optimal sampling position of the compensated first data signal (i.e., the second data signal below) is aligned with the initial sampling point of the first clock signal, thereby improving the integrity of subsequent sampling of the first data signal and ensuring the normal display of the screen.

[0105] Figure 10 is a schematic diagram of a display driving circuit according to another example provided in this embodiment. In another possible implementation, as shown in Figure 10, the phase compensation sub-circuit 103 is integrated in the timing controller 101. The timing controller 101 further includes a clock signal transmitting sub-circuit 11, a data signal transmitting sub-circuit 12, a clock signal generating sub-circuit 13, and a data signal generating sub-circuit 14. The clock signal generating sub-circuit 13 is configured to send a generated first clock signal to the phase compensation sub-circuit 103; the data signal generating sub-circuit 14 sends a generated first data signal to the phase compensation sub-circuit 103. The phase compensation sub-circuit 103 is configured to determine the phase offset between the first clock signal and the first data signal based on the received first clock signal and first data signal; and to perform phase compensation on the currently received first data signal using the phase offset to obtain a second data signal, so that the optimal sampling position of the second data signal is aligned with the initial sampling point of the first clock signal, thereby improving the integrity of subsequent sampling of the second data signal and ensuring the normal display of the screen. The clock signal generation subcircuit 13 is further configured to send the generated first clock signal to the clock signal transmission subcircuit 11; the clock signal transmission subcircuit 11 is configured to send the first clock signal to the source driver 102 through the first output terminal 1011. The data signal transmission subcircuit 12 is configured to send the received second data signal to the source driver 102 through the second output terminal 1012.

[0106] Figure 11 is a schematic diagram of a display driving circuit according to another example provided in this embodiment. In another possible implementation, as shown in Figure 11, the phase compensation sub-circuit 103 is integrated in the timing controller 101. The timing controller 101 further includes a clock signal generation sub-circuit 13 and a data signal generation sub-circuit 14. The clock signal generation sub-circuit 13 is configured to send a generated first clock signal to the phase compensation sub-circuit 103; the data signal generation sub-circuit 14 sends a generated first data signal to the phase compensation sub-circuit 103. The phase compensation sub-circuit 103 is configured to determine the phase offset between the first clock signal and the first data signal based on the received first clock signal and first data signal; and to perform phase compensation on the currently received first clock signal using the phase offset, so that the initial sampling point of the compensated first clock signal (i.e., the second clock signal hereinafter) is aligned with the optimal sampling position of the first data signal, thereby improving the integrity of subsequent sampling of the first data signal and ensuring the normal display of the screen.

[0107] In any of the above embodiments, phase compensation for the first clock signal or the first data signal is achieved, so that the initial sampling point of the clock signal CLK and the optimal sampling position of the data signal Data are aligned, thereby eliminating the influence of time-domain jitter caused by the first clock signal under the cascading of multiple source drivers 102.

[0108] In some embodiments, as shown in FIG8, the phase compensation sub-circuit 103 is integrated in the source driver 102, and the source driver 102 further includes a clock signal receiving sub-circuit 21, a data signal receiving sub-circuit 22, a data sampling sub-circuit 23, and a data output sub-circuit 24.

[0109] The clock signal receiving sub-circuit 21 is configured to transmit the received first clock signal to the phase compensation sub-circuit 103. The clock signal receiving sub-circuit 21 is a clock signal CLK receiving interface.

[0110] The data signal receiving sub-circuit 22 is configured to transmit the received first data signal to the data sampling sub-circuit 23 and the phase compensation sub-circuit 103. The data signal receiving sub-circuit 22 is a data signal receiving interface.

[0111] The phase compensation sub-circuit 103 is configured to calculate the phase offset between the first clock signal and the first data signal; and to use the phase offset to perform phase compensation on the first clock signal to obtain the second clock signal.

[0112] The data sampling sub-circuit 23 is configured to sample the first data signal according to the second clock signal to obtain display data. The data output sub-circuit 24 is configured to output the display data. Here, sampling the first data signal using the compensated first clock signal (i.e., the second clock signal) can improve the integrity of the display data and ensure the normal display of the screen.

[0113] In some embodiments, continuing as shown in FIG8, the data sampling sub-circuit 23, upon receiving the second clock signal, indicates that the phase compensation during the power-on initial stage has been completed, and the phase offset has already been calculated. Therefore, it is unnecessary to recalculate the phase offset by receiving the first data signal again. Thus, the function of the phase compensation sub-circuit 103 in receiving the first data signal needs to be disabled. Specifically, the data sampling sub-circuit 23 is also configured to send a feedback signal to the phase compensation sub-circuit 103 in response to receiving the second clock signal. Here, the feedback signal is a control signal indicating that the phase compensation sub-circuit 103 should be disabled from receiving the data signal Data. The phase compensation sub-circuit 103 is also configured to stop receiving the first data signal in response to receiving the feedback signal.

[0114] The phase compensation sub-circuit 103 includes a phase offset detection unit 1031 and a phase calibration unit 1032. In response to receiving a feedback signal, the phase offset detection unit 1031 stops receiving the first data signal until power is off; upon restarting, it recalculates the phase offset. After stopping receiving the first data signal, the phase offset detection unit 1031 can still continuously receive the first clock signal, but since no first data signal is received at this time, there is no need to calculate the tangent offset, and the first clock signal can be directly sent to the phase calibration unit 1032. The phase calibration unit 1032 can use the already calculated phase offset to continuously compensate the received first clock signal until power is off.

[0115] Optionally, the first clock signal used to calculate the phase offset can be the clock signal CLK corresponding to the first sub-signal 01 in the first data signal. The clock signals CLK corresponding to other sub-signals (referring to the first data signals received sequentially) are directly transmitted to the phase calibration unit 1032 through the phase offset detection unit 1031 for phase calibration and output to the data sampling sub-circuit 23. That is, before the data sampling sub-circuit 23 samples valid display data, the phase calibration unit 1032 performs phase calibration on the first clock signal, which can prevent the data sampling sub-circuit 23 from missing accurate sampling of valid display data. At the same time, in this embodiment, a single calibration can realize the screen display after power-on for this round (including multiple frames), avoiding repeated calibration at the beginning of each frame, saving the transmission of the phase calibration signal (which is a part of the first data signal sub-signal), that is, shortening the transmission amount of the first data signal; it also saves power consumption and improves the lifespan of the source driver 102.

[0116] Figure 12 is a schematic diagram of the first clock signal before and after phase adjustment according to an embodiment of this disclosure. In some embodiments, the phase offset detection unit 1031 calculates the phase offset between the first clock signal and the first data signal in the following manner: as shown in Figure 12, firstly, it acquires the initial sampling point of the first clock signal CLK1, and the initial position point and termination position point of the first data signal Data1 in the effective level phase. The initial sampling point is the initial position point of the first clock signal CLK1 in the effective level phase. In this embodiment of the disclosure, the effective level of both the first clock signal CLK1 and the first data signal Data1 is high. The effective level phase is also known as the high level phase.

[0117] Next, calculate the first phase step size between the initial sampling point and the initial position point. For example, if the initial sampling point of the first clock signal precedes the initial position point of the first data signal, the first phase step size between the initial sampling point and the initial position point is calculated to be -1, based on the first phase 0 corresponding to the initial sampling point and the second phase -1 corresponding to the initial position point. Here, the "negative sign (-)" indicates a leftward movement.

[0118] Next, calculate the second phase step size between the initial sampling point and the termination position. For example, if the initial sampling point of the first clock signal is after the termination position of the first data signal, the second phase step size between the initial sampling point and the termination position is calculated to be +3, based on the first phase 0 corresponding to the initial sampling point and the third phase +3 corresponding to the termination position. Here, a "positive sign (+)" indicates a rightward movement.

[0119] Finally, based on the first and second phase step sizes, the phase offset between the initial sampling point and the center position of the effective level is determined, i.e., ((-1)+(+3)) / 2=+1; where the center position of the effective level is the optimal sampling position of the first clock signal CLK1 for the first data signal Data1 during the effective level phase. The phase 0 position of the second clock signal CLK2 relative to the first clock signal CLK1 before calibration is finally determined, and a step size of 1 is added to the right to align the initial sampling point of the second clock signal CLK2 with the optimal sampling position of the first data signal Data1. This ensures optimal sampling of the first data signal Data1 by the second clock signal CLK2, guaranteeing the sampling integrity of the first data signal Data1 and improving sampling accuracy.

[0120] Figures 13a to 13c are signal transmission structure diagrams under different examples of the display driving circuit provided in the embodiments of this disclosure. In some embodiments, as shown in Figures 13a and 13b, the phase compensation sub-circuit 103 includes a phase offset detection unit 1031 and a phase calibration unit 1032, wherein the phase offset detection unit 1031 is integrated in the source driver 102, and the phase calibration unit 1032 is integrated in the timing controller 101; the source driver 102 also includes a clock signal receiving sub-circuit 21, a data signal receiving sub-circuit 22, a data sampling sub-circuit 23, and a data output sub-circuit 24; the timing controller 101 also includes a clock signal transmitting sub-circuit 11 and a data signal transmitting sub-circuit 12.

[0121] The clock signal transmitting sub-circuit 11 is configured to transmit a first clock signal to the clock signal receiving sub-circuit 21 through a first output terminal 1011. The clock signal transmitting sub-circuit 11 includes multiple first output terminals 1011. The number of first output terminals 1011 is less than the number of source drivers 102.

[0122] Optionally, the timing controller 101 further includes a clock signal generation sub-circuit 13 for generating a first clock signal and sending it to the clock signal transmission sub-circuit 11.

[0123] The data signal transmitting sub-circuit 12 is configured to transmit a phase calibration signal to the data signal receiving sub-circuit 22 via a second output terminal 1012. The phase calibration signal is used for phase calibration. The data signal transmitting sub-circuit 12 includes a plurality of second output terminals 1012, the number of which is greater than or equal to the number of source drivers 102.

[0124] Optionally, the phase calibration signal is the first data signal.

[0125] Figure 14 is a structural diagram of an exemplary first data signal provided in an embodiment of this disclosure. As shown in Figure 14, the first data signal Data1 includes a first sub-signal 01 and a second sub-signal 02; the timing controller 101 transmits the first sub-signal 01 before transmitting the second sub-signal 02. Optionally, the first sub-signal 01 is a phase calibration signal. The second sub-signal 02 includes a signal representing displayed data.

[0126] Optionally, the timing controller 101 further includes a data signal generation sub-circuit 14 for generating a phase calibration signal and sending it to the data signal transmission sub-circuit 12.

[0127] The clock signal receiving sub-circuit 21 is configured to transmit the received first clock signal to the phase offset detection unit 1031. The clock signal receiving sub-circuit 21 is a clock signal receiving interface.

[0128] The data signal receiving sub-circuit 22 is configured to transmit the received phase calibration signal to the phase offset detection unit 1031. The data signal receiving sub-circuit 22 serves as a data signal receiving interface.

[0129] The phase offset detection unit 1031 is configured to calculate the phase offset between the first clock signal and the phase calibration signal, and send the phase offset to the phase calibration unit 1032. The phase offset can be transmitted by configuring a data transmission channel between the phase offset detection unit 1031 and the phase calibration unit 1032.

[0130] The phase calibration unit 1032 is configured to perform phase compensation on the first data signal using a phase offset to obtain a second data signal; and to transmit the second data signal to the data signal transmitting sub-circuit 12. Specifically, the data signal generating sub-circuit 14 is also configured to generate the first data signal and send it to the phase calibration unit 1032.

[0131] The data signal transmitting sub-circuit 12 is further configured to transmit the received second data signal to the data signal receiving sub-circuit 22 via the second output terminal 1012. The data signal receiving sub-circuit 22 is further configured to transmit the received second data signal to the data sampling sub-circuit 23.

[0132] The data sampling sub-circuit 23 is configured to sample the second data signal based on the received first clock signal to obtain display data. The data output sub-circuit 24 is configured to output the display data. Here, sampling the compensated first data signal (i.e., the second data signal) using the first clock signal can improve the integrity of the display data and ensure the normal display of the screen.

[0133] Optionally, as shown in FIG13c, the phase calibration unit 1032 is a function originally present in the data signal transmission sub-circuit 12 in the timing controller 101. Specifically, the data signal transmission sub-circuit 12 is configured to perform phase compensation on the first data signal using a phase offset to obtain a second data signal; and send the second data signal to the source driver 102 through the second output terminal 1012. In this way, the cost of the phase calibration unit 1032 in the source driver 102 can be reduced.

[0134] In some embodiments, continuing as shown in Figures 13a and 13b, the data sampling sub-circuit 23 responds to the receipt of the second data signal, indicating that the phase compensation during the power-on initial stage has been completed. At this point, the phase offset has been calculated, and there is no need to receive the phase calibration signal again to recalculate the phase offset. Therefore, it is necessary to disable the function of the phase compensation sub-circuit 103 in receiving the first data signal.

[0135] It should be noted that the second data signal is transmitted after the phase calibration signal. Since the first clock signal and the phase calibration signal are transmitted synchronously, the data sampling sub-circuit 23 receives the first clock signal slightly earlier than the second data signal. To avoid wasting power, the data sampling sub-circuit 23 no longer waits for the corresponding second data signal to send a feedback signal; instead, it sends a feedback signal upon receiving the first clock signal.

[0136] Optionally, as shown in FIG13a, the phase offset detection unit 1031 is further configured to send the received first clock signal to the data sampling sub-circuit 23. The data sampling sub-circuit 23 is further configured to send a feedback signal to the phase offset detection unit 1031 in response to receiving the first clock signal. Here, the feedback signal is a control signal indicating to disable the phase offset detection unit 1031 from receiving data signals (here, the data signal refers to the second data signal to be transmitted subsequently). The phase offset detection unit 1031 is further configured to stop receiving the second data signal in response to receiving the feedback signal.

[0137] Here, the phase offset detection unit 1031 has the function of sending a first clock signal to the data sampling sub-circuit 23. By configuring a data transmission channel for the phase offset detection unit 1031 and the data sampling sub-circuit 23, the transmission of the clock signal CLK can be realized.

[0138] Here, after the phase offset detection unit 1031 stops receiving the first data signal, it can still continuously receive the first clock signal. However, since no first data signal is received at this time, there is no need to calculate the tangent offset, and the first clock signal can be directly sent to the data sampling sub-circuit 23. Subsequently, the phase calibration unit 1032 can use the already calculated phase offset to continuously perform phase compensation on the received first data signal, obtain the second data signal, and transmit it to the data sampling sub-circuit 23 until power is cut off.

[0139] Optionally, as shown in FIG13b, the data sampling sub-circuit 23 is further configured to send a feedback signal to the phase offset detection unit 1031 in response to receiving a first clock signal sent by the clock signal receiving sub-circuit 21. Here, the feedback signal is a control signal instructing the phase offset detection unit 1031 to stop receiving the second data signal and the first clock signal. The phase offset detection unit 1031 is further configured to stop receiving the second data signal and the first clock signal in response to receiving the feedback signal.

[0140] The data sampling sub-circuit 23 responds to receiving the first clock signal sent by the clock signal receiving sub-circuit 21, indicating that the clock signal receiving sub-circuit 21 will also necessarily send the first clock signal to the phase offset detection unit 1031. Therefore, the data sampling sub-circuit 23 can respond to receiving the first clock signal by sending a feedback signal to stop the phase offset detection unit 1031 from receiving the second data signal and the first clock signal, thus avoiding wasted power consumption.

[0141] In this embodiment, phase calibration is performed first, and the second data signal (including valid display data) is sent later, which can prevent the data sampling sub-circuit 23 from missing accurate sampling of valid display data.

[0142] Figure 15 is a schematic diagram of the first data signal before and after phase adjustment according to an embodiment of this disclosure. In some embodiments, the phase offset detection unit 1031 calculates the phase offset between the first clock signal and the first data signal in the following manner: as shown in Figure 15, firstly, the initial sampling point of the first clock signal CLK1, and the initial position point and termination position point of the first data signal Data1 in the effective level phase are obtained. The initial sampling point is the initial position point of the first clock signal CLK1 in the effective level phase. In this embodiment of the disclosure, the effective level of both the first clock signal CLK1 and the first data signal Data1 is high level. The effective level phase is also known as the high level phase.

[0143] Next, calculate the third phase step from the initial position point to the initial sampling point. For example, if the initial position point of the first data signal is after the initial sampling point of the first clock signal, based on the fourth phase 0 corresponding to the initial position point of the first data signal and the fifth phase +1 corresponding to the initial position point, calculate the third phase step from the initial position point to the initial sampling point as +1. Here, a "positive sign (+)" indicates a rightward movement.

[0144] Next, calculate the fourth phase step from the termination point to the initial sampling point. For example, if the termination point of the first data signal precedes the initial sampling point of the first clock signal, based on the seventh phase 0 corresponding to the termination point and the eighth phase -3 corresponding to the initial sampling point, calculate the fourth phase step from the termination point to the initial sampling point as -3. Here, the "negative sign (-)" indicates a leftward movement.

[0145] Finally, based on the third and fourth phase step sizes, the phase offset between the effective level center position and the initial sampling point is determined, i.e., ((+1)+(-3)) / 2=-1; where the effective level center position is the optimal sampling position of the first clock signal CLK1 for the first data signal Data1 during the effective level phase. Finally, the phase 0 position of the second data signal Data2 relative to the first data signal Data1 before calibration is determined, and the step size is reduced by 1 to the left, aligning the optimal sampling position of the second data signal Data2 with the initial sampling point of the first clock signal CLK1. This ensures optimal sampling of the second data signal Data2 by the first clock signal CLK1, guaranteeing the sampling integrity of the second data signal Data2 and improving sampling accuracy.

[0146] Figure 16 is a schematic diagram of a timing controller according to an example embodiment of this disclosure. In another possible implementation, as shown in Figure 16, the timing controller 101 further includes a clock signal transmitting subcircuit 11 and a data signal transmitting subcircuit 12. The clock signal transmitting subcircuit 11 is configured to transmit a first clock signal to the source driver 102 through a first output terminal 1011; the data signal transmitting subcircuit 12 is configured to perform phase compensation on the first data signal using a preset phase offset to obtain a second data signal, so that the optimal sampling position of the second data signal is aligned with the initial sampling point of the first clock signal. Then, the second data signal is transmitted to the source driver 102 through a second output terminal 1012. In this way, the compensated first data signal (i.e., the second data signal) is sampled using the first clock signal to improve the integrity of the display data sampling and ensure the normal display of the screen.

[0147] The pre-set phase offset is the phase deviation between the initial sampling point and the optimal sampling point obtained from the eye diagram of the data signal Data and the clock signal CLK measured during the test phase. This phase offset is recorded as the phase offset and stored.

[0148] Figure 17 is a schematic diagram of the eye diagram of the first data signal before and after improvement according to the embodiments of this disclosure. As shown in Figure 17, Figure (a) shows the eye diagram before improvement and Figure (b) shows the eye diagram after improvement. Based on the optimal sampling position of the first data signal Data1 and the initial sampling point of the first clock signal CLK1 (that is, the center position of the rising edge or falling edge of the first clock signal), it is determined that the first data signal Data1 should be offset to the left by Δ relative to the first clock signal CLK1, which is recorded as the phase offset amount -Δ and stored.

[0149] In this embodiment, the data signal transmission sub-circuit 12 within the timing controller 101 inherently possesses phase compensation functionality. When the data signal transmission sub-circuit 12 receives a pre-set phase offset, it can directly utilize the phase offset to perform phase compensation on the first data signal. This saves on the cost of the phase compensation sub-circuit 103 (phase offset detection unit 1031 and phase calibration unit 1032).

[0150] Figure 18 is a schematic diagram of a timing controller according to another example provided in the embodiments of this disclosure. In another possible implementation, as shown in Figure 18, the timing controller 101 includes a clock signal transmitting sub-circuit 11 and a data signal transmitting sub-circuit 12; the data signal transmitting sub-circuit 12 is configured to transmit a first data signal through a second output terminal 1012 to a source driver 102; the clock signal transmitting sub-circuit 11 is configured to perform phase compensation on the first clock signal using a preset phase offset to obtain a second clock signal; and transmit the second clock signal through a first output terminal 1011 to the source driver 102.

[0151] Figure 19 is a schematic diagram of the eye diagram of the first clock signal before and after improvement according to the embodiments of this disclosure. As shown in Figure 19, Figure (a) shows the eye diagram before improvement and Figure (b) shows the eye diagram after improvement. Based on the optimal sampling position of the first data signal Data1 and the initial sampling point of the first clock signal CLK1 (that is, the center position of the rising edge or falling edge of the first clock signal), it is determined that the first clock signal CLK1 should be offset to the right by Δ relative to the first data signal Data1, which is recorded as the phase offset +Δ and stored.

[0152] As described above, by compensating for the phase of the first clock signal or the phase of the first data signal, the initial sampling point of the clock signal CLK is aligned with the optimal sampling position of the data signal Data. This eliminates the impact of phase jitter caused by the multi-Drop architecture used in high-speed transmission of the clock signal CLK, thereby improving signal integrity and ultimately increasing the signal transmission rate. Furthermore, as shown in Formula 1 below, the signal transmission rate is directly proportional to the refresh rate. Therefore, this disclosure employs a point-to-point PTP architecture + multi-Drop architecture, combined with phase compensation, which not only improves the signal transmission rate but also means that the product refresh rate can be further improved.

[0153] Formula 1:

[0154] Where Htotal represents the total number of horizontal pixels; Vtotal represents the total number of vertical rows; bit represents the number of bits for pixel color depth; port represents the number of clock signal CLK groups; and pair represents the number of differential pairs for data signals.

[0155] In some embodiments, in order to increase register control and without using extended encoding (such as 8B / 9B encoding), a new control instruction signal CM is added; the segmented transmission of the target data signal Data0 is achieved by controlling the high and low level changes of the control instruction signal CM itself.

[0156] Figure 20 is a circuit architecture diagram of another display driving circuit provided in an embodiment of this disclosure. As shown in Figure 20, in addition to the timing controller 101 including a first output terminal 1011 and a second output terminal 1012, the timing controller 101 also includes a third output terminal 1013. The third output terminal 1013 is an interface for transmitting control command signals CM. Optionally, there is one third output terminal 1013, which is electrically connected to multiple source drivers 102. The control command signal CM is different from differential signals and belongs to single-ended signals. Optionally, there are at least two third output terminals 1013, which can be electrically connected to multiple different source drivers 102 respectively. The fewer the third output terminals 1013, the lower the cost and the less space occupied by the timing controller 101. This disclosure uses one third output terminal 1013 as an example for explanation.

[0157] The timing controller 101 is also configured to output control command signals CM to each source driver 102 via a third output terminal 1013. The source drivers 102 are further configured to control the output of display data based on the received target clock signal CLK0, target data signal Data0, and control command signals CM. The target clock signal CLK0 is used to sample the target data signal Data0, and the control command signal CM is used to control the execution of instructions or data transmission of the sampling results. The sampling results of the target data signal Data0 include, but are not limited to, the first frame control command, the first line control command, display data, the second frame control command, and the second line control command.

[0158] It should be noted that "first frame control instruction" and "second frame control instruction" here refer to different frame control instructions. They are names defined to distinguish different "frame control instructions," and are not the control instructions for the first and second frames. Similarly, "first line control instruction" and "second line control instruction" are names defined to distinguish different "line control instructions," and are not the control instructions for the first and second lines.

[0159] The target clock signal CLK0 is the first clock signal, and the target data signal Data0 is the second data signal; or, the target clock signal CLK0 is the second clock signal, and the target data signal Data0 is the first data signal; or, the target clock signal CLK0 is the first clock signal, and the target data signal Data0 is the first data signal.

[0160] Figure 21 is a timing diagram showing the segmented transmission of the target data signal Data0 using the control command signal CM provided in an embodiment of this disclosure. As shown in Figure 21, the target data signal Data0 includes a first sub-signal 01, a second sub-signal 02, a third sub-signal 03, a fourth sub-signal 04, a fifth sub-signal 05, and a sixth sub-signal 06. The first sub-signal 01 is an Auto Phase skew Calibration (APSC) signal. The second sub-signal 02 is a signal representing the display data (Line Data). The third sub-signal 03 is a signal representing the first frame control command (Frame-C). The fourth sub-signal 04 is a signal representing the first line control command (Line-C). The fifth sub-signal 05 is a signal representing the line waiting period (H-blanking). The sixth sub-signal 06 is a signal representing the frame waiting period (V-blanking).

[0161] The timing of the transmission of the first sub-signal 01 is before the timing of the transmission of the second sub-signal 02, which can prevent the data sampling sub-circuit 23 from missing accurate sampling of valid display data.

[0162] The transmission timing of the first sub-signal 01 precedes the transmission timing of the third sub-signal 03; the transmission timing of the third sub-signal 03 precedes the transmission timing of the second sub-signal 02; the transmission timing of the second sub-signal 02 precedes the transmission timing of the fourth sub-signal 04; the transmission timing of the fourth sub-signal 04 precedes the transmission timing of the fifth sub-signal 05; and the transmission timing of the fifth sub-signal 05 precedes the transmission timing of the sixth sub-signal 06.

[0163] The timing controller 101 predefines the high and low levels and transmission timing of the control command signal CM. The first level signal of the control command signal CM, such as a low level signal, mainly corresponds to the transmission phases of the first sub-signal 01 and the fourth sub-signal 04. For example, if the sampling result of the first sub-signal 01 is a phase calibration signal (APSC) or the sampling result of the fourth sub-signal 04 is a first line control command (Line-C), the control command signal M1 must be at the first level signal for at least a portion of the sampling phase to execute subsequent data processing procedures, such as phase calibration or retrieving the second output strategy information of a line of display data. The second level signal of the control command signal CM, such as a high level signal, mainly corresponds to the transmission phases of the second sub-signal 02, the third sub-signal 03, the fifth sub-signal 05, and the sixth sub-signal 06. For example, if the sampling result of the second sub-signal 02 is a display data (Line Data) signal, the control command signal M1 must be at the second level signal for at least a portion of the sampling phase to execute subsequent control display data output.

[0164] Figure 22 is a schematic diagram of an exemplary source driver provided in an embodiment of this disclosure. As shown in Figure 22, the source driver 102 includes a control signal receiving subcircuit 26, a data sampling subcircuit 23, and a data processing subcircuit 25. The control signal receiving subcircuit 26 is configured to transmit a received control command signal CM to the data processing subcircuit 25. Exemplarily, the control signal receiving subcircuit 26 is a single-ended interface for transmitting the control command signal CM.

[0165] The data sampling sub-circuit 23 is configured to sequentially sample the target data signal Data0 using the target clock signal CLK0, and the sampling results include, for example, the first frame control instruction, the first line control instruction, and the display data.

[0166] The sampling process is as follows: the target data signal Data0 is in the form of a digital signal, and each sub-signal contained in the target data signal Data0 contains its own independent identification number. Therefore, after the data sampling sub-circuit 23 samples the target data signal Data0 using the target clock signal CLK0, it determines the sampling result as the first frame control command, the first line control command, or display data based on the identification number.

[0167] The data processing sub-circuit 25 is configured to, in response to receiving a sampling result, and if the sampling result is a first frame control command, and in response to the control command signal CM being a second level signal, retrieve the first output strategy information for each frame of display data. Here, the first output strategy information can be understood as a pre-set strategy for instructing how the entire frame of display data should be output, that is, charging the pixels according to the method indicated by the first output strategy information. This first output strategy information includes, but is not limited to, a pre-set Gamma voltage, a pre-selected differential pair (for example, the data signal differential pair can be divided into multiple pairs; for example, a timing controller 101 can connect one, two, or more data signal differential pairs to the same source driver 102, which can increase the amount of data received by a single source driver 102; generally, the source driver 102 is designed with more than one group, and one group, two groups, or more groups can be selected based on the total amount of data to be transmitted), and a pre-set number of channels for display data transmission (for example, different display panels 20 have different numbers of channels, which can be configured according to the actual display panel 20 used).

[0168] It should be noted that the identity numerical representation of the first frame control command is not unique. For example, the regular data grayscale L255 is eight consecutive 1s in 8-bit color depth, i.e., 11111111. If the data representation of the first frame control command is also set to 11111111, the source driver 102 will not be able to distinguish and identify it. Therefore, this disclosure adds a control command signal CM. Given that the sampling result has been determined, further response to the control command signal CM allows for a more accurate determination of the identity of the sampling result.

[0169] The data processing sub-circuit 25 is also configured to, when the sampling result is a first line control command, retrieve second output strategy information for a line of display data in response to the control command signal CM being a first level signal. Here, the second output strategy information can be understood as a pre-set strategy indicating how a line of display data should be output, i.e., charging the pixels according to the method indicated by the second output strategy information. This second output strategy information includes, but is not limited to, whether to perform polarity reversal on the driving voltage corresponding to the display data; specifically, polarity reversal control can be achieved by setting polarity control signals (polarity control signal POL, polarity control signal POLC between the two source drivers 102, and pixel-by-pixel polarity reversal H2DOT).

[0170] The data processing sub-circuit 25 is further configured to, when the sampling result is display data, control the display data output according to the first output strategy information and the second output strategy information in response to the control command signal CM being a second-level signal. For example, display data is output according to a preset Gamma voltage, a preset differential pair, a preset number of channels for display data transmission, and a polarity control signal set for the current row of display data.

[0171] Optionally, the data processing sub-circuit 25 is also configured to continuously respond to the control command signal CM being a second level signal when the sampling result is a row waiting period, and wait for an idle period until the control command signal CM is a first level signal.

[0172] Here, the voltage of the first level signal is lower than the voltage of the second level signal. This disclosure uses the example of the first level signal being low and the second level signal being high as an example for illustration.

[0173] The high and low level transitions of the control command signal CM allow the data processing sub-circuit 25 to quickly switch and execute different logic.

[0174] During the first high-level period after power-on, the data processing subcircuit 25 can control the execution of the first frame control command to obtain the first output strategy information. Subsequently, the data sampling subcircuit 23 continues sequential sampling. When the control command signal CM jumps to a low level, during this low-level period, the data processing subcircuit 25 can control the execution of the first row control command to obtain the second output strategy information. The data sampling subcircuit 23 then continues sequential sampling. When the control command signal CM jumps to a high level again, during this high-level period, the data processing subcircuit 25 can control the display data, outputting it according to the methods indicated by the first and second output strategy information, until all the display data for the first row is output, entering a row waiting period. Afterwards, the control command signal CM jumps to a low level again to notify the data processing subcircuit 25 to control the output of the next row of display data; this process continues until all the display data for a frame is output, entering a frame waiting period.

[0175] In this embodiment, a new control command signal CM is added. By rapidly switching between high and low levels of the control command signal CM, the orderly execution of frame control commands, the orderly execution of line control commands, and the orderly output of display data are achieved, ensuring signal quality under high-speed transmission.

[0176] In some embodiments, FIG23 is a schematic diagram of a specific instruction for a frame waiting period under an example provided by an embodiment of the present disclosure. As shown in FIG23, the target data signal Data0 further includes a seventh sub-signal 07 and an eighth sub-signal 08. Both the seventh sub-signal 07 and the eighth sub-signal 08 are located in the frame waiting period (V-blanking). The seventh sub-signal 07 is a signal representing the second frame control instruction (Frame-C). The eighth sub-signal 08 is a signal representing the intermediate wait signal (IDEL). The transmission timing of the seventh sub-signal 07 precedes the transmission timing of the eighth sub-signal 08.

[0177] The timing controller 101 predefines the high and low levels and transmission timing of the control command signal CM, wherein the first level signal of the control command signal CM also corresponds to the transmission stage of the seventh sub-signal 07. The second level signal of the control command signal CM also corresponds to the transmission stage of the eighth sub-signal 08.

[0178] The data sampling sub-circuit 23 is configured to sample the seventh sub-signal 07 using the target clock signal CLK0, and determine the sampled result as the second frame control command within the frame waiting period based on the identification number. Similarly, the eighth sub-signal 08 is sampled using the target clock signal CLK0, and the sampled result as the intermediate waiting signal within the frame waiting period based on the identification number.

[0179] The data processing sub-circuit 25 is also configured to, in the event that the sampling result is a second frame control command within the frame waiting period, respond to the control command signal CM being a first level signal, disable the receiving function of the first data signal and / or the sending function of the display data; the frame waiting period refers to the idle period from the output of the current frame display data to the output of the next frame display data, specifically the idle period from the end of the line waiting period of the last line of the previous frame to the start of the first line control command of the next frame.

[0180] During the frame wait period, if the control command signal CM is low, it indicates that there is an instruction (second frame control command) to be processed. During this idle period, the function of disabling the reception of the first data signal and / or the function of sending display data are specifically executed. In this way, the source driver 102 can enter a sleep state during the idle period, thereby saving power consumption.

[0181] In some embodiments, continuing as shown in FIG23, the data processing sub-circuit 25 is further configured to, when the reception function of the first data signal and / or the transmission function of display data are currently disabled, enable the reception function of the first data signal and / or the transmission function of display data in response to the control command signal CM being a first level signal. That is, after the frame waiting period, the timing controller 101 can re-wake up the source driver 102 by pulling the control command signal CM low, so as to ensure that the source driver 102 can enter the working state in time before the next frame of valid display data is transmitted.

[0182] Optionally, before the frame waiting period ends and the next frame display data transmission is about to begin, the data processing sub-circuit 25 is also configured to enable the receiving function of the first data signal and / or the sending function of display data in response to the control command signal CM being a first level signal. Here, the control command signal CM is the control command signal CM corresponding to the first line control command of the next frame.

[0183] Optionally, if the period during which the reception function of the first data signal and / or the transmission function of the display data are disabled falls within a frame waiting period, the data processing sub-circuit 25 is further configured to enable the reception function of the first data signal and / or the transmission function of the display data in response to the control command signal CM being a first level signal during the frame waiting period.

[0184] The source driver 102 can quickly go to sleep and wake up by rapidly switching between high and low levels of the control command signal CM, thereby reducing power consumption.

[0185] In some embodiments, FIG24 is a schematic diagram of a specific instruction for a frame waiting period under another example provided by an embodiment of the present disclosure. As shown in FIG24, the target data signal Data0 further includes a ninth sub-signal 09 and a tenth sub-signal 010. Both the ninth sub-signal 09 and the tenth sub-signal 010 are located in the frame waiting period and are located between two adjacent eighth sub-signals 08. The transmission timing of the ninth sub-signal 09 is before the transmission timing of the tenth sub-signal 010. The ninth sub-signal 09 is a signal representing the second line control instruction (Line-C). The tenth sub-signal 010 is a signal representing the preset grayscale voltage (Gray).

[0186] The timing controller 101 predefines the high and low levels and transmission timing of the control command signal CM, wherein the first level signal of the control command signal CM also corresponds to the transmission stage of the ninth sub-signal 09. The second level signal of the control command signal CM also corresponds to the transmission stage of the tenth sub-signal 010.

[0187] The data sampling sub-circuit 23 is configured to sample the ninth sub-signal 09 using the target clock signal CLK0, and determine the sampled result as the second line of control instructions within the frame waiting period based on the identification number. Similarly, the tenth sub-signal 010 is sampled using the target clock signal CLK0, and the sampled result as the preset grayscale voltage within the frame waiting period based on the identification number.

[0188] The data processing sub-circuit 25 is further configured to, during the frame waiting period, respond to the control command signal CM being a first-level signal, acquire the sampling result as a second-line control command, adjust the driving voltage of the display data corresponding to the current frame to a preset grayscale voltage and output it, so as to maintain the voltage on the data line 30 during the frame waiting period. The data line 30 is used to electrically connect the source driver 102 and the pixel driving circuit; the preset grayscale voltage has the opposite polarity to the driving voltage. S-out represents the driving voltage; V1 represents the driving voltage of the display data corresponding to the current frame; V0 represents the preset grayscale voltage.

[0189] Optionally, the data processing sub-circuit 25 is further configured to continue sampling in response to the control command signal CM being a second-level signal, if the sampling result is a second-line control command within the frame waiting period, to obtain a preset grayscale voltage. Therefore, the preset grayscale voltage is the result of continued sampling of the tenth sub-signal 010 after the second-line control command.

[0190] Alternatively, the preset grayscale voltage can also be information read from an external source for grayscale compensation.

[0191] Since it is in the frame waiting period, the second frame control command is in the order of timing. The source driver 102 is in the state of turning off the receiving function of the first data signal and / or the sending function of the display data. At this time, the receiving function of the first data signal and / or the sending function of the display data are woken up by responding to the first level signal of the frame control command, and the sampling results of the ninth sub-signal 09 and the tenth sub-signal 010 are received successively. The sampling result of the ninth sub-signal 09 is the second line control command. The second line control command is used to instruct the data processing sub-circuit 25 to perform the adjustment of the driving voltage.

[0192] It should be noted that the display panel uses a liquid crystal panel, and the internal liquid crystal deflects with voltage changes. This deflection is alternating symmetrical. If the liquid crystal deflects only to one side, it will become polarized, losing its deflection characteristic. In this case, even if the alternating deflection voltage is increased, the human eye will see continuous flickering, mainly due to the inconsistent light transmission brightness caused by the alternating deflection of the liquid crystal under polarization. Therefore, to avoid the aforementioned drawbacks caused by the voltage on data line 30 remaining constant for a long time, this embodiment sets the driving voltage of the display data for the next frame to be different from that of the current frame. As shown in Figure 24, the driving voltage of the display data corresponding to the current frame is V1, and the driving voltage of the display data corresponding to the next frame is V2. The voltage difference between V2 and V1 is large, and during the driving voltage output process, it is impossible to quickly increase from the lower driving voltage V1 to the higher driving voltage V2. Therefore, the voltage polarity is reversed using the second line of control instructions. The driving voltage of the display data corresponding to the current frame is adjusted to a preset grayscale voltage V0.

[0193] Taking V2 > V1 as an example, as shown in Figure 23, the driving voltage V1 of the display data corresponding to the current frame is less than the preset grayscale voltage V0, and the preset grayscale voltage V0 is less than the driving voltage V2 of the display data corresponding to the next frame. Optionally, the preset grayscale voltage V0 is greater than the common voltage (Vcom). The common voltage (Vcom) is the voltage of the common electrode in the display panel 20 side. The driving voltage (S-out) is the voltage supplied to the pixel electrode in the display panel 20 side.

[0194] Taking V2 < V1 as an example, the driving voltage V1 of the display data corresponding to the current frame is greater than the preset grayscale voltage V0, and the preset grayscale voltage V0 is greater than the driving voltage V2 of the display data corresponding to the next frame.

[0195] Here, the preset grayscale voltage V0 is located between V1 and V2, making the difference |V2-V0| between V0 and V2 output by the source driver 102 smaller during the frame wait period, i.e., smaller than the difference |V2-V1| between V2 and V1. This can reduce pixel leakage to a certain extent, thereby making the pixel grayscale brightness maintained for a longer time during the frame wait period. Especially in variable refresh rate modes (such as Freesync mode), since the pixel grayscale brightness is maintained for a longer time during the frame wait period at low refresh rates, the resulting leakage is greater. Therefore, the method provided in this disclosure can effectively reduce pixel leakage.

[0196] This embodiment can control the output driving voltage during the frame waiting period by customizing the preset grayscale voltage. Combined with polarity reversal, it can reduce pixel leakage to a certain extent, thereby making the grayscale brightness of the pixel remain for a longer time during the frame waiting period.

[0197] In some embodiments, the display driving circuit 10 further includes a power supply sub-circuit, which provides power signals to the timing controller 101 and the source driver 102.

[0198] In some embodiments, the display driving circuit 10 further includes a gate driver. The timing controller 101 is also configured to provide a first clock signal to the gate driver to control the gate driver to output a gate control signal to the pixel driving circuit.

[0199] In addition, this disclosure also provides a display device, which includes the display driving circuit 10 of any of the above embodiments. As shown in FIG4, the display device further includes a display panel 20.

[0200] Optionally, the display panel 20 is a liquid crystal display panel. The pixel driving circuit includes a pixel electrode, to which a driving voltage (S-out) is provided to charge the pixel electrode.

[0201] For example, the display device can be any product with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of the display device are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0202] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display driving circuit comprising a timing controller and a plurality of source drivers; the timing controller comprising at least one first output and a plurality of second outputs; one of the first outputs being electrically connected to at least one of the source drivers; The second output end is connected with the source driver one by one; The timing controller is configured to output a first clock signal through the first output end and output a first data signal through the second output end; The source driver is configured to sample the first data signal by using the first clock signal and output the sampled display data.

2. The display drive circuit of claim 1, wherein, The display driving circuit further comprises a phase compensation sub-circuit; The phase compensation sub-circuit is configured to determine a phase offset between the first clock signal and the first data signal according to the received first clock signal and first data signal, and perform phase compensation on the currently received first clock signal or first data signal by using the phase offset.

3. The display drive circuit of claim 2, wherein, The phase compensation sub-circuit is integrated in the source driver, and the source driver further comprises a clock signal receiving sub-circuit, a data signal receiving sub-circuit, a data sampling sub-circuit and a data output sub-circuit; The clock signal receiving sub-circuit is configured to transmit the received first clock signal to the phase compensation sub-circuit; The data signal receiving sub-circuit is configured to transmit the received first data signal to the data sampling sub-circuit and the phase compensation sub-circuit; The phase compensation sub-circuit is configured to calculate a phase offset between the first clock signal and the first data signal, and perform phase compensation on the first clock signal to obtain a second clock signal by using the phase offset; The data sampling sub-circuit is configured to sample the first data signal according to the second clock signal to obtain display data; The data output sub-circuit is configured to output the display data.

4. The display drive circuit of claim 3, wherein, The data sampling sub-circuit is further configured to send a feedback signal to the phase compensation sub-circuit in response to receiving the second clock signal; The phase compensation sub-circuit is further configured to stop receiving the first data signal in response to receiving the feedback signal.

5. The display drive circuit of claim 3, wherein, The phase compensation sub-circuit calculates a phase offset between the first clock signal and the first data signal, specifically comprising: Obtaining an initial sampling point of the first clock signal, and initial position points and terminal position points of the first data signal in the valid level stage; Calculating a first phase step from the initial sampling point to the initial position point; Calculating a second phase step from the initial sampling point to the terminal position point; According to the first phase step and the second phase step, determining a phase offset between the initial sampling point and a valid level center position; the valid level center position is the best sampling position of the first clock signal to the first data signal in the valid level stage.

6. The display drive circuit of claim 1, wherein, The display driving circuit further includes a phase compensation sub-circuit; the phase compensation sub-circuit includes a phase offset detection unit and a phase calibration unit, wherein the phase offset detection unit is integrated in the source driver and the phase calibration unit is integrated in the timing controller; the source driver further includes a clock signal receiving sub-circuit, a data signal receiving sub-circuit, a data sampling sub-circuit, and a data output sub-circuit; the timing controller further includes a clock signal transmitting sub-circuit and a data signal transmitting sub-circuit. The clock signal transmitting sub-circuit is configured to transmit the first clock signal to the clock signal receiving sub-circuit through the first output terminal; The data signal transmitting sub-circuit is configured to transmit a phase calibration signal to the data signal receiving sub-circuit through the second output terminal; And, the received second data signal is sent to the data signal receiving sub-circuit through the second output terminal; The clock signal receiving sub-circuit is configured to transmit the received first clock signal. To the phase offset detection unit; The data signal receiving sub-circuit is configured to transmit the received phase calibration signal to the phase offset detection unit; And, the received second data signal is sent to the data sampling sub-circuit; The phase offset detection unit is configured to calculate the phase offset between the first clock signal and the phase calibration signal, and send the phase offset to the phase calibration unit; The phase calibration unit is configured to perform phase compensation on the first data signal using the phase offset to obtain the second data signal; The second data signal is transmitted to the data signal transmitting sub-circuit; The data sampling sub-circuit is configured to sample the second data signal according to the received first clock signal to obtain display data; The data output sub-circuit is configured to output the display data.

7. The display drive circuit of claim 6, wherein, The phase offset detection unit is further configured to send the received first clock signal to the data sampling sub-circuit; and, in response to receiving a feedback signal, to stop receiving the second data signal; the data sampling sub-circuit is further configured to send a feedback signal to the phase offset detection unit in response to receiving the first clock signal; or... The data sampling sub-circuit is further configured to send a feedback signal to the phase offset detection unit in response to receiving the first clock signal sent by the clock signal receiving sub-circuit; the phase offset detection unit is further configured to stop receiving the second data signal and the first clock signal in response to receiving the feedback signal.

8. The display drive circuit of claim 6, wherein, The phase offset detection unit is specifically configured to acquire the initial sampling point of the first clock signal, and the initial position point and termination position point of the first data signal in the effective level phase. Calculate the third phase step from the initial position point to the initial sampling point; calculate the fourth phase step from the termination position point to the initial sampling point; determine the phase offset between the effective level center position and the initial sampling point based on the third phase step and the fourth phase step; the effective level center position is the optimal sampling position of the first clock signal for the first data signal during the effective level phase.

9. The display drive circuit of claim 6, wherein, The phase calibration signal is the first data signal; or, the first data signal includes a first sub-signal and a second sub-signal; the timing controller transmits the first sub-signal before transmitting the second sub-signal, and the second sub-signal includes a signal representing the display data; the first sub-signal is the phase calibration signal.

10. The display drive circuit of claim 1, wherein, The timing controller includes a clock signal transmitting sub-circuit and a data signal transmitting sub-circuit; The clock signal transmitting sub-circuit is configured to transmit the first clock signal to the source driver through the first output terminal; The data signal transmitting sub-circuit is configured to perform phase compensation on the first data signal using a preset phase offset to obtain a second data signal; and to send the second data signal to the source driver through the second output terminal.

11. The display drive circuit of claim 1, wherein, The timing controller includes a clock signal transmitting sub-circuit, a phase compensation sub-circuit, and a data signal transmitting sub-circuit; The clock signal transmitting sub-circuit is configured to transmit the first clock signal to the source driver through the first output terminal; The phase compensation sub-circuit is configured to determine the phase offset between the first clock signal and the first data signal based on the received first clock signal and the first data signal; and to perform phase compensation on the currently received first data signal using the phase offset to obtain a second data signal. The data signal transmitting sub-circuit is configured to send the received second data signal to the source driver through the second output terminal.

12. The display drive circuit according to any one of claims 1 to 11, wherein The timing controller also includes a third output terminal; The timing controller is also configured to output control command signals to each of the source drivers through the third output terminal; The source driver is further configured to control the output of the display data according to the received target clock signal, target data signal and control command signal; The target clock signal is a first clock signal, and the target data signal is a second data signal; or, the target clock signal is a second clock signal, and the target data signal is a first data signal; or, the target clock signal is the first clock signal, and the target data signal is the first data signal.

13. The display drive circuit of claim 12, wherein, The source driver includes a data sampling sub-circuit and a data processing sub-circuit; The data sampling sub-circuit is configured to sequentially sample the target data signal using the target clock signal; The data processing sub-circuit is configured to, when the sampling result is a first frame control instruction, and in response to the control instruction signal being a second level signal, retrieve the first output strategy information of the display data of each frame; If the sampling result is the first line of control command, in response to the control command signal being a first level signal, the second output strategy information of one line of the displayed data is retrieved. If the sampling result is the displayed data, in response to the control command signal being a second level signal, the display data is output according to the first output strategy information and the second output strategy information.

14. The display drive circuit of claim 13, wherein, The data processing sub-circuit is further configured to, in the event that the sampling result is a second frame control command within the frame waiting period, respond to the control command signal being a first level signal, disable the receiving function of the first data signal and / or the sending function of the display data; the frame waiting period represents an idle period from the output of the display data in the current frame to the output of the display data in the next frame.

15. The display drive circuit of claim 14, wherein, The data processing sub-circuit is further configured to, in response to the control command signal being a first level signal, enable the receiving function of the first data signal and / or the sending function of the display data when the receiving function of the first data signal and / or the sending function of the display data are currently disabled.

16. The display driver circuit of claim 14, wherein, The data processing sub-circuit is further configured to, during the frame waiting period, in response to the control command signal being a first level signal, acquire the sampling result as a second line of control command and a preset grayscale voltage, and adjust the driving voltage of the display data corresponding to the current frame to the preset grayscale voltage and output it, so as to maintain the voltage on the data line during the frame waiting period. The data line is used to electrically connect the source driver and the pixel driving circuit. The preset grayscale voltage has the opposite polarity to the driving voltage.

17. The display driver circuit of claim 16, wherein, The data processing sub-circuit is further configured to continue sampling in response to the control command signal being a second-level signal, if the sampling result is a second-line control command within the frame waiting period, to obtain the preset grayscale voltage.

18. The display driver circuit of claim 16, wherein, The driving voltage of the display data corresponding to the current frame is less than the preset grayscale voltage, and the preset grayscale voltage is less than the driving voltage of the display data corresponding to the next frame; or, the driving voltage of the display data corresponding to the current frame is greater than the preset grayscale voltage, and the preset grayscale voltage is greater than the driving voltage of the display data corresponding to the next frame.

19. The display driver circuit of claim 1, wherein, Both the first clock signal and the first data signal are low-voltage differential signals.

20. A display device comprising a display driving circuit as claimed in any one of claims 1 to 19.

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