Surface oxidation- and band alignment-based iii-nitride semiconductor devices

Abstract

A device includes a substrate and a heterostructure supported by the substrate. The heterostructure includes a III-nitride semiconductor layer and an oxide layer supported by the III-nitride semiconductor layer. The oxide layer includes a Group IIIB element and a Group III metal.

Description

Atty. Docket No. 10110-23009ASURFACE OXIDATION- AND BAND ALIGNMENT-BASED lll-NITRIDE SEMICONDUCTOR DEVICESCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. provisional application entitled “Surface Oxidation- and Band Alignment-Based Ill-Nitride Semiconductor Devices,” filed April 23, 2024, and assigned Serial No. 63 / 637,566, the entire disclosure of which is hereby expressly incorporated by reference.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under Contracts Nos. HR0011- 22-2-002 and HR0011 -22-C-0087 awarded by the U.S. Department of Defense, Defense Advanced Research Projects Agency. The government has certain rights in the invention.BACKGROUND OF THE DISCLOSUREField of the Disclosure

[0003] The disclosure relates generally to Group Ill-nitride materials and heterostructures.Brief Description of Related Technology

[0004] The development of Ill-nitride-based high-electron-mobility transistors (HEMT) devices has spawned a technological revolution in high-power and high-speed electronics. To further enhance the performance and functionality of HEMT devices for next-generation electronics, innovative ideas and device designs have been developed. For example, there is growing interest in integrating Ill-nitrides with other functional materials to unleash the full potential of Ill-nitride semiconductors. For HEMT structures, new functionalities and superior electrical characteristics are expected through this strategy. To date, however, one of the major challenges is the lattice mismatch and manufacturing compatibilities between Ill-nitride and the functional materials, which has constrained the range of possible device designs. In this context, it has been demonstrated that the addition of the rare-earth Sc element into a Ill-nitride wurtzite lattice would endow different lattice parameter rules. With 18%-ScAtty. Docket No. 10110-23009A incorporation, the lattice constant of ScAIN alloys is matched with that of GaN, which can fundamentally reduce undesirable strain, dislocations, and electron scattering at the heterostructure interface. Also, Sco.i8Alo.82N has a large band gap and stronger piezoelectric and spontaneous polarization fields than the conventional AIGaN alloy, which provides better charge carrier confinement, higher breakdown voltages, and high-concentration two- dimensional electron gases (2DEGs). Recent studies have also shown that fully epitaxial wurtzite phase ScAIN films can exhibit ferroelectric properties, with giant tunable remnant polarization and tunable coercive field. Such new, oxide-free nitride ferroelectrics provide great opportunities for Ill-nitride materials, not only unlocking their potential in advanced memory architectures but also providing a new platform to enrich the concept and functionalities of HEMT devices.

[0005] For the design of ScAIN / l I l-nitride heterojunction devices, a detailed understanding of fundamental properties, such as energy band structure, band discontinuities, band alignment, interface / surface quality, stability, dislocation, disorder, and impurity incorporation, is useful. Among them, the band alignment, including valence and conduction band discontinuities, is a factor that determines the 2DEG density and charge carrier transport behavior of the device. Among previously reported methods, X-ray photoelectron spectroscopy (XPS) is one of the most common techniques to determine the valence band offset (VBO) of a heterojunction. As the typical sampling depth of XPS is about 10 nm, the measurement results are easily affected by the surface status of materials. Due to the large oxygen affinity of the Sc element, there is an unavoidable oxidation process at the ScAIN surface when it is exposed to air, which is much faster and more complicated than conventional Ill-nitrides. This spontaneous oxide layer formation can significantly impact device performance and the characterization of intrinsic material parameters, such as the accuracy of ScAIN XPS results and the final calculation of the valence band offset. However, to date, no detailed systematic investigation into the evolution of the surface chemical status of ScAIN and its influence on band alignment measurement of ScAIN / l I l-nitride heterostructures has been performed.SUMMARY OF THE DISCLOSURE

[0006] In accordance with one aspect of the disclosure, a device includes a substrate and a heterostructure supported by the substrate, the heterostructure including a Ill-nitride semiconductor layer and an oxide layer supported by the Ill-nitride semiconductor layer. The oxide layer includes a Group 11 IB element and a Group III metal.Atty. Docket No. 10110-23009A

[0007] In accordance with another aspect of the disclosure, a method of fabricating a device includes providing a substrate, growing a Ill-nitride alloy layer supported by the substrate, the Ill-nitride alloy being doped with a Group 11 IB element, and forming an oxide layer on an exposed surface of the Ill-nitride alloy layer via exposure of the exposed surface of the Ill-nitride alloy layer to oxygen. The oxide layer includes a native oxide of the Ill- nitride alloy layer.

[0008] In accordance with yet another aspect of the disclosure, a device includes a substrate and a heterostructure supported by the substrate. The heterostructure includes an n-type Ill-nitride semiconductor layer, a p-type Ill-nitride semiconductor layer spaced from the n-type Ill-nitride semiconductor layer, and an active region disposed between the n-type Ill-nitride semiconductor layer and the p-type Ill-nitride semiconductor layer, and an electronblocking layer disposed between the p-type Ill-nitride semiconductor layer and the active region. The electron-blocking layer includes a Ill-nitride alloy. The Ill-nitride alloy includes a Group 11 IB element. The Ill-nitride alloy is disposed within the heterostructure such that a type-11 energy band alignment arrangement is established.

[0009] In connection with any one of the aforementioned aspects, the devices and / or methods described herein may alternatively or additionally include or involve any combination of one or more of the following aspects or features. The oxide layer is in contact with the Ill-nitride semiconductor layer. The oxide layer is patterned relative to the Ill-nitride semiconductor layer. The oxide layer completely coats an outer surface of the Ill- nitride semiconductor layer. The heterostructure further includes a Ill-nitride alloy layer disposed between the Ill-nitride semiconductor layer and the oxide layer. The Ill-nitride alloy layer includes the Group 11 IB element. The Ill-nitride alloy layer is monocrystalline, wurtzite phase, and ferroelectric. The Ill-nitride alloy layer and the Ill-nitride semiconductor layer are lattice matched. The Ill-nitride alloy layer and the Ill-nitride semiconductor layer are in contact with one another. The Ill-nitride semiconductor layer includes GaN. The oxide layer includes ScAIOx. The device further includes a metal layer supported by the oxide layer such that the oxide layer is positioned in the heterostructure as a gate dielectric layer. The device further includes a metal layer supported by the oxide layer, wherein the Ill-nitride semiconductor layer is doped with a Group 11 IB element. The substrate includes a metal such that the oxide layer and the Ill-nitride semiconductor layer are disposed between the metal layer and the metal of the substrate in a stacked arrangement. Forming the oxide layer is controllably implemented for a predetermined period of time. Forming the oxide layer partially consumes the Ill-nitride alloy layer. Forming the oxide layer completely consumes the Ill-nitride alloy layer. The method further includes depositing a metal layerAtty. Docket No. 10110-23009A such that the metal layer is supported by the Ill-nitride alloy layer. Forming the oxide layer is implemented after depositing the metal layer such that the oxide layer is patterned in accordance with a layout of the metal layer to define an active area of the device. Forming the oxide layer is implemented before depositing the metal layer. The method further includes patterning the oxide layer and the metal layer into a gate oxide and a gate, respectively. The method further includes growing a Ill-nitride semiconductor layer supported by the substrate before growing the Ill-nitride alloy layer such that the Ill-nitride semiconductor layer is disposed between the Ill-nitride alloy layer and the substrate. The optoelectronic device further includes an intrinsic Ill-nitride semiconductor layer disposed between the p-type Ill-nitride semiconductor layer and the active region. The intrinsic Ill- nitride semiconductor layer is in contact with the electron-blocking layer to establish the type- 11 energy band alignment arrangement. The intrinsic Ill-nitride semiconductor layer includes GaN. The electron-blocking layer includes ScAIN. The intrinsic Ill-nitride semiconductor layer and the electron-blocking layer are lattice-matched.BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0010] For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawing figures, in which like reference numerals identify like elements in the figures.

[0011] Figure 1 depicts (a) a schematic illustration of the surface oxidation process of a ScAIN film, high-resolution graphical plots of (b) Sc 2p & N 1 s, (c) Al 2p, (d) O 1 s XPS spectra, and (e) valance band (VB) spectra of fresh and 24h air-oxidated ScAIN films, as well as (f) a STEM image and EDS elemental mapping images of a ScAIN surface after 24 h oxidation.

[0012] Figure 2 depicts (a) schematic views of an MBE-grown 100 nm GaN film (sample A), a 5 nm Sco.i8Alo.82N / I OO nm GaN film (sample B) and a 100 nm ScAIN / 100 nm GaN film (sample C) on GaN / sapphire templates, (b) RHEED patterns of the three samples captured along the <1 120> and <1 00> azimuths at the end of growth, and (c) a graphical plot of (0002) plane XRD 20-co line scans of the three samples and the GaN template.

[0013] Figure 3 depicts (a) a cross-sectional atomic-resolved HAADF-STEM image of an example Sco.i8Alo.82N / GaN hetero interface, as well as (b, c) nanobeam electron diffraction patterns acquired along the [1 OO] zone-axis for (b) GaN and (c) Sco.i8Alo.82N.

[0014] Figure 4 depicts graphical plots of (a) core level and valence band XPS results of the three samples shown in Figure 2, and (b) the energy band alignment diagram of theAtty. Docket No. 10110-23009ASco.i8Alo.82N / GaN heterostructure, as well as (c) schematic views of HEMT structures using Sco.i8Alo.82N (left) and AIGaN (right) as the barrier layer, and (d) a graphical plot of the band structure and 2DEG distribution near the interface of an example Sco.i8Alo.82N / GaN and Alo.sGaoj / GaN heterostructure.

[0015] Figure 5 depicts a cross-sectional, schematic view of a metal-oxide-semiconductor (MOS) structure having a ScAIOxoxide layer in accordance with one example.

[0016] Figure 6 depicts a cross-sectional, schematic view of a metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) device having a ScAIOx gate oxide layer in accordance with one example.

[0017] Figure 7 depicts a cross-sectional, schematic view of a memory device having a ScAIOx oxide layer in accordance with one example.

[0018] Figure 8 depicts a cross-sectional, schematic view of a catalytic device having a heterostructure with a ScAIOx oxide layer in accordance with one example.

[0019] Figure 9 depicts a method of device fabrication in which in-situ metal deposition within an MBE chamber prevents oxide layer formation in a working zone or active area of a ScAIN-based device in accordance with one example.

[0020] Figure 10 is a flow diagram of a method of fabricating a heterostructure having a native ScAIOx layer in accordance with one example.

[0021] Figure 1 1 A depicts a cross-sectional, schematic view of an optoelectronic device with an AIGaN electron-blocking layer (EBL).

[0022] Figure 1 1 B depicts a cross-sectional, schematic view of an optoelectronic device with with a single-crystal, or monocrystalline, layer of an alloy of a Ill-nitride material as an electron-blocking layer (EBL) in accordance with one example.

[0023] The embodiments of the disclosed devices and methods may assume various forms. Specific embodiments are illustrated in the drawing and hereafter described with the understanding that the disclosure is intended to be illustrative. The disclosure is not intended to limit the invention to the specific embodiments described and illustrated herein.DETAILED DESCRIPTION OF THE DISCLOSURE

[0024] Described herein are applications of the findings of a detailed investigation into the surface chemical status (e.g., surface oxidation and band alignment) of rare earth (or Group 111 B-doped) Ill-nitride alloys (collectively referred to herein at times as "Ill-nitride alloys"),Atty. Docket No. 10110-23009A such as ScAIN. The applications include a number of heterostructures and devices that incorporate a layer of the Ill-nitride alloy (e.g., ScAIN), both with and without native oxides of such Ill-nitride alloys. In some cases, the Ill-nitride alloy layer is ferroelectric. Methods for fabricating such heterostructures and devices, in which the native oxide is intentionally and controllably formed, are also described.

[0025] The evolution of the surface chemical status of rare earth (or Group 11 IB-doped) Ill- nitride alloys such as ScAIN was investigated. The results of the investigation demonstrated that the surface chemical status has a significant impact on material characterization and electronic structure evaluation. Detailed XPS measurements showed that the spontaneous oxidation process of ScAIN, when exposed to air, is much faster and more complicated compared to conventional Ill-nitride materials, which has a significant impact on the accuracy of the band alignment calculation. By excluding the possible impact from the surface oxide layer, it was determined that a Sco.i8Alo.82N / GaN heterostructure has a type-ll energy band alignment, with a valence band offset (VBO) of 0.2 eV and conduction band offset (CBO) of 2.3 eV. The investigation also shows that a detailed and systematic understanding of the evolution of the surface chemical status of rare earth-ill nitride materials is useful for further material characterization and device applications. For instance, utilizing band offset data, simulations were conducted to compare the 2DEG density and the band structures of Sco.i8Alo.82N / GaN and AIGaN / GaN heterojunctions. As described herein, the useful ferroelectric property of Sco.i8Alo.82N combined with the excellent electric characteristics of the Sco.i8Alo.82N / GaN heterostructure may be applied to realize a number of devices, including multi-functional, high efficiency, high power, and high frequency HEMT devices.

[0026] Described herein are example devices and methods that apply the properties of Ill- nitride alloys, such as ScAIN, including the ability to seamlessly integrate such Ill-nitride alloys with Ill-nitride semiconductors, such as GaN. For instance, the surface properties and band alignment of ScAIN / l I l-nitride heterostructures were investigated via high-resolution X- ray photoelectron spectroscopy measurements, which revealed the existence of a considerable oxidation layer on ScAIN when it is exposed to air. The oxidation layer has a significant impact on the material characterization and electronic structure evaluation. By excluding the possible impact from the surface oxide layer, the band alignment of Sco.i8Alo.82N / GaN was correctly determined. The investigation also included simulation results that establish that the Sco.i8Alo.82N barrier layer may be useful in connection with charge carrier confinement and a high density of two-dimensional electron gas (2DEG) at the heterostructure interface, which, in turn, is useful for GaN-based high electron mobilityAtty. Docket No. 10110-23009A transistor (HEMT) devices with enhanced performance. The investigation both identifies the band alignment between Sco.i8Alo.82N and GaN for various ScAIN / l I l-nitride device applications and highlights the utility of the prevalent surface oxidation in various devices (e.g., devices within the ferroelectric nitride family).

[0027] Although described in connection with examples of epitaxially grown ScxAli.xN layers, the disclosed methods and devices may be applied to a wide variety of Ill-nitride alloys. The disclosed methods and devices may thus include or involve the incorporation of scandium into other Ill-nitride wurtzite structures. For instance, the disclosed methods and devices may include or involve one or more epitaxially grown ScxAlyGai-x.yN layers, ScxGai-XN layers, or Scxlni.xN layers. The configuration, construction, fabrication, and other characteristics of the heterostructures may also vary from the examples described. For instance, the heterostructures may include any number of epitaxially grown layers of ferroelectric and non-ferroelectric nature. The disclosed methods and devices are not limited to Ill-nitride alloys including scandium. For instance, the Ill-nitride alloys may include additional group I IIB elements, such as yttrium (Y) and lanthanum (La).

[0028] Although the disclosed methods are described in connection with MBE growth procedures, additional or alternative non-sputtered epitaxial growth procedures may be used. For instance, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), and atomic layer epitaxy (ALE) growth procedures may be used. Still other procedures may be used, including, for instance, pulsed laser deposition procedures.

[0029] A number of sample heterostructures are described below in connection with Figures 1-4. The samples were grown on GaN / sapphire templates by a Veeco GENxplor MBE system equipped with a radio frequency (RF) plasma source for supplying active nitrogen (N*, purity 7N), dual filaments SUMO cells for providing gallium (Ga, purity 7N) and aluminum (Al, purity 6N5), and a high-temperature Knudsen effusion cell for providing scandium (Sc, purity 5N), respectively. GaN and ScAIN layers were grown at a substrate temperature of 700 °C, which was monitored by a thermocouple located at the backside of the substrate. A nitrogen flow of 0.3 seem (standard cubic centimeters per minute) with a forward power of 350 W was used for all the growth experiments. The corresponding growth rate for GaN under slightly metal-rich conditions was 200 nm / h. The ScAIN layers were grown under N-rich conditions with a lll / V ratio of 0.85. The Sc and Al flux was carefully controlled to achieve a Sc content of 0.18. The growth rate for the ScAIN films was approximately 3 nm / min. The epitaxy process was monitored using an in situ reflection highAtty. Docket No. 10110-23009A energy electron diffraction (RHEED) system. The X-ray diffraction (XRD) was characterized by using a Rigaku SmartLab diffractometer with a Cu Karadiation x-ray source (1 .5406 A). STEM specimens were prepared by a Thermo Fisher Scientific Helios G4 UXe focus ion beam (FIB). HAADF-STEM and ABF-STEM images were collected using a Cs corrected JEOL 3100R05 microscope operated at 300 kV, with a convergence angle of 22 mrad. The collection ranges for HAADF and ABF were 59-200 mrad and 11-22 mrad, respectively. Elemental distribution analyses were performed utilizing a Thermo Fisher Scientific Talos F200X S / TEM equipped with a Super-X EDS detector operated at 200 kV. The HR-XPS was performed using a Kratos Axis Ultra XPS system with a monochromatic Al Ka source (hv = 1486.6 eV). The C1s peak (284.8 eV) was used as the reference to calibrate the values of all HR-XPS results.

[0030] One or more parameters of the fabrication process may vary in connection with the fabrication of other example devices. Further details on the epitaxial growth conditions, procedures, and related parameters that may be used to form the ferroelectric films and heterostructures described herein are set forth in WO 2023 / 022768 ("Epitaxial Nitride Ferroelectronics"), International Application No. PCT / US23 / 13727 ("Epitaxial Nitride Ferroelectronic Devices" filed February 23, 2023), P. Wang, et al., "Fully epitaxial ferroelectric ScAIN grown by molecular beam epitaxy," Applied Physics Letters, vol. 118, p. 223504 (2021), D. Wang et al., "An Epitaxial Ferroelectric ScAIN / GaN Heterostructure Memory," Advanced Electronic Materials, p. 2200005 (2022), and D. Wang, et al., "Fully epitaxial ferroelectric ScGaN grown on GaN by molecular beam epitaxy," Appl Phys Lett 119 (11), 111902 (2021), the entire disclosures of which are hereby incorporated by reference.

[0031] The addition of Sc atoms endows Ill-nitride wide / ultra-wide bandgap semiconductors with distinct ferroelectric functionality, e.g., high Curie temperature, tunable coercive field, large remnant polarization, and linear displacement, that was not possible by conventional oxide ferroelectrics. These unique properties, together with its compatibility with the Ill-nitride and mainstream semiconductor technologies, have made ScAIN one of the most promising materials for a wide range of device applications. However, the embedded Sc atoms may also induce unstable surface status in nitride materials. Due to the large oxygen affinity of both Sc and Al elements, a surface oxidation process is expected for ScAIN films, schematically illustrated in Figure 1 , part (a).

[0032] Because XPS is a surface-sensitive technique, it is useful to verify the surface properties of the example Sco.i8Alo.82N film and confirm whether the oxidation process and oxide layer affect the accuracy of the ScAIN XPS test results and the final calculation of the valence band offset. To minimize the influence of surface oxidation, the 100-nm-thick ScAINAtty. Docket No. 10110-23009A samples were sealed in vacuum immediately after removal from the MBE load-lock chamber (referred to herein as fresh samples). Another set of ScAIN samples were intentionally exposed to air for 24 h. Subsequently, both groups of samples were transferred to the XPS chamber for characterization.

[0033] Figure 1 , parts (b)-(e), show the high-resolution Sc 2p & N 1 s, Al 2p, O 1 s, and valance band XPS spectra of the fresh ScAIN and 24 hour-oxidized ScAIN samples. Shown in Figure 1 , part (b), for the fresh sample, there are clear N 1 s peak and Sc 2p peaks present. However, for the sample exposed to air for 24 hours, the intensity of the N 1 s peak decreased dramatically, which directly corroborates the reduction of Al-N and Sc-N bonds at the ScAIN surface. At the same time, the Sc 2p peaks shifted to a higher binding energy, which implies a transition from the Sc-N bond to the Sc-0 bond. Al 2p XPS spectra were measured to determine the evolution of the Al coordination after 24 hours of exposure to air. For the fresh sample, the spectra were deconvoluted using two peaks. The main peak located at 72.7 eV corresponds to Al-N. For the fresh samples, there is still an AI-0 peak at 73.7 eV, indicating the inevitable generation of an ultra-thin native oxide layer during the sample preparation / transfer process. When exposed to air for 24 hours, accompanied with the decrease of the peak intensity of the Al-N and Al-Oxbonds, two new high binding energy peaks appear, which are assigned to the AI-OH / -OOH species. The Al 2p XPS spectra of an AIN film were also measured, but such peaks were not observed, which indicates that the incorporation of Sc atoms in the Ill-nitride lattice has a significant impact on the surface oxidation. Those results are also consistent with the O 1 s XPS spectra, in that, after 24 hours of oxidation, high absorption O 1 s peaks appear, which is likely due to the -OH / - OOH / H2O species.

[0034] Figure 1 , part (e), depicts the evolution of the valence band after 24 hours of oxidation. The valence band maxima (VBM) energy of two samples were determined by linearly extrapolating the edge of the valence band to the spectral baseline. The VBM of the fresh ScAIN film was found to be 1 .7 eV above the Fermi level. Interestingly, for the 24 hour- oxidized ScAIN film, there are two edges existing in the valence band region. From the linear extrapolation of the two edges, two VBM values were obtained. The 1 .7 eV edge is consistent with the fresh ScAIN film, and there is another edge at about 6 eV with respect to the Fermi level. According to previous reports, for one heterostructure, if the top layer is thin and the energy band discontinuities between two layers are large enough, the VBM spectra could collect the contributions from both layers and both valence-band edges are visible in the spectra. The difference between the Fermi level and VBM for unintentionally doped Sco.i8Alo.82N is unlikely to exceed its bandgap (about 5.5 eV), suggesting the edge of 6 eV isAtty. Docket No. 10110-23009A not related to ScAIN species. Combining the Al oxide density of states (DOS) results with the evidence of the existence of an oxide layer on top of the ScAIN film, the high energy edge is attributed to the VBM signal from the oxide layer. It follows that there is an evolution of the surface chemical status of ScAIN when exposed to air for an extended period.

[0035] To further confirm the existence of a surface oxide layer, scanning transmission electron microscopy (STEM) and corresponding energy-dispersive spectroscopy (EDS) mapping analysis were applied to discern the detailed element distribution at the sample surface. The EDS mapping results shown in Figure 1 , part (f), display the elemental distribution of Al, Sc, O, and N across the film surface. It can be clearly seen that the O element signals are significantly enriched on the sample surface, confirming the existence of a surface oxide layer. These studies clearly show that the oxidation process of ScAIN materials is much faster and more complicated than conventional Ill-nitrides, due to the influence of Sc incorporation.

[0036] Based on the above analysis, to further determine the band alignment of the Sco.i8Alo.82N / GaN heterostructure, all the samples were kept in vacuum before the XPS measurement, to minimize the impact of surface oxide layer formation. Direct measurement of the valence band discontinuity for the Sco.i8Alo.82N / GaN heterojunction interfaces is difficult. Thus, to determine the band alignment of Sco.i8Alo.82N / GaN heterostructure, three separate samples were designed, which were thick films of GaN and Sco.i8Alo.82N film for collection of the valence band maximum (VBM) and core level energy, and a thin Sco.i8Alo.82N layer grown on GaN for collection of the core level energy from each segment of the heterostructure. Figure 2, part (a), depicts schematic views of the three samples (labeled A, B, C). Because the escape depth of photoemitted electrons is about 5-10 nm in the XPS measurement, for sample B, approximately 5 nm thick Sco.i8Alo.82N layer was grown on GaN to make sure the photoemission signals from both Sco.i8Alo.82N and GaN layers could be collected simultaneously. To further collect the XPS signals of bulk Sco.i8Alo.82N, the Sco.i8Alo.82N layer is sufficiently thick to eliminate the influence of the GaN layer. Thus, sample C has a thick ScAIN layer (100 nm) grown on GaN.

[0037] Figure 2, part (b), shows the RHEED patterns captured along the <1120> and <1 100> azimuths at the end of growth. Narrow and streaky patterns with clear Kikuchi lines were observed for all three samples, indicating the epitaxially grown GaN and ScAIN films have a single-crystalline wurtzite structure with an atomically smooth surface. The X-ray diffraction (XRD) 20 / w scans are presented in Figure 2, part (c). The characteristic diffraction peak for wurtzite ScAIN was observed at 35.9°, while this peak is almost unobservable forAtty. Docket No. 10110-23009A sample B due to the ultrathin thickness. The broad peak observed at 35.5° in Sample A is consistent with the bump seen at the same angle in the GaN template (gray curve), indicating that it likely originated from the underlying GaN template. This broad peak could be attributed to the thin AIN buffer layer that was used to improve the crystal quality of the GaN templates.

[0038] For practical device applications, the heterostructure design is often constrained by the critical thickness of each epilayer, which is directly related to the lattice mismatch at the heterointerface. In this context, atomic-resolved HAADF-STEM measurements around the interface region were performed to further elucidate the quality of the Sco.i8Alo.82N / GaN hetero interface. The cross-sectional image in Figure 3, part (a), shows a clean and atomically sharp interface between the Sco.i8Alo.82N and the GaN layer, with a well-aligned wurtzite phase atomic stacking sequence. In HAADF-STEM images, brightness is the characteristic of atomic number. According to the large Z-contrast differences, the brighter dots shown in Figure 3, part (a), correspond to the heavier atoms. Therefore, the brighter upper segment is identified as Sco.i8Alo.82N.

[0039] Parts (b) and (c) of Figure 3 illustrate the nanobeam electron diffraction (NBED) patterns collected from the GaN and Sco.i8Alo.82N segments, respectively, both of which are consistent with the features of a single-phase wurtzite crystal structure. Shown in Figure 3, the ratio of reciprocal lattice spacing between the (1120) and (0002) plane spot remains the same for the Sco.i8Alo.82N and GaN layers, confirming that the incorporation of Sc atoms did not introduce rock salt Sc-N species or any other intermetallic phases and the in-plane lattice for ScAIN and GaN are well-matched. Therefore, the Sco.i8Alo.82N / GaN hetero interface is free of compressive or tensile strain.

[0040] To gain a fundamental understanding of the energy band structure of the Sco.i8Alo.82N / GaN heterostructure, high-resolution XPS spectra were taken separately from the three samples described above. From the theory derived by Kraut et al., the valence band offset (AEV) at the Sco.i8Alo.82N / GaN heterostructure interface can be calculated from the following formula:A C / cScAIN cScAINx / cGaN HSaN x / cScAIN / GaN cScAIN / GaNx ZAtv= (tAI2p 'fcVBM ) ' (^Ga3d ’ tVBMt+ttGaSd ’fcAI2p )

[0041] The XPS core levels of the Al 2p and Ga 3d signals were adopted for evaluation. E^Nand EVBMNdenote the Al 2p and VBM position of the thick Sco.i8Alo.82N sample, whileGa3dand EVBM represent the Ga 3d core level energy and VBM position of the thick GaNAtty. Docket No. 10110-23009A film. £A(2^N / GaN-£Ga3dN / GaNrepresents the energy separation between the Al 2p and Ga 3d from Sco.i8Alo.82N / GaN heterostructure.

[0042] As shown in Figure 4, part (a), the Al 2p spectra acquired from the Sco.i8Alo.82N sample exhibited a main peak located at 72.7 eV, which corresponds to Al-N, while the AI-0 peak at 73.7 eV is attributed to the inevitable generation of an ultra-thin native oxide layer during the sample preparation / transfer process. The VBM of Sco.i8Alo.82N was extracted to be around 1 .7 eV. As a result, regarding the thick Sco.i8Alo.82N layer, the binding energy difference between Al 2p and the VBM is calculated to be 71 .0 eV. In the case of the GaN sample, the Ga 3d spectrum was deconvoluted into three peaks to accurately determine the binding energy position. The main peak at 19.2 eV was assigned to Ga-N, while the 16.4 eV and 20.1 eV peaks were denoted as N 2s and Ga 3d spectra of Ga-O, respectively. The VBM of the GaN sample is extracted to be around 1 .9 eV. Thus, the difference between the binding energy of the primary Ga-N peak 3d and the VBM is determined to be 17.3 eV, which is the second term in the foregoing equation. Lastly, for the Sco.i8Alo.82N / GaN heterostructure, considering the oxidation process during sample transfer, the Al 2p peak was deconvoluted into two peaks as Al-N and Al-O, respectively. As the GaN layer is situated underneath and is not affected by the sample transfer process, the Ga 3d CL spectrum was deconvoluted as Ga-N and N 2s peak. The binding energy of the Al-N 2p peak is found to be 73 eV and the deconvoluted Ga 3d CL spectra revealed that the Ga-N peak is located at 19.5 eV. Those two peaks shifted to a higher binding energy compared to the bulk films, mainly due to the shift of binding energy at the heterostructure interface. Therefore, the energy separation between the Al 2p and Ga 3d is calculated to be 53.5 eV, which is the last term in the foregoing equation. Therefore, the valence band offset of Sco.i8Alo.82N / GaN heterostructure can be obtained by the equation, which is calculated to be 0.2 eV.

[0043] To date, the bandgap values for ScAIN have been reported for samples grown by different approaches, including sputtering deposition and MBE. Due to the variations of Sc content, crystal quality, impurity density, as well as residual strain, there is a variation in the reported values across different works. However, the most recent experimental reports are consistent with the theoretical calculated bandgap. To ensure the comparability of the present measured results, the bandgap value measured from ScAIN samples grown by MBE was used. By substituting the energy bandgaps of the Sco.i8Alo.82N (Eg= 5.5 eV), GaN (Eg= 3.4 eV), and the valence band offset (AEV) in the equation below, the resultant conductionAtty. Docket No. 10110-23009A band offset (AEC) was calculated to be 2.3 eV.

[0044] Therefore, the band alignment diagram of the Sco.i8Alo.82N / GaN heterostructure can be constructed, which is depicted in Figure 4, part (b). Because the band gap of GaN is smaller than that of Sco.i8Alo.82N, a type-ll heterostructure is formed, with the valence and conduction band offsets being 0.2 eV and 2.3 eV, respectively. This result is close to a previous report. Such a unique type-ll alignment is favorable for electrons and holes to separate to opposite sides of the heterointerface, which can be exploited for various applications, such as photodetectors, solar cells, and solar water splitting devices, examples of which are described and shown in connection with Figures 5-8. Interestingly, for optoelectronic applications, as a result of the unique large conduction band offset (2.3 eV), small valence band offset (0.2 eV), and lattice matched features of the Sco.i8Alo.82N / GaN heterostructure, such a heterojunction may be designed as a quantum barrier or electron blocking layer in Ill-nitride light emitters by confining the electrons in the active region, blocking the overflowed electrons and facilitating hole injection. An example of a Ill-nitride light emitter is described and shown in connection with Figure 11 B.

[0045] Sco.i8Alo.82N may also be employed as a barrier layer in GaN-based electronics. Previous studies have shown that the power density and total power availabilities of GaN- based HEMT devices are superior to those of traditional transistors (for example, Si, GaAs, or oxide-based). However, when GaN integrates with other Ill-nitride alloys, due to the severe lattice-mismatch between each epi-layer, the total device thickness is limited and undesirable strain and high dislocation densities are induced, which hinder further improvement of the device performance. By replacing the AIGaN barrier layer with a lattice- matched ScAIN layer, these issues can be largely addressed and the device performance of GaN-based HEMT devices can be brought to a new level. The Sco.i8Alo.82N / GaN heterojunction can possibly offer the largest CBO in the HEMT device context, high- concentration polarization-doped 2DEGs at the interface, and high breakdown voltage, compared with devices having a conventional AIGaN / GaN heterojunction.

[0046] Figure 4, part (c), schematically illustrates an example ScAIN / GaN HEMT device 400, as well as a conventional AIGaN / GaN-based HEMT device 402. A GaN cap layer 404 of each device 400, 402 is set as 5 nm and the thickness of a barrier layer 406 is chosen to be 30 nm. An unintentionally doped GaN layer 408 is set as 200 nm. For practical applications, the thickness of the barrier layer 406 is considered. Because of the lattice mismatch between AIGaN and GaN, the composition of Al in AIGaN is typically limited toAtty. Docket No. 10110-23009A30%. With the lattice-matched feature between Sco.i8Alo.82N and GaN, the composition of Sc in the ScAIN barrier layer may be 18%, or further tuned over a wide range. The calculation was performed by using the self-consistent coupled Schrodinger and the Poisson formulas in a commercially available software SILVACO. The band structures and corresponding 2DEG concentrations of each device are shown in Figure 4, part (d). Noticeably, the 2DEG concentration of the Sco.i8Alo.82N / GaN heterostructure 400 is much higher than the conventional Alo.3Gao.7N / GaN structure 402, indicating an approximately 358% increase in the sheet carrier concentration. Compared with previously predicted type I band alignment for the ScAIN / GaN heterostructure, this type-ll band profile configuration suggests a potentially higher energy barrier for electrons, providing better quantum confinement and reducing the penetration of wavefunction in the barriers, which, in turn, lowers the effect of alloy disorder and impurity in the barriers and favors high electron mobility.

[0047] The above-described samples establish that surface oxidation is pertinent to material characterization and device applications in the ferroelectric nitride family. Surface oxidation, which is inevitable when ScAIN is exposed to air, has a significant impact on the surface structural, chemical, and electronic properties of ScAIN. By minimizing the surface oxidation effect, the VBO and CBO between Sco.i8Alo.82N and GaN have been determined to be 0.2 eV and 2.3 eV, respectively, establishing a type-ll band alignment. The strain-free, lattice-matched, and atomically sharp heterointerface of the Sco.i8Alo.82N / GaN heterostructure grown by MBE are further verified through detailed structural characterization. The better carrier confinement and attractive high-density 2DEG, as well as the spontaneous polarization of a ScAIN barrier layer in ScAIN / GaN heterojunctions, can be controllably varied by applying an external electric field, allowing more freedom for tuning the polarization difference between each segment and corresponding carrier concentration at the interface, thereby improving the performance and functionality of HEMT and other devices. Moreover, ScAIN and other Group 11 IB-doped Ill-nitride materials are to date the only non-oxide materials that demonstrate ferroelectricity. The integration of 2DEGs with ferroelectricity may be used to provide novel device architectures with useful functionalities and excellent device performance. Via MBE, ultrathin (e.g., down to a single monolayer) nitride ferroelectric heterostructures may be provided, e.g., in high-density memory and computing architectures with diverse merged logic-memory functionalities to overcome the memory-logic interconnect bottleneck in the von Neumann architecture.

[0048] Described above are examples of heterostructures having high-quality, wurtzite phase, ferroelectric ScAIN grown via plasma-assisted MBE. The heterostructures may beAtty. Docket No. 10110-23009A incorporated into a variety of devices. Examples of devices having such heterostructures are described below and shown in connection with Figures 5-8.

[0049] Some of the devices may utilize the above-described oxidation of ScAIN as a way to provide controllable growth of a high-quality dielectric layer in connection with Ill-nitride- based heterostructures. Controllable growth of a high-quality dielectric layer on Ill-nitride materials has remained a significant challenge, hindering the development of Ill-nitride- based devices, particularly regarding stability and reliability. Instead of conventional external deposition, an intrinsic passivation layer derived from a Ill-nitride material is useful for establishing a clean passivation / lll-nitride interface. Nonetheless, procuring a high-quality self-oxidation layer on the Ill-nitride surface is difficult using conventional thermal treatments due to the intrinsically chemically inert nature of the material. As described herein, incorporating the Group 111 B element scandium into the Ill-nitride wurtzite lattice not only bestows the material with distinct ferroelectric properties but also significantly influences surface oxidation behavior, enabling the formation of a high-quality ScAIOxdielectric oxide layer under mild conditions. The broad bandgap, along with the chemical and thermal inertness, of the ScAIOx layer, renders it well-suited for dielectric layer applications in Ill- nitride-based devices, including, for instance, MOSHEMT devices, MOS structures, ScAIN memory devices, and photocatalytic devices for, e.g., artificial photosynthesis.

[0050] Figure 5 depicts a device 500 having a heterostructure with an oxide layer 502 in accordance with one example. In this case, the device 500 is configured as, or otherwise includes, a MOS structure. The oxide layer 502 includes a Group 11 IB element, such as Sc, and a Group III metal, such as Al. The oxide layer 502 may be a native oxide of a Ill-nitride alloy, such as ScAIN, and be formed as described herein. For instance, the oxide layer 502 be formed via consumption (e.g., complete consumption) of a sacrificial Ill-nitride alloy layer.

[0051] The oxide layer 502 may be formed via self-oxidation in the ambient atmosphere. Alternative or additional processes may be used to form the oxide layer 502, including, for instance, oxygen plasma treatment and / or wet / dry oxidation processes, such as annealing in an oxygen or moisture containing environment.

[0052] The heterostructure includes a Ill-nitride semiconductor layer 504 and a metal layer 506. As shown in Figure 5, the oxide layer 502 is disposed between the Ill-nitride semiconductor layer 504 and the metal layer 506. In the example of Figure 5, the Ill-nitride semiconductor layer 504 is composed of, or otherwise includes, GaN. Alternative or additional Ill-nitride semiconductors may be used, including, for instance, AIGaN.Atty. Docket No. 10110-23009A

[0053] In the example of Figure 5, the oxide layer 502 is in contact with the Ill-nitride semiconductor layer 504. In other cases, the heterostructure may include an intervening layer. For instance, the intervening layer may be composed of, or otherwise include, the Ill- nitride alloy from which the oxide layer 502 is formed. Alternative or additional layers may be used, including, for instance, a further Ill-nitride layer acting as, e.g., a template layer.

[0054] The oxide layer 502 may or may not be patterned relative to the Ill-nitride semiconductor layer 504. The common layout of the two layers 502, 504 shown in Figure 5 is schematically shown for ease in illustration only.

[0055] The oxide layer 502 may be composed, or otherwise include, ScAIOx. Alternative or additional oxide materials may be used, including, for instance, oxides including an alternative Group 11 IB element. In some cases, the oxide layer 502 may include nitrogen remaining from the oxidation of the sacrificial Ill-nitride alloy layer. For instance, the oxide layer 502 may be configured as, or otherwise include, an oxynitride portion, aspect, or feature. In other cases, some or all of the nitrogen is displaced during the oxidation process.

[0056] Figure 6 depicts a transistor device 600 having a heterostructure with an oxide layer 602 in accordance with one example. The transistor device 600 may be configured as a HEMT device (e.g., a MOSHEMT device) with gate, source, and drain electrodes as shown. In this case, the oxide layer 602 is configured as a gate oxide layer. As described herein, the oxide layer 602 includes a Group 111 B element, such as Sc, and a Group III metal, such as Al. The oxide layer 602 may be a native oxide of a Ill-nitride alloy, such as ScAIN, and be formed as described herein. For instance, the oxide layer 602 be formed via consumption (e.g., complete consumption) of a sacrificial Ill-nitride alloy layer.

[0057] As shown in Figure 6, the transistor device 600 includes a Ill-nitride alloy layer 604 disposed between the oxide layer 602 and a channel layer 606. The Ill-nitride alloy layer 604 may be configured as a barrier layer. The Ill-nitride alloy layer 604 may be composed of, or otherwise include, ScAIN. Alternative or additional Ill-nitride alloys may be used. The Ill-nitride layer 604 may or may not be ferroelectric.

[0058] Figure 7 depicts a memory device 700 having a heterostructure with an oxide layer 702 in accordance with one example. In this case, the oxide layer 702 is disposed between a top electrode 704 and a Ill-nitride alloy layer 706. As described herein, the oxide layer 702 includes a Group 11 IB element, such as Sc, and a Group III metal, such as Al. The oxide layer 702 may be a native oxide of the Ill-nitride alloy (e.g., ScAIN), of the Ill-nitride alloy layer 706. For instance, the oxide layer 702 be formed via consumption (e.g., partial consumption) of the Ill-nitride alloy layer 706.Atty. Docket No. 10110-23009A

[0059] In the example of Figure 7, the memory device 700 includes a substrate 708 composed of, or otherwise including, a metal. Additional or alternative materials may be used, including, for instance, conductive n-GaN. The top electrode 704, the oxide layer 702, and the Ill-nitride semiconductor layer 706 may be disposed in a stacked arrangement on the substrate 708. The substrate 708 may thus act as a bottom electrode of the memory device 700.

[0060] Figure 8 depicts a catalytic device 800 having a heterostructure with an oxide layer 802 in accordance with one example. In some cases, the catalytic device 800 is a photocatalytic device, but alternative or additional types of catalysis may be supported, such as thermal catalysis. In the example shown, the catalytic device 800 is configured for artificial photosynthesis, including water splitting and reduction of carbon dioxide. Alternative or additional reactions may be implemented.

[0061] The heterostructure of the catalytic device 800 includes a Ill-nitride semiconductor layer 804, such as GaN. In this example, the oxide layer 802 is in contact with the Ill-nitride semiconductor layer 804. In other cases, the heterostructure may include an intervening layer. For instance, the intervening layer may be composed of, or otherwise include, the Ill- nitride alloy from which the oxide layer is formed.

[0062] The oxide layer 802 may completely coat an outer surface of the Ill-nitride semiconductor layer 804. Coating of the Ill-nitride semiconductor layer 804 may be useful for, e.g., passivation or other protective purposes.

[0063] The oxide layer 802 may be composed, or otherwise include, ScAIOx. Alternative or additional oxide materials may be used, including, for instance, oxides including an alternative Group 11 IB element. In some cases, the oxide layer 802 may include nitrogen remaining from the oxidation of the sacrificial Ill-nitride alloy layer. For instance, the oxide layer 802 may be configured as, or otherwise include, an oxynitride portion, aspect, or feature. In other cases, some or all of the nitrogen is displaced during the oxidation process.

[0064] Figure 9 depicts a method 900 of device fabrication that includes a number of acts directed to controllably forming a Ill-nitride-based heterostructure with a native oxide layer. Aspects of the method 900 may both address or prevent the formation of the oxide layer. In this example, the oxide layer is composed of, or otherwise includes, ScAIOx, but alternative or additional oxide materials may be used, including, for instance, oxides including an alternative Group 11 IB element.

[0065] The method 900 utilizes the significant oxygen affinity of the scandium (Sc) element. As described herein, the oxidation process of ScAIN layers is notably faster and moreAtty. Docket No. 10110-23009A complex than conventional Ill-nitrides. The unavoidable spontaneous oxide layer formation can substantially affect device performance and the characterization of intrinsic material parameters.

[0066] The method 900 of Figure 9 addresses and / or prevents oxide layer formation during ScAIN device fabrication, despite the ultrafast self-oxidation nature of the ScAIN surface in the atmosphere. Although growing a GaN cap layer can partially mitigate this issue, it may introduce new challenges, such as diffusion, additional stress, and a more intricate band structure and working mechanism. The method 900 may instead utilize the inherent advantages of the molecular beam epitaxy (MBE) growth method, to deposit one or more metal layers in an act 902, such as, titanium (Ti), nickel (Ni), and aluminum (Al). The metal layer(s) may be in-situ grown on the ScAIN surface within a high-vacuum MBE chamber. The deposition of the metal protects the underlying ScAIN surface from self-oxidation in the atmosphere.

[0067] The method 900 of Figure 9 may be useful in additional ways. For instance, the method 900 may eliminate metal-related damage in the conventional fabrication process, and / or passivate dangling bonds and surface states along the surface of the ScAIN layer.

[0068] The controlled formation of the oxide layer may or may not include patterning the metal layer(s) in an act 904, as shown in Figure 9. Patterning the metal layers may establish an active area of the device in which the oxide is not present.

[0069] Surface oxidation of the ScAIN layer may be alternatively or additionally achieved controllably through oxygen plasma treatment, and / or dry / wet oxidation process, such as annealing in an oxygen or moisture containing environment.

[0070] Figure 10 depicts a method 1000 of fabricating a heterostructure having a wurtzite structure of an alloy of a Ill-nitride material with a Group 111 B element incorporated therein in accordance with one example. As described herein, the method 1000 is configured such that the wurtzite structure exhibits ferroelectric behavior. The heterostructure may form a device, or a part of a device, in which one or more layers or regions of the device exhibit the ferroelectric behavior. The method 1000 may be used to fabricate the examples of ScxAli.xN films and layers described herein.

[0071] The method 1000 may begin with an act 1002 in which a substrate is prepared and / or otherwise provided. In some cases, the act 1002 includes providing a sapphire substrate in an act 1004. The sapphire substrate may have an on-axis, or off-axis, c-plane at the growth front. The act 1004 may include patterning or otherwise processing the substrate to establish an off-cut angle. The sapphire substrate may thus be or include off-Atty. Docket No. 10110-23009A cut sapphire. Additional or alternative patterning of the substrate may be used to configure the substrate to reduce defect formation in subsequently grown layers of the heterostructure and / or otherwise improve material quality therein. Such processing may also facilitate the formation of a heterostructure having alternating regions of metal- and nitrogen-polarity.

[0072] Alternative or additional substrate materials may be used, including, for instance, silicon, bulk GaN, bulk AIN, or other semiconductor material. Still other materials may be used, including, for instance, silicon carbide. The substrate may be cleaned in an act 1006. In some cases, a native or other oxide layer may be removed from a substrate surface in an act 1008. In the example of Figure 10 (e.g., sapphire examples), the act 1002 may include implementing a nitridation procedure in an act 1009. Additional or alternative processing may be implemented in other cases, including, for instance, doping or deposition procedures. The substrate thus may or may not have a uniform composition. The substrate may be a uniform or composite structure.

[0073] In an act 1010, one or more growth templates, buffer, or other layers are formed. The layer(s) are thus formed on, or otherwise supported by, the substrate. The layer(s) may or may not be in contact with the substrate. In some cases, the layer(s) are composed of, or otherwise include, a semiconductor material. For instance, the act 1010 may include an act 1012 in which a semiconductor layer is formed. For example, a Ill-nitride layer, such as a GaN layer, may be grown or otherwise formed on the substrate. Other compound or other semiconductor materials may be used, including, for instance, AIGaN. The semiconductor layer(s) may be N-polar, metal-polar, or alternating or otherwise mixed polarity (e.g., periodically poled structures). The semiconductor layer(s) may form a part of the heterostructure underlying the ferroelectric layer to be grown. The semiconductor layer be undoped or doped (e.g., Si-doped). The act 1012 may thus be implemented before (e.g., in preparation for) implementing an epitaxial growth procedure in which a wurtzite structure is formed. The wurtzite structure may thus be formed on the semiconductor layer. The semiconductor layer may be configured or used as a growth template for the wurtzite structure and / or other elements of the heterostructure. In some cases, the act 1012 may include growing the semiconductor layer in an epitaxial growth chamber in which the epitaxial growth procedure for the wurtzite structure is implemented. As a result, the substrate may remain within, e.g., is not removed from, the epitaxial growth chamber between forming the semiconductor layer and implementing the epitaxial growth procedure for growing the wurtzite structure.

[0074] Alternatively or additionally, the act 1010 includes an act 1014 in which one or more metal or other conductive layers are deposited and patterned. For example, an aluminumAtty. Docket No. 10110-23009A layer may be deposited on a silicon substrate in preparation for the epitaxial growth of the wurtzite structure.

[0075] The method 1000 may include an act 1016 in which one or more contacts or other layers are formed. The layer(s) may form a part of the heterostructure underlying the ferroelectric layer to be grown. Examples of the underlying layer(s) include a lower or bottom contact of the heterostructure or a channel layer of the heterostructure. The nature of the underlying layer(s) may vary with the device being fabricated. The Si-doped layer may or may not be grown on top of the template or buffer layer formed in the act 1010. In the example of Figure 10, the act 1016 includes growing a silicon-doped GaN layer in an act 1018. The Si-doped GaN layer may be N-polar or metal-polar. Other materials may be used. For instance, the underlying layer(s) may be composed of, or otherwise include, AIGaN, In AIN, InGaN, or InAIGaN. Still other materials may be used. For instance, a channel layer may be composed of, or otherwise include, other types of semiconductors, e.g., Ga2Os, diamond, Si, SiGe, GaAs, InGaAs, or InP, in addition to one or more of the above-referenced Ill-nitride alloys, Additional or alternative conductive structures, such as a gate structure, may be deposited and / or patterned in an act 1020.

[0076] In an act 1022, a non-sputtered epitaxial growth procedure is implemented at a growth temperature to form a wurtzite structure supported by the substrate. As described herein, the wurtzite structure is composed of, or otherwise includes, an alloy of a Ill-nitride material. For instance, the Ill-nitride material may be AIN. Additional or alternative Ill-nitride materials may be used, including, for instance, gallium nitride (GaN), indium nitride (InN), and their alloys. As also described herein, the epitaxial growth procedure is configured to incorporate scandium (Sc) into the alloy of the Ill-nitride material. The alloy may thus be SCxAh-xN, for example. The composition of the alloy may vary. For instance, the alloy may include one or more additional group IIIB elements. In some cases, the act 1022 includes an act 1024 in which an MBE procedure is implemented. In other cases, an MOCVD or other non-sputtered epitaxial growth procedure is implemented in an act 1026.

[0077] The act 1022 may constitute a continuation, or part of a sequence, of growth procedures. The growth procedures may be implemented in a common, or same, growth chamber. The act 1022 may thus include an act 1028 in which epitaxial growth is continued in the same chamber in which one or more other layers of the heterostructure were grown. For instance, one or more of the growth template and the underlying semiconductor layer(s) formed in the acts 1010 and 1016 may be formed in the same chamber as the ferroelectric layer. Sequential layers of the heterostructure may thus be grown without exposure to the ambient. The quality of the interface between the layers may accordingly be improved.Atty. Docket No. 10110-23009A

[0078] The growth temperature may be at a level such that the wurtzite structure exhibits a breakdown field strength greater than a ferroelectric coercive field strength of the wurtzite structure. Ferroelectric switching and other behavior may thus be achieved.

[0079] The growth temperature is at a level lower than what would be expected given the Ill-nitride material. In some examples, the growth temperature level is significantly less than the temperature at which the Ill-nitride material would typically be grown. For instance, the growth temperature level may be such that attempts to grow a structure composed of the Ill- nitride material (i.e., without Sc) at the growth temperature level would not be worthwhile. The resulting structure would be of such poor quality (e.g., possess far too many defects) to be useful. Growth of a single crystal of the scandium-including alloy (e.g., a monocrystalline layer of the alloy) at the growth temperature level may nonetheless be achieved. For example, in some cases, a ScxAli.xN alloy may be epitaxially grown at a growth temperature of about 650 degrees Celsius despite that the corresponding (scandium-free) Ill-nitride material, AIN, is conventionally grown at much higher temperatures, e.g., about 1000 degrees Celsius. Conversely, attempts to grow AIN at about 650 degrees Celsius or lower would result in structures of such poor quality so as to be useless. In contrast, the epitaxially grown ScxAli.xN layer grown at that low temperature is unexpectedly monocrystalline and of high quality.

[0080] Growth of the ScxAli.xN layer at the conventional AIN growth temperature (and other temperatures above the upper bound) unexpectedly results in the formation of dislocations and / or other leakage paths in the ScxAli.xN layer. With the leakage paths, the ScxAli.xN layer has a breakdown field strength level too low (e.g., below the ferroelectric coercive field strength level). The layer accordingly does not exhibit ferroelectric behavior.

[0081] In some cases, the growth temperature may be about 650 degrees Celsius or less. The growth temperature may correspond with the temperature measured at a thermocouple in the growth chamber. The growth temperature at the epitaxial surface may be slightly different. The growth temperature is accordingly approximated via the temperature measurement at the thermocouple.

[0082] The upper bound of the growth temperature range may vary in accordance with the alloy and / or the epitaxial growth technique. For instance, in other cases, the upper bound on the growth temperature may be higher, such as about 680 degrees Celsius, or about 690 degrees Celsius. In still other cases, the upper bound may be lower, including, for instance, about 600 degrees Celsius or about 620 degrees Celsius.Atty. Docket No. 10110-23009A

[0083] At each level within the above-described ranges of suitable growth temperatures, the resulting wurtzite structure is monocrystalline. The resulting wurtzite structure is monocrystalline to a degree not realizable via, for instance, sputtering-based procedures for forming ScxAli.xN layers. Such procedures are only capable of producing structures with x- ray diffraction rocking curve line widths on the order of a few degrees at best. In contrast, the structures grown by the disclosed methods exhibit x-ray diffraction rocking curve line widths on the order of a few hundred arc-seconds or less, well over an order of magnitude less. In this manner, leakage current paths are minimized or otherwise sufficiently reduced so that the resulting wurtzite structure has a suitably high breakdown field strength level, e.g., sufficiently greater than the ferroelectric coercive field strength.

[0084] The above-noted differences in crystal quality evidenced via x-ray diffraction rocking curve line widths may also be used to distinguish between monocrystalline and polycrystalline structures. As used herein, the term "polycrystalline" refers to structures having x-ray diffraction rocking curve line widths on the order of a few degrees or higher. As used herein, the term "monocrystalline" refers to structures having x-ray diffraction rocking curve line widths at least one order of magnitude lower than the order of a few degrees.

[0085] Comparing the wurtzite structures of the layers grown by MBE or other nonsputtered techniques (e.g., MOCVD or HVPE) with sputtering deposition techniques, the microstructure of the former techniques is more uniform with highly ordered stacking sequence of atoms. In sputter deposited layers, domains with cubic phase or domains with in-plane mis-orientation are readily observed. The existence of these mis-aligned domains suppresses the complete switching of polarization, and further results in the fast loss of polarization during fatigue testing. Regarding phase purity, the highly crystallographic orientation of layers grown by MBE or other non-sputtered techniques exhibits more repeatable ferroelectric switching, which is useful in a number of device applications.

[0086] The wurtzite structure of the ferroelectric layer may be nitrogen-polar (N-polar) or metal-polar. The polarity of an underlying layer formed in the act 1010 and / or the act 1016 may be used to establish the polarity of the ferroelectric layer formed in the act 1022. As described herein, the polarity of the underlying layer may, in turn, be established by a characteristic of the substrate. The polarity may continue across the interface between the underlying layer and the ferroelectric layer. Either N- or metal-polarity may thus persist as the composition changes from the underlying layer to the ferroelectric layer.

[0087] The growth of the wurtzite structure may include an anneal. The annealing may be implemented at a temperature greater than the growth temperature. In some cases, theAtty. Docket No. 10110-23009A annealing temperature falls in a range from about 700 Celsius to about 1500 degrees Celsius. Examples of films prepared with such annealing exhibited stable polarization switching with further reduced leakage current relative to non-annealed films. Film or device uniformity was also improved via the annealing, thereby further improving the polarization switching behavior of the ferroelectric Sc-lll-N alloys. The underlying mechanism for the improved performance and uniformity with annealing is attributed to the reduced threading dislocation density and defect density, which usually act as electric leakage paths. Such usefulness of the post-growth annealing is realized despite past concerns that high processing temperatures can lead to a loss of ferroelectricity.

[0088] Such post-growth high-temperature annealing of ScxAli.xN may be performed in-situ in the same growth chamber (e.g., the same MBE chamber). In other cases, the annealing is performed ex-situ in a chamber directed to annealing procedures.

[0089] The annealing process may be implemented under high vacuum i (e.g., in-situ in the growth chamber). In other cases, the annealing may be implemented either with nitrogen plasma radiation or under nitrogen gas flow.

[0090] The above-described annealing procedure may be implemented in connection with films grown under any of the above-described growth conditions. For instance, the annealing procedure may be implemented after growth under slightly to moderately N-rich conditions at a growth temperature below about 650 degrees Celsius. The annealing procedure may also be implemented after growth under unbalanced flux ratios (e.g., N-rich or extreme N-rich conditions) at growth temperatures above about 650 degrees Celsius.

[0091] The method 1000 may include an act 1030 in which an oxide layer is formed on an exposed surface of the Ill-nitride alloy layer via exposure of the exposed surface to oxygen. The oxide layer may therefore be composed of, or otherwise include, a native oxide of the Ill-nitride alloy layer.

[0092] The act 1030 may include controllably exposing the surface for a predetermined period of time in an act 1032. Depending on the time period and thickness of the Ill-nitride alloy layer, the exposure may partially or completely consume the Ill-nitride alloy layer. The exposure may be implemented as part of an anneal process in an act 1034.

[0093] The method 1000 may further include depositing and patterning one or more metal layers such that the metal layer is supported by the Ill-nitride alloy layer in an act 1036. In such cases, the oxide layer is formed after the metal deposition such that the oxide layer is patterned in accordance with a layout of the metal layer. In this manner, an active area of the device may be defined.Atty. Docket No. 10110-23009A

[0094] Alternatively or additionally, the oxide layer is formed before the metal layer(s) are deposited. In such cases, the method 1000 may further include patterning the oxide layer and the metal layer into a gate oxide and a gate, respectively.

[0095] The method 1000 may include an act 1038 in which one or more layers (e.g., semiconductor layers) are formed after growth of the wurtzite structure. As a result, the layer(s) may be in contact with the wurtzite structure. For instance, one or more Ill-nitride (e.g., GaN or AIGaN) or other semiconductor layers may be epitaxially grown in an act 1040. The act 1040 may be implemented in the same epitaxial growth chamber used to grow the wurtzite structure. As a result, the substrate (and heterostructure) is not removed from the epitaxial growth chamber between implementing the acts 1022 and 1038.

[0096] Alternatively or additionally, the act 1038 includes an act 1042 in which one or more metal or other conductive layers or structures are formed. The layers or structures may be deposited or otherwise formed. In some cases, the conductive structure is configured as an upper or top contact. For instance, the conductive structure may be a gate.

[0097] The method 1000 may include one or more additional acts. For example, one or more acts may be directed to forming other structures or regions of the device that includes the heterostructure. In a transistor device example, the regions may correspond with source and drain regions. The nature of the regions or structures may vary in accordance with the nature of the device.

[0098] The order of the acts of the method 1000 may differ from the example shown in Figure 10. For example, the acts 1016, 1018, and 1020 in which contacts and / or other conductive structures formed may be implemented after the growth of the ferroelectric layer.

[0099] A number of different types of devices may be fabricated by the method 1000 of Figure 10, and / or another method of fabricating a heterostructure having a wurtzite structure of an alloy of a Ill-nitride material with, e.g., scandium, incorporated therein. For example, the ferroelectric ScxAli.xN or other alloy of a Ill-nitride material may be useful in various types of nonvolatile memory devices (e.g., FeRAM, FeFET, FTJ, and FeSFET devices), various types of reconfigurable electronic and other devices (e.g., Fe-HEMT, Fe-capacitor, and SAW devices), various types of photodetection, photovoltaic and optoelectronic devices (e.g., selfdriven photodetector and solar cell devices), and various homojunction devices (e.g., devices that use a laterally distributed charge plate to tune the Fermi level in adjacent layers). Still other types of devices may be fabricated, including, for instance, FE-based thin- film bulk acoustic wave resonators (FBAR) devices.Atty. Docket No. 10110-23009A

[0100] A number of example devices are now described. In each example, the device includes a substrate and a heterostructure supported by the substrate. The heterostructure includes a monocrystalline layer of an alloy of a Ill-nitride material. As described herein, the alloy includes yttrium. As also described herein, the monocrystalline layer exhibits a breakdown field strength greater than a ferroelectric coercive field strength of the monocrystalline layer. In some cases, the Ill-nitride material is aluminum nitride (AIN), but other Ill-nitrides may be used.

[0101] In some of the devices described below, the device also includes a semiconductor layer disposed between the substrate and the heterostructure. The semiconductor layer may include a further Ill-nitride material, such as GaN. In some cases, the semiconductor layer is in contact with the heterostructure. The epitaxial growth of the layers may result in a high quality interface between the layers. Alternatively or additionally, the device also includes a metal or other conductive layer disposed between the substrate and the heterostructure. The metal layer may be in contact with the heterostructure, examples of which are described below.

[0102] Figures 11 A and 11 B schematically depict example GaN-based light emitting diode (LED) devices 1100, 1102 with an AIGaN electron blocking layer (EBL) 1104 and a Ill-nitride alloy-based EBL 1106, respectively. Due to the large valence band offset, the AIGaN EBL 1102 shown in Figure 11A undesirably also blocks hole injection. In addition, the growth of AIGaN introduces undesired strain distribution in the heterostructure.

[0103] The use of a Ill-nitride alloy, such as ScAIN, as the EBL 1106 of the LED device 1102 shown in Figure 11 B avoids those problems. As described herein, the Ill-nitride alloy is disposed within the heterostructure such that a type-ll energy band alignment arrangement is established. In addition, the valence band offset may be negligibly small by optimizing the Sc composition, which can effectively reduce electron leakage / overflow, which leads to no negative effect on hole injection.

[0104] The ScAIN layer 1106 may also be configured (e.g., via composition) to be lattice matched with one or both of the adjacent Ill-nitride layers 1108, 1100. For example, the lattice-matched Sco.i8Alo.82N / GaN heterojunction may form a type-ll heterostructure, with valence and conduction band offsets of 0.2 eV and 2.3 eV, respectively. This type-ll alignment promotes the separation of electrons and holes to opposite sides of the heterointerface, which is useful in connection with various optoelectronic devices and applications, including photodetectors, and solar cells, as well as non-optoelectronicAtty. Docket No. 10110-23009A applications, including solar water splitting devices and barrier layers in GaN-based electronics.

[0105] In optoelectronic applications, as a result of the largest conduction band offsets with the GaN layer (2.3 eV), the lattice-matched Sco.i8Alo.82N layer 1 106 may be disposed or configured as a quantum barrier or electron blocking layer (e.g., in Ill-nitride light emitters) by confining the electrons in an active region 1 112, blocking the overflowed electrons and facilitating hole injection as shown in Figure 11 B. These benefits may be realized in addition to the reduced strain, improved crystal quality, and reduced polarization effects resulting from the lattice matching.

[0106] The term "about" is used herein in a manner to include deviations from a specified value that would be understood by one of ordinary skill in the art to effectively be the same as the specified value due to, for instance, the absence of appreciable, detectable, or otherwise effective difference in operation, outcome, characteristic, or other aspect of the disclosed methods and devices.

[0107] The present disclosure has been described with reference to specific examples that are intended to be illustrative only and not to be limiting of the disclosure. Changes, additions and / or deletions may be made to the examples without departing from the spirit and scope of the disclosure.

[0108] The foregoing description is given for clearness of understanding only, and no unnecessary limitations should be understood therefrom.

Claims

Atty. Docket No. 10110-23009AWhat is Claimed is:

1. A device comprising: a substrate; and a heterostructure supported by the substrate, the heterostructure comprising: a Ill-nitride semiconductor layer; and an oxide layer supported by the Ill-nitride semiconductor layer; wherein the oxide layer comprises a Group 111 B element and a Group III metal.

2. The device of claim 1 , wherein the oxide layer is in contact with the Ill-nitride semiconductor layer.

3. The device of claim 2, wherein the oxide layer is patterned relative to the Ill-nitride semiconductor layer.

4. The device of claim 2, wherein the oxide layer completely coats an outer surface of the Ill-nitride semiconductor layer.

5. The device of claim 1 , wherein: the heterostructure further comprises a Ill-nitride alloy layer disposed between the Ill- nitride semiconductor layer and the oxide layer; and the Ill-nitride alloy layer comprises the Group II IB element.

6. The device of claim 5, wherein the Ill-nitride alloy layer is monocrystalline, wurtzite phase, and ferroelectric.

7. The device of claim 5, wherein the Ill-nitride alloy layer and the Ill-nitride semiconductor layer are lattice matched.

8. The device of claim 5, wherein the Ill-nitride alloy layer and the Ill-nitride semiconductor layer are in contact with one another.

9. The device of claim 1 , wherein: the Ill-nitride semiconductor layer comprises GaN; and the oxide layer comprises ScAIOx.

10. The device of claim 1 , further comprising a metal layer supported by the oxide layer such that the oxide layer is positioned in the heterostructure as a gate dielectric layer.Atty. Docket No. 10110-23009A11. The device of claim 1 , further comprising a metal layer supported by the oxide layer, wherein the Ill-nitride semiconductor layer is doped with a Group 11 IB element.

12. The device of claim 11 , wherein the substrate comprises a metal such that the oxide layer and the Ill-nitride semiconductor layer are disposed between the metal layer and the metal of the substrate in a stacked arrangement.

13. A method of fabricating a device, the method comprising: providing a substrate; growing a Ill-nitride alloy layer supported by the substrate, the Ill-nitride alloy being doped with a Group I IIB element; and forming an oxide layer on an exposed surface of the Ill-nitride alloy layer via exposure of the exposed surface of the Ill-nitride alloy layer to oxygen; wherein the oxide layer comprises a native oxide of the Ill-nitride alloy layer.

14. The method of claim 13, wherein forming the oxide layer is controllably implemented for a predetermined period of time.

15. The method of claim 13, wherein forming the oxide layer partially consumes the Ill- nitride alloy layer.

16. The method of claim 13, wherein forming the oxide layer completely consumes the Ill-nitride alloy layer.

17. The method of claim 13, further comprising depositing a metal layer such that the metal layer is supported by the Ill-nitride alloy layer.

18. The method of claim 17, wherein forming the oxide layer is implemented after depositing the metal layer such that the oxide layer is patterned in accordance with a layout of the metal layer to define an active area of the device.

19. The method of claim 17, wherein forming the oxide layer is implemented before depositing the metal layer.

20. The method of claim 19, further comprising patterning the oxide layer and the metal layer into a gate oxide and a gate, respectively.Atty. Docket No. 10110-23009A21. The method of claim 13, further comprising growing a Ill-nitride semiconductor layer supported by the substrate before growing the Ill-nitride alloy layer such that the Ill-nitride semiconductor layer is disposed between the Ill-nitride alloy layer and the substrate.

22. An optoelectronic device comprising: a substrate; and a heterostructure supported by the substrate, the heterostructure comprising: an n-type Ill-nitride semiconductor layer; a p-type Ill-nitride semiconductor layer spaced from the n-type Ill-nitride semiconductor layer; and an active region disposed between the n-type Ill-nitride semiconductor layer and the p-type Ill-nitride semiconductor layer; and an electron-blocking layer disposed between the p-type Ill-nitride semiconductor layer and the active region; wherein: the electron-blocking layer comprises a Ill-nitride alloy; the Ill-nitride alloy comprises a Group II IB element; and the Ill-nitride alloy is disposed within the heterostructure such that a type-ll energy band alignment arrangement is established.

23. The optoelectronic device of claim 22, further comprising an intrinsic Ill-nitride semiconductor layer disposed between the p-type Ill-nitride semiconductor layer and the active region, wherein the intrinsic Ill-nitride semiconductor layer is in contact with the electron-blocking layer to establish the type-ll energy band alignment arrangement.

24. The optoelectronic device of claim 23, wherein: the intrinsic Ill-nitride semiconductor layer comprises GaN; and the electron-blocking layer comprises ScAIN.

25. The optoelectronic device of claim 23, wherein the intrinsic Ill-nitride semiconductor layer and the electron-blocking layer are lattice-matched.

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