Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a gate driving circuit, a first low-level power supply line, and a second low-level power supply line. The gate driving circuit comprises a plurality of cascaded shift registers. The second low-level power supply line is located on the side of the first low-level power supply line close to a display area. The orthographic projection of the first low-level power supply line on a base at least partially overlaps the orthographic projection of at least one transistor in a shift sub-circuit on the base. The orthographic projection of the second low-level power supply line on the base is located between the orthographic projection of the at least one transistor in the shift sub-circuit on the base and the orthographic projection of at least one output transistor in an output sub-circuit on the base. The line width of the first low-level power supply line in a first direction is less than the line width of the second low-level power supply line in the first direction.

Description

Display substrate and its preparation method, display device

[0001] This application claims priority to Chinese Patent Application No. 202411498314.9, filed on October 24, 2024, entitled "Display Substrate and Method for Preparing the Same, Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a display substrate having a display area and a non-display area located on at least one side of the display area, comprising: a substrate and a gate driving circuit, a first low-level power supply line, and a second low-level power supply line disposed on the substrate and located in the non-display area. The gate driving circuit includes: a plurality of cascaded shift registers, at least one shift register including: a shift sub-circuit and an output sub-circuit. The shift sub-circuit is electrically connected to a first low-level power supply terminal and a cascaded signal output terminal, respectively. The output sub-circuit is electrically connected to a first low-level power supply terminal, a second low-level power supply terminal, and a drive signal output terminal, respectively. The shift sub-circuit includes: at least one transistor, and the output sub-circuit includes: at least one output transistor.

[0006] The first low-level power line is electrically connected to the first low-level power supply terminal of the at least one level shift register, and the second low-level power line is electrically connected to the second low-level power supply terminal of the at least one level shift register. The second low-level power line is located on the side of the first low-level power line closer to the display area.

[0007] The orthographic projection of the first low-level power line on the substrate at least partially overlaps with the orthographic projection of at least one transistor in the shift sub-circuit on the substrate, and the orthographic projection of the second low-level power line on the substrate is located between the orthographic projection of at least one transistor in the shift sub-circuit on the substrate and the orthographic projection of at least one output transistor in the output sub-circuit on the substrate.

[0008] The width of the first low-level power line along the first direction is smaller than the width of the second low-level power line along the first direction.

[0009] In an exemplary embodiment, at least one of the first low-level power lines and the second low-level power lines extends at least partially along a second direction, where the first direction and the second direction intersect.

[0010] The signal of at least one of the first low-level power line and the second low-level power line is a negative voltage signal, and the absolute value of the voltage of the power signal of the first low-level power line is less than the absolute value of the voltage of the power signal of the second low-level power line.

[0011] In an exemplary embodiment, the first low-level power line includes at least one first power connection line, and the second low-level power line includes multiple second power connection lines that are disposed in different layers and interconnected with each other.

[0012] The first power connection line and the second power connection line extend at least partially along the second direction, and a plurality of second power connection lines are stacked sequentially along a direction away from the substrate, and at least two of the plurality of second power connection lines have orthographic projections on the substrate that at least partially overlap.

[0013] The number of first power connection lines included in the first low-level power line is less than the number of second power connection lines included in the second low-level power line.

[0014] The at least one first power connection line is disposed in the same layer as at least one of the plurality of second power connection lines, and the film layer containing at least one of the plurality of second power connection lines is located on the side of the film layer containing at least one first power connection line closer to the substrate.

[0015] In an exemplary embodiment, the first low-level power line includes: a first power connection line, and the second low-level power line includes: two second power connection lines that are disposed in different layers and connected to each other, wherein the second power connection line is located on the side of the first power connection line away from the substrate.

[0016] The first power connection cable and the second power connection cable are arranged on the same layer;

[0017] Alternatively, the first low-level power line includes: two first power connection lines that are disposed in different layers and interconnected with each other; the second low-level power line includes: three second power connection lines that are disposed in different layers and interconnected with each other; the second first power connection line is located on the side of the first first power connection line away from the substrate; the first second power connection line is located on the side of the second second power connection line close to the substrate; and the third second power connection line is located on the side of the second second power connection line away from the substrate.

[0018] The first power connection line is arranged on the same layer as the second power connection line, and the second power connection line is arranged on the same layer as the third power connection line.

[0019] In an exemplary embodiment, the system further includes: a first clock signal line group disposed on the substrate and located in the non-display area; the at least one level shift register includes: a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal; the shift sub-circuit of the at least one level shift register is respectively connected to the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal; the first clock signal line group includes: a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line arranged sequentially along the direction close to the display area.

[0020] At least one of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line extends at least partially along the second direction;

[0021] The first clock signal terminal of the 4i-3 stage shift register is electrically connected to the first clock signal line; the second clock signal terminal of the 4i-3 stage shift register is electrically connected to the second clock signal line; the third clock signal terminal of the 4i-3 stage shift register is electrically connected to the third clock signal line; the first clock signal terminal of the 4i-2 stage shift register is electrically connected to the second clock signal line; the second clock signal terminal of the 4i-2 stage shift register is electrically connected to the third clock signal line; and the third clock signal terminal of the 4i-2 stage shift register is electrically connected to the fourth clock signal line. The first clock signal terminal of the 4i-1 stage shift register is electrically connected to the third clock signal line, the second clock signal terminal of the 4i-1 stage shift register is electrically connected to the fourth clock signal line, the third clock signal terminal of the 4i-1 stage shift register is electrically connected to the first clock signal line, the first clock signal terminal of the 4i stage shift register is electrically connected to the fourth clock signal line, the second clock signal terminal of the 4i stage shift register is electrically connected to the first clock signal line, and the third clock signal terminal of the 4i stage shift register is electrically connected to the second clock signal line.

[0022] The orthographic projection of the first low-level power line on the substrate is located between the orthographic projections of the second clock signal line on the substrate and the third clock signal line on the substrate. The orthographic projection of the second low-level power line on the substrate is located on the side of the orthographic projection of at least one clock signal line in the first clock signal line group that is closer to the display area.

[0023] In an exemplary embodiment, the shift sub-circuit of at least one shift register includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; wherein, the control electrode of the first transistor is electrically connected to a first clock signal terminal, the first electrode of the first transistor is connected to a signal input terminal, the second electrode of the first transistor is electrically connected to a first node, the control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to a second node; the control electrode of the third transistor is electrically connected to the first clock signal terminal, the first electrode of the third transistor is electrically connected to a first low-level power supply terminal, and the second electrode of the third transistor is electrically connected to the second node; the control electrode of the fourth transistor is electrically connected to the second node, and the eighth transistor... The first terminal of the fourth transistor is electrically connected to the high-level power supply terminal; the second terminal of the fourth transistor is electrically connected to the cascaded signal output terminal; the control terminal of the fifth transistor is electrically connected to the third node; the first terminal of the fifth transistor is electrically connected to the second clock signal terminal; the second terminal of the fifth transistor is electrically connected to the cascaded signal output terminal; the control terminal of the sixth transistor is electrically connected to the second node; the first terminal of the sixth transistor is electrically connected to the high-level power supply terminal; the second terminal of the sixth transistor is electrically connected to the fourth node; the control terminal of the seventh transistor is electrically connected to the third clock signal terminal; the first terminal of the seventh transistor is electrically connected to the fourth node; the second terminal of the seventh transistor is electrically connected to the first node; the control terminal of the eighth transistor is electrically connected to the first low-level power supply terminal; the first terminal of the eighth transistor is electrically connected to the first node; the second terminal of the eighth transistor is electrically connected to the third node.

[0024] The control electrode of the first transistor and the control electrode of the third transistor are integrally structured and extend at least partially along the first direction. The orthographic projection of the control electrode of the first transistor on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the first clock signal line, the second clock signal line, the first low-level power supply line, the third clock signal line, and the fourth clock signal line.

[0025] At least a portion of the control electrode of the second transistor extends along the first direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the second clock signal line and the first low-level power line.

[0026] The control electrode of the fourth transistor and the control electrode of the sixth transistor are integrally structured and extend at least partially along the first direction. The orthographic projection of the control electrode of the fourth transistor on the substrate at least partially overlaps with the orthographic projection of at least one of the third clock signal line and the fourth clock signal line on the substrate.

[0027] The control electrode of the fifth transistor extends at least partially along the first direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the second clock signal line, the first low-level power supply line, the third clock signal line, and the fourth clock signal line.

[0028] The control electrode of the seventh transistor extends at least partially along the first direction, and its orthogonal projection on the substrate at least partially overlaps with the orthogonal projections on the substrate of at least one of the first clock signal line, the second clock signal line, the first low-level power supply line, the third clock signal line, and the fourth clock signal line.

[0029] The control electrode of the eighth transistor extends at least partially along a first direction, and its orthogonal projection on the substrate at least partially overlaps with the orthogonal projections on the substrate of at least one of the first clock signal line, the second clock signal line, the first low-level power supply line, the third clock signal line, and the fourth clock signal line.

[0030] In an exemplary embodiment, it further includes: a plurality of vias exposing the control electrode of the first transistor, wherein two of the plurality of vias exposing the control electrode of the first transistor respectively expose both ends of the control electrode of the first transistor;

[0031] Multiple vias that expose the control electrode of the seventh transistor are provided, and two of the multiple vias that expose the control electrode of the seventh transistor expose the two ends of the control electrode of the seventh transistor, respectively.

[0032] In an exemplary embodiment, the system further includes: a plurality of first connection lines disposed on the substrate and located in the non-display area, one of the plurality of first connection lines being electrically connected to the first electrode of the fifth transistor of at least one level shift register, the first connection line extending along a first direction.

[0033] The orthographic projection of the first terminal of the fifth transistor of at least one level shift register on the substrate at least partially overlaps with the orthographic projection of the fourth clock signal line and one of the plurality of first connection lines on the substrate. The orthographic projection of one of the plurality of first connection lines on the substrate at least partially overlaps with the orthographic projection of at least one of the first clock signal line, the second clock signal line, the first low-level power supply line and the third clock signal line on the substrate.

[0034] The first connection line is located on the side of the film layer where the first and second electrodes of at least one transistor of the at least one level shift register are located, close to the substrate.

[0035] In an exemplary embodiment, the method further includes: a plurality of vias exposing the first connecting line, wherein two of the plurality of vias exposing the first connecting line expose one end of the first connecting line closer to the display area and the other end of the first connecting line farther from the display area, respectively.

[0036] In an exemplary embodiment, the line width of one of the first low-level power lines and the second low-level power lines along the first direction is smaller than the line width of at least one clock signal line in the first clock signal line group along the first direction.

[0037] In an exemplary embodiment, the system further includes: a second clock signal line group disposed on the substrate and located in the non-display area, the second clock signal line group being located on the side of the first clock signal line group closer to the display area; the at least one level shift register includes: a fourth clock signal terminal; the output sub-circuit of the at least one level shift register is electrically connected to the fourth clock signal terminal; the second clock signal line group includes: a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line arranged sequentially along the direction closer to the display area;

[0038] The fifth clock signal line and the seventh clock signal line receive the same clock signal, the sixth clock signal line and the eighth clock signal line receive the same signal, and at least one of the fifth clock signal line, the sixth clock signal line, the seventh clock signal line and the eighth clock signal line extends at least partially along the second direction;

[0039] The fourth clock signal terminal of at least one shift register is electrically connected to one of the signal line groups of the first and second signal line groups. The fourth clock signal terminals of adjacent shift registers are connected to different signal line groups. The first signal line group includes a fifth clock signal line and a seventh clock signal line, and the second signal line group includes a sixth clock signal line and an eighth clock signal line.

[0040] The orthographic projection of the second low-level power line on the substrate lies between the orthographic projections of the sixth clock signal line and the seventh clock signal line on the substrate.

[0041] In an exemplary embodiment, the output sub-circuit of at least one level shift register includes: a tenth transistor and a third capacitor, wherein the control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the fourth clock signal terminal, the second electrode of the tenth transistor is electrically connected to the drive signal output terminal, the first plate of the third capacitor is electrically connected to the fourth clock signal terminal, and the second plate of the third capacitor is electrically connected to the fifth node.

[0042] When the fourth clock signal terminal of at least one shift register is electrically connected to the first signal line group, the first terminal of the tenth transistor of at least one shift register is electrically connected to the seventh clock signal line, and the first plate of the third capacitor of at least one shift register is electrically connected to the fifth clock signal line.

[0043] When the fourth clock signal terminal of at least one shift register is electrically connected to the second signal line group, the first terminal of the tenth transistor of at least one shift register is electrically connected to the eighth clock signal line, and the first plate of the third capacitor of at least one shift register is electrically connected to the sixth clock signal line.

[0044] In an exemplary embodiment, the output sub-circuit of the at least one level shift register further includes: a ninth transistor and an eleventh transistor, wherein the control electrode of the ninth transistor is electrically connected to the fifth node, the first electrode of the ninth transistor is electrically connected to the second low-level power supply terminal, the second electrode of the ninth transistor is electrically connected to the drive signal output terminal, the control electrode of the eleventh transistor is electrically connected to the first low-level power supply terminal, the first electrode of the eleventh transistor is electrically connected to the second node, and the second electrode of the eleventh transistor is electrically connected to the fifth node.

[0045] The orthographic projection of at least one of the fifth clock signal line, the sixth clock signal line, and the second low-level power line onto the substrate lies between the orthographic projection of at least one of the transistors in the shift sub-circuit and the eleventh transistor in the output sub-circuit onto the substrate and the orthographic projection of at least one of the ninth and tenth transistors in the output sub-circuit onto the substrate. The orthographic projection of at least one of the seventh and eighth clock signal lines onto the substrate lies on the side of the orthographic projection of at least one of the ninth and tenth transistors in the output sub-circuit closer to the display area.

[0046] In an exemplary embodiment, at least one of the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line, the seventh clock signal line, and the eighth clock signal line has a line width in the first direction that is greater than the line width in the first direction of at least one of the fifth clock signal line, the sixth clock signal line, and the second low-level power line.

[0047] In an exemplary embodiment, at least one of the clock signal lines from the fifth clock signal line to the eighth clock signal line includes: a first clock connection line and a second clock connection line that are disposed in different layers and interconnected with each other, wherein the first clock connection line and the second clock connection line extend at least partially along a second direction, and the orthographic projections of the first clock connection line and the second clock connection line of at least one of the clock signal lines from the fifth clock signal line to the eighth clock signal line on the substrate at least partially overlap.

[0048] The film layer containing the first clock connection line of at least one clock signal line from the fifth clock signal line to the eighth clock signal line is located on the side of the film layer containing the second clock connection line closer to the substrate. The second clock connection line of at least one clock signal line from the fifth clock signal line to the eighth clock signal line is disposed in the same layer as at least one clock signal line from the first clock signal line to the fourth clock signal line.

[0049] In an exemplary embodiment, it further includes: an initial signal line and a high-level power supply line disposed on the substrate and located in the non-display area; at least one shift register includes: a signal input terminal and a high-level power supply terminal; the high-level power supply line is electrically connected to the high-level power supply terminal of the at least one shift register; the initial signal line is electrically connected to the signal input terminal of the at least one shift register; at least a portion of at least one of the initial signal line and the high-level power supply line extends along a second direction.

[0050] The orthographic projection of the initial signal line on the substrate is located on the side of the first clock signal line group away from the display area, and the orthographic projection of the high-level power line on the substrate is located between the orthographic projections of the first clock signal line group on the substrate and the orthographic projections of the second clock signal line group on the substrate.

[0051] In an exemplary embodiment, the orthographic projection of the high-level power line on the substrate at least partially overlaps with the orthographic projection of the control electrode of at least one of the fourth and fifth transistors in at least one level shift register on the substrate.

[0052] In an exemplary embodiment, the linewidth of the high-level power line along the first direction is greater than the linewidth of at least one of the first low-level power line and the initial signal line along the first direction, and less than the linewidth of at least one of the clock signal lines in the first clock signal line group along the first direction.

[0053] In an exemplary embodiment, the shift sub-circuit further includes a first capacitor, and the output sub-circuit further includes a second capacitor and a third capacitor. At least one of the first capacitor, the second capacitor, and the third capacitor includes a first plate and a second plate. The second plate of the at least one capacitor is located on the side of the first plate of the at least one capacitor away from the substrate. The first plate of the first capacitor is electrically connected to a third node, and the second plate of the first capacitor is electrically connected to a cascaded signal output terminal. The first plate of the second capacitor is electrically connected to a fifth node and a second low-level power supply terminal. The first plate of the third capacitor is electrically connected to a fourth clock signal terminal, and the second plate of the third capacitor is electrically connected to the fifth node.

[0054] The orthographic projection of the first capacitor on the substrate is located between the orthographic projections of the first clock signal line group on the substrate and the orthographic projections of the second clock signal line group on the substrate, and at least partially overlaps with the orthographic projection of the high-level power line on the substrate.

[0055] The orthographic projection of the second capacitor onto the substrate lies between the orthographic projection of the second low-level power line onto the substrate and the orthographic projection of the seventh clock signal line onto the substrate;

[0056] The orthogonal projection of the third capacitor on the substrate lies between the orthogonal projection of the sixth clock signal line on the substrate and the orthogonal projection of at least one output transistor in the output sub-circuit on the substrate, and at least partially overlaps with the orthogonal projection of the second low-level power supply line on the substrate.

[0057] In an exemplary embodiment, at least one of the first and second plates of the at least one capacitor includes a main body and a connecting part, and the main body and the connecting part of the at least one plate are connected.

[0058] The orthographic projection of the main body of the first plate of the first capacitor onto the substrate covers the orthographic projection of the main body of the second plate of the first capacitor onto the substrate, the orthographic projection of the main body of the second plate of the second capacitor onto the substrate covers the orthographic projection of the main body of the first plate of the second capacitor onto the substrate, and the orthographic projection of the main body of the second plate of the third capacitor onto the substrate covers the orthographic projection of the main body of the first plate of the third capacitor onto the substrate.

[0059] The orthographic projection of the connection portion of the second plate of the third capacitor on the substrate at least partially overlaps with the orthographic projection of at least one of the fifth and sixth clock signal lines on the substrate.

[0060] In an exemplary embodiment, the length of the main body portion of the second plate of the third capacitor along the first direction is greater than the line width of the second low-level power line along the first direction, and the orthographic projection of the portion of the second low-level power line near the boundary of the display area and away from the boundary of the display area on the substrate is within the range of the orthographic projection of the main body portion of the second plate of the third capacitor on the substrate.

[0061] The distance between the orthographic projection of the main body of the second plate of the third capacitor away from the display area and the orthographic projection of the sixth clock signal line near the display area on the substrate is greater than 1 micrometer, and the distance between the orthographic projection of the second low-level power line away from the display area and the orthographic projection on the substrate is greater than 1 micrometer.

[0062] The distance between the orthographic projection of the main body of the second plate of the third capacitor near the boundary of the display area on the substrate and the orthographic projection of the second low-level power line near the boundary of the display area on the substrate is greater than 1 micrometer.

[0063] In an exemplary embodiment, the area of ​​the first capacitor is larger than the area of ​​at least one of the second capacitor and the third capacitor;

[0064] The area of ​​the third capacitor is larger than the area of ​​the second capacitor.

[0065] In an exemplary embodiment, the active patterns of the first transistor and the third transistor are arranged along a first direction, and a straight line extending along the first direction passes through at least a portion of the control electrode of the first transistor and the active pattern of the second transistor.

[0066] In an exemplary embodiment, the output sub-circuit of at least one level shift register includes: a tenth transistor, wherein the tenth transistor is an output transistor;

[0067] The control electrode of the tenth transistor includes: a first connection segment, a second connection segment, and a plurality of first branch segments, wherein the second connection segment is located on the side of the first connection segment closer to the display area, and the plurality of first branch segments are located on the side of the second connection segment closer to the display area; the second electrode of the tenth transistor includes: a third connection segment and a plurality of second branch segments, wherein the plurality of second branch segments are located on the side of the third connection segment closer to the display area;

[0068] The first connecting segment extends along a first direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the fifth clock signal line, the sixth clock signal line, and the second low-level power line; the second connecting segment extends along a second direction, one of the plurality of first branch segments extends along the first direction, and the plurality of first branch segments are arranged along the second direction; the third connecting segment extends along the second direction, one of the plurality of second branch segments extends along the first direction, and the plurality of second branch segments are arranged along the second direction.

[0069] The orthographic projection of the third connecting segment on the substrate at least partially overlaps with the orthographic projection of the first connecting segment on the substrate, but does not overlap with the orthographic projection of the second connecting segment on the substrate. At least one of the plurality of first branch segments does not overlap with the orthographic projections of the third connecting segment and at least one of the plurality of second branch segments on the substrate. The orthographic projection of at least one of the plurality of first branch segments on the substrate is located between the orthographic projections of at least two of the plurality of second branch segments on the substrate.

[0070] In an exemplary embodiment, the aspect ratio of the channel region of the active pattern of the tenth transistor is greater than 40.

[0071] In an exemplary embodiment, the linewidth of the first low-level power line along the first direction is in the range of 4 micrometers to 20 micrometers, and the linewidth of the second low-level power line along the first direction is in the range of 4 micrometers to 50 micrometers.

[0072] In an exemplary embodiment, at least one of the clock signal lines of the seventh clock signal line and the eighth clock signal line has a linewidth in the range of 10 micrometers to 50 micrometers along the first direction.

[0073] In an exemplary embodiment, the capacitance value of the first capacitor is greater than or equal to 0.3pF.

[0074] In an exemplary embodiment, it further includes: a circuit structure layer disposed on a substrate, the circuit structure layer including: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked sequentially on the substrate, at least one level shift register including: a plurality of transistors and a plurality of capacitors, the gate drive circuit, the first low-level power supply line and the second low-level power supply line disposed on the circuit structure layer;

[0075] The display substrate further includes: a first connection line, an initial signal line, a high-level power supply line, and a first clock signal line to an eighth clock signal line;

[0076] The semiconductor layer includes at least: an active pattern of at least one transistor from a plurality of transistors in at least one level shift register;

[0077] The first conductive layer includes: a control electrode of at least one transistor among a plurality of transistors in at least one level shift register and a first plate of at least one capacitor among a plurality of capacitors;

[0078] The second conductive layer includes: a second plate of at least one capacitor located in at least one of the transistors of a first-stage shift register;

[0079] The third conductive layer includes: a first and second electrode of at least one of a plurality of transistors located in at least one level shift register, and an initial signal line;

[0080] The fourth conductive layer includes: a high-level power supply line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line;

[0081] The first connection line is located in the first conductive layer or the second conductive layer, the first low-level power line is located in the fourth conductive layer, the second low-level power line is located in the third and fourth conductive layers, and at least one of the fifth to eighth clock signal lines is located in the third and fourth conductive layers.

[0082] In an exemplary embodiment, it further includes: a circuit structure layer disposed on a substrate, the circuit structure layer including: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked sequentially on the substrate, at least one level shift register including: a plurality of transistors and a plurality of capacitors, the gate drive circuit, the first low-level power supply line and the second low-level power supply line disposed on the circuit structure layer;

[0083] The display substrate further includes: a first connection line, an initial signal line, a high-level power supply line, and first to eighth clock signal lines.

[0084] The semiconductor layer includes at least: an active pattern of at least one transistor from a plurality of transistors in at least one level shift register;

[0085] The first conductive layer includes: a control electrode of at least one transistor among a plurality of transistors in at least one level shift register and a first plate of at least one capacitor among a plurality of capacitors;

[0086] The second conductive layer includes: a second plate of at least one capacitor located in at least one of the transistors of a first-stage shift register;

[0087] The third conductive layer includes: a first and second electrode of at least one of a plurality of transistors located in at least one level shift register, and an initial signal line;

[0088] The fourth conductive layer includes: a high-level power supply line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line;

[0089] The first connection line is located in the first conductive layer or the second conductive layer, the first low-level power line is located in at least one of the fourth and fifth conductive layers, the second low-level power line is located in the third, fourth and fifth conductive layers, and at least one of the fifth to eighth clock signal lines is located in at least two of the third, fourth and fifth conductive layers.

[0090] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0091] Thirdly, this disclosure also provides a method for preparing a display substrate, configured to prepare the above-mentioned display substrate, the method comprising:

[0092] Provide a base;

[0093] A gate drive circuit, a first low-level power supply line, and a second low-level power supply line located in a non-display area are formed on the substrate.

[0094] The gate drive circuit includes: a plurality of cascaded shift registers, at least one shift register including: a shift sub-circuit and an output sub-circuit, the shift sub-circuit including: at least one transistor, the output sub-circuit including: at least one output transistor; the orthographic projection of the first low-level power line on the substrate at least partially overlaps with the orthographic projection of at least one transistor in the shift sub-circuit on the substrate, and the orthographic projection of the second low-level power line on the substrate is located between the orthographic projection of at least one transistor in the shift sub-circuit on the substrate and the orthographic projection of at least one output transistor in the output sub-circuit on the substrate;

[0095] The width of the first low-level power line along the first direction is smaller than the width of the second low-level power line along the first direction.

[0096] In an exemplary embodiment, the method further includes:

[0097] A first clock signal line group, a second clock signal line group, an initial signal line, and a high-level power supply line are formed on the substrate in the non-display area.

[0098] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0099] Overview of the attached figures

[0100] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0101] Figure 1 is a schematic diagram of the structure of a display device;

[0102] Figure 2A is a schematic diagram of a planar structure of a display substrate;

[0103] Figure 2B is a schematic diagram of a planar structure of a display substrate;

[0104] Figure 2C is a schematic diagram of a planar structure of a display substrate;

[0105] Figure 3 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0106] Figure 4 is a timing diagram of the pixel driving circuit provided in Figure 3;

[0107] Figure 5 shows the equivalent circuit diagram of the shift register;

[0108] Figure 6 is the timing diagram of the shift register provided in Figure 5;

[0109] Figure 7 is a top view of the display substrate provided in an embodiment of this disclosure;

[0110] Figure 8 is a schematic diagram of multiple shift registers cascaded together;

[0111] Figure 9 is a top view of a four-stage shift register;

[0112] Figure 10 is a schematic diagram of a portion of the film layers in Figure 7;

[0113] Figure 11 is a schematic diagram of a portion of the film layers in Figure 7;

[0114] Figure 12 is a magnified view of a partial area of ​​Figure 7;

[0115] Figure 13 is a schematic diagram after the semiconductor layer pattern is formed in Figure 9;

[0116] Figure 14 is a schematic diagram of the first conductive layer pattern in Figure 9;

[0117] Figure 15 is a schematic diagram after the first conductive layer pattern in Figure 9 is formed;

[0118] Figure 16 is a schematic diagram of the second conductive layer pattern in Figure 9;

[0119] Figure 17 is a schematic diagram after the second conductive layer pattern is formed in Figure 9;

[0120] Figure 18 is a schematic diagram after the third insulating layer pattern is formed in Figure 9;

[0121] Figure 19 is a schematic diagram of the third conductive layer pattern in Figure 9;

[0122] Figure 20 is a schematic diagram after the third conductive layer pattern is formed in Figure 9;

[0123] Figure 21 is a schematic diagram after the first planarization layer pattern in Figure 9 is formed;

[0124] Figure 22 is a schematic diagram of the fourth conductive layer pattern in Figure 9;

[0125] Figure 23 is a schematic diagram of the fourth conductive layer pattern formed in Figure 9.

[0126] Detailed Explanation

[0127] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0128] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the length and spacing of each signal line along the first direction can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0129] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0130] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0131] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0132] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0133] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0134] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0135] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0136] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0137] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0138] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0139] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a gate driver, and a pixel array. The timing controller is connected to the data driver and the gate driver. The data driver is connected to multiple data signal lines (D1 to Dn), and the gate driver is connected to multiple gate lines (G1 to Gm). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the gate lines and the data signal lines.

[0140] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages that will be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number.

[0141] In an exemplary embodiment, the gate driver can generate scan signals to be provided to gate lines G1, G2, G3, ... to Gm by receiving a clock signal, a gate start signal, etc., from a timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to gate lines G1 to Gm. For example, the gate driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number.

[0142] Figure 2A is a schematic diagram of a planar structure of a display substrate (Figure 1), Figure 2B is a schematic diagram of a planar structure of a display substrate (Figure 22), and Figure 2C is a schematic diagram of a planar structure of a display substrate (Figure 23). As shown in Figures 2A to 2C, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a gate line and a data signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the gate line and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0143] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light.

[0144] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side or in a triangular pattern, which is not limited in this disclosure.

[0145] In an exemplary embodiment, a pixel unit may include three sub-pixels. These three sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement, etc., and this disclosure does not limit the specific arrangement. Figures 2A and 2B are illustrated using the example of a pixel unit comprising three sub-pixels. In Figure 2A, the three sub-pixels are arranged horizontally side-by-side, and in Figure 2B, the three sub-pixels are arranged in a triangular arrangement.

[0146] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged horizontally side-by-side, vertically side-by-side, or in a square, etc., and this disclosure does not limit the arrangement. Figure 2C illustrates an example where a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square.

[0147] The pixel driving circuit includes multiple transistors. These transistors include low-temperature polysilicon (LTPS) thin-film transistors and oxide transistors. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current.

[0148] When multiple transistors in a pixel driving circuit are low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), the display substrate containing the pixel driving circuit is called an LTPS display substrate, which has high mobility. When some transistors in the pixel driving circuit are LTPS TFTs, or some are LTPO TFTs, the display substrate containing the pixel driving circuit is called a low-temperature polycrystalline silicon and oxide semiconductor combined display substrate. This type of substrate integrates LTPS and oxide TFTs onto a single display substrate, forming an LTPO display substrate. It leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality. When multiple transistors in the pixel driving circuit are oxide semiconductor TFTs, the display substrate containing the pixel driving circuit is called an oxide semiconductor display substrate. Oxide semiconductor display substrates can achieve high-frequency and high-resolution displays while also reducing power consumption.

[0149] The pixel driving circuit in an oxide semiconductor display substrate can have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0150] Figure 3 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 3, the pixel driving circuit in the oxide semiconductor display substrate may include seven transistors (first transistor M1 to seventh transistor M7) and two storage capacitors (first storage capacitor Cst1 and second storage capacitor Cst2). Specifically, the gate electrode of the first transistor M1 is electrically connected to the first reset signal line Reset1, the first terminal of the first transistor M1 is electrically connected to the first initial signal line INIT1, and the second terminal of the first transistor M1 is electrically connected to the first node N1; the gate electrode of the second transistor M2 is electrically connected to the second reset signal line Gate2, the first terminal of the second transistor M2 is electrically connected to the first initial signal line INIT1, and the second terminal of the second transistor M2 is electrically connected to the fourth node N4; the gate electrode of the third transistor M3 is electrically connected to the first node N1, the first terminal of the third transistor M3 is electrically connected to the second node N2, and the second terminal of the third transistor M3 is electrically connected to the third node N3; the gate electrode of the fourth transistor M4 is electrically connected to the scan signal line Gate, the first terminal of the fourth transistor M4 is electrically connected to the data signal line Data, and the second terminal of the fourth transistor M4 is electrically connected to the first node N1; the gate electrode of the fifth transistor M5 is electrically connected to the first... A light-emitting signal line EM1 is electrically connected; the first electrode of the fifth transistor M5 is electrically connected to the first power supply line VDD; the second electrode of the fifth transistor M5 is electrically connected to the second node N2; the gate electrode of the sixth transistor M6 is electrically connected to the second light-emitting signal line EM2; the first electrode of the sixth transistor M6 is electrically connected to the third node N3; the second electrode of the sixth transistor M6 is electrically connected to the fifth node N5; the gate electrode of the seventh transistor M7 is electrically connected to the third reset signal line Reset3; the first electrode of the seventh transistor M7 is electrically connected to the third initial signal line INIT3; the second electrode of the seventh transistor M7 is electrically connected to the fifth node N5; the first plate of the first storage capacitor Cst1 is electrically connected to the third node N3; the second plate of the first storage capacitor Cst1 is electrically connected to the fourth node N4; the first plate of the second storage capacitor Cst2 is electrically connected to the first node N1; the second plate of the second storage capacitor Cst2 is electrically connected to the fourth node N4.

[0151] In an exemplary embodiment, at least one of the first transistors M1 to the seventh transistor M7 is an oxide semiconductor thin-film transistor.

[0152] In an exemplary embodiment, at least one of the first transistor M1 to the seventh transistor M7 is an N-type transistor.

[0153] In an exemplary embodiment, the light-emitting device L can be electrically connected to the fifth node N5 and the second power line VSS, respectively. For example, the first electrode of the light-emitting device L is connected to the fifth node N5, and the second electrode of the light-emitting device L is connected to the second power line VSS.

[0154] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the second power line VSS continuously provides a low-level signal.

[0155] In an exemplary embodiment, the voltage value of the signal on the first initial signal line INIT1 is constant and is a DC signal; the voltage value of the signal on the first initial signal line INIT1 can be -3V.

[0156] In an exemplary embodiment, the voltage value of the signal of at least one of the second initial signal line INIT2 and the third initial signal line INIT3 is constant and is a DC signal; the voltage value of the signal of at least one of the second initial signal line INIT2 and the third initial signal line INIT3 can be 0V.

[0157] In an exemplary embodiment, the signal received by the second initial signal line INIT2 and the signal received by the third initial signal line INIT3 can be the same signal.

[0158] In an exemplary embodiment, the first initial signal line INIT1 can receive a first initial signal. The first transistor M1 can be referred to as the first initial transistor. Under the signal control of the first reset signal line Reset1, the first transistor M1 writes the first initial signal into the first node N1 to initialize the first node N1.

[0159] In an exemplary embodiment, the second initial signal line INIT2 can receive a second initial signal. The second transistor M2 can be referred to as the second initial transistor. Under the signal control of the second reset signal line Reset2, the second transistor M2 writes the second initial signal to the fourth node N4 to initialize the fourth node N4.

[0160] In an exemplary embodiment, the third initial signal line INIT3 can receive a third initial signal. The seventh transistor M7 can be referred to as the second initial transistor. Under the signal control of the third reset signal line Reset3, the seventh transistor M7 writes the third initial signal into the fifth node N5, initializing the fifth node N5 (which is also the first electrode of the light-emitting device L).

[0161] In an exemplary embodiment, the third transistor M3 can be referred to as a driving transistor. The connection method of the third transistor in this disclosure can improve the output saturation characteristics of the third transistor M3.

[0162] In an exemplary embodiment, the data signal line Data can receive data signals, and the fourth transistor M4 can be referred to as the write transistor. Under the control of the signal of the scan signal line Gate, the fourth transistor M4 writes the data signal to the first node N1.

[0163] In an exemplary embodiment, the first power line VDD can receive a first power signal, and the fifth transistor M5 can be referred to as the first light-emitting transistor. Under the signal control of the first light-emitting signal line EM1, the fifth transistor M5 writes the first power signal into the second node N2. The sixth transistor M6 can be referred to as the second light-emitting transistor. Under the signal control of the second light-emitting signal line EM2, the sixth transistor M6 writes the drive signal output from the third node N3 into the fifth node N5 (which is also the first electrode of the light-emitting device L).

[0164] In an exemplary embodiment, the content displayed on the display substrate includes multiple display frames. Figure 4 is a timing diagram of the pixel driving circuit provided in Figure 3. Figure 4 is a timing diagram of the pixel driving circuit provided in Figure 3 operating in one display frame.

[0165] Referring to Figures 3 and 4, the operation of the pixel driving circuit can include:

[0166] In the first stage S1, also known as the initialization stage, the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, and the second light-emitting signal line EM2 are high-level signals, while the signals of the scan signal line Gate and the first light-emitting signal line EM1 are low-level signals. The first transistor M1, the second transistor M2, the sixth transistor M6, and the seventh transistor M7 are turned on, while the fourth transistor M4 and the fifth transistor M5 are turned off.

[0167] The first transistor M1 is turned on, and the first initial signal of the first initial signal line INIT1 is written to the first node N1 to initialize (reset) the first node N1, clearing its internal pre-stored voltage and completing the initialization. The second transistor M2 is turned on, and the second initial signal of the second initial signal line INIT2 is written to the fourth node N4 to initialize (reset) the fourth node N4, clearing its internal pre-stored voltage and completing the initialization. The sixth transistor T6 and the seventh transistor M7 are turned on, and the third initial signal of the third initial signal line INIT3 is written to the fifth node N5 and the third node N3 in sequence to initialize (reset) the third node N3 and the fifth node N5 (that is, the first electrode of the light-emitting device L), clearing its internal pre-stored voltage and completing the initialization.

[0168] The second stage, S2, is called the first buffer stage. The signals on the first reset signal line Reset1 and the second reset signal line Reset2 are high-level signals, while the signals on the scan signal line Gate, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals. The signal on the third reset signal line Reset3 changes from high-level to low-level. The first transistor M1 and the second transistor M2 are turned on, the seventh transistor M7 changes from an on state to an off state, and the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off.

[0169] When the first transistor M1 is turned on, the first initial signal of the first initial signal line INIT1 is continuously written to the first node N1 to initialize (reset) the first node N1, clearing its internal pre-stored voltage and completing the initialization. When the second transistor M2 is turned on, the second initial signal of the second initial signal line INIT2 is continuously written to the fourth node N4 to initialize (reset) the fourth node N4, clearing its internal pre-stored voltage and completing the initialization. During the period when the seventh transistor M7 is turned on, the third initial signal of the third initial signal line INIT3 is written to the fifth node N5 to initialize (reset) the fifth node N5 (that is, the first electrode of the light-emitting device L), clearing its internal pre-stored voltage and completing the initialization.

[0170] The third stage, S3, is called the threshold compensation stage. The signals of the first reset signal line Reset1, the second reset signal line Reset2, and the first light-emitting signal line EM1 are high-level signals, while the signals of the second light-emitting signal line EM2, the third reset signal line Reset3, and the scan signal line Gate are low-level signals. The first transistor M1, the second transistor M2, and the fifth transistor M5 are turned on, while the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are turned off.

[0171] The first transistor M1 is turned on, and the first initial signal of the first initial signal line INIT1 is continuously written to the first node N1. The second transistor M2 is turned on, and the second initial signal of the second initial signal line INIT2 is continuously written to the fourth node N4. The fifth transistor M5 is turned on, and the power signal of the first power line VDD is written to the third node N3 through the turned-on fifth transistor M5 and the third transistor M3, until the voltage value of the signal at the third node N3 is Vinit1-Vth, where Vinit1 is the voltage value of the first initial signal and Vth is the threshold voltage of the third transistor M3. The voltage difference stored in the first storage capacitor Cst1 is Vth, and the voltage difference stored in the second storage capacitor Cst2 is 0.

[0172] The fourth stage, S4, is called the second buffer stage. The signal on the second reset signal line Reset2 is high, while the signals on the first light-emitting signal line EM1, the second light-emitting signal line EM2, the third reset signal line Reset3, and the scan signal line Gate are low. The signal on the first reset signal line Reset1 changes from high to low. The second transistor M2 is turned on, the first transistor M1 changes from on to off, and the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned off.

[0173] During the conduction phase of the first transistor M1, the first initial signal of the first initial signal line INIT1 is written to the first node N1, the second transistor M2 is turned on, and the second initial signal of the second initial signal line INIT2 is continuously written to the fourth node N4.

[0174] The fifth stage, S5, is called the data writing stage. The second reset signal line Reset2 and the scan signal line Gate are high-level signals, while the first reset signal line Reset1, the third reset signal line Reset3, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals. The second transistor M2 and the fourth transistor M4 are turned on, the first transistor M1 and the fifth transistor M5 are turned on, and the sixth transistor M6 and the seventh transistor M7 are turned off.

[0175] When the second transistor M2 is turned on, the first initial signal of the first initial signal line INIT1 is continuously written to the fourth node N4, the signal of the third node N3 remains unchanged, the fourth transistor M4 is turned on, and the signal of the data signal line Data is written to the first node N1.

[0176] In the sixth stage, S6, also known as the third buffer stage, the signals of the scan signal line Gate, the first reset signal line Reset1, the third reset signal line Reset3, and the first light-emitting signal line EM1 are at low level. The signal of the second light-emitting signal line EM2 changes from low to high level, and the second reset signal line Reset2 changes from high to low level. The second transistor M2 changes from the on state to the off state, and the sixth transistor T6 changes from the off state to the on state. The first transistor M1, the fourth transistor T4, the fifth transistor M5, and the seventh transistor M7 are disconnected.

[0177] During the conduction phase of the second transistor M2, the second initial signal of the second initial signal line INIT2 is continuously written to the fourth node N4. During the conduction phase of the sixth transistor T6, the third node N3 and the fifth node N5 are connected.

[0178] In the seventh stage, S7, also known as the light-emitting stage, the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, while the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, and the scan signal line Gate are low-level signals. The fifth transistor M5 and the sixth transistor M6 are turned on, while the first transistor M1, the second transistor M2, the fourth transistor M4, and the seventh transistor M7 are turned off.

[0179] When the fifth transistor M5 and the sixth transistor M6 are turned on, the power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, third transistor M3 and sixth transistor M6, driving the light-emitting device L to emit light.

[0180] During the pixel driving circuit operation, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage value of the signal at the first node N1 is Vdata, and the voltage value of the signal at the third node N3 is Vinit1-Vth, the driving current I of the third transistor M3 is: I = K*(Vgs-Vth) 2 =K*[(Vdata-Vinit1+Vth)-Vth] 2 =K*(Vdata-Vinit1) 2

[0181] Here, the driving current is the driving current that drives the light-emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3.

[0182] In exemplary embodiments, the light-emitting device may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). Typical dimensions (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. Typical dimensions (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0183] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0184] In an exemplary embodiment, the gate driver includes at least one gate driving circuit. The number of gate driving circuits depends on the number of gate lines. Taking a display substrate including the pixel driving circuit shown in FIG3 as an example, the gate driving circuit includes a first scan driving circuit. The scan driving circuit can be electrically connected to a scan signal line.

[0185] In an exemplary embodiment, any gate driving circuit in the gate driver may include: a plurality of cascaded shift registers. At least one shift register includes: a shift sub-circuit and an output sub-circuit. The shift sub-circuit is electrically connected to a signal input terminal, a cascaded signal output terminal, a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a first low-level power supply terminal, and a high-level power supply terminal, respectively, and is configured to provide a signal from the second clock signal terminal or the high-level power supply terminal to the cascaded signal output terminal under the control of a signal from at least one of the signal input terminal, the first clock signal terminal, the third clock signal terminal, and the second power supply terminal. The output sub-circuit is also electrically connected to the shift sub-circuit, a fourth clock signal terminal, a first low-level power supply terminal, a second low-level power supply terminal, and a drive signal output terminal, respectively, and is configured to provide a signal from the second low-level power supply terminal or the fourth clock signal terminal to the drive signal output terminal.

[0186] In some embodiments, Figure 5 is an equivalent circuit diagram of a shift register. As shown in Figure 5, the shift sub-circuit in at least one stage of the shift register includes an output sub-circuit. For example, the shift sub-circuit in at least one stage of the shift register includes a first node, a second node N2, and a third node N3. Under the control of the first node, the second node N2, and the third node N3, the shift sub-circuit provides a second clock signal or a high-level power supply signal to the cascaded signal output terminal. The output sub-circuit is coupled to the second node N2 and the third node N3, and under the control of the second node N2 and the third node N3, provides a second low-level power supply or a fourth clock signal to the drive signal output terminal.

[0187] As shown in Figure 5, the shift sub-circuit in at least one level shift register includes at least a portion of the first transistor T1 to the eighth transistor T8 and the first capacitor C1, and the output sub-circuit includes the ninth transistor T9 to the eleventh transistor T11, the second capacitor C2 and the third capacitor C3.Specifically, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first terminal of the first transistor T1 is electrically connected to the signal input terminal IN, and the second terminal of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first terminal of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second terminal of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first terminal of the third transistor T3 is electrically connected to the first low-level power supply terminal VGL1, and the second terminal of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, and the fourth transistor... The first terminal of transistor T4 is electrically connected to the high-level power supply terminal VGH; the second terminal of transistor T4 is electrically connected to the cascaded signal output terminal Carry; the control terminal of transistor T5 is electrically connected to the third node N3; the first terminal of transistor T5 is electrically connected to the second clock signal terminal CK2; the second terminal of transistor T5 is electrically connected to the cascaded signal output terminal Carry; the control terminal of transistor T6 is electrically connected to the second node N2; the first terminal of transistor T6 is electrically connected to the high-level power supply terminal VGH; the second terminal of transistor T6 is electrically connected to the fourth node N4; the control terminal of transistor T7 is electrically connected to the third clock signal terminal CK3; the first terminal of transistor T7 is electrically connected to the fourth node N4; the seventh... The second terminal of transistor T7 is electrically connected to the first node N1; the control terminal of the eighth transistor T8 is electrically connected to the first low-level power supply terminal VGL1, the first terminal of the eighth transistor T8 is electrically connected to the first node N1, and the second terminal of the eighth transistor T8 is electrically connected to the third node N3; the control terminal of the ninth transistor T9 is electrically connected to the fifth node N5, the first terminal of the ninth transistor T9 is electrically connected to the second low-level power supply terminal VGL2, and the second terminal of the ninth transistor T9 is electrically connected to the drive signal output terminal GOUT; the control terminal of the tenth transistor T10 is electrically connected to the third node N3, the first terminal of the tenth transistor T10 is electrically connected to the fourth clock signal terminal CK4, and the second terminal of the tenth transistor T10 is electrically connected to the drive signal output terminal GOUT. The control electrode of the eleventh transistor T11 is electrically connected to the first low-level power supply terminal VGL1; the first electrode of the eleventh transistor T11 is electrically connected to the second node N2; and the second electrode of the eleventh transistor T11 is electrically connected to the fifth node N5. The first plate C11 of the first capacitor C1 is electrically connected to the third node N3; and the second plate of the first capacitor C1 is electrically connected to the cascaded signal output terminal Carry. The first plate C21 of the second capacitor C2 is electrically connected to the fifth node N5; and the second plate C22 of the second capacitor C2 is electrically connected to the second low-level power supply terminal VGL2. The first plate C31 of the third capacitor C3 is electrically connected to the fourth clock signal terminal CK4; and the second plate C32 of the third capacitor C3 is electrically connected to the fifth node N5.

[0188] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0189] In an exemplary embodiment, at least one of the first transistor T1 to the eleventh transistor T11 may be a P-type transistor.

[0190] In an exemplary embodiment, the duration of the first signal at at least one of the first clock signal terminals CK1, CK2, and CK3 of the at least one-level shift register being the duration of the second signal in one cycle is greater than the duration of the second signal in one cycle of the first clock signal terminal CK1, CK2, and CK3 of the at least one-level shift register. The first signal is a positive voltage signal, and the second signal is a negative voltage signal.

[0191] In an exemplary embodiment, the duration of the signal at the fourth clock signal terminal CK4 of at least one shift register being the first signal within one cycle is less than the duration of the signal at the fourth clock signal terminal CK4 of at least one shift register being the second signal within one cycle.

[0192] In an exemplary embodiment, the duration of the first signal at at least one of the first clock signal terminals CK1, CK2, and CK3 of the at least one-level shift register is greater than the period of the signal at the fourth clock signal terminal CK4 of the at least one-level shift register within one cycle.

[0193] In an exemplary embodiment, the shift sub-circuit outputs a cascaded signal to the cascaded signal output terminal for other shift registers, and the output sub-circuit outputs a drive signal to the drive signal output terminal for the pixel drive circuit.

[0194] In an exemplary embodiment, the signal input terminal of at least one shift register is electrically connected to the cascaded signal output terminal of at least one shift register.

[0195] Figure 6 is the timing diagram of the shift register provided in Figure 5. Figure 6 is illustrated using the example where all transistors in Figure 5 are P-type transistors. In Figure 5, the eighth transistor T8 and the eleventh transistor T11 are always on.

[0196] As shown in Figures 5 and 6, the operation of the shift register in Figure 5 may include:

[0197] In the first stage, the signals at P11, signal input IN, first clock signal CK1, and fourth clock signal CK4 are low-level signals, while the signals at the second clock signal CK2 and third clock signal CK3 are high-level signals. The first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off.

[0198] The first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written to the first node N1. The first node N1 is written to the third node N3 through the turned-on eighth transistor T8. The signals of the first node N1 and the third node N3 are low-level signals. The second transistor T2, the fifth transistor T5, and the tenth transistor T10 are turned on, and the low-level signal of the first clock signal terminal CK1 is written to the second node N2. The high-level signal of the second clock signal terminal CK2 is written to the cascaded signal output terminal Carry. The low-level signal of the fourth clock signal terminal CK4 is written to the drive signal output terminal GOUT. The third transistor T3 is turned on, and the signal of the first low-level power supply terminal VGL1 is written to the second node N2. The signal of the second node N2 is low-level signal. The signal of the second node N2 is written to the fifth node N5 through the turned-on eleventh transistor T11. The fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are turned on, and the high-level signal of the high-level power supply terminal VGH is written to the fourth node N4 and the cascaded signal output terminal Carry. The low-level signal of the second low-level power supply terminal VGL2 is written to the drive signal output terminal GOUT.

[0199] During this stage, the signals of the first node N1, the second node N2, the third node N3, and the fifth node N5 are low-level signals, the signal of the fourth node N4 is a high-level signal, the cascade signal output terminal Carry outputs a high-level signal, and the drive signal output terminal GOUT outputs a low-level signal.

[0200] In the second stage, the signals at P12, the signal input terminal IN, and the fourth clock signal terminal CK4 are low-level signals, while the signals at the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 are high-level signals. The first transistor T1, the third transistor T3, and the seventh transistor T7 are disconnected.

[0201] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 maintain the low level signal of the previous stage. The second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned on. The high level signal of the first clock signal terminal CK1 is written to the second node N2. The high level signal of the second clock signal terminal CK2 is written to the cascaded signal output terminal Carry. The low level signal of the fourth clock signal terminal CK4 is written to the drive signal output terminal GOUT. The high level signal of the second node N2 is written to the fifth node N5 through the turned-on eleventh transistor T11. The fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned off.

[0202] In this stage, the signals of the first node N1 and the third node N3 are low-level signals, the signals of the second node N2 and the fifth node N5 are high-level signals, the cascade signal output terminal Carry outputs a high-level signal, and the drive signal output terminal GOUT outputs a low-level signal.

[0203] In the third stage, the signals at P13, signal input IN, second clock signal CK2, and fourth clock signal CK4 are low-level signals, while the signals at first clock signal CK1 and third clock signal CK3 are high-level signals. First transistor T1, third transistor T3, and seventh transistor T7 are disconnected.

[0204] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 maintain the low level signal of the previous stage. The second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned on. The high level signal of the first clock signal terminal CK1 is written to the second node N2. The low level signal of the second clock signal terminal CK2 is written to the cascade signal output terminal Carry. The low level signal of the fourth clock signal terminal CK4 is written to the drive signal output terminal GOUT. The high level signal of the second node N2 is written to the fifth node N5 through the turned-on eleventh transistor T11. The fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned off.

[0205] In this stage, the signals of the first node N1 and the third node N3 are low-level signals, while the signals of the second node N2, the fourth node N4, and the fifth node N5 are high-level signals. The cascade signal output terminal Carry outputs the cascade signal, which is a low-level signal. The drive signal output terminal GOUT outputs a low-level signal.

[0206] In the fourth stage, the signals at P14, the signal input terminal IN, and the second clock signal terminal CK2 are low-level signals, while the signals at the first clock signal terminal CK1, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 are high-level signals. The first transistor T1, the third transistor T3, and the seventh transistor T7 are disconnected.

[0207] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 remain at the low level of the previous stage. The second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned on. The high level signal of the first clock signal terminal CK1 is written to the second node N2. The low level signal of the second clock signal terminal CK2 is written to the cascaded signal output terminal Carry. The high level signal of the fourth clock signal terminal CK4 is written to the drive signal output terminal GOUT. The high level signal of the second node N2 is written to the fifth node N5 through the turned-on eleventh transistor T11. The fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned off.

[0208] In this stage, the signals of the first node N1 and the third node N3 are low-level signals, while the signals of the second node N2, the fourth node N4, and the fifth node N5 are high-level signals. The cascade signal output terminal Carry outputs the cascade signal, which is a low-level signal. The drive signal output terminal GOUT outputs the drive signal, which is a high-level signal.

[0209] In the fifth stage, the signals at P15, the second clock signal terminal CK2, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 are low-level signals, while the signals at the signal input terminal IN and the first clock signal terminal CK1 are high-level signals. The first transistor T1 and the third transistor T3 are off, and the seventh transistor T7 is on.

[0210] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 remain at the low level of the previous stage. The second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned on. The high level signal of the first clock signal terminal CK1 is written to the second node N2. The low level signal of the second clock signal terminal CK2 is written to the cascaded signal output terminal Carry. The low level signal of the fourth clock signal terminal CK4 is written to the drive signal output terminal GOUT. The high level signal of the second node N2 is written to the fifth node N5 through the turned-on eleventh transistor T11. The fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned off. The seventh transistor T7 is turned on. The signal of the first node N1 is written to the fourth node N4.

[0211] In this stage, the signals of the first node N1, the third node N3, and the fourth node N4 are low-level signals, the signals of the second node N2 and the fifth node N5 are high-level signals, the cascade signal output terminal Carry outputs the cascade signal, the cascade signal is a low-level signal, and the drive signal output terminal GOUT outputs a low-level signal.

[0212] In the sixth stage, the signals at P16, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 are low-level signals, while the signals at the signal input terminal IN, the first clock signal terminal CK1, and the second clock signal terminal CK2 are high-level signals. The first transistor T1 and the third transistor T3 are off, and the seventh transistor T7 is on.

[0213] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 remain at the low level of the previous stage. The second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned on. The high level signal of the first clock signal terminal CK1 is written to the second node N2. The high level signal of the second clock signal terminal CK2 is written to the cascaded signal output terminal Carry. The low level signal of the fourth clock signal terminal CK4 is written to the drive signal output terminal GOUT. The high level signal of the second node N2 is written to the fifth node N5 through the turned-on eleventh transistor T11. The fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned off. The seventh transistor T7 is turned on. The signal of the first node N1 is written to the fourth node N4.

[0214] In this stage, the signals of the first node N1, the third node N3, and the fourth node N4 are low-level signals, the signals of the second node N2 and the fifth node N5 are high-level signals, the cascade signal output terminal Carry outputs the cascade signal, which is a high-level signal, and the drive signal output terminal GOUT outputs a low-level signal.

[0215] In stage seven (P17), the signal at the first clock signal terminal CK1 is low, while the signals at the signal input terminal IN and the second clock signal terminal CK2 are high. The signal at the third clock signal terminal CK3 changes from low to high, and the signal at the fourth clock signal terminal CK4 changes from low to high and then back to low. The first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 changes from on to off.

[0216] The first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is written to the first node N1. The signal at the first node N1 is written to the third node N3 through the turned-on eighth transistor T8. The signals at the first node N1 and the third node N3 are high-level signals. The second transistor T2, the fifth transistor T5, and the tenth transistor T10 are turned off. The third transistor T3 is turned on, and the signal at the first low-level power supply terminal VGL1 is written to the second node N2. The signal at the second node N2 is low-level. The signal at the second node N2 is written to the fifth node N5 through the turned-on eleventh transistor T11. The fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are turned on, and the high-level signal at the high-level power supply terminal VGH is written to the fourth node N4 and the cascaded signal output terminal Carry. The low-level signal at the second low-level power supply terminal VGL2 is written to the drive signal output terminal GOUT.

[0217] In this stage, the signals of the second node N2 and the fifth node N5 are low-level signals, while the signals of the first node N1, the third node N3, and the fourth node N4 are high-level signals. The cascade signal output terminal Carry outputs a low-level signal, and the drive signal output terminal GOUT outputs a low-level signal.

[0218] In stage 8, the signals at P18 and the fourth clock signal terminal CK4 are low-level signals, while the signals at signal input terminal IN, the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 are high-level signals. The first transistor T1, the third transistor T3, and the seventh transistor T7 are disconnected.

[0219] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 remain at the high level of the previous stage. The second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned off. Under the combined action of the second capacitor C2 and the third capacitor C3, the second node N2 and the fifth node N5 remain at the low level of the previous stage. The fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned on. The high level signal of the high-level power supply terminal VGH is written to the fourth node N4 and the cascaded signal output terminal Carry. The low level signal of the first low-level power supply terminal VGL1 is written to the drive signal output terminal GOUT.

[0220] In this stage, the signals of the first node N1, the third node N3, and the fourth node N4 are high-level signals, the signals of the second node N2 and the fifth node N5 are low-level signals, the cascade signal output terminal Carry outputs a high-level signal, and the drive signal output terminal GOUT outputs a low-level signal.

[0221] In the ninth stage (P19), the signal at the second clock signal terminal CK2 is low, while the signals at the signal input terminal IN and the first clock signal terminal CK1 are high. The signal at the third clock signal terminal CK3 changes from high to low, and the signal at the fourth clock signal terminal CK4 changes from low to high and then back to low. The first transistor T1 and the third transistor T3 are disconnected. The seventh transistor T7 changes from off to on.

[0222] Under the action of the first capacitor C1, the signals of the first node N1 and the third node N3 remain at the high level of the previous stage. The second transistor T2, the fifth transistor T5 and the tenth transistor T10 are turned off. Under the combined action of the second capacitor C2 and the third capacitor C3, the second node N2 and the fifth node N5 remain at the low level of the previous stage. The fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are turned on. The high level signal of the high-level power supply terminal VGH is written to the fourth node N4 and the cascaded signal output terminal Carry. The low level signal of the first low-level power supply terminal VGL1 is written to the drive signal output terminal GOUT.

[0223] In this stage, the signals of the first node N1, the third node N3, and the fourth node N4 are high-level signals, the signals of the second node N2 and the fifth node N5 are low-level signals, the cascade signal output terminal Carry outputs a high-level signal, and the drive signal output terminal GOUT outputs a low-level signal.

[0224] In an exemplary embodiment, the fifth node P15 and the sixth stage P16 occur cyclically until the signal at the signal input terminal IN becomes a low-level signal.

[0225] The poor output stability of the gate drive circuit of the display substrate affects the display effect.

[0226] To this end, this disclosure provides a display substrate having a display area and a non-display area located on at least one side of the display area. Figure 7 is a top view of the display substrate provided in an embodiment of this disclosure. As shown in Figure 7, the display substrate provided in an embodiment of this disclosure includes: a substrate and a gate driving circuit disposed on the substrate and located in the non-display area, a first low-level power supply line VL1 and a second low-level power supply line VL2. The gate driving circuit includes: a plurality of cascaded shift registers, at least one of which includes: a shift sub-circuit and an output sub-circuit. The shift sub-circuit is electrically connected to the first low-level power supply terminal and the cascaded signal output terminal, respectively. The output sub-circuit is electrically connected to the first low-level power supply terminal, the second low-level power supply terminal and the drive signal output terminal, respectively.

[0227] In an exemplary embodiment, the shift sub-circuit includes at least one transistor. Exemplarily, the shift sub-circuit includes a first transistor T1 through an eighth transistor T8. The output sub-circuit includes at least one output transistor. Exemplarily, the output sub-circuit includes a ninth transistor T9 through an eleventh transistor T11, wherein the ninth transistor T9 and the tenth transistor T10 are output transistors.

[0228] In an exemplary embodiment, a first low-level power line VL1 is electrically connected to a first low-level power supply terminal of at least one level shift register, and a second low-level power line VL2 is electrically connected to a second low-level power supply terminal of at least one level shift register. The second low-level power line VL2 is located on the side of the first low-level power line VL1 that is closer to the display area.

[0229] In an exemplary embodiment, as shown in FIG7, the orthographic projection of the first low-level power line VL1 on the substrate at least partially overlaps with the orthographic projection of at least one transistor (e.g., the first transistor T1 to the eighth transistor T8) on the substrate in the shift sub-circuit, and the orthographic projection of the second low-level power line VL2 on the substrate lies between the orthographic projection of at least one transistor (e.g., the first transistor T1 to the eighth transistor T8) on the substrate in the shift sub-circuit and the orthographic projection of at least one output transistor (e.g., the ninth transistor T9 and the tenth transistor T10) on the substrate in the output sub-circuit.

[0230] In an exemplary embodiment, as shown in FIG7, the line width of the first low-level power line VL1 along the first direction D1 is smaller than the line width of the second low-level power line VL2 along the first direction D1.

[0231] This disclosure separates the first low-level power supply line connected to the shift sub-circuit and the second low-level power supply line connected to the output sub-circuit. The line width of the first low-level power supply line along the first direction is smaller than that of the second low-level power supply line along the first direction. The smaller line width of the first low-level power supply line along the first direction and the fact that the orthographic projection of the first low-level power supply line on the substrate at least partially overlap with the orthographic projection of at least one transistor in the shift sub-circuit on the substrate can achieve a narrow bezel. The larger line width of the second low-level power supply line along the first direction can ensure the output stability of the shift register.

[0232] In an exemplary embodiment, as shown in FIG7, at least one of the first low-level power lines VL1 and the second low-level power lines VL2 extends at least partially along the second direction D2, and the first direction D1 and the second direction D2 intersect. Exemplarily, the first direction D1 and the second direction D2 are disposed.

[0233] In an exemplary embodiment, the signal of at least one of the first low-level power line VL1 and the second low-level power line VL2 is a negative voltage signal, and the absolute value of the voltage value of the power signal of the first low-level power line VL1 is less than the absolute value of the voltage value of the power signal of the second low-level power line VL2.

[0234] In this disclosure, the absolute value of the voltage of the power supply signal of the first low-level power supply line VL1 is less than the absolute value of the voltage of the power supply signal of the second low-level power supply line VL2, which can ensure the stability of the output of the shift register.

[0235] In an exemplary embodiment, the voltage value of the power signal of the first low-level power line VL1 can be in the range of -2 volts to -10 volts. The voltage value of the power signal of the first low-level power line VL1 can be -6 volts.

[0236] In an exemplary embodiment, the voltage value of the power signal of the second low-level power line VL2 can be in the range of -4 volts to -12 volts. The voltage value of the power signal of the second low-level power line VL2 can be -8 volts.

[0237] In an exemplary embodiment, the linewidth of the first low-level power line VL1 along the first direction D1 can be in the range of 4 micrometers to 20 micrometers. For example, the linewidth of the first low-level power line VL1 along the first direction D1 can be 8 micrometers.

[0238] In an exemplary embodiment, the linewidth of the second low-level power line VL2 along the first direction D1 can be in the range of 4 micrometers to 50 micrometers. For example, the linewidth of the second low-level power line VL2 along the first direction D1 can be 15 micrometers.

[0239] In an exemplary embodiment, the display substrate further includes: a circuit structure layer disposed on the substrate, the circuit structure layer comprising: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a first planarization layer, and a fourth conductive layer sequentially stacked on the substrate, or comprising: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a first planarization layer, a fourth conductive layer, a second planarization layer, and a fifth conductive layer sequentially stacked on the substrate. At least one level of shift register includes: multiple transistors and multiple capacitors, and a gate driving circuit, a first low-level power supply line, and a second low-level power supply line are disposed in the circuit structure layer.

[0240] The semiconductor layer includes at least: an active pattern of at least one transistor of a plurality of transistors in at least one level shift register.

[0241] The first conductive layer includes: the control electrode of at least one transistor of a plurality of transistors located in at least one level shift register, and the first plate of at least one capacitor of a plurality of capacitors.

[0242] The second conductive layer includes: the second plate of at least one capacitor located in at least one of the transistors of at least one level shift register.

[0243] The third conductive layer includes: the first and second terminals of at least one transistor among a plurality of transistors in at least one level shift register.

[0244] In an exemplary embodiment, the first low-level power line VL1 can be a single-layer structure or a multi-layer structure. The first low-level power line VL1 includes at least one first power connection line. The multi-layer structure can be a two-layer structure, a three-layer structure, or a more layer structure, and this disclosure does not limit it in any way.

[0245] In an exemplary embodiment, the second low-level power line VL2 can be a multi-layer structure. The second low-level power line VL2 includes: multiple second power connection lines arranged in different layers and interconnected with each other. The second power connection lines extend at least partially along a second direction, the multiple second power connection lines are stacked sequentially in a direction away from the substrate, and at least two of the multiple second power connection lines have orthographic projections on the substrate that at least partially overlap.

[0246] In this disclosure, multiple second power supply lines in the second low-level power supply line VL2 are connected in parallel, and the parallel connection of multiple second power supply lines can reduce the resistance of the second low-level power supply line VL2.

[0247] In an exemplary embodiment, the number of first power connection lines included in the first low-level power line VL1 is less than the number of second power connection lines included in the second low-level power line VL2. For example, the number of first power connection lines included in the first low-level power line VL1 can be 1, and the number of second power connection lines included in the second low-level power line VL2 can be 2; alternatively, the number of first power connection lines included in the first low-level power line VL1 can be 2, and the number of second power connection lines included in the second low-level power line VL2 can be 3.

[0248] In an exemplary embodiment, at least one first power connection line is disposed in the same layer as at least one of the plurality of second power connection lines, and the film layer containing at least one of the plurality of second power connection lines is located on the side of the film layer containing at least one first power connection line closer to the substrate.

[0249] In an exemplary embodiment, when the first low-level power line includes multiple first power connection lines, at least two of the multiple first power connection lines may have the same or different line widths along the first direction. The line width of the first low-level power line along the first direction is the line width of the first power connection line with the largest line width along the first direction among the multiple first power connection lines. The more first power connection lines the first low-level power line includes, the smaller the line width of the first low-level power line along the first direction can be.

[0250] In an exemplary embodiment, at least two of the plurality of second power connection lines may have the same or different line widths along the first direction. The line width of the second low-level power line along the first direction is the line width of the second power connection line with the largest line width along the first direction among the plurality of second power connection lines. The more second power connection lines the second low-level power line includes, the smaller the line width of the second low-level power line along the first direction can be.

[0251] In an exemplary embodiment, the first low-level power line VL1 includes a first power connection line, and the second low-level power line VL2 includes two second power connection lines that are disposed on different layers and interconnected, with the second power connection line located on the side of the first power connection line away from the substrate. The first power connection line and the second power connection line are disposed on the same layer.

[0252] In an exemplary embodiment, when the first low-level power line VL1 includes a first power connection line and the second low-level power line VL2 includes two second power connection lines that are disposed in different layers and connected to each other, the first power connection line may be located in the fourth conductive layer, the first second power connection line may be located in the third conductive layer, and the second second power connection line may be located in the fourth conductive layer.

[0253] In an exemplary embodiment, the first low-level power line VL1 includes two first power connection lines that are disposed on different layers and interconnected. The second low-level power line VL2 includes three second power connection lines that are disposed on different layers and interconnected. The second first power connection line is located on the side of the first first power connection line away from the substrate, the first second power connection line is located on the side of the second second power connection line close to the substrate, and the third second power connection line is located on the side of the second second power connection line away from the substrate. The first first power connection line and the second second power connection line are disposed on the same layer, and the second first power connection line and the third second power connection line are disposed on the same layer.

[0254] In an exemplary embodiment, the first low-level power line VL1 includes two first power connection lines that are disposed on different layers and interconnected with each other. When the second low-level power line VL2 includes three second power connection lines that are disposed on different layers and interconnected with each other, the first first power connection line is located in the fourth conductive layer, the second first power connection line is located in the fifth conductive layer, the first second power connection line is located in the third conductive layer, the second second power connection line is located in the fourth conductive layer, and the third second power connection line is located in the fifth conductive layer.

[0255] In an exemplary embodiment, as shown in FIG7, the display substrate further includes: a first clock signal line group disposed on the substrate and located in the non-display area; at least one level shift register including: a first clock signal terminal, a second clock signal terminal and a third clock signal terminal; the shift sub-circuit of the at least one level shift register is respectively connected to the first clock signal terminal, the second clock signal terminal and the third clock signal terminal; the first clock signal line group includes: a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3 and a fourth clock signal line CLK4 arranged sequentially along the direction close to the display area.

[0256] In an exemplary embodiment, as shown in FIG7, at least one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 extends at least partially along the second direction D2.

[0257] In an exemplary embodiment, Figure 8 is a schematic diagram of the cascaded multiple shift registers, and Figure 9 is a top view of a four-stage shift register. As shown in Figures 8 and 9, the first clock signal terminal of the 4i-3 stage shift register GOA(4i-3) is electrically connected to the first clock signal line CLK1, the second clock signal terminal of the 4i-3 stage shift register GOA(4i-3) is electrically connected to the second clock signal line CLK2, the third clock signal terminal of the 4i-3 stage shift register GOA(4i-3) is electrically connected to the third clock signal line CLK3, the first clock signal terminal of the 4i-2 stage shift register GOA(4i-2) is electrically connected to the second clock signal line CLK2, the second clock signal terminal of the 4i-2 stage shift register GOA(4i-2) is electrically connected to the third clock signal line CLK3, and the third clock signal terminal of the 4i-2 stage shift register GOA(4i-2) is electrically connected to the fourth clock signal line CLK3. Signal line CLK4 is electrically connected. The first clock signal terminal of the 4i-1 stage shift register GOA(4i-1) is electrically connected to the third clock signal line CLK3. The second clock signal terminal of the 4i-1 stage shift register GOA(4i-1) is electrically connected to the fourth clock signal line CLK4. The third clock signal terminal of the 4i-1 stage shift register GOA(4i-1) is electrically connected to the first clock signal line CLK1. The first clock signal terminal of the 4i stage shift register GOA(4i) is electrically connected to the fourth clock signal line CLK4. The second clock signal terminal of the 4i stage shift register GOA(4i) is electrically connected to the first clock signal line CLK1. The third clock signal terminal of the 4i stage shift register GOA(4i) is electrically connected to the second clock signal line CLK2.

[0258] In an exemplary embodiment, as shown in FIG7, the orthographic projection of the first low-level power line VL1 on the substrate is located between the orthographic projection of the second clock signal line CLK2 on the substrate and the orthographic projection of the third clock signal line CLK3 on the substrate, and the orthographic projection of the second low-level power line VL2 on the substrate is located on the side of the orthographic projection of at least one clock signal line in the first clock signal line group on the substrate that is closer to the display area.

[0259] In an exemplary embodiment, FIG10 is a schematic diagram of a portion of the film layers in FIG7. FIG10 includes: a first conductive layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first planarization layer, and a fourth conductive layer. As shown in FIG10, the control electrode 12 of the first transistor T1 and the control electrode 32 of the third transistor T3 are integral structures and extend at least partially along the first direction D1. The orthographic projection of the control electrode 12 of the first transistor T1 on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power supply line VL1, the third clock signal line CLK3, and the fourth clock signal line CLK4. The orthographic projection of the control electrode 12 of the first transistor T1 on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power supply line VL1, the third clock signal line CLK3, and the fourth clock signal line CLK4. This ensures that the overlapping area between the control electrode 12 of the first transistor T1 and the first clock signal line group is the same in at least two stages of the cascaded shift registers. Consequently, the coupling capacitance between the control electrode 12 of the first transistor T1 and the first clock signal line group is approximately the same in at least two stages of the shift registers, thus guaranteeing the reliability of the shift registers.

[0260] In an exemplary embodiment, FIG11 is a second schematic diagram of a portion of the film layers in FIG7. FIG11 includes a semiconductor layer, a first conductive layer, a second insulating layer, and a second conductive layer. As shown in FIG11, the display substrate is further provided with a plurality of vias H1 exposing the control electrode 12 of the first transistor T1, and two of the vias exposing the control electrode 12 of the first transistor T1 expose both ends of the control electrode 12 of the first transistor T1. In this disclosure, exposing two of the vias exposing the control electrode 12 of the first transistor T1 exposes both ends of the control electrode 12 of the first transistor T1 to avoid static electricity in the shift register.

[0261] In an exemplary embodiment, referring to Figures 7 and 10, at least a portion of the control electrode 22 of the second transistor T2 extends along the first direction D1, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the signal lines, the second clock signal line CLK2 and the first low-level power supply line VL1.

[0262] In an exemplary embodiment, referring to Figures 7 and 10, the control electrode 42 of the fourth transistor T4 and the control electrode 62 of the sixth transistor T6 are an integral structure and extend at least partially along the first direction D1. The orthographic projection of the control electrode 42 of the fourth transistor T4 on the substrate at least partially overlaps with the orthographic projection of at least one of the third clock signal line CLK3 and the fourth clock signal line CLK4 on the substrate.

[0263] In an exemplary embodiment, referring to Figures 7 and 10, the control electrode 52 of the fifth transistor T5 extends at least partially along the first direction D1, and its orthogonal projection on the substrate at least partially overlaps with the orthogonal projections on the substrate of at least one of the following signal lines: the second clock signal line CLK2, the first low-level power supply line VL1, the third clock signal line CLK3, and the fourth clock signal line CLK4.

[0264] In an exemplary embodiment, referring to Figures 7 and 10, the control electrode 72 of the seventh transistor T7 extends at least partially along the first direction D1, and its orthogonal projection on the substrate at least partially overlaps with the orthogonal projections on the substrate of at least one of the following signal lines: the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power supply line VL1, the third clock signal line CLK3, and the fourth clock signal line CLK4.

[0265] In an exemplary embodiment, as shown in FIG11, the display substrate is further provided with a plurality of vias H2 exposing the control electrode 72 of the seventh transistor T7, and two of the vias exposing the control electrode 72 of the seventh transistor T7 expose both ends of the control electrode 72 of the seventh transistor T7. The fact that two of the vias exposing the control electrode 72 of the seventh transistor T7 in this disclosure can avoid static electricity in the shift register.

[0266] In an exemplary embodiment, referring to Figures 7 and 10, the control electrode 82 of the eighth transistor T8 extends at least partially along the first direction D1, and its orthogonal projection on the substrate at least partially overlaps with the orthogonal projections on the substrate of at least one of the following signal lines: the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power supply line VL1, the third clock signal line CLK3, and the fourth clock signal line CLK4. In at least one shift register, the control electrode 82 of the eighth transistor T8 and the control electrode 112 of the eleventh transistor T11 are integrally formed.

[0267] In an exemplary embodiment, as shown in FIG10, the display substrate may further include: a plurality of first connection lines L1 disposed on the substrate and located in the non-display area, one of the plurality of first connection lines L1 being electrically connected to the first terminal 53 of the fifth transistor T5 of at least one level shift register, and the first connection line L1 extending along the first direction D1.

[0268] In an exemplary embodiment, referring to Figures 7 and 10, the orthographic projection of the first pole 53 of the fifth transistor of at least one level shift register on the substrate at least partially overlaps with the orthographic projection of the fourth clock signal line CLK4 and one of the plurality of first connection lines L1 on the substrate. The orthographic projection of one of the plurality of first connection lines L1 on the substrate at least partially overlaps with the orthographic projection of at least one of the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power supply line VL1, and the third clock signal line CLK3 on the substrate.

[0269] In an exemplary embodiment, the film layer containing the first connection line L1 is located on the side of the film layer containing the first and second electrodes of at least one transistor in at least one level of shift register, closer to the substrate. Exemplarily, the first connection line L1 may be located in either a first conductive layer or a second conductive layer. Figure 7 illustrates an example where the first connection line L1 is located in the second conductive layer.

[0270] In an exemplary embodiment, as shown in FIG11, the display substrate further includes a plurality of vias H3 exposing the first connection line L1, wherein two of the vias exposing the first connection line respectively expose one end of the first connection line near the display area and the other end far from the display area. In this disclosure, having two of the vias exposing the first connection line respectively expose one end near the display area and the other end far from the display area can avoid static electricity in the shift register.

[0271] In an exemplary embodiment, as shown in Figures 7 and 10, the line width of one of the first low-level power lines VL1 and VL2 along the first direction D1 is smaller than the line width of at least one clock signal line in the first clock signal line group along the first direction D1.

[0272] In an exemplary embodiment, as shown in FIG7, the display substrate further includes: a second clock signal line group disposed on the substrate and located in the non-display area, the second clock signal line group being located on the side of the first clock signal line group closer to the display area, at least one level shift register including: a fourth clock signal terminal, the output sub-circuit of at least one level shift register being electrically connected to the fourth clock signal terminal, and the second clock signal line group including: a fifth clock signal line CLK5, a sixth clock signal line CLK6, a seventh clock signal line CLK7 and an eighth clock signal line CLK8 arranged sequentially along the direction closer to the display area.

[0273] In an exemplary embodiment, as shown in FIG7, the fifth clock signal line CLK5 and the seventh clock signal line CLK7 receive the same clock signal, the sixth clock signal line CLK6 and the eighth clock signal line CLK8 receive the same signal, and at least one of the fifth clock signal line CLK5, the sixth clock signal line CLK6, the seventh clock signal line CLK7 and the eighth clock signal line CLK8 extends at least partially along the second direction D2.

[0274] In an exemplary embodiment, as shown in FIG7, the fourth clock signal terminal of at least one level shift register is electrically connected to one of the signal line groups of the first signal line group and the second signal line group. The fourth clock signal terminals of adjacent shift registers are connected to different signal line groups. The first signal line group includes: the fifth clock signal line CLK5 and the seventh clock signal line CLK7, and the second signal line group includes: the sixth clock signal line CLK6 and the eighth clock signal line CLK8.

[0275] In an exemplary embodiment, as shown in FIG7, the orthographic projection of the second low-level power line VL2 on the substrate is located between the orthographic projection of the sixth clock signal line CLK6 on the substrate and the orthographic projection of the seventh clock signal line CLK7 on the substrate.

[0276] In an exemplary embodiment, when the fourth clock signal terminal of at least one shift register is electrically connected to the first signal line group, the first terminal of the tenth transistor T10 of at least one shift register is electrically connected to the seventh clock signal line CLK7, and the first plate of the third capacitor C3 of at least one shift register is electrically connected to the fifth clock signal line CLK5.

[0277] In an exemplary embodiment, when the fourth clock signal terminal of at least one shift register is electrically connected to the second signal line group, the first terminal of the tenth transistor T10 of at least one shift register is electrically connected to the eighth clock signal line CLK8, and the first plate of the third capacitor C3 of at least one shift register is electrically connected to the sixth clock signal line CLK6.

[0278] In an exemplary embodiment, as shown in FIG7, the orthogonal projection of at least one of the fifth clock signal line CLK5, the sixth clock signal line CLK6, and the second low-level power line VL2 onto the substrate lies between the orthogonal projections of at least one transistor in the shift sub-circuit and at least one transistor in the eleventh transistor T11 in the output sub-circuit onto the substrate and the orthogonal projections of at least one transistor in the ninth transistor T9 and the tenth transistor T10 in the output sub-circuit onto the substrate. This arrangement of the fifth clock signal line CLK5, the sixth clock signal line CLK6, and the second low-level power line VL2 reduces the number of cross-line connections between the fifth clock signal line CLK5, the sixth clock signal line CLK6, and the second low-level power line VL2 and other transistors, and reduces the overlap capacitance between the fifth clock signal line CLK5, the sixth clock signal line CLK6, and the second low-level power line VL2 and other structures, thereby reducing the impact of noise on the output of the shift register.

[0279] In an exemplary embodiment, as shown in FIG7, the orthogonal projection of at least one of the seventh clock signal lines CLK7 and the eighth clock signal line CLK8 onto the substrate is located on the side of the orthogonal projection of at least one of the ninth transistor T9 and the tenth transistor T10 in the output sub-circuit that is close to the display area.

[0280] In an exemplary embodiment, as shown in FIG7, at least one of the first clock signal lines CLK1, CLK2, CLK3, CLK4, CLK7, and CLK8 has a linewidth along the first direction D1 that is greater than the linewidth along the first direction of at least one of the fifth clock signal lines CLK5, CLK6, and VL2. The larger linewidth of at least one of the first clock signal lines CLK1, CLK2, CLK3, CLK4, CLK7, and CLK8 reduces the resistance of at least one of the clock signal lines, thereby enabling high-frequency output from the display substrate where the shift register is located.

[0281] In an exemplary embodiment, at least one of the clock signal lines, the seventh clock signal line CLK7 and the eighth clock signal line CLK8, has a linewidth in the range of 10 micrometers to 50 micrometers along the first direction.

[0282] In an exemplary embodiment, at least one clock signal line from the fifth clock signal line CLK5 to the eighth clock signal line CLK8 includes: a first clock connection line and a second clock connection line that are disposed on different layers and interconnected with each other, the first clock connection line and the second clock connection line extending at least partially along the second direction D2, and the orthographic projections of the first clock connection line and the second clock connection line of at least one clock signal line from the fifth clock signal line CLK5 to the eighth clock signal line CLK8 on the substrate at least partially overlap.

[0283] In an exemplary embodiment, the film layer containing the first clock connection line of at least one of the clock signal lines from the fifth clock signal line CLK5 to the eighth clock signal line CLK8 is located on the side of the film layer containing the second clock connection line closer to the substrate. The second clock connection line of at least one of the clock signal lines from the fifth clock signal line CLK5 to the eighth clock signal line CLK8 is disposed in the same layer as at least one of the first clock signal lines CLK1 to the fourth clock signal line CLK4. Exemplarily, the film layer containing the first clock connection line of at least one of the clock signal lines from the fifth clock signal line CLK5 to the eighth clock signal line CLK8 is located in the third conductive layer, and the second clock connection line of at least one of the clock signal lines from the fifth clock signal line CLK5 to the eighth clock signal line CLK8 is located in the fourth conductive layer.

[0284] In an exemplary embodiment, as shown in FIG7, the display substrate further includes: an initial signal line STV and a high-level power supply line VH disposed on the substrate and located in a non-display area; at least one level shift register includes: a signal input terminal and a high-level power supply terminal; the high-level power supply line VH is electrically connected to the high-level power supply terminal of the at least one level shift register; the initial signal line STV is electrically connected to the signal input terminal of the at least one level shift register; at least a portion of at least one of the initial signal line STV and the high-level power supply line VH extends along the second direction D2.

[0285] In an exemplary embodiment, as shown in FIG7, the orthographic projection of the initial signal line STV on the substrate is located on the side of the first clock signal line group away from the display area, and the orthographic projection of the high-level power line VH on the substrate is located between the orthographic projections of the first clock signal line group and the second clock signal line group on the substrate.

[0286] In an exemplary embodiment, as shown in FIG10, the orthogonal projection of the high-level power line VH on the substrate at least partially overlaps with the orthogonal projection of the control electrode of at least one of the fourth transistor T4 and the fifth transistor T5 in at least one level shift register on the substrate.

[0287] In an exemplary embodiment, as shown in Figures 7 and 10, the line width of the high-level power line VH along the first direction D1 is greater than the line width of at least one of the first low-level power line VL1 and the initial signal line STV along the first direction D1, and less than the line width of at least one of the first clock signal lines in the first clock signal line group along the first direction D1.

[0288] In an exemplary embodiment, as shown in FIG7, the orthogonal projection of the first capacitor C1 on the substrate is located between the orthogonal projections of the first clock signal line group on the substrate and the second clock signal line group on the substrate, and at least partially overlaps with the orthogonal projection of the high-level power line VH on the substrate.

[0289] In an exemplary embodiment, as shown in FIG7, the orthogonal projection of the second capacitor C2 on the substrate is located between the orthogonal projection of the second low-level power line VL2 on the substrate and the orthogonal projection of the seventh clock signal line CLK7 on the substrate.

[0290] In an exemplary embodiment, as shown in FIG7, the orthogonal projection of the third capacitor C3 on the substrate is located between the orthogonal projection of the sixth clock signal line CLK6 on the substrate and the orthogonal projection of at least one output transistor in the output sub-circuit on the substrate, and at least partially overlaps with the orthogonal projection of the second low-level power supply line VL2 on the substrate.

[0291] In an exemplary embodiment, at least one of the first and second plates of at least one capacitor includes a main body and a connecting part, wherein the main body and the connecting part of at least one plate are connected.

[0292] In an exemplary embodiment, as shown in FIG11, the orthographic projection of the main body of the first plate C11 of the first capacitor C1 on the substrate covers the orthographic projection of the main body of the second plate C12 of the first capacitor C1 on the substrate.

[0293] In an exemplary embodiment, as shown in FIG11, the orthographic projection of the main body of the second plate of the second capacitor C2 onto the substrate covers the orthographic projection of the main body of the first plate of the second capacitor C2 onto the substrate.

[0294] In an exemplary embodiment, as shown in FIG11, the orthographic projection of the main body C32A of the second plate C32 of the third capacitor C3 onto the substrate covers the orthographic projection of the main body C31 of the first plate C31 of the third capacitor C3 onto the substrate. The first plate C31 of the third capacitor C3 is electrically connected to one of the fifth clock signal lines and the sixth clock signal line. The main body C32A of the second plate C32 of the third capacitor C3 is the orthographic projection of the main body C31 of the first plate C31 onto the substrate. The second plate C32 of the third capacitor C3 completely isolates the first plate C31 of the third capacitor from the second low-level power supply line VL2. This avoids the influence of the clock signal of one of the fifth and sixth clock signal lines on the second low-level power supply line VL2, reduces the coupling capacitance between the second and sixth clock signal lines, and thus reduces the rise time and fall time of the output signal when the display substrate outputs at high frequency, ensuring the output stability of the shift register.

[0295] In an exemplary embodiment, as shown in FIG11, the orthographic projection of the connection portion C32B of the second plate C32 of the third capacitor C3 on the substrate at least partially overlaps with the orthographic projection of at least one of the clock signal lines CLK5 and CLK6 on the substrate.

[0296] In an exemplary embodiment, FIG12 is a partial enlarged view of FIG7. As shown in FIG12, the length L11 of the main body portion C32A of the second plate C32 of the third capacitor C3 along the first direction is greater than the linewidth L12 of the second low-level power line VL2 along the first direction. The orthographic projection of the portion of the second low-level power line VL2 near the boundary of the display area and away from the boundary of the display area on the substrate is within the range of the orthographic projection of the main body portion of the second plate of the third capacitor C3 on the substrate.

[0297] In an exemplary embodiment, as shown in FIG12, the distance W1 between the orthographic projection of the main body of the second plate C32 of the third capacitor C3 away from the display area on the substrate and the orthographic projection of the sixth clock signal line CLK6 near the display area on the substrate is greater than 1 micrometer, and the distance W1 between the second low-level power line VL2 away from the display area on the substrate is greater than 1 micrometer.

[0298] In an exemplary embodiment, as shown in FIG12, the distance W3 between the orthographic projection of the main body of the second plate of the third capacitor C3 near the boundary of the display area and the orthographic projection of the second low-level power line VL2 near the boundary of the display area on the substrate is greater than 1 micrometer.

[0299] In an exemplary embodiment, as shown in Figures 7 and 11, the area of ​​the first capacitor C1 is larger than the area of ​​at least one of the second capacitor C2 and the third capacitor C3.

[0300] In an exemplary embodiment, the capacitance value of the first capacitor C1 is greater than or equal to 0.3pF. The large capacitance value of the first capacitor C1 ensures the stability of the cascaded signal output by the shift register.

[0301] In an exemplary embodiment, as shown in Figures 7 and 11, the area of ​​the third capacitor C3 is larger than the area of ​​the second capacitor C2.

[0302] In an exemplary embodiment, as shown in FIG11, the active pattern 11 of the first transistor T1 and the active pattern 31 of the third transistor T3 are arranged along a first direction, and a straight line extending along the first direction D1 passes through at least a portion of the control electrode 12 of the first transistor T1 and the active pattern 21 of the second transistor T2. The arrangement of the first to third transistors in this disclosure facilitates the connection of the first to third transistors to at least one clock signal line in the first clock signal line group.

[0303] In an exemplary embodiment, as shown in FIG10, the control electrode 102 of the tenth transistor T10 includes: a first connection segment 102A, a second connection segment 102B, and a plurality of first branch segments 102C, wherein the second connection segment 102B is located on the side of the first connection segment 102A near the display area, and the plurality of first branch segments 102C are located on the side of the second connection segment 102B near the display area; the second electrode of the tenth transistor T10 includes: a third connection segment 104A and a plurality of second branch segments 104B, wherein the plurality of second branch segments 104B are located on the side of the third connection segment 104A near the display area. The first connecting segment 102A extends along the first direction D1, and its orthographic projection on the substrate at least partially overlaps with the orthographic projections on the substrate of at least one of the signal lines CLK5, CLK6, and VL2. The second connecting segment 102B extends along the second direction D2, and one of the plurality of first branch segments 102C extends along the first direction D1, and the plurality of first branch segments 102C are arranged along the second direction D2. The third connecting segment 104A extends along the second direction D2, and one of the plurality of second branch segments 104B extends along the first direction D1, and the plurality of second branch segments 104B are arranged along the second direction D2.

[0304] In an exemplary embodiment, as shown in FIG10, the orthographic projection of the third connecting segment 104A on the substrate at least partially overlaps with the orthographic projection of the first connecting segment 102A on the substrate, but does not overlap with the orthographic projection of the second connecting segment 102B on the substrate. At least one branch of the plurality of first branch segments 102C does not overlap with the orthographic projections of the third connecting segment 104A and at least one branch of the plurality of second branch segments 104B on the substrate. The orthographic projection of at least one branch of the plurality of first branch segments 102C on the substrate is located between the orthographic projections of at least two of the plurality of second branch segments 104B on the substrate. The arrangement of the control electrode and the second electrode of the tenth transistor in this disclosure can reduce the overlap area between the second electrode and the control electrode of the tenth transistor, improve the impact of noise on the output of the shift register, and enhance the reliability of the shift register.

[0305] In an exemplary embodiment, the aspect ratio of the channel region of the active pattern of the tenth transistor T10 is greater than 40. A aspect ratio greater than 40 in the channel region of the active pattern of the tenth transistor T10 can improve the output performance of the tenth transistor and reduce the rise and fall times of the output signal of the shift register when the display substrate is operating at high frequencies.

[0306] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0307] The embodiments provided in this disclosure are further illustrated below with reference to the fabrication process of the display substrate shown in Figure 9.

[0308] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film using a patterning process to form a semiconductor layer pattern. As shown in FIG13, FIG13 is a schematic diagram after the semiconductor layer pattern is formed in FIG9.

[0309] In an exemplary embodiment, as shown in FIG13, the semiconductor layer pattern may include at least: active patterns of transistors located in at least one level shift register, such as: active patterns 11 of the first transistor to active patterns 111 of the eleventh transistor.

[0310] In an exemplary embodiment, as shown in FIG13, the active pattern 21 of the second transistor and the active pattern 31 of the third transistor are integrally formed, the active pattern 61 of the sixth transistor and the active pattern 71 of the seventh transistor are integrally formed, and the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor are integrally formed. The active patterns 11 of the first transistor, 41 of the fourth transistor, 51 of the fifth transistor, 81 of the eighth transistor, and 111 of the eleventh transistor are individually formed.

[0311] In an exemplary embodiment, as shown in FIG13, the active pattern 11 of the first transistor and the active pattern 81 of the eighth transistor are arranged along the second direction D2, and the active pattern 81 of the eighth transistor of the nth-stage shift register is located on the side of the active pattern 11 of the first transistor closer to the (n+1)th-stage shift register. The integrated structure of the active pattern 21 of the second transistor and the active pattern 31 of the third transistor is located on the side of the active pattern 11 of the first transistor closer to the display area. The integrated structure of the active pattern 61 of the sixth transistor and the active pattern 71 of the seventh transistor is located on the side of the integrated structure of the active pattern 21 of the second transistor and the active pattern 31 of the third transistor closer to the display area. The active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, and the active pattern 111 of the eleventh transistor are located on the side of the integrated structure of the active pattern 61 of the sixth transistor and the active pattern 71 of the seventh transistor, closer to the display area. The active pattern 41 of the fourth transistor of the nth-stage shift register is located on the side of the active pattern 51 of the fifth transistor away from the (n+1)th-stage shift register. The active pattern 111 of the eleventh transistor of the nth-stage shift register is located on the side of the active pattern 51 of the fifth transistor closer to the (n+1)th-stage shift register. The integrated structure of the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor is located on the side of at least one of the active patterns of the fourth transistor 41, the fifth transistor 51, and the eleventh transistor 111, closer to the display area. The active pattern 101 of the tenth transistor of the nth-stage shift register is located on the side of the active pattern 91 of the ninth transistor closer to the (n+1)th-stage shift register.

[0312] In an exemplary embodiment, any one of the active patterns of the first transistor 11, the third transistor 31, the eighth transistor 81, the ninth transistor 91, and the tenth transistor 101 of at least one level of shift register is strip-shaped and extends along the second direction D2. At least one of the active patterns of the second transistor 21, the fourth transistor 41, the fifth transistor 51, the sixth transistor 61, the seventh transistor 71, and the eleventh transistor 111 extends at least partially along the first direction D1.

[0313] In an exemplary embodiment, the active pattern 21 of the second transistor and the active pattern 31 of the third transistor are arranged at right angles. The active pattern 61 of the sixth transistor and the active pattern 71 of the seventh transistor are arranged in a straight line.

[0314] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region.

[0315] As shown in Figure 13, the second region 31-2 of the active pattern 31 of the third transistor can be used as the second region 21-1 of the active pattern 21 of the second transistor, the second region 61-2 of the active pattern 61 of the sixth transistor can be used as the first region 71-1 of the active pattern 71 of the seventh transistor, and the second region 91-2 of the active pattern 91 of the ninth transistor can be used as the second region 101-2 of the active pattern 101 of the tenth transistor. The first region 11-1 and the second region 11-2 of the active pattern 11 of the first transistor, the first region 21-1 of the active pattern 21 of the second transistor, the first region 31-1 of the active pattern 31 of the third transistor, the first region 41-1 and the second region 41-2 of the active pattern 41 of the fourth transistor, the first region 51-1 and the second region 51-2 of the active pattern 51 of the fifth transistor, the first region 61-1 of the active pattern 61 of the sixth transistor, the second region 71-2 of the active pattern 71 of the seventh transistor, the first region 81-1 and the second region 81-2 of the active pattern 81 of the eighth transistor, the first region 91-1 of the active pattern 91 of the ninth transistor, the first region 101-1 of the active pattern 101 of the tenth transistor, and the first region 111-1 and the second region 111-2 of the active pattern 111 of the eleventh transistor are set separately.

[0316] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a first insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the first insulating layer, as shown in Figures 14 and 15. Figure 14 is a schematic diagram of the first conductive layer pattern in Figure 9, and Figure 15 is a schematic diagram of Figure 9 after the first conductive layer pattern has been formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0317] In an exemplary embodiment, as shown in Figures 14 and 15, the first conductive layer pattern may include at least the control electrode of at least one transistor and the first plate of a capacitor. For example, the first conductive layer pattern includes: the control electrode 12 of the first transistor to the control electrode 112 of the eleventh transistor located in at least one level shift register, and the first plate C111 of the first capacitor to the first plate C31 of the third capacitor.

[0318] In an exemplary embodiment, the control electrode 12 of the first transistor and the control electrode 32 of the third transistor are integrally formed. The control electrode 12 of the first transistor is shaped like an "n" with its opening facing the display area, and includes two branches extending along a first direction D1. The control electrode 32 of the third transistor is strip-shaped and extends along the first direction D1, and the control electrode 32 of the third transistor is connected to one of the branches of the control electrode 12 of the first transistor. There are two overlapping areas between the control electrode 12 of the first transistor and the active pattern of the first transistor; therefore, the first transistor has a dual-gate structure.

[0319] In an exemplary embodiment, the control electrode 22 of the second transistor is provided separately. The control electrode 22 of the second transistor is in the shape of an inverted "T".

[0320] In an exemplary embodiment, the control electrode 42 of the fourth transistor and the control electrode 62 of the sixth transistor are integrally formed. The control electrode 42 of the fourth transistor is shaped like an "L" rotated 90 degrees to the right, and the control electrode 62 of the sixth transistor is shaped like an "F" rotated 90 degrees to the right.

[0321] In an exemplary embodiment, the control electrode 52 of the fifth transistor, the first plate C11 of the first capacitor, and the control electrode 102 of the tenth transistor are integrally formed. The control electrode 52 of the fifth transistor is located on the side of the first plate C11 of the first capacitor away from the display area, and the control electrode 102 of the tenth transistor is located on the side of the first plate C11 of the first capacitor closer to the display area. The control electrode 52 of the fifth transistor is strip-shaped and extends along the first direction D1. The first plate C11 of the first capacitor is rectangular. The control electrode 102 of the tenth transistor has a comb-like structure, and the comb teeth are located on the back of the comb closer to the display area.

[0322] In an exemplary embodiment, the control electrode 72 of the seventh transistor is provided separately, and the shape of the control electrode 72 of the seventh transistor is an inverted "T".

[0323] In an exemplary embodiment, the control electrode 82 of the eighth transistor and the control electrode 112 of the eleventh transistor are integrally formed. The control electrode 82 of the eighth transistor is strip-shaped and extends along the first direction D1, and the control electrode 112 of the eleventh transistor is strip-shaped and extends along the second direction D2. The control electrodes 82 of the eighth transistor and the control electrode 112 of the eleventh transistor are arranged at right angles.

[0324] In an exemplary embodiment, the control electrode 92 of the ninth transistor and the first plate C21 of the second capacitor are integrally formed. There are multiple control electrodes 92 of the ninth transistor, each being strip-shaped and extending along a first direction D1. The main body of the first plate C21 of the second capacitor is rectangular. The connection portion of the first plate C21 is located on the side of the main body of the first plate C21 furthest from the display area. The control electrode 92 of the ninth transistor is located on the side of the first plate C21 of the second capacitor closest to the display area.

[0325] In an exemplary embodiment, the first plate C31 of the third capacitor is provided separately. The main body of the first plate C31 of the third capacitor is rectangular in shape, and the connecting part of the first plate C31 of the third capacitor is located on the side of the main body of the first plate C31 of the third capacitor away from the display area.

[0326] In an exemplary embodiment, the control electrode 12 of the first transistor (also the control electrode 32 of the third transistor) spans the active patterns of the first transistor and the third transistor; the control electrode 22 of the second transistor spans the active pattern of the second transistor; the control electrode 42 of the fourth transistor (also the control electrode 62 of the sixth transistor) spans the active patterns of the fourth transistor and the sixth transistor; the control electrode 52 of the fifth transistor (also the first plate C21 of the first capacitor and the control electrode 102 of the tenth transistor) spans the active patterns of the fifth transistor and the tenth transistor; the control electrode 72 of the seventh transistor spans the active pattern of the seventh transistor; the control electrode 82 of the eighth transistor (also the control electrode 112 of the eleventh transistor) spans the active pattern of the eighth transistor; and the control electrode 92 of the ninth transistor (also the first plate C21 of the second capacitor) spans the active pattern of the ninth transistor.

[0327] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform a conductor-enhancing process on the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor to the twenty-sixth transistor, while the semiconductor layer in the region not shielded by the first conductive layer is conductor-enhanced. That is, the first and second regions of the active pattern of any one of the first to fifteenth transistors are conductor-enhanced. As shown in FIG15, the second region of the active pattern of the sixth transistor in this disclosure after conductor-enhancing (which is also the first region of the active pattern of the seventh transistor) serves as the second electrode 64 of the sixth transistor (which is also the first electrode 73 of the seventh transistor).

[0328] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second insulating film and a second conductive film on a substrate having the aforementioned pattern, and patterning the second conductive film using a patterning process to form a second insulating layer pattern covering the first conductive layer pattern and a second conductive layer pattern located on the second insulating layer pattern, as shown in Figures 16 and 17. Figure 16 is a schematic diagram of the second conductive layer pattern in Figure 9, and Figure 17 is a schematic diagram of Figure 9 after the second conductive layer pattern has been formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0329] In an exemplary embodiment, as shown in Figures 16 and 17, the second conductive layer pattern may include at least: the second plate of the first capacitor, for example: the second plate C12 of the first capacitor located in at least one level shift register to the second plate C32 of the third capacitor, the first connecting line L1, the second connecting line L2, the third connecting line L3, and the drive signal output line OUTL.

[0330] In an exemplary embodiment, the second electrode C12 of the first capacitor is rectangular in shape. The orthographic projection of the main body of the second electrode C12 onto the substrate at least partially overlaps with the orthographic projection of the main body of the first electrode of the first capacitor onto the substrate. Exemplarily, the orthographic projection of the main body of the first electrode of the first capacitor onto the substrate covers the orthographic projection of the main body of the second electrode C12 onto the substrate.

[0331] In an exemplary embodiment, the second plate C22 of the second capacitor is rectangular in shape. The orthographic projection of the main body of the second plate C22 onto the substrate at least partially overlaps with the orthographic projection of the main body of the first plate onto the substrate. Exemplarily, the orthographic projection of the main body of the second plate C22 onto the substrate covers the orthographic projection of the main body of the first plate onto the substrate.

[0332] In an exemplary embodiment, the main body of the second plate C32 of the third capacitor is rectangular in shape. The orthographic projection of the main body of the second plate C32 onto the substrate at least partially overlaps with the orthographic projection of the main body of the first plate onto the substrate. Exemplarily, the orthographic projection of the main body of the second plate C32 onto the substrate covers the orthographic projection of the main body of the first plate onto the substrate. The second plate C32 of the third capacitor includes two connecting portions; one connecting portion is located on the side of the main body of the second plate C32 away from the display area, and the other connecting portion is located on the side of the main body of the second plate C32 closer to the display area.

[0333] In an exemplary embodiment, the first connecting line L1 is located on the side of the second plate C12 of the first capacitor away from the display area. The first connecting line L1 is straight and extends at least partially along the first direction D1.

[0334] In an exemplary embodiment, the second connecting line L2 is located on the side of the second plate C32 of the third capacitor away from the display area. The second connecting line L2 is straight and extends at least partially along the first direction D1.

[0335] In an exemplary embodiment, the third connecting line L3 is located on the side of the second plate C22 of the second capacitor closer to the display area. The third connecting line L3 is straight and extends at least partially along the first direction D1.

[0336] In an exemplary embodiment, the drive signal output line OUTL is located on the side of the second plate C12 of the first capacitor closer to the display area. The drive signal output line OUTL is straight and extends at least partially along the first direction D1.

[0337] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, and patterning the third insulating film using a patterning process to form a third insulating layer pattern covering the aforementioned structure. The third insulating layer has multiple via patterns, as shown in FIG18, which is a schematic diagram of FIG9 after the third insulating layer pattern is formed.

[0338] In an exemplary embodiment, as shown in FIG18, the third insulating layer pattern may include at least: a first via V1 to a thirty-fourth via V34 located in at least one level shift register.

[0339] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the first transistor onto the substrate. The first insulating layer and the second insulating layer within the first via V1 are etched away, exposing the surface of the first region of the active pattern of the first transistor. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active pattern of the first transistor through the via.

[0340] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the orthographic projection of the second region of the active pattern of the first transistor onto the substrate. The first and second insulating layers within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the first transistor. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the eighth transistor) to be connected to the second region of the active pattern of the first transistor through the via.

[0341] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the second transistor onto the substrate. The first and second insulating layers within the third via V3 are etched away, exposing the surface of the first region of the active pattern of the second transistor. The third via V3 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the first region of the active pattern of the second transistor through the via.

[0342] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the third transistor) onto the substrate. The first and second insulating layers within the fourth via V4 are etched away, exposing the surface of the second region of the active pattern of the second transistor. The fourth via V4 is configured to allow the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor) to be connected to the second region of the active pattern of the second transistor (which is also the second region of the active pattern of the third transistor) through the via.

[0343] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the orthographic projection of the first region of the active pattern of the third transistor onto the substrate. The first and second insulating layers within the fifth via V5 are etched away, exposing the surface of the first region of the active pattern of the third transistor. The fifth via V5 is configured to allow the first electrode of the subsequently formed third transistor to be connected to the first region of the active pattern of the third transistor through the via.

[0344] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the orthographic projection of the first region of the active pattern of the fourth transistor onto the substrate. The first and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The sixth via V6 is configured to allow the first electrode of the subsequently formed fourth transistor (which is also the first electrode of the sixth transistor) to be connected to the first region of the active pattern of the fourth transistor through the via.

[0345] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the orthographic projection of the second region of the active pattern of the fourth transistor onto the substrate. The first and second insulating layers within the seventh via V7 are etched away, exposing the surface of the second region of the active pattern of the fourth transistor. The seventh via V7 is configured to allow the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to be connected to the second region of the active pattern of the fourth transistor through the via.

[0346] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the fifth transistor onto the substrate. The first and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the active pattern of the fifth transistor. The eighth via V8 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0347] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the orthographic projection of the second region of the active pattern of the fifth transistor onto the substrate. The first and second insulating layers within the ninth via V9 are etched away, exposing the surface of the second region of the active pattern of the fifth transistor. The ninth via V9 is configured to allow the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to be connected to the second region of the active pattern of the fifth transistor through the via.

[0348] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the sixth transistor onto the substrate. The first and second insulating layers within the tenth via V10 are etched away, exposing the surface of the first region of the active pattern of the sixth transistor. The tenth via V10 is configured to allow the first electrode of the subsequently formed fourth transistor (the first electrode of the sixth transistor) to be connected to the first region of the active pattern of the sixth transistor through the via.

[0349] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the seventh transistor onto the substrate. The first and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the second region of the active pattern of the seventh transistor. The eleventh via V11 is configured to allow the second electrode of the subsequently formed seventh transistor to be connected to the second region of the active pattern of the seventh transistor through the via.

[0350] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the orthographic projection of the first region of the active pattern of the eighth transistor onto the substrate. The first and second insulating layers within the twelfth via V12 are etched away, exposing the surface of the first region of the active pattern of the eighth transistor. The twelfth via V12 is configured to allow the first electrode of the subsequently formed first transistor (which is also the first electrode of the eighth transistor) to be connected to the first region of the active pattern of the eighth transistor through the via.

[0351] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the eighth transistor onto the substrate. The first and second insulating layers within the thirteenth via V13 are etched away, exposing the surface of the second region of the active pattern of the eighth transistor. The thirteenth via V13 is configured to allow the second electrode of the subsequently formed eighth transistor to be connected to the second region of the active pattern of the eighth transistor through the via.

[0352] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate is within the orthographic projection range of the first region of the active pattern of the ninth transistor onto the substrate. The first and second insulating layers within the fourteenth via V14 are etched away, exposing the surface of the first region of the active pattern of the ninth transistor. The fourteenth via V14 is configured to allow the first electrode of the subsequently formed ninth transistor to be connected to the first region of the active pattern of the ninth transistor through the via.

[0353] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the orthographic projection of the second region of the active pattern of the ninth transistor onto the substrate. The first and second insulating layers within the fifteenth via V15 are etched away, exposing the surface of the second region of the active pattern of the ninth transistor. The fifteenth via V15 is configured to allow the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) to be connected to the second region of the active pattern of the ninth transistor through the via.

[0354] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate is within the orthographic projection of the first region of the active pattern of the tenth transistor onto the substrate. The first and second insulating layers within the sixteenth via V16 are etched away, exposing the surface of the first region of the active pattern of the tenth transistor. The sixteenth via V16 is configured to allow the first electrode of the subsequently formed tenth transistor to be connected to the first region of the active pattern of the tenth transistor through the via.

[0355] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the orthographic projection of the second region of the active pattern of the tenth transistor onto the substrate. The first and second insulating layers within the seventeenth via V17 are etched away, exposing the surface of the second region of the active pattern of the tenth transistor. The seventeenth via V17 is configured to allow the second terminal of the subsequently formed ninth transistor (which is also the second terminal of the tenth transistor) to be connected to the second region of the active pattern of the tenth transistor through the via.

[0356] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 onto the substrate is within the orthographic projection of the first region of the active pattern of the eleventh transistor onto the substrate. The first and second insulating layers within the eighteenth via V18 are etched away, exposing the surface of the first region of the active pattern of the eleventh transistor. The eighteenth via V18 is configured to allow the first electrode of the subsequently formed eleventh transistor to be connected to the first region of the active pattern of the eleventh transistor through the via.

[0357] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the eleventh transistor onto the substrate. The first and second insulating layers within the nineteenth via V19 are etched away, exposing the surface of the second region of the active pattern of the eleventh transistor. The nineteenth via V19 is configured to allow the second electrode of the subsequently formed eleventh transistor to be connected to the second region of the active pattern of the eleventh transistor through the via.

[0358] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate is located within the range of the orthographic projection of the control electrode of the first transistor (which is also the control electrode of the third transistor) onto the substrate. The second insulating layer within the twentieth via V20 is etched away, exposing the surface of the control electrode of the first transistor (which is also the control electrode of the third transistor). The twentieth via V20 is configured to allow the first electrodes of the subsequently formed plurality of first connection electrodes and the first electrodes of the second transistor to be connected to the control electrode of the first transistor (which is also the control electrode of the third transistor) through the via.

[0359] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the control electrode of the second transistor onto the substrate. The second insulating layer within the 21st via V21 is etched away, exposing the surface of the control electrode of the second transistor. The 21st via V21 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the eighth transistor) and the second electrode of the seventh transistor to be connected to the control electrode of the second transistor through the via.

[0360] In an exemplary embodiment, the orthogonal projection of the 22nd via V22 onto the substrate is within the range of the orthogonal projection of the control electrode of the fourth transistor (which is also the control electrode of the sixth transistor) onto the substrate. The second insulating layer within the 22nd via V22 is etched away, exposing the surface of the control electrode of the fourth transistor (which is also the control electrode of the sixth transistor). The 22nd via V22 is configured to allow the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor) and the first electrode of the eleventh transistor to be connected to the control electrode of the fourth transistor (which is also the control electrode of the sixth transistor) through the via.

[0361] In an exemplary embodiment, the orthogonal projection of the 23rd via V23 onto the substrate lies within the orthogonal projection of the control electrode of the fifth transistor (which is also the control electrode of the tenth transistor and the first plate of the first capacitor) onto the substrate. The second insulating layer within the 23rd via V23 is etched away, exposing the surface of the control electrode of the fifth transistor (which is also the control electrode of the tenth transistor and the first plate of the first capacitor). The 23rd via V23 is configured to allow the second electrode of the subsequently formed eighth transistor to be connected to the control electrode of the fifth transistor (which is also the control electrode of the tenth transistor and the first plate of the first capacitor) through the via.

[0362] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate is within the range of the orthographic projection of the control electrode of the 7th transistor onto the substrate. The second insulating layer within the 24th via V24 is etched away, exposing the surface of the control electrode of the 7th transistor. The 24th via V24 is configured to allow a plurality of subsequently formed third connection electrodes to be connected to the control electrode of the 7th transistor through the via.

[0363] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate is within the range of the orthographic projection of the control electrode of the 8th transistor (which is also the control electrode of the 11th transistor) onto the substrate. The second insulating layer within the 25th via V25 is etched away, exposing the surface of the control electrode of the 8th transistor (which is also the control electrode of the 11th transistor). The 25th via V25 is configured to allow the fourth connection electrode to be connected to the control electrode of the 8th transistor (which is also the control electrode of the 11th transistor) through the via.

[0364] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate is within the range of the orthographic projection of the control electrode of the 9th transistor (which is also the first electrode of the 2nd capacitor) onto the substrate. The second insulating layer within the 26th via V26 is etched away, exposing the surface of the control electrode of the 9th transistor (which is also the first electrode of the 2nd capacitor). The 26th via V26 is configured to allow the subsequently formed fifth connection electrode to be connected to the control electrode of the 9th transistor (which is also the first electrode of the 2nd capacitor) through the via.

[0365] In an exemplary embodiment, the orthographic projection of the 27th via V27 onto the substrate is within the range of the orthographic projection of the first plate of the third capacitor onto the substrate. The second insulating layer within the 27th via V27 is etched away, exposing the surface of the first plate of the third capacitor. The 27th via V27 is configured to allow the first clock connection line of one of the subsequently formed fifth clock signal lines and sixth clock signal lines to be connected to the first plate of the third capacitor through the via.

[0366] In an exemplary embodiment, the orthographic projection of the 28th via V28 on the substrate is within the range of the orthographic projection of the second plate of the first capacitor on the substrate. The 28th via V28 exposes the surface of the second plate of the first capacitor. The 28th via V28 is configured to allow the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to be connected to the second plate of the first capacitor through the via.

[0367] In an exemplary embodiment, the orthographic projection of the 29th via V29 on the substrate is within the range of the orthographic projection of the second plate of the second capacitor on the substrate. The 29th via V29 exposes the surface of the second plate of the second capacitor. The 29th via V29 is configured to allow the first electrode of the subsequently formed ninth transistor to be connected to the second plate of the second capacitor through the via.

[0368] In an exemplary embodiment, the orthogonal projection of the thirtieth via V30 onto the substrate is within the range of the orthogonal projection of the second plate of the third capacitor onto the substrate. The thirtieth via V30 exposes the surface of the second plate of the third capacitor. The thirtieth via V30 is configured to allow the second electrode of the subsequently formed eleventh transistor to be connected to the second plate of the third capacitor through the via.

[0369] In an exemplary embodiment, the orthographic projection of the 31st via V31 on the substrate is within the range of the orthographic projection of the second connection line on the substrate. The 31st via V31 exposes the surface of the second connection line. The 31st via V31 is configured to allow the first electrode of the subsequently formed first transistor and the cascaded signal output line to be connected to the second connection line through the via.

[0370] In an exemplary embodiment, the orthographic projection of the 32nd via V32 on the substrate is within the range of the orthographic projection of the first connecting line on the substrate. The 32nd via V32 exposes the surface of the first connecting line. The 32nd via V32 is configured to allow the first electrode and a plurality of second connecting electrodes of the subsequently formed fifth transistor to be connected to the first connecting line through the via.

[0371] In an exemplary embodiment, the orthographic projection of the 33rd via V33 on the substrate is within the range of the orthographic projection of the third connection line on the substrate. The 33rd via V33 exposes the surface of the third connection line. The 33rd via V33 is configured to allow the first clock connection line of one of the signal lines of the first pole of the subsequently formed 10th transistor and the 7th and 8th clock signal lines to be connected to the third connection line through the via.

[0372] In an exemplary embodiment, the orthographic projection of the 34th via V34 on the substrate is within the range of the orthographic projection of the drive signal output line on the substrate. The 34th via V34 exposes the surface of the drive signal output line. The 34th via V34 is configured to allow the second terminal of the subsequently formed 9th transistor (which is also the second terminal of the 10th transistor) to be connected to the drive signal output line through the via.

[0373] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fifth insulating layer, as shown in Figures 19 and 20. Figure 19 is a schematic diagram of the third conductive layer pattern in Figure 9, and Figure 20 is a schematic diagram of the third conductive layer pattern after it has been formed in Figure 9. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0374] In an exemplary embodiment, as shown in Figures 19 and 20, the third conductive layer pattern may include at least: an initial signal line STV, a first clock connection line CLK5A of the fifth clock signal line, a first clock connection line CLK6A of the sixth clock signal line, a first clock connection line CLK7A of the seventh clock signal line, a first clock connection line CLK8A of the eighth clock signal line, a first second power connection line VL21 of the second low-level power line VL2, and the first pole 13 and second pole 14 of the first transistor to the first pole 113 and second pole 114 of the eleventh transistor located in at least one level shift register, a plurality of first connection electrodes E1, a plurality of second connection electrodes E2, a plurality of third connection electrodes E3, a fourth connection electrode E4, and a fifth connection electrode E5.

[0375] In an exemplary embodiment, at least one of the following signal lines extends at least partially along the second direction D2: the initial signal line STV, the first clock connection line CLK5A of the fifth clock signal line, the first clock connection line CLK6A of the sixth clock signal line, the first clock connection line CLK7A of the seventh clock signal line, the first clock connection line CLK8A of the eighth clock signal line, and the first second power connection line VL21 of the second low-level power line VL2.

[0376] In an exemplary embodiment, the initial signal line STV is located on the side of the display area away from the first and second poles of at least one transistor in at least one level shift register.

[0377] In an exemplary embodiment, the first clock connection line CLK5A of the fifth clock signal line, the first clock connection line CLK6A of the sixth clock signal line, and the first second power connection line VL21 of the second low-level power line VL2 are located on the side of the first and second poles of at least one of the first to eighth transistors and the eleventh transistor in at least one level shift register that are close to the display area, and are located on the side of the first and second poles of at least one of the ninth and tenth transistors in at least one level shift register that are far from the display area.

[0378] In an exemplary embodiment, the first clock connection line CLK7A of the seventh clock signal line and the first clock connection line CLK8A of the eighth clock signal line are located on the side of the first and second poles of at least one of the ninth and tenth transistors in at least one level shift register that are close to the display area.

[0379] In an exemplary embodiment, the first electrode 13 of the first transistor is provided separately. The first electrode 13 of the first transistor is strip-shaped and extends at least partially along the first direction D1. The first electrode 13 of the first transistor is connected to the first region of the active pattern of the first transistor through a first via and to the second connection line through a thirty-first via.

[0380] In an exemplary embodiment, the second electrode 14 of the first transistor and the first electrode 83 of the eighth transistor are integrally formed. The integral structure of the second electrode 14 of the first transistor and the first electrode 83 of the eighth transistor is a zigzag shape and extends at least partially along the second direction D2. The second electrode 14 of the first transistor (which is also the first electrode 83 of the eighth transistor) is connected to the second region of the active pattern of the first transistor through a second via, to the first region of the active pattern of the eighth transistor through a twelfth via, and to the control electrode of the second transistor through a twenty-first via.

[0381] In an exemplary embodiment, the first electrode 23 of the second transistor is provided separately. The first electrode 23 of the second transistor is strip-shaped and extends along the first direction D1. The first electrode 23 of the second transistor is connected to the first region of the active pattern of the second transistor through a third via, and is connected to the control electrode of the first transistor (which is also the control electrode of the third transistor) through a twentieth via.

[0382] In an exemplary embodiment, the second electrode 24 of the second transistor and the second electrode 34 of the third transistor are an integral structure. The integral structure of the second electrode 24 of the second transistor and the second electrode 34 of the third transistor is strip-shaped and extends along the first direction D1. The second electrode 24 of the second transistor (which is also the second electrode 34 of the third transistor) is connected to (which is also the second region of the active pattern of the third transistor) through a fourth via, and is connected to the control electrode of the fourth transistor (which is also the control electrode of the sixth transistor) through a twenty-second via.

[0383] In an exemplary embodiment, the first electrode 33 of the third transistor is provided separately. The first electrode 33 of the third transistor is strip-shaped and extends along the first direction D1. The first electrode 33 of the third transistor is connected to the first region of the active pattern of the third transistor through a fifth via.

[0384] In an exemplary embodiment, the first electrode 43 of the fourth transistor and the first electrode 63 of the sixth transistor are an integral structure. The integral structure of the first electrode 43 of the fourth transistor and the first electrode 63 of the sixth transistor is zigzag-shaped and extends at least partially along the first direction D1. The first electrode 43 of the fourth transistor (which is also the first electrode 63 of the sixth transistor) is connected to the first region of the active pattern of the fourth transistor through a sixth via and to the first region of the active pattern of the sixth transistor through a tenth via.

[0385] In an exemplary embodiment, the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor are an integral structure. The integral structure of the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor is in an "n" shape with the opening facing away from the display area. The second electrode 44 of the fourth transistor (the second electrode 54 of the fifth transistor) is connected to the second region of the active pattern of the fourth transistor through a seventh via, connected to the second region of the active pattern of the fifth transistor through a ninth via, and connected to the second plate of the first capacitor through a twenty-eighth via.

[0386] In an exemplary embodiment, the first electrode 53 of the fifth transistor is provided separately. The first electrode 53 of the fifth transistor is strip-shaped and extends along the first direction D1. The first electrode 53 of the fifth transistor is connected to the first region of the active pattern of the fifth transistor through an eighth via and to the first connection line through a thirty-second via.

[0387] In an exemplary embodiment, the second electrode 74 of the seventh transistor is provided separately. The second electrode 74 of the seventh transistor is strip-shaped and extends along the first direction D1. The second electrode 74 of the seventh transistor is connected to the second region of the active pattern of the seventh transistor through an eleventh via and to the first connection line through a thirty-second via.

[0388] In an exemplary embodiment, the second electrode 84 of the eighth transistor is provided separately. The second electrode 84 of the eighth transistor is strip-shaped and extends along the first direction D1. The second electrode 84 of the eighth transistor is connected to the second region of the active pattern of the eighth transistor through a thirteenth via, and is connected to the control electrode of the fifth transistor (which is also the control electrode of the tenth transistor and the first plate of the first capacitor) through a twenty-third via.

[0389] In an exemplary embodiment, the first electrode 93 of the ninth transistor and the first second power connection line VL21 of the second low-level power line are integrally formed. The first electrode 93 of the ninth transistor is strip-shaped and extends along the first direction D1. The first electrode 93 of the ninth transistor is connected to the first region of the active pattern of the ninth transistor through the fourteenth via, and connected to the second plate of the second capacitor through the twenty-ninth via.

[0390] In an exemplary embodiment, the second electrode 94 of the ninth transistor and the second electrode 104 of the tenth transistor are an integral structure. The second electrode 94 of the ninth transistor is shaped like an "n" with its opening facing away from the display area, while the second electrode 104 of the tenth transistor is shaped like an "m" with its opening facing the display area. One side of the second electrode 94 of the ninth transistor extending along the first direction D1 is the same side of the second electrode 104 of the tenth transistor extending along the first direction D1. The second electrode 94 of the ninth transistor (which is also the second electrode 104 of the tenth transistor) is connected to the second region of the active pattern of the ninth transistor through a fifteenth via, to the second region of the active pattern of the tenth transistor through a seventeenth via, and to the drive signal output line through a thirty-fourth via.

[0391] In an exemplary embodiment, the first electrode 103 of the tenth transistor is provided separately. The first electrode 103 of the tenth transistor is shaped like an "n" with its opening facing away from the display area. The first electrode 103 of the tenth transistor is connected to the first region of the active pattern of the tenth transistor through the sixteenth via, and connected to the third connection line through the thirty-third via.

[0392] In an exemplary embodiment, the first electrode 113 of the eleventh transistor is provided separately. The first electrode 113 of the eleventh transistor is strip-shaped and extends along a second direction. The first electrode 113 of the eleventh transistor is connected to the first region of the active pattern of the eleventh transistor through an eighteenth via, and is connected to the control electrode of the fourth transistor (which is also the control electrode of the sixth transistor) through a twenty-second via.

[0393] In an exemplary embodiment, the second electrode 114 of the eleventh transistor is provided separately. The second electrode 114 of the eleventh transistor is strip-shaped and extends along the second direction D2. The second electrode 114 of the eleventh transistor is connected to the second region of the active pattern of the eleventh transistor through the nineteenth via, and is connected to the second plate of the third capacitor through the thirtieth via.

[0394] In an exemplary embodiment, there are four first connection electrodes E1. The first to fourth first connection electrodes are arranged sequentially along the direction close to the display area, and the first, third, and fourth first connection electrodes are arranged along a first direction. The first electrode 23 of the second transistor is multiplexed as the second first connection electrode. At least one of the multiple first connection electrodes is connected to the control electrode of the first transistor (which is also the control electrode of the third transistor) through a 20th via.

[0395] In an exemplary embodiment, there are four second connection electrodes E2. The first to fourth second connection electrodes are arranged sequentially along the direction close to the display area, and the first electrode 53 of the fifth transistor is multiplexed as the fourth second connection electrode. At least one of the multiple second connection electrodes is connected to the first connection line through a thirty-second via.

[0396] In an exemplary embodiment, there are four third connection electrodes E3, with the first third connection electrode E3 to the fourth second connection electrode arranged sequentially along the direction close to the display area. At least one of the plurality of third connection electrodes is connected to the control electrode of the seventh transistor through a twenty-fourth via.

[0397] In an exemplary embodiment, the fourth connection electrode E4 is strip-shaped and extends along the second direction D2. The fourth connection electrode E4 is connected to the control electrode of the eighth transistor (which is also the control electrode of the eleventh transistor) through the twenty-fifth via.

[0398] In an exemplary embodiment, the fifth connection electrode E5 is strip-shaped and extends along the first direction D1. The fifth connection electrode E5 is connected to the control electrode of the ninth transistor (which is also the first plate of the second capacitor) through the twenty-sixth via.

[0399] In an exemplary embodiment, the clock signal line (that is, one of the fifth clock signal line and the sixth clock signal line) connected to the first plate of the third capacitor of the shift register is connected to the first plate of the third capacitor through the twenty-seventh via.

[0400] In an exemplary embodiment, the clock signal line (i.e., one of the seventh and eighth clock signal lines) connected to the first terminal of the tenth transistor of the shift register is connected to the third connection line through the thirty-third via.

[0401] In an exemplary embodiment, the nth cascaded signal output line OUTCL(n) is integrated with the second terminals 54 of the fourth and fifth transistors in the nth-stage shift register, and is connected to the second connection line in the (n+1)th-stage shift register via a thirty-first via. The second terminals 54 of the fourth and fifth transistors in the nth-stage shift register are sequentially connected to the first terminal 13 of the first transistor in the (n+1)th-stage shift register via the nth cascaded signal output line OUTCL(n) and the second connection line in the (n+1)th-stage shift register.

[0402] In an exemplary embodiment, the arrangement of the first to fifth connecting electrodes can reduce the via depth in the display substrate and improve the reliability of the display substrate.

[0403] (6) Forming a first planarization layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern has been formed, then coating a first planarization film, and patterning the fourth insulating film and the first planarization film by a patterning process to form a fourth insulating layer covering the aforementioned structure and a first planarization layer disposed on the fourth insulating layer. The first planarization layer has a plurality of via patterns, as shown in FIG21. FIG21 is a schematic diagram of FIG9 after the formation of the first planarization layer pattern.

[0404] In an exemplary embodiment, as shown in FIG21, the planarization layer pattern may include at least: the thirty-fifth via V35 to the forty-fourth via V44 located in at least one level shift register.

[0405] In an exemplary embodiment, the orthographic projection of the 35th via V35 onto the substrate lies within the orthographic projection range of one of the plurality of first connection electrodes onto the substrate. The fourth insulating layer within the 35th via V35 is etched away, exposing the surface of one of the plurality of first connection electrodes. The 35th via V35 is configured to allow one of the clock signal lines in a subsequently formed first clock signal line group to be connected to one of the plurality of first connection electrodes through this via. Exemplarily, the 35th via in the 4i-3 level shift register exposes the orthographic projection range of the first first connection electrode onto the substrate, the 35th via in the 4i-2 level shift register exposes the orthographic projection range of the second first connection electrode onto the substrate, the 35th via in the 4i-1 level shift register exposes the orthographic projection range of the third first connection electrode onto the substrate, and the 35th via in the 4i level shift register exposes the orthographic projection range of the fourth first connection electrode onto the substrate.

[0406] In an exemplary embodiment, the orthographic projection of the 36th via V36 onto the substrate is within the range of the orthographic projection of the first electrode of the third transistor onto the substrate. The fourth insulating layer within the 36th via V36 is etched away, exposing the surface of the first electrode of the third transistor. The 36th via V36 is configured to allow a subsequently formed first low-level power line to be connected to the first electrode of the third transistor through the via.

[0407] In an exemplary embodiment, the orthogonal projection of the 37th via V37 onto the substrate is located within the range of the orthogonal projection of the first electrode of the fourth transistor (the first electrode of the sixth transistor) onto the substrate. The fourth insulating layer within the 37th via V37 is etched away, exposing the surface of the first electrode of the second transistor. The 37th via V37 is configured to allow a subsequently formed high-level power line to be connected to the first electrode of the fourth transistor (the first electrode of the sixth transistor) through the via.

[0408] In an exemplary embodiment, the orthographic projection of the 38th via V38 onto the substrate lies within the orthographic projection range of one of the plurality of second connection electrodes onto the substrate. The fourth insulating layer within the 38th via V38 is etched away, exposing the surface of one of the plurality of second connection electrodes. The 38th via V38 is configured to allow one of the clock signal lines in a subsequently formed clock signal line group to connect to one of the plurality of second connection electrodes through this via. Exemplarily, the 38th via in the 4i-3 level shift register exposes the orthographic projection range of the third second connection electrode onto the substrate, the 38th via in the 4i-2 level shift register exposes the orthographic projection range of the fourth second connection electrode onto the substrate, the 38th via in the 4i-1 level shift register exposes the orthographic projection range of the first second connection electrode onto the substrate, and the 38th via in the 4i level shift register exposes the orthographic projection range of the second first connection electrode onto the substrate.

[0409] In an exemplary embodiment, the orthographic projection of the 39th via V39 onto the substrate lies within the orthographic projection range of one of the plurality of third connection electrodes onto the substrate. The fourth insulating layer within the 39th via V39 is etched away, exposing the surface of one of the plurality of third connection electrodes. The 39th via V39 is configured to allow one of the clock signal lines in a subsequently formed first clock signal line group to connect to one of the plurality of third connection electrodes through this via. Exemplarily, the 39th via in the 4i-3 level shift register exposes the orthographic projection range of the fourth third connection electrode onto the substrate, the 39th via in the 4i-2 level shift register exposes the orthographic projection range of the first third connection electrode onto the substrate, the 39th via in the 4i-1 level shift register exposes the orthographic projection range of the second third connection electrode onto the substrate, and the 39th via in the 4i level shift register exposes the orthographic projection range of the third first connection electrode onto the substrate.

[0410] In an exemplary embodiment, the orthographic projection of the 40th via V40 on the substrate is within the range of the orthographic projection of the fourth connection electrode on the substrate. The fourth insulating layer within the 40th via V40 is etched away, exposing the surface of the fourth connection electrode. The 40th via V40 is configured to allow a subsequently formed first low-level power line to be electrically connected to the fourth connection electrode through the via.

[0411] In an exemplary embodiment, the orthographic projection of the forty-first via V41 on the substrate is within the range of the orthographic projection of the first clock connection line of the fifth clock signal line on the substrate. The fourth insulating layer within the forty-first via V41 is etched away, exposing the surface of the first clock connection line of the fifth clock signal line. The forty-first via V41 is configured to allow the second clock connection line of the subsequently formed fifth clock signal line to be connected to the first clock connection line of the fifth clock signal line through the via.

[0412] In an exemplary embodiment, the orthographic projection of the forty-second via V42 on the substrate is within the range of the orthographic projection of the first clock connection line of the sixth clock signal line on the substrate. The fourth insulating layer within the forty-second via V42 is etched away, exposing the surface of the first clock connection line of the sixth clock signal line. The forty-second via V42 is configured to allow the second clock connection line of the subsequently formed sixth clock signal line to be connected to the first clock connection line of the sixth clock signal line through the via.

[0413] In an exemplary embodiment, the orthographic projection of the forty-third via V43 on the substrate is within the range of the orthographic projection of the first clock connection line of the seventh clock signal line on the substrate. The fourth insulating layer within the forty-third via V43 is etched away, exposing the surface of the first clock connection line of the seventh clock signal line. The forty-third via V43 is configured to allow the second clock connection line of the subsequently formed seventh clock signal line to be connected to the first clock connection line of the seventh clock signal line through the via.

[0414] In an exemplary embodiment, the orthographic projection of the forty-fourth via V44 on the substrate is within the range of the orthographic projection of the first clock connection line of the eighth clock signal line on the substrate. The fourth insulating layer within the forty-fourth via V44 is etched away, exposing the surface of the first clock connection line of the eighth clock signal line. The forty-fourth via V44 is configured to allow the second clock connection line of the subsequently formed eighth clock signal line to be connected to the first clock connection line of the eighth clock signal line through the via.

[0415] In an exemplary embodiment, the orthographic projection of the forty-fifth via V45 on the substrate is within the range of the orthographic projection of the first second power connection line of the second low-level power line on the substrate. The fourth insulating layer within the forty-fifth via V45 is etched away, exposing the surface of the first second power connection line of the second low-level power line. The forty-fifth via V45 is configured to allow the second second power connection line of the subsequently formed second low-level power line to be connected to the first second power connection line of the second low-level power line through the via.

[0416] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a fourth insulating layer, as shown in Figures 22 and 23. Figure 22 is a schematic diagram of the fourth conductive layer pattern of Figure 9, and Figure 23 is a schematic diagram of Figure 9 after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0417] In an exemplary embodiment, as shown in Figures 22 and 23, the fourth conductive layer pattern may include at least: a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a first low-level power supply line VL, a high-level power supply line VH, a second second power supply connection line VL22 of the second low-level power supply line, a second clock connection line CLK5B of the fifth clock signal line, a second clock connection line CLK6B of the sixth clock signal line, a second clock connection line CLK7B of the seventh clock signal line, and a second clock connection line CLK8B of the eighth clock signal line.

[0418] In an exemplary embodiment, at least one of the following signal lines extends at least partially along the second direction D2: first clock signal line CLK1, second clock signal line CLK2, third clock signal line CLK3, fourth clock signal line CLK4, first low-level power supply line VL, high-level power supply line VH, second second power supply connection line VL22 of the second low-level power supply line, second clock connection line CLK5B of the fifth clock signal line, second clock connection line CLK6B of the sixth clock signal line, second clock connection line CLK7B of the seventh clock signal line, and second clock connection line CLK8B of the eighth clock signal line.

[0419] In an exemplary embodiment, the first clock signal line CLK1, the second clock signal line CLK2, the first low-level power supply line VL, the third clock signal line CLK3, the fourth clock signal line CLK4, the high-level power supply line VH, the second clock connection line CLK5B of the fifth clock signal line, the second clock connection line CLK6B of the sixth clock signal line, the second second power supply connection line VL22 of the second low-level power supply line, the second clock connection line CLK7B of the seventh clock signal line, and the second clock connection line CLK8B of the eighth clock signal line are arranged sequentially along the direction close to the display area.

[0420] In an exemplary embodiment, the first clock signal line CLK1 is connected to the first first connection electrode through the thirty-fifth via in the 4i-3 level shift register, to the first second connection electrode through the thirty-eighth via in the 4i-1 level shift register, and to the first third connection electrode through the thirty-ninth via in the 4i-2 level shift register.

[0421] In an exemplary embodiment, the second clock signal line CLK2 is connected to the second connection electrode through the thirty-fifth via in the 4i-2 level shift register, to the second first connection electrode through the thirty-eighth via in the 4i level shift register, and to the second third connection electrode through the thirty-ninth via in the 4i-1 level shift register.

[0422] In an exemplary embodiment, the third clock signal line CLK3 is connected to the third first connection electrode through the thirty-fifth via in the 4i-1 level shift register, to the third second connection electrode through the thirty-eighth via in the 4i-3 level shift register, and to the third first connection electrode through the thirty-ninth via in the 4i level shift register.

[0423] In an exemplary embodiment, the fourth clock signal line CLK4 is connected to the fourth first connection electrode through the thirty-fifth via in the fourth-i-th stage shift register, to the fourth second connection electrode through the thirty-eighth via in the fourth-i-2-th stage shift register, and to the fourth third connection electrode through the thirty-ninth via in the fourth-i-3-th stage shift register.

[0424] In an exemplary embodiment, the first low-level power line VL1 is connected to the first electrode of the third transistor through the thirty-sixth via and is electrically connected to the fourth connection electrode through the fortieth via.

[0425] In an exemplary embodiment, the high-level power line VH is connected to the first terminal of the fourth transistor (the first terminal of the sixth transistor) through the thirty-seventh via.

[0426] In an exemplary embodiment, the orthographic projection of the second clock connection line CLK5B of the fifth clock signal line on the substrate at least partially overlaps with the orthographic projection of the first clock connection line of the fifth clock signal line on the substrate, and is connected to the first clock connection line of the fifth clock signal line through the forty-first via.

[0427] In an exemplary embodiment, the orthographic projection of the second clock connection line CLK6B of the sixth clock signal line on the substrate at least partially overlaps with the orthographic projection of the first clock connection line of the sixth clock signal line on the substrate, and is connected to the first clock connection line of the sixth clock signal line through the forty-second via.

[0428] In an exemplary embodiment, the orthographic projection of the second clock connection line CLK7B of the seventh clock signal line on the substrate at least partially overlaps with the orthographic projection of the first clock connection line of the seventh clock signal line on the substrate, and is connected to the first clock connection line of the seventh clock signal line through the forty-third via.

[0429] In an exemplary embodiment, the orthographic projection of the second clock connection line CLK8B of the eighth clock signal line on the substrate at least partially overlaps with the orthographic projection of the first clock connection line of the eighth clock signal line on the substrate, and is connected to the first clock connection line of the eighth clock signal line through the forty-fourth via.

[0430] In an exemplary embodiment, the second second power connection line VL22 of the second low-level power line at least partially overlaps with the orthographic projection of the first second power connection line of the second low-level power line on the substrate, and is connected to the first second power connection line of the second low-level power line through the forty-fifth via.

[0431] At this point, the circuit structure layer on the substrate is complete. In a plane parallel to the display substrate, the circuit structure layer may include multiple shift registers. In a plane perpendicular to the display substrate, the circuit structure layer may be disposed on the substrate.

[0432] In an exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be, but is not limited to, one or more of glass and metal sheets; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0433] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0434] In an exemplary embodiment, the semiconductor layer can be an amorphous silicon layer or a polycrystalline silicon layer, or it can be a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, a double layer, or a multilayer.

[0435] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0436] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0437] In an exemplary embodiment, after the circuit structure layer is fabricated, a light-emitting structure layer is fabricated on the circuit structure layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0438] On the substrate with the aforementioned pattern, an anodic conductive film is deposited, and the anodic conductive film is patterned using a patterning process to form an anodic conductive layer pattern disposed on a second planarization layer. On the substrate with the aforementioned pattern, a pixel definition film is deposited, and the pixel definition film is patterned using a patterning process to form a pixel definition layer pattern that exposes the anodic conductive layer pattern. On the substrate with the pixel definition layer pattern, an organic light-emitting material is coated, and the organic light-emitting material is patterned using a patterning process to form an organic structure layer pattern. On the substrate with the organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned using a patterning process to form a cathode conductive layer.

[0439] At this point, the luminescent structure layer has been successfully fabricated on the substrate.

[0440] In an exemplary embodiment, the anode conductive layer includes at least a plurality of anode patterns. These plurality of anode patterns may include the anode of a first light-emitting device, the anode of a second light-emitting device, the anode of a third light-emitting device, and the anode of a fourth light-emitting device. The anode of the first light-emitting device is located in a red sub-pixel emitting red light, the anode of the second light-emitting device may be located in a blue sub-pixel emitting blue light, the anode of the third light-emitting device may be located in a first green sub-pixel emitting green light, and the anode of the fourth light-emitting device may be located in a second green sub-pixel emitting green light.

[0441] In an exemplary embodiment, the anodes of the first and second light-emitting devices can be alternately arranged along a first direction, and the anodes of the third and fourth light-emitting devices can be alternately arranged along the first direction. Alternatively, the anodes of the first and second light-emitting devices can be alternately arranged along a second direction, and the anodes of the third and fourth light-emitting devices can be alternately arranged along the second direction.

[0442] In an exemplary embodiment, the anode shape and area of ​​the four sub-pixels in a pixel unit may be the same or different.

[0443] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0444] In an exemplary embodiment, the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.

[0445] In an exemplary embodiment, the cathode conductive layer may include at least the cathodes of a plurality of light-emitting devices.

[0446] In an exemplary embodiment, the cathode layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or the aforementioned conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0447] The display substrate described in this embodiment can be used in display products of any resolution.

[0448] In an exemplary embodiment, the subsequent preparation process may include: forming an encapsulation structure layer on the cathode conductive layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0449] This disclosure also provides a method for preparing a display substrate, configured to prepare the display substrate provided in any of the foregoing embodiments. The method for preparing the display substrate may include the following steps:

[0450] Provide a base.

[0451] A gate drive circuit, a first low-level power supply line, and a second low-level power supply line are formed on the substrate in the non-display area.

[0452] In an exemplary embodiment, the gate drive circuit includes: a plurality of cascaded shift registers, at least one shift register including: a shift sub-circuit and an output sub-circuit, the shift sub-circuit including: at least one transistor, the output sub-circuit including: at least one output transistor; the orthographic projection of a first low-level power line on the substrate at least partially overlaps with the orthographic projection of at least one transistor in the shift sub-circuit on the substrate, and the orthographic projection of a second low-level power line on the substrate is located between the orthographic projection of at least one transistor in the shift sub-circuit on the substrate and the orthographic projection of at least one output transistor in the output sub-circuit on the substrate.

[0453] In an exemplary embodiment, the line width of the first low-level power line along the first direction is smaller than the line width of the second low-level power line along the first direction.

[0454] In an exemplary embodiment, the method for preparing the display substrate may further include:

[0455] A first clock signal line group, a second clock signal line group, an initial signal line, and a high-level power supply line are formed on the substrate in the non-display area.

[0456] This disclosure also provides a display device, which may include a display substrate.

[0457] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0458] In an exemplary embodiment, the display device can be any product or component with display function, such as a wearable device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0459] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0460] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0461] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate having a display area and a non-display area located on at least one side of the display area, characterized in that, include: The data includes a substrate and a gate driving circuit, a first low-level power supply line, and a second low-level power supply line disposed on the substrate and located in the non-display area. The gate driving circuit includes a plurality of cascaded shift registers, at least one of which includes a shift sub-circuit and an output sub-circuit. The shift sub-circuit is electrically connected to a first low-level power supply terminal and a cascaded signal output terminal, respectively. The output sub-circuit is electrically connected to a first low-level power supply terminal, a second low-level power supply terminal, and a drive signal output terminal, respectively. The shift sub-circuit includes at least one transistor, and the output sub-circuit includes at least one output transistor. The first low-level power line is electrically connected to the first low-level power supply terminal of the at least one level shift register, and the second low-level power line is electrically connected to the second low-level power supply terminal of the at least one level shift register. The second low-level power line is located on the side of the first low-level power line closer to the display area. The orthographic projection of the first low-level power line on the substrate at least partially overlaps with the orthographic projection of at least one transistor in the shift sub-circuit on the substrate, and the orthographic projection of the second low-level power line on the substrate is located between the orthographic projection of at least one transistor in the shift sub-circuit on the substrate and the orthographic projection of at least one output transistor in the output sub-circuit on the substrate. The width of the first low-level power line along the first direction is smaller than the width of the second low-level power line along the first direction.

2. The display substrate according to claim 1, characterized in that, At least one of the first low-level power lines and the second low-level power lines extends at least partially along a second direction, where the first direction and the second direction intersect. The signal of at least one of the first low-level power line and the second low-level power line is a negative voltage signal, and the absolute value of the voltage of the power signal of the first low-level power line is less than the absolute value of the voltage of the power signal of the second low-level power line.

3. The display substrate according to claim 1, characterized in that, The first low-level power line includes at least one first power connection line, and the second low-level power line includes multiple second power connection lines that are arranged in different layers and interconnected with each other. The first power connection line and the second power connection line extend at least partially along the second direction, and a plurality of second power connection lines are stacked sequentially along a direction away from the substrate, and at least two of the plurality of second power connection lines have orthographic projections on the substrate that at least partially overlap. The number of first power connection lines included in the first low-level power line is less than the number of second power connection lines included in the second low-level power line. The at least one first power connection line is disposed in the same layer as at least one of the plurality of second power connection lines, and the film layer containing at least one of the plurality of second power connection lines is located on the side of the film layer containing at least one first power connection line closer to the substrate.

4. The display substrate according to claim 3, characterized in that, The first low-level power line includes: a first power connection line; the second low-level power line includes: two second power connection lines that are disposed in different layers and connected to each other, wherein the second power connection line is located on the side of the first power connection line away from the substrate. The first power connection cable and the second power connection cable are arranged on the same layer; Alternatively, the first low-level power line includes: two first power connection lines that are disposed in different layers and interconnected with each other; the second low-level power line includes: three second power connection lines that are disposed in different layers and interconnected with each other; the second first power connection line is located on the side of the first first power connection line away from the substrate; the first second power connection line is located on the side of the second second power connection line close to the substrate; and the third second power connection line is located on the side of the second second power connection line away from the substrate. The first power connection line is arranged on the same layer as the second power connection line, and the second power connection line is arranged on the same layer as the third power connection line.

5. The display substrate according to claim 1, characterized in that, Also includes: The first clock signal line group is disposed on the substrate and located in the non-display area. The at least one level shift register includes: a first clock signal terminal, a second clock signal terminal and a third clock signal terminal. The shift sub-circuit of the at least one level shift register is respectively connected to the first clock signal terminal, the second clock signal terminal and the third clock signal terminal. The first clock signal line group includes: a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line arranged sequentially along the direction close to the display area. At least one of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line extends at least partially along the second direction; The first clock signal terminal of the 4i-3 stage shift register is electrically connected to the first clock signal line; the second clock signal terminal of the 4i-3 stage shift register is electrically connected to the second clock signal line; the third clock signal terminal of the 4i-3 stage shift register is electrically connected to the third clock signal line; the first clock signal terminal of the 4i-2 stage shift register is electrically connected to the second clock signal line; the second clock signal terminal of the 4i-2 stage shift register is electrically connected to the third clock signal line; and the third clock signal terminal of the 4i-2 stage shift register is electrically connected to the fourth clock signal line. The first clock signal terminal of the 4i-1 stage shift register is electrically connected to the third clock signal line, the second clock signal terminal of the 4i-1 stage shift register is electrically connected to the fourth clock signal line, the third clock signal terminal of the 4i-1 stage shift register is electrically connected to the first clock signal line, the first clock signal terminal of the 4i stage shift register is electrically connected to the fourth clock signal line, the second clock signal terminal of the 4i stage shift register is electrically connected to the first clock signal line, and the third clock signal terminal of the 4i stage shift register is electrically connected to the second clock signal line. The orthographic projection of the first low-level power line on the substrate is located between the orthographic projections of the second clock signal line on the substrate and the third clock signal line on the substrate. The orthographic projection of the second low-level power line on the substrate is located on the side of the orthographic projection of at least one clock signal line in the first clock signal line group that is closer to the display area.

6. The display substrate according to claim 5, characterized in that, The shift sub-circuit of at least one shift register includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; wherein, the control electrode of the first transistor is electrically connected to a first clock signal terminal, the first electrode of the first transistor is electrically connected to a signal input terminal, the second electrode of the first transistor is electrically connected to a first node, the control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to a second node; the control electrode of the third transistor is electrically connected to the first clock signal terminal, the first electrode of the third transistor is electrically connected to a first low-level power supply terminal, and the second electrode of the third transistor is electrically connected to the second node; the control electrode of the fourth transistor is electrically connected to the second node, and the fourth transistor's... The first transistor is electrically connected to the high-level power supply terminal; the second transistor of the fourth transistor is electrically connected to the cascaded signal output terminal; the control electrode of the fifth transistor is electrically connected to the third node; the first transistor of the fifth transistor is electrically connected to the second clock signal terminal; the second transistor of the fifth transistor is electrically connected to the cascaded signal output terminal; the control electrode of the sixth transistor is electrically connected to the second node; the first transistor of the sixth transistor is electrically connected to the high-level power supply terminal; the second transistor of the sixth transistor is electrically connected to the fourth node; the control electrode of the seventh transistor is electrically connected to the third clock signal terminal; the first transistor of the seventh transistor is electrically connected to the fourth node; the second transistor of the seventh transistor is electrically connected to the first node; the control electrode of the eighth transistor is electrically connected to the first low-level power supply terminal; the first transistor of the eighth transistor is electrically connected to the first node; the second transistor of the eighth transistor is electrically connected to the third node. The control electrode of the first transistor and the control electrode of the third transistor are integrally structured and extend at least partially along the first direction. The orthographic projection of the control electrode of the first transistor on the substrate at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the first clock signal line, the second clock signal line, the first low-level power supply line, the third clock signal line, and the fourth clock signal line. At least a portion of the control electrode of the second transistor extends along the first direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the second clock signal line and the first low-level power line. The control electrode of the fourth transistor and the control electrode of the sixth transistor are integrally structured and extend at least partially along the first direction. The orthographic projection of the control electrode of the fourth transistor on the substrate at least partially overlaps with the orthographic projection of at least one of the third clock signal line and the fourth clock signal line on the substrate. The control electrode of the fifth transistor extends at least partially along the first direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the second clock signal line, the first low-level power supply line, the third clock signal line, and the fourth clock signal line. The control electrode of the seventh transistor extends at least partially along the first direction, and its orthogonal projection on the substrate at least partially overlaps with the orthogonal projections on the substrate of at least one of the first clock signal line, the second clock signal line, the first low-level power supply line, the third clock signal line, and the fourth clock signal line. The control electrode of the eighth transistor extends at least partially along a first direction, and its orthogonal projection on the substrate at least partially overlaps with the orthogonal projections on the substrate of at least one of the first clock signal line, the second clock signal line, the first low-level power supply line, the third clock signal line, and the fourth clock signal line.

7. The display substrate according to claim 6, characterized in that, Also includes: Multiple vias that expose the control electrode of the first transistor, and two of the multiple vias that expose the control electrode of the first transistor respectively expose the two ends of the control electrode of the first transistor; Multiple vias that expose the control electrode of the seventh transistor are provided, and two of the multiple vias that expose the control electrode of the seventh transistor expose the two ends of the control electrode of the seventh transistor, respectively.

8. The display substrate according to claim 6, characterized in that, Also includes: Multiple first connection lines are disposed on the substrate and located in the non-display area. One of the multiple first connection lines is electrically connected to the first electrode of the fifth transistor of at least one level shift register. The first connection line extends along a first direction. The orthographic projection of the first terminal of the fifth transistor of at least one level shift register on the substrate at least partially overlaps with the orthographic projection of the fourth clock signal line and one of the plurality of first connection lines on the substrate. The orthographic projection of one of the plurality of first connection lines on the substrate at least partially overlaps with the orthographic projection of at least one of the first clock signal line, the second clock signal line, the first low-level power supply line and the third clock signal line on the substrate. The first connection line is located on the side of the film layer where the first and second electrodes of at least one transistor of the at least one level shift register are located, close to the substrate.

9. The display substrate according to claim 8, characterized in that, Also includes: Multiple vias of the first connecting line are exposed, and two of the multiple vias of the first connecting line expose the end of the first connecting line closer to the display area and the end farther away from the display area, respectively.

10. The display substrate according to claim 5, characterized in that, The line width of one of the first low-level power lines and the second low-level power lines along the first direction is smaller than the line width of at least one clock signal line in the first clock signal line group along the first direction.

11. The display substrate according to claim 5, characterized in that, Also includes: The second clock signal line group is disposed on the substrate and located in the non-display area. The second clock signal line group is located on the side of the first clock signal line group closer to the display area. The at least one level shift register includes: a fourth clock signal terminal. The output sub-circuit of the at least one level shift register is electrically connected to the fourth clock signal terminal. The second clock signal line group includes: a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line arranged sequentially along the direction closer to the display area. The fifth clock signal line and the seventh clock signal line receive the same clock signal, the sixth clock signal line and the eighth clock signal line receive the same signal, and at least one of the fifth clock signal line, the sixth clock signal line, the seventh clock signal line and the eighth clock signal line extends at least partially along the second direction; The fourth clock signal terminal of at least one shift register is electrically connected to one of the signal line groups of the first and second signal line groups. The fourth clock signal terminals of adjacent shift registers are connected to different signal line groups. The first signal line group includes a fifth clock signal line and a seventh clock signal line, and the second signal line group includes a sixth clock signal line and an eighth clock signal line. The orthographic projection of the second low-level power line on the substrate lies between the orthographic projections of the sixth clock signal line and the seventh clock signal line on the substrate.

12. The display substrate according to claim 11, characterized in that, The output sub-circuit of at least one shift register includes: a tenth transistor and a third capacitor, wherein the control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the fourth clock signal terminal, the second electrode of the tenth transistor is electrically connected to the drive signal output terminal, the first plate of the third capacitor is electrically connected to the fourth clock signal terminal, and the second plate of the third capacitor is electrically connected to the fifth node. When the fourth clock signal terminal of at least one shift register is electrically connected to the first signal line group, the first terminal of the tenth transistor of at least one shift register is electrically connected to the seventh clock signal line, and the first plate of the third capacitor of at least one shift register is electrically connected to the fifth clock signal line. When the fourth clock signal terminal of at least one shift register is electrically connected to the second signal line group, the first terminal of the tenth transistor of at least one shift register is electrically connected to the eighth clock signal line, and the first plate of the third capacitor of at least one shift register is electrically connected to the sixth clock signal line.

13. The display substrate according to claim 12, characterized in that, The output sub-circuit of the at least one level shift register further includes: a ninth transistor and an eleventh transistor, wherein the control electrode of the ninth transistor is electrically connected to the fifth node, the first electrode of the ninth transistor is electrically connected to the second low-level power supply terminal, the second electrode of the ninth transistor is electrically connected to the drive signal output terminal, the control electrode of the eleventh transistor is electrically connected to the first low-level power supply terminal, the first electrode of the eleventh transistor is electrically connected to the second node, and the second electrode of the eleventh transistor is electrically connected to the fifth node. The orthographic projection of at least one of the fifth clock signal line, the sixth clock signal line, and the second low-level power line onto the substrate lies between the orthographic projection of at least one of the transistors in the shift sub-circuit and the eleventh transistor in the output sub-circuit onto the substrate and the orthographic projection of at least one of the ninth and tenth transistors in the output sub-circuit onto the substrate. The orthographic projection of at least one of the seventh and eighth clock signal lines onto the substrate lies on the side of the orthographic projection of at least one of the ninth and tenth transistors in the output sub-circuit closer to the display area.

14. The display substrate according to claim 11, characterized in that, The line width of at least one of the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line, the seventh clock signal line, and the eighth clock signal line along the first direction is greater than the line width of at least one of the fifth clock signal line, the sixth clock signal line, and the second low-level power line along the first direction.

15. The display substrate according to claim 11, characterized in that, At least one clock signal line from the fifth clock signal line to the eighth clock signal line includes: a first clock connection line and a second clock connection line that are disposed in different layers and interconnected with each other, wherein the first clock connection line and the second clock connection line extend at least partially along a second direction, and the orthographic projections of the first clock connection line and the second clock connection line of at least one clock signal line from the fifth clock signal line to the eighth clock signal line on the substrate at least partially overlap. The film layer containing the first clock connection line of at least one clock signal line from the fifth clock signal line to the eighth clock signal line is located on the side of the film layer containing the second clock connection line closer to the substrate. The second clock connection line of at least one clock signal line from the fifth clock signal line to the eighth clock signal line is disposed in the same layer as at least one clock signal line from the first clock signal line to the fourth clock signal line.

16. The display substrate according to claim 11, characterized in that, Also includes: An initial signal line and a high-level power supply line are disposed on the substrate and located in the non-display area. At least one shift register includes: a signal input terminal and a high-level power supply terminal. The high-level power supply line is electrically connected to the high-level power supply terminal of the at least one shift register. The initial signal line is electrically connected to the signal input terminal of the at least one shift register. At least a portion of at least one of the initial signal line and the high-level power supply line extends along a second direction. The orthographic projection of the initial signal line on the substrate is located on the side of the first clock signal line group away from the display area, and the orthographic projection of the high-level power line on the substrate is located between the orthographic projections of the first clock signal line group on the substrate and the orthographic projections of the second clock signal line group on the substrate.

17. The display substrate according to claim 16, characterized in that, The orthographic projection of the high-level power line on the substrate at least partially overlaps with the orthographic projection of the control electrode of at least one of the fourth and fifth transistors in at least one level shift register on the substrate.

18. The display substrate according to claim 16, characterized in that, The linewidth of the high-level power line along the first direction is greater than the linewidth of at least one of the first low-level power line and the initial signal line along the first direction, and less than the linewidth of at least one of the clock signal lines in the first clock signal line group along the first direction.

19. The display substrate according to claim 11, characterized in that, The shift sub-circuit further includes a first capacitor, and the output sub-circuit further includes a second capacitor and a third capacitor. At least one of the first capacitor, the second capacitor, and the third capacitor includes a first plate and a second plate. The second plate of the at least one capacitor is located on the side of the first plate of the at least one capacitor away from the substrate. The first plate of the first capacitor is electrically connected to a third node, and the second plate of the first capacitor is electrically connected to a cascaded signal output terminal. The first plate of the second capacitor is electrically connected to a fifth node and a second low-level power supply terminal. The first plate of the third capacitor is electrically connected to a fourth clock signal terminal, and the second plate of the third capacitor is electrically connected to the fifth node. The orthographic projection of the first capacitor on the substrate is located between the orthographic projections of the first clock signal line group on the substrate and the orthographic projections of the second clock signal line group on the substrate, and at least partially overlaps with the orthographic projection of the high-level power line on the substrate. The orthographic projection of the second capacitor onto the substrate lies between the orthographic projection of the second low-level power line onto the substrate and the orthographic projection of the seventh clock signal line onto the substrate; The orthogonal projection of the third capacitor on the substrate lies between the orthogonal projection of the sixth clock signal line on the substrate and the orthogonal projection of at least one output transistor in the output sub-circuit on the substrate, and at least partially overlaps with the orthogonal projection of the second low-level power supply line on the substrate.

20. The display substrate according to claim 19, characterized in that, At least one of the first and second plates of the at least one capacitor includes a main body and a connecting part, wherein the main body and the connecting part of the at least one plate are connected. The orthographic projection of the main body of the first plate of the first capacitor onto the substrate covers the orthographic projection of the main body of the second plate of the first capacitor onto the substrate, the orthographic projection of the main body of the second plate of the second capacitor onto the substrate covers the orthographic projection of the main body of the first plate of the second capacitor onto the substrate, and the orthographic projection of the main body of the second plate of the third capacitor onto the substrate covers the orthographic projection of the main body of the first plate of the third capacitor onto the substrate. The orthographic projection of the connection portion of the second plate of the third capacitor on the substrate at least partially overlaps with the orthographic projection of at least one of the fifth and sixth clock signal lines on the substrate.

21. The display substrate according to claim 19, characterized in that, The length of the main body of the second plate of the third capacitor along the first direction is greater than the line width of the second low-level power line along the first direction. The orthographic projection of the portion of the second low-level power line near the boundary of the display area and away from the boundary of the display area on the substrate is within the range of the orthographic projection of the main body of the second plate of the third capacitor on the substrate. The distance between the orthographic projection of the main body of the second plate of the third capacitor away from the display area and the orthographic projection of the sixth clock signal line near the display area on the substrate is greater than 1 micrometer, and the distance between the orthographic projection of the second low-level power line away from the display area and the orthographic projection on the substrate is greater than 1 micrometer. The distance between the orthographic projection of the main body of the second plate of the third capacitor near the boundary of the display area on the substrate and the orthographic projection of the second low-level power line near the boundary of the display area on the substrate is greater than 1 micrometer.

22. The display substrate according to claim 19, characterized in that, The area of ​​the first capacitor is larger than the area of ​​at least one of the second capacitor and the third capacitor; The area of ​​the third capacitor is larger than the area of ​​the second capacitor.

23. The display substrate according to claim 6, characterized in that, The active patterns of the first transistor and the third transistor are arranged along a first direction, and a straight line extending along the first direction passes through at least a portion of the control electrode of the first transistor and the active pattern of the second transistor.

24. The display substrate according to claim 11, characterized in that, The output sub-circuit of at least one shift register includes: a tenth transistor, wherein the tenth transistor is an output transistor; The control electrode of the tenth transistor includes: a first connection segment, a second connection segment, and a plurality of first branch segments, wherein the second connection segment is located on the side of the first connection segment closer to the display area, and the plurality of first branch segments are located on the side of the second connection segment closer to the display area; the second electrode of the tenth transistor includes: a third connection segment and a plurality of second branch segments, wherein the plurality of second branch segments are located on the side of the third connection segment closer to the display area; The first connecting segment extends along a first direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the fifth clock signal line, the sixth clock signal line, and the second low-level power line; the second connecting segment extends along a second direction, one of the plurality of first branch segments extends along the first direction, and the plurality of first branch segments are arranged along the second direction; the third connecting segment extends along the second direction, one of the plurality of second branch segments extends along the first direction, and the plurality of second branch segments are arranged along the second direction. The orthographic projection of the third connecting segment on the substrate at least partially overlaps with the orthographic projection of the first connecting segment on the substrate, but does not overlap with the orthographic projection of the second connecting segment on the substrate. At least one of the plurality of first branch segments does not overlap with the orthographic projections of the third connecting segment and at least one of the plurality of second branch segments on the substrate. The orthographic projection of at least one of the plurality of first branch segments on the substrate is located between the orthographic projections of at least two of the plurality of second branch segments on the substrate.

25. The display substrate according to claim 24, characterized in that, The aspect ratio of the channel region of the active pattern of the tenth transistor is greater than 40.

26. The display substrate according to claim 2, characterized in that, The linewidth of the first low-level power line along the first direction is in the range of 4 micrometers to 20 micrometers, and the linewidth of the second low-level power line along the first direction is in the range of 4 micrometers to 50 micrometers.

27. The display substrate according to claim 11, characterized in that, The linewidth of at least one of the seventh and eighth clock signal lines along the first direction is in the range of 10 micrometers to 50 micrometers.

28. The display substrate according to claim 20, characterized in that, The capacitance value of the first capacitor is greater than or equal to 0.3pF.

29. The display substrate according to claim 1, characterized in that, Also includes: A circuit structure layer disposed on a substrate, the circuit structure layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked sequentially on the substrate, at least one level shift register comprising: a plurality of transistors and a plurality of capacitors, the gate drive circuit, the first low-level power supply line and the second low-level power supply line disposed on the circuit structure layer; The display substrate further includes: a first connection line, an initial signal line, a high-level power supply line, and a first clock signal line to an eighth clock signal line; The semiconductor layer includes at least: an active pattern of at least one transistor from a plurality of transistors in at least one level shift register; The first conductive layer includes: a control electrode of at least one transistor among a plurality of transistors in at least one level shift register and a first plate of at least one capacitor among a plurality of capacitors; The second conductive layer includes: a second plate of at least one capacitor located in at least one of the transistors of a first-stage shift register; The third conductive layer includes: a first and second electrode of at least one of a plurality of transistors located in at least one level shift register, and an initial signal line; The fourth conductive layer includes: a high-level power supply line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; The first connection line is located in the first conductive layer or the second conductive layer, the first low-level power line is located in the fourth conductive layer, the second low-level power line is located in the third and fourth conductive layers, and at least one of the fifth to eighth clock signal lines is located in the third and fourth conductive layers.

30. The display substrate according to claim 1, characterized in that, Also includes: A circuit structure layer disposed on a substrate, the circuit structure layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially stacked on the substrate, at least one level shift register comprising: a plurality of transistors and a plurality of capacitors, the gate drive circuit, the first low-level power supply line and the second low-level power supply line disposed on the circuit structure layer; The display substrate further includes: a first connection line, an initial signal line, a high-level power supply line, and first to eighth clock signal lines. The semiconductor layer includes at least: an active pattern of at least one transistor from a plurality of transistors in at least one level shift register; The first conductive layer includes: a control electrode of at least one transistor among a plurality of transistors in at least one level shift register and a first plate of at least one capacitor among a plurality of capacitors; The second conductive layer includes: a second plate of at least one capacitor located in at least one of the transistors of a first-stage shift register; The third conductive layer includes: a first and second electrode of at least one of a plurality of transistors located in at least one level shift register, and an initial signal line; The fourth conductive layer includes: a high-level power supply line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; The first connection line is located in the first conductive layer or the second conductive layer, the first low-level power line is located in at least one of the fourth and fifth conductive layers, the second low-level power line is located in the third, fourth and fifth conductive layers, and at least one of the fifth to eighth clock signal lines is located in at least two of the third, fourth and fifth conductive layers.

31. A display device, characterized in that, include: The display substrate as described in any one of claims 1 to 30.

32. A method for preparing a display substrate, characterized in that, The method, configured to prepare a display substrate as described in any one of claims 1 to 30, comprises: Provide a base; A gate drive circuit, a first low-level power supply line, and a second low-level power supply line located in a non-display area are formed on the substrate. The gate drive circuit includes: a plurality of cascaded shift registers, at least one shift register including: a shift sub-circuit and an output sub-circuit, the shift sub-circuit including: at least one transistor, the output sub-circuit including: at least one output transistor; the orthographic projection of the first low-level power line on the substrate at least partially overlaps with the orthographic projection of at least one transistor in the shift sub-circuit on the substrate, and the orthographic projection of the second low-level power line on the substrate is located between the orthographic projection of at least one transistor in the shift sub-circuit on the substrate and the orthographic projection of at least one output transistor in the output sub-circuit on the substrate; The width of the first low-level power line along the first direction is smaller than the width of the second low-level power line along the first direction.

33. The method according to claim 32, characterized in that, The method further includes: A first clock signal line group, a second clock signal line group, an initial signal line, and a high-level power supply line are formed on the substrate in the non-display area.

Images