Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a gate driving circuit (GOA) and a clock signal line set (CLK). The clock signal line set (CLK) comprises multiple clock signal lines. The gate driving circuit (GOA) comprises multiple cascaded shift registers, and at least one stage of shift register among the multiple cascaded shift registers is electrically connected to at least one clock signal line among the multiple clock signal lines. The at least one stage of shift register among the multiple cascaded shift registers comprises at least one output transistor. An orthographic projection of the at least one clock signal line among the multiple clock signal lines onto a base at least partially overlaps with an orthographic projection of the at least one output transistor of the at least one stage of shift register among the multiple cascaded shift registers onto the base.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202411578814.3, filed on November 6, 2024, entitled "Display Substrate and Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), and liquid crystal displays are all light-emitting display devices, possessing advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays, controlled by thin-film transistors (TFTs), have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a display substrate having a display area and a non-display area located on at least one side of the display area. The display substrate includes: a substrate and a gate driving circuit and a clock signal line group disposed on the substrate and located in the non-display area. The clock signal line group includes: a plurality of clock signal lines. The gate driving circuit includes: a plurality of cascaded shift registers. At least one of the plurality of cascaded shift registers is electrically connected to at least one of the plurality of clock signal lines. The at least one of the plurality of cascaded shift registers includes: at least one output transistor.

[0006] The orthographic projection of at least one of the multiple clock signal lines on the substrate at least partially overlaps with the orthographic projection of at least one output transistor of at least one stage of the multiple cascaded shift registers on the substrate.

[0007] In an exemplary embodiment, the at least one output transistor includes a fourth transistor and a fifth transistor, wherein the second terminals of the fourth transistor and the fifth transistor are electrically connected to a signal output terminal, and the first terminal of the fifth transistor is electrically connected to a first clock signal terminal.

[0008] The plurality of clock signal lines include: a first clock signal line and a second clock signal line, wherein at least a portion of at least one of the first clock signal line and the second clock signal line extends along a second direction;

[0009] The first clock signal terminal of at least one shift register is electrically connected to one of the first clock signal lines and the second clock signal line, and the first clock signal terminals of adjacent shift registers are connected to different clock signal lines;

[0010] The orthographic projection of at least one of the first clock signal lines and the second clock signal line onto the substrate at least partially overlaps with the orthographic projection of at least one of the fourth and fifth transistors in at least one level shift register onto the substrate.

[0011] In an exemplary embodiment, at least one shift register further includes: a first transistor, a second transistor, a third transistor, and a seventh transistor, wherein the control electrode of the first transistor, the first electrode of the second transistor, and the control electrode of the third transistor are electrically connected to a second clock signal terminal, and the control electrode of the seventh transistor is electrically connected to a third clock signal terminal.

[0012] The plurality of clock signal lines further includes: a third clock signal line and a fourth clock signal line, wherein at least a portion of at least one of the third clock signal line and the fourth clock signal line extends along a second direction;

[0013] The second clock signal terminal of at least one stage shift register is electrically connected to one of the third and fourth clock signal lines, and the third clock signal terminal of at least one stage shift register is electrically connected to the other of the third and fourth clock signal lines. The second clock signal terminals of adjacent stages shift registers are connected to different signal lines, and the third clock signal terminals of adjacent stages shift registers are connected to different signal lines.

[0014] The orthographic projection of at least one of the third and fourth clock signal lines onto the substrate is located on the side of the orthographic projection of at least one of the first and second clock signal lines onto the substrate that is away from the display area.

[0015] In an exemplary embodiment, it further includes: a power signal line group disposed on the substrate and located in the non-display area; at least one level shift register further includes: an eighth transistor, wherein the first electrode of the third transistor and the control electrode of the eighth transistor are respectively electrically connected to the first power supply terminal;

[0016] The power signal line group includes: a first power line, at least a portion of which extends along a second direction, and a first power supply terminal of at least one shift register is electrically connected to the first power line;

[0017] The orthographic projection of the first power line on the substrate lies between the orthographic projections of at least one of the first and second clock signal lines on the substrate and the orthographic projections of at least one of the third and fourth clock signal lines on the substrate, and at least partially overlaps with the orthographic projection of at least one transistor in at least one level shift register on the substrate.

[0018] In an exemplary embodiment, the first terminal of the fourth transistor in at least one level shift register is electrically connected to the second power supply terminal;

[0019] The power signal line group further includes: a second power line, at least a portion of which extends along a second direction, and the second power supply terminal of at least one shift register is electrically connected to the second power line;

[0020] The orthographic projection of the second power line on the substrate is located on the side of the orthographic projection of at least one of the first clock signal line and the second clock signal line on the substrate that is closer to the display area.

[0021] In an exemplary embodiment, at least one shift register further includes: a sixth transistor, wherein the first terminal of the sixth transistor is electrically connected to a third power supply terminal;

[0022] The power signal line group further includes: a third power line, at least a portion of which extends along the second direction, and the third power supply terminal of at least one shift register is electrically connected to the third power line;

[0023] The orthographic projection of the third power line onto the substrate lies between the orthographic projection of at least one of the third and fourth clock signal lines onto the substrate and the orthographic projection of the first power line onto the substrate.

[0024] In an exemplary embodiment, the first terminal of the first transistor in at least one shift register is electrically connected to the signal input terminal;

[0025] The display substrate further includes: an initial signal line disposed on the substrate and located in the non-display area, the initial signal line extending at least partially along a second direction, and the signal input terminal of at least one shift register being electrically connected to the initial signal line;

[0026] The orthographic projection of the initial signal line on the substrate is located on the side of the orthographic projection of at least one of the third and fourth clock signal lines on the substrate that is away from the display area.

[0027] In an exemplary embodiment, the signal lines connected to at least one shift register include: a first clock signal line, a second clock signal line, and a first power supply line;

[0028] The signal lines connected to at least one shift register further include at least one of a first signal line and a second signal line, wherein the first signal line is a signal line among the third clock signal line, the fourth clock signal line, the second power supply line, and the third power supply line that at least partially overlaps with the orthogonal projection of at least one transistor in the at least one shift register on the substrate, and the second signal line is a signal line among the third clock signal line, the fourth clock signal line, the second power supply line, and the third power supply line that does not overlap with the orthogonal projection of at least one transistor in the at least one shift register on the substrate.

[0029] In an exemplary embodiment, the system further includes: a circuit structure layer disposed on the substrate, the circuit structure layer comprising: a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; the first signal line is a signal line among the third clock signal line, the fourth clock signal line, the second power supply line, the third power supply line, and the initial signal line that at least partially overlaps with the orthographic projection of at least one transistor in at least one level shift register on the substrate; the second signal line is a signal line among the third clock signal line, the fourth clock signal line, the second power supply line, the third power supply line, and the initial signal line that does not overlap with the orthographic projection of at least one transistor in at least one level shift register on the substrate.

[0030] The first clock signal line, the second clock signal line, the first power line, and the first signal line are located in the fifth conductive layer;

[0031] The second signal line includes: a first connecting line and a second connecting line that are interconnected, wherein the orthographic projection of the first connecting line on the substrate and the orthographic projection of the second connecting line on the substrate at least partially overlap;

[0032] The first connection line of at least one second signal line is located in the fourth conductive layer, and the second connection line of at least one second signal line is located in the fifth conductive layer.

[0033] In an exemplary embodiment, the system further includes: a circuit structure layer disposed on the substrate, the circuit structure layer comprising: a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer; the first signal line is a signal line among the third clock signal line, the fourth clock signal line, the second power line, the third power line, and the initial signal line that at least partially overlaps with the orthographic projection of at least one transistor in at least one level shift register on the substrate; the second signal line is a signal line among the third clock signal line, the fourth clock signal line, the second power line, the third power line, and the initial signal line that does not have an overlapping region with the orthographic projection of at least one transistor in at least one level shift register on the substrate.

[0034] At least one of the first clock signal line, the second clock signal line, the first power line, and the first signal line includes: a third connection line and a fourth connection line that are interconnected, wherein the orthographic projection of the third connection line on the substrate and the orthographic projection of the fourth connection line on the substrate at least partially overlap, the third connection line of at least one signal line is located in the fifth conductive layer, and the fourth connection line of at least one signal line is located in the sixth conductive layer.

[0035] The second signal line includes: a fifth connecting line, a sixth connecting line, and a seventh connecting line that are interconnected. The orthographic projections of at least two of the fifth connecting lines, the sixth connecting line, and the seventh connecting line located on the same signal line on the substrate at least partially overlap. The fifth connecting line of at least one signal line is located in the fourth conductive layer, the sixth connecting line of at least one signal line is located in the fifth conductive layer, and the seventh connecting line of at least one signal line is located in the sixth conductive layer.

[0036] In an exemplary embodiment, at least one shift register includes: a plurality of transistors, at least one of the plurality of transistors being an N-type transistor, and at least one of the plurality of transistors including: a first control electrode and a second control electrode interconnected with each other;

[0037] The first control electrode of at least one transistor is located on the side of the active pattern of at least one transistor close to the substrate, and the second control electrode of at least one transistor is located on the side of the active pattern of at least one transistor away from the substrate. The orthographic projection of the first control electrode of at least one transistor on the substrate and the orthographic projection of the second control electrode of at least one transistor on the substrate at least partially overlap.

[0038] In an exemplary embodiment, the first control electrode of at least one transistor is located in the second conductive layer, the second control electrode of at least one transistor is located in the third conductive layer, and the active pattern of at least one transistor is located in the semiconductor layer.

[0039] The semiconductor layer is a metal oxide layer.

[0040] In an exemplary embodiment, it further includes: a plurality of first signal connection lines and a plurality of second signal connection lines, wherein at least a portion of at least one of the plurality of first signal connection lines extends along a first direction, and at least a portion of at least one of the plurality of second signal connection lines extends along the first direction, wherein the first direction and the second direction intersect.

[0041] At least one first signal connection line is electrically connected to at least one electrode of the first control electrode and the second control electrode of the first transistor, at least one electrode of the control electrode and the second control electrode of the third transistor, and one of the signal lines of the third clock signal line and the fourth clock signal line, respectively; at least one second signal connection line is electrically connected to one electrode of the first control electrode and the second control electrode of the seventh transistor and the other signal line of the third clock signal line and the fourth clock signal line, respectively.

[0042] At least one of the first signal connection line and the second signal connection line is located in the first conductive layer or the second conductive layer.

[0043] In an exemplary embodiment, it further includes: a plurality of connection vias disposed on the substrate and located in the non-display area;

[0044] The number of connection vias exposing at least one first control electrode of a transistor is at least one, and the number of connection vias exposing at least one second control electrode of a transistor is at least one.

[0045] In an exemplary embodiment, at least one level shift register further includes: a second capacitor, the first plate of the second capacitor being electrically connected to the control electrode of the fifth transistor, the second plate of the second capacitor being electrically connected to the signal output terminal, and the plurality of connection vias including: a first connection via, a second connection via, a third connection via, and a fourth connection via.

[0046] The first and second connection vias expose the first control electrode of the fifth transistor, the second connection via is located on the side of the first connection via closer to the display area, the third and fourth connection vias expose the second control electrode of the fifth transistor, and the fourth connection via is located on the side of the third connection via closer to the display area;

[0047] For at least one level shift register, the orthographic projections of the first and third connection vias onto the substrate are within the range of the orthographic projection of the second capacitor onto the substrate.

[0048] In an exemplary embodiment, the second control electrode of the fifth transistor includes: a first connection segment and a plurality of branch segments, the first connection segment extending along a second direction, at least one of the plurality of branch segments extending along a first direction, and at least one of the plurality of branch segments being located on the side of the first connection segment closer to the display area and electrically connected to the first connection segment;

[0049] For at least one level shift register, the orthographic projection of the first connection segment onto the substrate is within the range of the orthographic projection of the second capacitor onto the substrate, the third connection via exposes the first connection segment, and the fourth connection via exposes one of the plurality of branch segments at an end away from the first connection segment.

[0050] In an exemplary embodiment, the second control electrode of the fifth transistor further includes: a second connection segment extending along a second direction;

[0051] The second connection segment is located on the side of the plurality of branch segments closest to the display area and is connected to at least one of the plurality of branch segments.

[0052] In an exemplary embodiment, it further includes: a plurality of first virtual structures, at least one of the plurality of first virtual structures being disposed on the same layer as the active pattern of at least one transistor located in at least one level shift register;

[0053] The distance between the orthographic projection of at least one of the plurality of first virtual structures on the substrate and the orthographic projection of at least one of the active patterns, first control electrode and second control electrode of at least one transistor located in at least one level shift register on the substrate is greater than 2 micrometers.

[0054] In an exemplary embodiment, the orthographic projection of at least one of the plurality of first virtual structures on the substrate at least partially overlaps with the orthographic projection of at least one of the third clock signal line, the fourth clock signal line, and the third power line on the substrate, and is electrically connected to at least one of the third clock signal line, the fourth clock signal line, and the third power line.

[0055] In an exemplary embodiment, it further includes: a plurality of second virtual structures, wherein the orthographic projection of at least one of the plurality of second virtual structures on the substrate does not overlap with the orthographic projection of the active pattern, first control electrode, second control electrode, first electrode and second electrode of at least one transistor in at least one level shift register, and the signal line connected to at least one level shift register on the substrate.

[0056] The second virtual structure is located in at least one of the first conductive layer, the second conductive layer, and the third conductive layer.

[0057] In an exemplary embodiment, it further includes: a plurality of virtual vias, at least one of the first virtual structure and the second virtual structure.

[0058] In an exemplary embodiment, at least one level shift register further includes: a plurality of transistors, a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor include: a first plate and a second plate;

[0059] The first conductive layer includes at least: the first plate of the first capacitor and the first plate of the second capacitor located in at least one level shift register;

[0060] The second conductive layer includes at least: the second plate of the first capacitor and the second plate of the second capacitor located in at least one level shift register;

[0061] The fourth conductive layer includes at least: the first and second terminals of at least one transistor among a plurality of transistors located in at least one level shift register.

[0062] In an exemplary embodiment, the line width of at least one of the first clock signal line and the second clock signal line is greater than the line width of at least one of the third clock signal line and the fourth clock signal line.

[0063] In an exemplary embodiment, the line width of at least one of the first power line and the third power line is smaller than the line width of at least one of the first clock signal line and the second clock signal line.

[0064] The line width of the second power line is greater than the line width of at least one of the first power line and the third power line.

[0065] In an exemplary embodiment, the linewidth of at least one of the first clock signal line and the second clock signal line is in the range of 10 micrometers to 100 micrometers;

[0066] The linewidth of at least one of the third and fourth clock signal lines is in the range of 4 micrometers to 20 micrometers.

[0067] In an exemplary embodiment, the clock signal of at least one of the first clock signal line and the second clock signal line within one cycle includes: a first clock signal and a second clock signal; the clock signal of at least one of the third clock signal line and the fourth clock signal line within one cycle includes: a third clock signal and a fourth clock signal.

[0068] The first clock signal and the third clock signal are positive voltage signals, and the second clock signal and the fourth clock signal are negative voltage signals;

[0069] The voltage value of at least one of the first clock signal and the third clock signal is greater than 8 volts, and the voltage value of the third clock signal is greater than the voltage value of the first clock signal, the voltage value of the fourth clock signal is greater than -14 volts, and the voltage value of the second clock signal is greater than the voltage value of the fourth clock signal.

[0070] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0071] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0072] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0073] Overview of the attached figures

[0074] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0075] Figure 1 is a planar schematic diagram of a display substrate;

[0076] Figure 2 is an equivalent circuit diagram of a shift register;

[0077] Figure 3 is the timing diagram of the shift register provided in Figure 2;

[0078] Figure 4 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0079] Figure 5 is a second schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0080] Figure 6 is a schematic diagram of some of the films in Figures 4 and 5;

[0081] Figure 7 is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment;

[0082] Figure 8 is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment;

[0083] Figure 9 is a schematic diagram of a portion of the film layers in Figure 8;

[0084] Figure 10 is a schematic diagram after the semiconductor layer pattern is formed in Figure 8;

[0085] Figure 11 is a schematic diagram of the second conductive layer pattern in Figure 8;

[0086] Figure 12 is a schematic diagram after the first conductive layer pattern in Figure 8 is formed;

[0087] Figure 13 is a schematic diagram of the semiconductor layer pattern in Figure 8;

[0088] Figure 14 is a schematic diagram after the first conductive layer pattern in Figure 8 is formed;

[0089] Figure 15 is a schematic diagram of the third conductive layer pattern in Figure 8;

[0090] Figure 16 is a schematic diagram after the third conductive layer pattern is formed in Figure 8;

[0091] Figure 17 is a schematic diagram after the fourth insulating layer pattern is formed in Figure 8;

[0092] Figure 18 is a schematic diagram of the fourth conductive layer pattern in Figure 8;

[0093] Figure 19 is a schematic diagram after the fourth conductive layer pattern is formed in Figure 8;

[0094] Figure 20 is a schematic diagram after the planarization layer pattern in Figure 8 is formed;

[0095] Figure 21 is a schematic diagram of the fifth conductive layer pattern in Figure 8;

[0096] Figure 22 is a schematic diagram of the fifth conductive layer pattern formed in Figure 8.

[0097] Detailed Explanation

[0098] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0099] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0100] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0101] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0102] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0103] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0104] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0105] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0106] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0107] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0108] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0109] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0110] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0111] Figure 1 is a planar schematic diagram of a display substrate. As shown in Figure 1, the display substrate has a display area AA and a non-display area BB located on at least one side of the display area AA. The display area AA is provided with a plurality of pixel units P arranged in a matrix, and at least one pixel unit includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.

[0112] When the display substrate is an OLED display substrate, each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in each of the three sub-pixels are connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in each of the three sub-pixels are connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0113] When the display substrate is an LCD display substrate, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a transistor, a first electrode, a second electrode, and a liquid crystal layer. The transistor is connected to a scan signal line, a data signal line, and the first electrode, respectively. The transistor is configured to provide a data signal to the first electrode under the control of the scan signal line, and under the influence of the signals from the first and second electrodes, control the deflection degree of the liquid crystal molecules in the liquid crystal layer to emit light of corresponding brightness.

[0114] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light.

[0115] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal.

[0116] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement, without limitation herein.

[0117] In other exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0118] In an exemplary embodiment, as shown in FIG1, a gate driving circuit GOA is provided in the non-display area BB. The gate driving circuit GOA may be located on at least one side of the display area; FIG1 illustrates an example where the gate driving circuits are located on opposite sides of the display area.

[0119] In an exemplary embodiment, the gate driving circuit is electrically connected to multiple gate lines and configured to provide driving signals to the gate lines. The gate lines in an OLED display substrate include scan signal lines and light-emitting signal lines, while the gate lines in an LCD display substrate include scan signal lines.

[0120] In an exemplary embodiment, the gate drive circuit GOA may include multiple cascaded shift registers. Exemplarily, the circuit structure of the shift register may be 8T2C, 10T3C, 12T3C, 13T3C, or 16T3C, where T represents a transistor, the number preceding T indicates the number of transistors, and C represents a capacitor, the number preceding C indicates the number of capacitors.

[0121] Figure 2 is an equivalent circuit diagram of a shift register. Figure 2 is illustrated using an 8T2C shift register as an example. As shown in Figure 2, the shift register includes: first transistors T1 to eighth transistors T8, first capacitor C1, and second capacitor C2. The first capacitor C1 includes a first plate C11 and a second plate C12, and the second capacitor C2 includes a first plate C21 and a second plate C22.

[0122] As shown in Figure 2, the control electrode of the first transistor T1 is electrically connected to the second clock signal terminal CK2, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second clock signal terminal CK2, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second clock signal terminal CK2, the first electrode of the third transistor T3 is electrically connected to the first power supply terminal VGH, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL1, and the second electrode of the fourth transistor T4 is electrically connected to the signal output terminal OUT; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, and the first electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal CK2. Signal terminal CK1 is electrically connected; the second terminal of the fifth transistor T5 is electrically connected to the signal output terminal OUT; the control terminal of the sixth transistor T6 is electrically connected to the second node N2; the first terminal of the sixth transistor T6 is electrically connected to the third power supply terminal VGL2; the second terminal of the sixth transistor T6 is electrically connected to the first terminal of the seventh transistor T7; the control terminal of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3; the second terminal of the seventh transistor T7 is electrically connected to the first node N1; the control terminal of the eighth transistor T8 is electrically connected to the first power supply terminal VGH; the first terminal of the eighth transistor T8 is electrically connected to the first node N1; the second terminal of the eighth transistor T8 is electrically connected to the third node N3; the first plate C11 of the first capacitor C1 is electrically connected to the second power supply terminal VGL1; the second plate C12 of the first capacitor C1 is electrically connected to the second node N2; the first plate C21 of the second capacitor C2 is electrically connected to the signal output terminal OUT; the second plate C22 of the second capacitor C2 is electrically connected to the third node N3.

[0123] In an exemplary embodiment, the fourth transistor T4 and the fifth transistor T5 may be referred to as output transistors.

[0124] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0125] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be either a P-type transistor or an N-type transistor.

[0126] In an exemplary embodiment, any one of the first transistor T1 to the eighth transistor T8 can be an N-type transistor.

[0127] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high-level signal, while the second power supply terminal VGL1 and the third power supply terminal VGL2 continuously provide low-level signals.

[0128] In an exemplary embodiment, the signal at any one of the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 is a square wave signal that repeats between high and low voltages. Exemplarily, the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 may have the same period and may be configured as phase-shifted signals. Here, the signal at the third clock signal terminal CK3 may be phase-shifted by half a cycle compared to the signal at the second clock signal terminal CK2.

[0129] In an exemplary embodiment, the signals of the first clock signal terminal CK1 and the second clock signal terminal CK2 of at least one shift register are inverse signals for at least a portion of the time period. That is, when the signal of the first clock signal terminal CK1 is a high-level signal, the signal of the second clock signal terminal CK2 is a low-level signal, and when the signal of the second clock signal terminal CK2 is a high-level signal, the signal of the first clock signal terminal CK1 is a low-level signal.

[0130] In an exemplary embodiment, the signals of the first clock signal terminal CK1 and the third clock signal terminal CK3 of at least one shift register can be the same.

[0131] In an exemplary embodiment, either the first capacitor C1 or the second capacitor C2 can be a capacitor device manufactured through a process, for example, by fabricating dedicated capacitor electrodes. Multiple capacitor electrodes can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. Alternatively, either the first capacitor C1 or the second capacitor C2 can be a parasitic capacitance between multiple devices, implemented using the transistor itself and other devices or circuits. The connection method of either the first capacitor C1 or the second capacitor C2 includes, but is not limited to, the methods described above; other applicable connection methods can be used, as long as the level of the corresponding node is stored. Here, the exemplary embodiments of this disclosure do not limit this.

[0132] In an exemplary embodiment, the signal output terminal of at least one shift register is electrically connected to the signal input terminal of at least one shift register and at least one gate line, respectively. The signal output terminal of at least one shift register provides a cascaded signal to the signal input terminal of at least one shift register and provides a drive signal to at least one gate line.

[0133] Figure 3 is a timing diagram of the shift register provided in Figure 2. In at least one stage of the shift register, the eighth transistor T8 is connected to the first power supply terminal VGH. Since the signal at the first power supply terminal VGH is a high-level signal, the eighth transistor T8 is continuously turned on. As shown in Figure 3, the operation of the shift register provided in an exemplary embodiment includes the following stages:

[0134] In the first stage P1, i.e., the input stage, the signals at the signal input terminal IN and the second clock signal terminal CK2 are high-level signals, while the signals at the first clock signal terminal CK1 and the third clock signal terminal CK3 are low-level signals. The first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off.

[0135] The first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is written to the first node N1. The second transistor T2 is turned on, and the high-level signal at the second clock signal terminal CK2 is written to the second node N2. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is written to the second node N2, keeping the signal at the second node N2 high. The fourth transistor T4 and the sixth transistor T6 are turned on, and the high-level signal at the first node N1 is written to the third node N3 through the turned-on eighth transistor T8. The fifth transistor T5 is turned on. The fifth transistor T5 is turned on, and the low-level signal at the first clock signal terminal CK1 is written to the signal output terminal OUT. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL1 is written to the signal output terminal OUT, making the signal at the signal output terminal OUT low.

[0136] In the second stage, P2, which is the output stage, the signals on the first clock signal line CK1 and the third clock signal line CK3 are high-level signals, while the signals on the signal input line IN and the second clock signal line CK2 are low-level signals. The first transistor T1 and the third transistor T3 are off, and the seventh transistor T7 is on.

[0137] Under the action of the second capacitor C2, the first node N1 and the third node N3 remain at a high level signal, the fifth transistor T5 is continuously turned on, and the high level signal of the first clock signal line CK1 is written to the signal output terminal OUT. Since the signal at the signal output terminal OUT changes from a low level signal to a high level signal, under the action of the second capacitor C2, the signals of the first node N1 and the third node N3 also change to a high level signal. The second transistor T2 is turned on, and the signal at the second clock signal terminal CK2 is a low level signal written to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned off.

[0138] In the third stage (P3), the signal at the second clock signal terminal CK2 is high, while the signals at the signal input terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 are all low. The first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off.

[0139] The first transistor T1 is turned on, and the low-level signal at the signal input terminal IN is written to the first node N1. The second transistor T2 is turned off, and the low-level signal at the first node N1 is written to the third node N3 through the turned-on eighth transistor T8. The fifth transistor T5 is turned off. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is written to the second node N2, keeping the signal at the second node N2 at a high level. The fourth transistor T4 and the sixth transistor T6 are turned on, and the low-level signal at the second power supply terminal VGL1 is written to the signal output terminal OUT, making the signal at the signal output terminal OUT a low-level signal.

[0140] In the fourth stage (P4), the signals at the first clock signal terminal CK1 and the third clock signal terminal CK3 are high-level signals, while the signals at the signal input terminal IN and the second clock signal terminal CK2 are both low-level signals. The first transistor T1 and the third transistor T3 are off, and the seventh transistor T7 is on.

[0141] Under the influence of the second capacitor C2, the signals at the first node N1 and the third node N3 are low-level signals, and the second transistor T2 and the fifth transistor T5 remain off. Under the influence of the first capacitor C1, the signal at the second node N2 is a high-level signal, and the fourth transistor T4 and the sixth transistor T6 are turned on. When the fourth transistor T4 is turned on, the low-level signal at the second power supply terminal VGL1 is written to the signal output terminal OUT. When the sixth transistor T6 and the seventh transistor T7 are turned on, the low-level signal at the third power supply terminal VGL2 is written to the first node N1, keeping the signal at the first node N1 a low-level signal.

[0142] The shift register executes the third and fourth stages sequentially until the signal at the signal input becomes a high-level signal.

[0143] The shift register in the gate drive circuit of the aforementioned display substrate is prone to output abnormalities, which reduces the display effect of the display substrate.

[0144] Therefore, this disclosure provides a display substrate that can ensure stable output of the shift register and improve the display effect of the display substrate.

[0145] Figure 4 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure, and Figure 5 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure. As shown in Figures 4 and 5, the display substrate provided in the embodiment of this disclosure has a display area and a non-display area located on at least one side of the display area. Figures 4 and 5 only show the non-display area of ​​the display substrate.

[0146] As shown in Figures 4 and 5, the display substrate includes a substrate and a gate driving circuit and a clock signal line group CLK disposed on the substrate and located in a non-display area. The clock signal line group CLK includes multiple clock signal lines. The gate driving circuit includes multiple cascaded shift registers. At least one of the cascaded shift registers is electrically connected to at least one of the multiple clock signal lines. At least one of the cascaded shift registers includes at least one output transistor. Figures 4 and 5 illustrate a two-stage shift register in the gate driving circuit, specifically the m-th stage and the (m+1)-th stage. The shift register can be the one provided in Figure 2. The at least one output transistor can include a fourth transistor T4 and a fifth transistor T5.

[0147] As shown in Figures 4 and 5, the orthographic projection of at least one of the multiple clock signal lines onto the substrate at least partially overlaps with the orthographic projection of at least one output transistor in at least one stage of the multiple cascaded shift registers onto the substrate. Figures 4 and 5 are illustrated using the example of at least partial overlap between the orthographic projections of two clock signal lines onto the substrate and the orthographic projections of at least one output transistor in at least one stage of the multiple cascaded shift registers onto the substrate.

[0148] In an exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be, but is not limited to, one or more of glass and metal sheets; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0149] To ensure output stability, at least one output transistor in the at least one stage shift register of this disclosure occupies a relatively large area. This disclosure achieves this by having at least partial overlap between the orthogonal projection of at least one clock signal line on the substrate and the orthogonal projection of at least one output transistor in the at least one stage shift register of the multiple cascaded shift registers on the substrate. Because the area occupied by at least one output transistor in the at least one stage shift register is relatively large, this disclosure can increase the linewidth of at least one clock signal line, thereby reducing the resistance of the clock signal line and further ensuring the stability of the shift register output when the display substrate is displayed in high-frequency mode, thus improving the display effect of the display substrate.

[0150] In an exemplary embodiment, as shown in Figures 4 and 5, the plurality of clock signal lines include: a first clock signal line CLK1 and a second clock signal line CLK2. At least a portion of at least one of the first clock signal lines CLK1 and the second clock signal line CLK2 extends along a second direction D2;

[0151] In an exemplary embodiment, the first clock signal terminal of at least one level shift register is electrically connected to one of the first clock signal lines CLK1 and CLK2, and the first clock signal terminals of adjacent shift registers are connected to different clock signal lines. Figures 4 and 5 illustrate this with an example where the first clock signal terminal of the m-th level shift register is electrically connected to the first clock signal line CLK1, and the first clock signal terminal of the (m+1)-th level shift register is electrically connected to the second clock signal line CLK2.

[0152] In an exemplary embodiment, as shown in Figures 4 and 5, the orthogonal projection of at least one of the first clock signal lines CLK1 and the second clock signal line CLK2 onto the substrate at least partially overlaps with the orthogonal projection of at least one of the fourth transistor T4 and the fifth transistor T5 in at least one level shift register onto the substrate.

[0153] In an exemplary embodiment, as shown in Figures 4 and 5, at least one shift register further includes: a first transistor T1, a second transistor T2, a third transistor T3, and a seventh transistor T7, wherein the control electrode of the first transistor T1, the first electrode of the second transistor T2, and the control electrode of the third transistor T3 are electrically connected to the second clock signal terminal, and the control electrode of the seventh transistor T7 is electrically connected to the third clock signal terminal.

[0154] In an exemplary embodiment, as shown in Figures 4 and 5, the plurality of clock signal lines further include: a third clock signal line CLK3 and a fourth clock signal line CLK4, at least a portion of at least one of the third clock signal line CLK3 and the fourth clock signal line CLK4 extending along a second direction D2.

[0155] In an exemplary embodiment, the second clock signal terminal of at least one level shift register is electrically connected to one of the third clock signal lines CLK3 and CLK4, and the third clock signal terminal of at least one level shift register is electrically connected to the other of the third clock signal lines CLK3 and CLK4. The second clock signal terminals of adjacent shift registers are connected to different signal lines, and the third clock signal terminals of adjacent shift registers are connected to different signal lines. Figures 4 and 5 illustrate an example where the second clock signal terminal of the m-th level shift register is electrically connected to the fourth clock signal line CLK4, the third clock signal terminal of the m-th level shift register is electrically connected to the third clock signal line CLK3, the second clock signal terminal of the (m+1)-th level shift register is electrically connected to the third clock signal line CLK3, and the third clock signal terminal of the (m+1)-th level shift register is electrically connected to the fourth clock signal line CLK4.

[0156] In an exemplary embodiment, as shown in Figures 4 and 5, the orthographic projection of at least one of the third clock signal lines CLK3 and the fourth clock signal line CLK4 onto the substrate is located on the side of the orthographic projection of at least one of the first clock signal lines CLK1 and the second clock signal line CLK2 onto the substrate that is away from the display area.

[0157] In an exemplary embodiment, the third clock signal line CLK3 and the fourth clock signal line CLK4 are set separately from any one of the first clock signal line CLK1 and the second clock signal line CLK2, that is, there is no overlapping area between them and the orthogonal projection of at least one output transistor on the substrate. This can reduce the parasitic capacitance between at least one clock signal line and at least one output transistor, thereby reducing the rising and falling edge times of the signal output terminal of the shift register and ensuring the reliability of the shift register.

[0158] In an exemplary embodiment, the clock signal of at least one of the first clock signal lines CLK1 and the second clock signal line CLK2 within one cycle includes: a first clock signal and a second clock signal; the clock signal of at least one of the third clock signal lines CLK3 and the fourth clock signal line CLK4 within one cycle includes: a third clock signal and a fourth clock signal.

[0159] In an exemplary embodiment, the first clock signal and the third clock signal are positive voltage signals, at least one of the first clock signal and the third clock signal has a voltage value greater than 8 volts, and the voltage value of the third clock signal is greater than the voltage value of the first clock signal.

[0160] In an exemplary embodiment, the second clock signal and the fourth clock signal are negative voltage signals. The voltage value of the fourth clock signal is greater than -14 volts, and the voltage value of the second clock signal is greater than the voltage value of the fourth clock signal. In an exemplary embodiment, the lower the voltage value of the fourth clock signal, the more stable the signal output at the signal output terminal OUT.

[0161] In an exemplary embodiment, the display substrate further includes: a power signal line group disposed on the substrate and located in a non-display area; in at least one level shift register, the first electrode of the first transistor T1 is electrically connected to the signal input terminal, the first electrode of the third transistor T3 and the control electrode of the eighth transistor T8 are respectively electrically connected to the first power supply terminal, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal, and the first electrode of the sixth transistor T6 is electrically connected to the third power supply terminal.

[0162] In an exemplary embodiment, as shown in Figures 4 and 5, the power signal line group includes: a first power line VL1, which extends at least partially along a second direction D2, and a first power supply terminal of at least one shift register is electrically connected to the first power line VL1.

[0163] In an exemplary embodiment, as shown in Figures 4 and 5, the orthographic projection of the first power line VL1 on the substrate lies between the orthographic projections of at least one of the first clock signal lines CLK1 and the second clock signal line CLK2 on the substrate and the orthographic projections of at least one of the third clock signal lines CLK3 and the fourth clock signal line CLK4 on the substrate, and at least partially overlaps with the orthographic projection of at least one transistor in at least one level shift register on the substrate.

[0164] In an exemplary embodiment, as shown in Figures 4 and 5, the orthographic projection of the first power line VL1 onto the substrate may at least partially overlap with the orthographic projection of the eighth transistor T8 in at least one level shift register onto the substrate.

[0165] In an exemplary embodiment, as shown in Figures 4 and 5, the power signal line group further includes a second power line VL2, which extends at least partially along a second direction D2, and the second power supply terminal of at least one shift register is electrically connected to the second power line VL2.

[0166] In an exemplary embodiment, as shown in Figures 4 and 5, the orthographic projection of the second power line VL2 on the substrate is located on the side of the orthographic projection of at least one of the first clock signal lines CLK1 and CLK2 on the substrate that is closer to the display area.

[0167] In an exemplary embodiment, as shown in Figures 4 and 5, the power signal line group further includes a third power line VL3, which extends at least partially along the second direction D2, and the third power supply terminal of at least one shift register is electrically connected to the third power line VL3.

[0168] In an exemplary embodiment, as shown in Figures 4 and 5, the orthographic projection of the third power line VL3 on the substrate lies between the orthographic projection of at least one of the third clock signal lines CLK3 and the fourth clock signal line CLK4 on the substrate and the orthographic projection of the first power line VL1 on the substrate.

[0169] In an exemplary embodiment, as shown in Figures 4 and 5, the display substrate further includes: an initial signal line STV disposed on the substrate and located in a non-display area, the initial signal line STV extending at least partially along a second direction D2, and the signal input terminal of at least one shift register being electrically connected to the initial signal line STV.

[0170] In an exemplary embodiment, as shown in Figures 4 and 5, the orthographic projection of the initial signal line STV on the substrate is located on the side of the orthographic projection of at least one of the third clock signal lines CLK3 and the fourth clock signal line CLK4 on the substrate that is away from the display area.

[0171] In an exemplary embodiment, as shown in Figures 4 and 5, the orthogonal projection of at least one of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 in at least one level shift register is located on the side of the orthogonal projection of the first power line VL1 on the substrate that is away from the display area.

[0172] In an exemplary embodiment, as shown in Figures 4 and 5, at least one shift register further includes a first capacitor C1 and a second capacitor C2.

[0173] In an exemplary embodiment, as shown in Figures 4 and 5, the orthogonal projection of the first capacitor C1 in at least one level shift register onto the substrate is located on the side of the orthogonal projection of at least one of the first clock signal lines CLK1 and CLK2 onto the substrate that is closer to the display area.

[0174] In an exemplary embodiment, as shown in Figures 4 and 5, the orthogonal projection of the second capacitor C2 in at least one shift register onto the substrate lies between the orthogonal projection of at least one of the first clock signal lines CLK1 and CLK2 onto the substrate and the orthogonal projection of the first power supply line VL1 onto the substrate.

[0175] As shown in Figures 4 and 5, the signal lines connected to at least one shift register include: a first clock signal line CLK1, a second clock signal line CLK2, and a first power supply line VL1.

[0176] As shown in Figures 4 and 5, the signal lines connected to at least one shift register further include at least one of a first signal line and a second signal line. The first signal line is one of the third clock signal line CLK3, the fourth clock signal line CLK4, the second power supply line VL2, and the third power supply line VL3 that at least partially overlaps with the orthogonal projection of at least one transistor in the at least one shift register on the substrate. The second signal line is one of the third clock signal line CLK3, the fourth clock signal line CLK4, the second power supply line VL2, and the third power supply line VL3 that does not overlap with the orthogonal projection of at least one transistor in the at least one shift register on the substrate.

[0177] For example, when the signal lines connected to at least one shift register include a first signal line, the first signal line may include any one of the following: a third clock signal line CLK3, a fourth clock signal line CLK4, a second power supply line VL2, and a third power supply line VL3. That is, the orthographic projection of any one of the third clock signal line CLK3, the fourth clock signal line CLK4, the second power supply line VL2, and the third power supply line VL3 on the substrate at least partially overlaps with the orthographic projection of at least one transistor in at least one shift register on the substrate.

[0178] For example, when the signal lines connected to at least one shift register include a second signal line, the second signal line may include any one of the following: a third clock signal line CLK3, a fourth clock signal line CLK4, a second power supply line VL2, and a third power supply line VL3. That is, the orthographic projection of any one of the third clock signal line CLK3, the fourth clock signal line CLK4, the second power supply line VL2, and the third power supply line VL3 onto the substrate does not overlap with the orthographic projection of at least one transistor in the at least one shift register onto the substrate. Figure 4 illustrates this using the example of the signal lines connected to at least one shift register including a second signal line.

[0179] For example, when the signal lines connected to at least one shift register include a first signal line and a second signal line, the first signal line may include a third power supply line VL3, and the second signal line may include a third clock signal line CLK3, a fourth clock signal line CLK4, and a second power supply line VL2. Alternatively, the first signal line may include a third power supply line VL3 and a second power supply line VL2, and the second signal line may include a third clock signal line CLK3 and a fourth clock signal line CLK4. Alternatively, the first signal line may include a third power supply line VL3 and a fourth clock signal line CLK4, and the second signal line may include a third clock signal line CLK3 and a second power supply line VL2. Alternatively, the first signal line may include a third power supply line VL3, a fourth clock signal line CLK4, and a second power supply line VL2, and the second signal line may include a third clock signal line CLK3. Alternatively, the first signal line may include a third clock signal line CLK3, a fourth clock signal line CLK4, and a third power supply line VL3, and the second signal line may include a second power supply line VL2. Figure 5 illustrates an example of a shift register connected to at least one level, comprising a first signal line and a second signal line. The first signal line is the third power supply line VL3, and the second signal line includes the third clock signal line CLK3, the fourth clock signal line CLK4, and the second power supply line VL2.

[0180] In an exemplary embodiment, at least one of the signal lines connected to at least one level shift register can be a single-layer structure, a double-layer structure, or a multi-layer structure. For example, the number of layers included in the first signal line is less than or equal to the number of layers included in the second signal line.

[0181] In an exemplary embodiment, the display substrate further includes a circuit structure layer disposed on the substrate, the circuit structure layer including a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The circuit structure layer may further include a first insulating layer located between the first and second conductive layers, a second insulating layer located between the second conductive layer and the semiconductor layer, a third insulating layer located between the third and fourth conductive layers, and a fourth insulating layer located between the fourth and fifth conductive layers. Figures 4 and 5 are illustrated using an example where the circuit structure layer includes the first conductive layer, the second conductive layer, the semiconductor layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer.

[0182] In an exemplary embodiment, as shown in Figures 4 and 5, the first clock signal line CLK1, the second clock signal line CLK2, and the first signal line are located in the fifth conductive layer, while the first power line VL1 and the initial signal line STV are located in the fourth conductive layer.

[0183] In an exemplary embodiment, the second signal line includes: a first connecting line and a second connecting line interconnected with each other, wherein the orthographic projection of the first connecting line on the substrate and the orthographic projection of the second connecting line on the substrate at least partially overlap. The first connecting line of at least one second signal line is located in a fourth conductive layer, and the second connecting line of at least one second signal line is located in a fifth conductive layer. In Figure 4, the third clock signal line CLK3, the fourth clock signal line CLK4, the second power line VL2, and the third power line VL3 have a double-layer structure, while the first clock signal line CLK1, the second clock signal line CLK2, the first power line VL1, and the initial signal line STV have a single-layer structure. In Figure 5, the third clock signal line CLK3, the fourth clock signal line CLK4, and the second power line VL2 have a double-layer structure, while the first clock signal line CLK1, the second clock signal line CLK2, the first power line VL1, the third power line VL3, and the initial signal line STV have a single-layer structure.

[0184] In an exemplary embodiment, the display substrate further includes a circuit structure layer disposed on the substrate, the circuit structure layer including a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The circuit structure layer may further include a first insulating layer located between the first and second conductive layers, a second insulating layer located between the second conductive layer and the semiconductor layer, a third insulating layer located between the third and fourth conductive layers, a fourth insulating layer located between the fourth and fifth conductive layers, and a fifth insulating layer located between the fifth and sixth conductive layers.

[0185] In an exemplary embodiment, the initial signal line STV and the first power line VL1 are located in the fourth conductive layer.

[0186] In an exemplary embodiment, at least one of the first clock signal line CLK1, the second clock signal line CLK2, and the first signal line includes: a third connecting line and a fourth connecting line that are interconnected. The orthographic projection of the third connecting line on the substrate and the orthographic projection of the fourth connecting line on the substrate at least partially overlap. The third connecting line of at least one signal line is located in a fifth conductive layer, and the fourth connecting line of at least one signal line is located in a sixth conductive layer.

[0187] In an exemplary embodiment, the second signal line includes: a fifth connecting line, a sixth connecting line, and a seventh connecting line that are interconnected; at least two of the fifth connecting lines, the sixth connecting line, and the seventh connecting line located on the same signal line have orthographic projections on the substrate that at least partially overlap; the fifth connecting line of at least one signal line is located in the fourth conductive layer; the sixth connecting line of at least one signal line is located in the fifth conductive layer; and the seventh connecting line of at least one signal line is located in the sixth conductive layer.

[0188] In an exemplary embodiment, the more first signal lines there are, that is, the more signal lines that overlap with at least one transistor in at least one level of shift register, the smaller the area occupied by the shift register, thus enabling a narrow bezel on the display substrate.

[0189] In an exemplary embodiment, the more layers a signal line includes, the lower its resistivity and the smaller its linewidth. In another exemplary embodiment, the more layers at least one of the first, second, third, fourth, and third power lines includes, the smaller the linewidth of each signal line can be, thus achieving a narrow bezel on the display substrate.

[0190] At least one capacitor in the first capacitor and the second capacitor of the at least one stage shift register in this disclosure may include: a first plate and a second plate. In an exemplary embodiment, the first conductive layer includes at least: a first plate of the first capacitor and a first plate of the second capacitor located in the at least one stage shift register.

[0191] In an exemplary embodiment, the second conductive layer includes at least: the second plate of the first capacitor and the second plate of the second capacitor located in at least one level shift register.

[0192] In an exemplary embodiment, the fourth conductive layer includes at least: a first electrode and a second electrode of at least one of a plurality of transistors located in at least one level shift register.

[0193] In an exemplary embodiment, the line width of at least one of the first clock signal lines CLK1 and the second clock signal line CLK2 may be greater than the line width of at least one of the third clock signal lines CLK3 and the fourth clock signal line CLK4.

[0194] In an exemplary embodiment, the linewidth of at least one of the first clock signal lines CLK1 and the second clock signal line CLK2 is in the range of 10 micrometers to 100 micrometers. For example, the linewidth of at least one of the first clock signal lines CLK1 and the second clock signal line CLK2 may be 40 micrometers.

[0195] In an exemplary embodiment, the linewidth of at least one of the third clock signal lines CLK3 and the fourth clock signal line CLK4 is in the range of 4 micrometers to 20 micrometers. For example, the linewidth of at least one of the third clock signal lines CLK3 and the fourth clock signal line CLK4 may be 10 micrometers.

[0196] In an exemplary embodiment, as shown in Figures 4 and 5, the line width of at least one of the first power line VL1 and the third power line VL3 is smaller than the line width of at least one of the first clock signal line CLK1 and the second clock signal line CLK2.

[0197] In an exemplary embodiment, as shown in Figures 4 and 5, the line width of the second power line VL2 is greater than the line width of at least one of the first power line VL1 and the third power line VL3.

[0198] In an exemplary embodiment, at least one shift register includes: a plurality of transistors, at least one of which is an N-type transistor, and at least one of which includes: a first control electrode and a second control electrode connected to each other, i.e., at least one transistor has a dual-gate structure. Figure 6 is a schematic diagram of part of the film layers in Figures 4 and 5. As shown in Figure 6, the first transistor includes: a first control electrode 12A and a second control electrode 12B; the second transistor includes: a first control electrode 22A and a second control electrode 22B; the third transistor includes: a first control electrode 32A and a second control electrode 32B; the fourth transistor includes: a first control electrode 42A and a second control electrode 42B; the fifth transistor includes: a first control electrode 52A and a second control electrode 52B; the sixth transistor includes: a first control electrode 62A and a second control electrode 62B; the seventh transistor includes: a first control electrode 72A and a second control electrode 72B; and the eighth transistor includes: a first control electrode 82A and a second control electrode 82B.

[0199] In an exemplary embodiment, the first control electrode of at least one transistor is located on the side of the active pattern of at least one transistor close to the substrate, and the second control electrode of at least one transistor is located on the side of the active pattern of at least one transistor away from the substrate. The orthographic projection of the first control electrode of at least one transistor on the substrate and the orthographic projection of the second control electrode of at least one transistor on the substrate at least partially overlap.

[0200] In an exemplary embodiment, the first control electrode of at least one transistor is located in the second conductive layer, the second control electrode of at least one transistor is located in the third conductive layer, and the active pattern of at least one transistor is located in the semiconductor layer.

[0201] In an exemplary embodiment, the semiconductor layer may be a metal oxide layer.

[0202] In an exemplary embodiment, as shown in Figures 4 to 6, the display substrate further includes: a plurality of first signal connection lines L1 and a plurality of second signal connection lines L2, wherein at least one of the plurality of first signal connection lines L1 extends at least partially along a first direction D1, and at least one of the plurality of second signal connection lines L2 extends at least partially along the first direction D1, and the first direction D1 and the second direction D2 intersect.

[0203] For example, the intersection of the first direction D1 and the second direction D2 means that the included angle between the first direction D1 and the second direction D2 can be in the range of 80 degrees to 100 degrees. For example, the first direction D1 can be perpendicular to the second direction D2.

[0204] In an exemplary embodiment, as shown in Figures 4 to 6, at least one first signal connection line L1 is electrically connected to at least one electrode of the first control electrode and the second control electrode of the first transistor T1, at least one electrode of the control electrode and the second control electrode of the third transistor T3, and one of the third clock signal line CLK3 and the fourth clock signal line CLK4.

[0205] In an exemplary embodiment, as shown in Figures 4 to 6, at least one second signal connection line L2 is electrically connected to one of the electrodes of the first and second control electrodes of the seventh transistor T7 and the other signal line of the third clock signal line CLK3 and the fourth clock signal line CLK4.

[0206] In an exemplary embodiment, at least one of the first signal connection line L1 and the second signal connection line L2 is located in the first conductive layer or the second conductive layer. Figures 4 to 6 illustrate the example where the first signal connection line L1 and the second signal connection line L2 are located in the second conductive layer. In Figures 4 to 6, the first signal connection line L1 is integrally formed with the second control electrode 12B of the first transistor and the second control electrode 32B of the third transistor, and the second signal connection line L2 is integrally formed with the second control electrode 72B of the seventh transistor.

[0207] The first signal connection line L1 and the second signal connection line L2 in this disclosure are located in the first conductive layer, which can reduce the parasitic capacitance between the first signal connection line L1 and the second signal connection line L2 and at least one of the third clock signal line CLK3 and the fourth clock signal line CLK4, thereby reducing the power consumption of the shift register.

[0208] In an exemplary embodiment, as shown in FIG6, the display substrate further includes a plurality of connection vias disposed on the substrate and located in a non-display area. The number of connection vias exposing at least one first control electrode of a transistor is at least one, and the number of connection vias exposing at least one second control electrode of a transistor is at least one. FIG6 illustrates an example where one connection via exposes the first control electrode of at least one of the first, second, third, fourth, sixth, seventh, and eighth transistors, two connection vias expose the first control electrode of a fifth transistor, and two connection vias expose the second control electrode of the fifth transistor.

[0209] The fifth transistor in this disclosure is an output transistor. The fifth transistor is relatively large, that is, the first and second control electrodes of the fifth transistor are relatively large. If the number of vias exposing the first and second control electrodes of the fifth transistor is one, it will cause the voltage across the first and second control electrodes of the fifth transistor to be unstable or to attenuate. However, by setting the number of vias exposing the first and second control electrodes of the fifth transistor to two, the voltage difference across the first and second control electrodes of the fifth transistor can be reduced, thereby improving the reliability of the shift register.

[0210] In an exemplary embodiment, as shown in FIG6, at least one level shift register further includes: a second capacitor C2, the first plate C21 of the second capacitor C2 is electrically connected to the control electrode of the fifth transistor T5, the second plate C22 of the second capacitor C2 is electrically connected to the signal output terminal, and the plurality of connection vias include: a first connection via H1, a second connection via H2, a third connection via H3 and a fourth connection via H4.

[0211] In an exemplary embodiment, as shown in FIG6, the first connection via H1 and the second connection via H2 expose the first control electrode 52A of the fifth transistor T5, the second connection via H2 is located on the side of the first connection via H1 near the display area, the third connection via H3 and the fourth connection via H4 expose the second control electrode 52B of the fifth transistor T5, and the fourth connection via H4 is located on the side of the third connection via H3 near the display area.

[0212] In an exemplary embodiment, as shown in FIG6, for at least one level shift register, the orthogonal projections of the first connection via H1 and the third connection via H3 on the substrate are within the range of the orthogonal projection of the second capacitor C2 on the substrate. This arrangement saves the area occupied by the shift register, achieving a narrow bezel on the display substrate.

[0213] As shown in Figure 6, the configuration of the first connecting via H1, the second connecting via H2, the third connecting via H3, the fourth connecting via H4, and the second control electrode of the fifth transistor allows the voltage transmission path of the second control electrode of the fifth transistor to include a first path and a second path. The first path transmits voltage from the side of the first connecting segment near the third via to the end of the first branch segment and the end of the second branch segment. The second path transmits voltage from the side of the first connecting segment near the third via to the end of the third branch segment. This reduces the number of transmission paths for the voltage of the second control electrode of the fifth transistor, ensures the stability of the voltage of the second control electrode of the fifth transistor, and improves the reliability of the shift register.

[0214] In an exemplary embodiment, as shown in FIG6, the second control electrode 52B of the fifth transistor T5 includes a first connection segment 510 and a plurality of branch segments 520. The first connection segment 510 extends along a second direction D2, and at least one of the plurality of branch segments 520 extends along a first direction D1. At least one of the plurality of branch segments 520 is located on the side of the first connection segment 510 near the display area and is electrically connected to the first connection segment 510. FIG6 illustrates an example where the second control electrode 52B of the fifth transistor T5 includes three branch segments 520.

[0215] In an exemplary embodiment, as shown in FIG6, for at least one level shift register, the orthographic projection of the first connection segment 510 on the substrate is within the range of the orthographic projection of the second capacitor C2 on the substrate, the third connection via H3 exposes the first connection segment 510, and the fourth connection via H4 exposes one of the multiple branch segments 520 at one end away from the first connection segment 510.

[0216] In an exemplary embodiment, FIG7 is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment. As shown in FIG7, the second control electrode 52B of the fifth transistor T5 further includes a second connection segment 530, which extends along the second direction D2.

[0217] In an exemplary embodiment, the second connection segment 530 is located on the side of the plurality of branch segments 520 near the display area and is connected to at least one of the plurality of branch segments 520.

[0218] As shown in Figure 7, the configuration of the first connecting via H1, the second connecting via H2, the third connecting via H3, the fourth connecting via H4, and the second control electrode 52B of the fifth transistor allows the voltage transmission path of the second control electrode of the fifth transistor to include a first path and a second path. The first path is the first end from the first connecting segment to at least one branch end, and the second path is the second end from the second connecting segment to at least one branch segment. This reduces the number of transmission paths for the voltage of the second control electrode of the fifth transistor, ensures the stability of the voltage of the second control electrode of the fifth transistor, and improves the reliability of the shift register.

[0219] In an exemplary embodiment, FIG8 is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment, and FIG9 is a schematic diagram of a portion of the film layers in FIG8. As shown in FIG8 and FIG9, the display substrate further includes: a plurality of first virtual structures DA1, at least one of the plurality of first virtual structures DA1 being disposed on the same layer as the active pattern of at least one transistor located in at least one level shift register, that is, the plurality of first virtual structures DA1 are located in the semiconductor layer.

[0220] In an exemplary embodiment, as shown in FIG9, the distance W between the orthographic projection of at least one of the plurality of first virtual structures DA1 on the substrate and the orthographic projection of at least one of the active patterns, first control electrode and second control electrode of at least one transistor located in at least one level shift register on the substrate is greater than 2 micrometers.

[0221] In an exemplary embodiment, at least one of the plurality of first virtual structures DA1 can be arranged around the periphery of the active pattern of at least one transistor, which can improve the uniformity of at least one transistor in the shift register and thus improve the reliability of the shift register.

[0222] In an exemplary embodiment, as shown in FIG9, the orthographic projection of at least one of the plurality of first virtual structures DA1 on the substrate at least partially overlaps with the orthographic projection of at least one of the signal lines CLK3, CLK4, VL2, and VL3 on the substrate, and is electrically connected to at least one of the signal lines CLK3, CLK4, and VL3. FIG9 shows that the orthographic projection of at least one of the first virtual structures DA1 on the substrate at least partially overlaps with the orthographic projection of the third power line VL3 on the substrate, and is electrically connected to the third power line VL3.

[0223] In this disclosure, at least one of the multiple first virtual structures DA1 is electrically connected to at least one of the third clock signal line CLK3, the fourth clock signal line CLK4, and the third power supply line VL3. This can reduce the resistance of the signal lines connected to the first virtual structure, enabling the display substrate to achieve high-frequency display and reducing the power consumption of the display substrate.

[0224] In an exemplary embodiment, as shown in FIG9, the display substrate may further include: a plurality of second virtual structures DA2, wherein the orthographic projection of at least one of the plurality of second virtual structures DA2 on the substrate does not overlap with the orthographic projection of the active pattern, first control electrode, second control electrode, first electrode and second electrode of at least one transistor in at least one level shift register, and the signal line connected to at least one level shift register on the substrate, i.e., at least one of the plurality of second virtual structures DA2 is located in the blank area of ​​the shift register.

[0225] In an exemplary embodiment, as shown in FIG9, the second virtual structure DA2 is located in at least one of the first conductive layer, the second conductive layer, and the third conductive layer.

[0226] The second virtual structure configuration in this disclosure can optimize the etching uniformity of the shift register, improve the reliability of the shift register, and thus improve the display effect of the display substrate.

[0227] In an exemplary embodiment, as shown in FIG9, it further includes: a plurality of virtual vias DV, at least one virtual via DV exposing at least one of the first virtual structure DA1 and the second virtual structure DA2.

[0228] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0229] The following describes a method for fabricating a display substrate, illustrated in Figure 8, to further illustrate the display substrate provided in this embodiment. Figure 8 illustrates an example where the third clock signal line CLK3, the fourth clock signal line CLK4, the second power supply line VL2, and the third power supply line VL3 are used as second signal lines, and the circuit structure layers include: a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer.

[0230] (1) Forming a first conductive layer pattern on a substrate. In an exemplary embodiment, forming a first conductive layer pattern on a substrate may include: depositing a first conductive thin film on the substrate, and patterning the first conductive thin film using a patterning process to form a first conductive layer pattern. As shown in FIG10, FIG10 is a schematic diagram after the semiconductor layer pattern is formed in FIG8. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0231] In an exemplary embodiment, as shown in FIG10, the first conductive layer pattern may include: a first plate C11 of a first capacitor located in at least one level of shift register and a second plate C21 of a second capacitor.

[0232] In an exemplary embodiment, the first plate C11 of the first capacitor includes a main body portion 11A, a first connecting portion 11B, and a second connecting portion 11C. The first connecting portion 11B is located on the side of the main body portion 11A away from the display area, and the second connecting portion 11C is located on the side of the main body portion 11A closer to the display area. The main body portion 11A is electrically connected to the first connecting portion 11B and the second connecting portion 11C respectively.

[0233] In an exemplary embodiment, the main body 11A is rectangular in shape, the first connecting part 11B can be rectangular in shape, and the main body 11A and the first connecting part 11B can be set at right angles. The second connecting part 11C can be a horizontally flipped "7" shape, and the first plate C11 of the first capacitor can be a "T" shape.

[0234] In an exemplary embodiment, the first plate C21 of the second capacitor is rectangular in shape.

[0235] (2) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern includes: depositing a first insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the first insulating film and the second conductive film using a patterning process to form a first insulating layer and a second conductive layer pattern disposed on the first insulating layer, as shown in Figures 11 and 12. Figure 11 is a schematic diagram of the second conductive layer pattern in Figure 8, and Figure 12 is a schematic diagram of Figure 8 after the first conductive layer pattern has been formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0236] In an exemplary embodiment, as shown in Figures 11 and 12, the first conductive layer pattern may include: the first control electrode 12A of the first transistor to the control electrode 82A of the eighth transistor located in at least one level shift register, the second electrode C12 of the first capacitor, the second electrode C22 of the second capacitor, the first signal connection line L1, the second signal connection line L2, and the second virtual structure DA2.

[0237] In an exemplary embodiment, the first control electrode 12A of the first transistor, the first control electrode 32A of the third transistor, and the first signal connection line L1 are integrated into a single structure. The first control electrode 42A of the fourth transistor and the second plate C12 of the first capacitor are integrated into a single structure. The first control electrode 52A of the fifth transistor and the second plate C22 of the second capacitor are integrated into a single structure. The first control electrode 72A of the seventh transistor and the second signal connection line L2 are integrated into a single structure. The first control electrode 22A of the second transistor, the first control electrode 62A of the sixth transistor, and the first control electrode 82A of the eighth transistor are separately configured.

[0238] In an exemplary embodiment, the integrated structure of the first control electrode 42A of the fourth transistor and the second plate C12 of the first capacitor, and the integrated structure of the first control electrode 52A of the fifth transistor and the second plate C22 of the second capacitor are arranged along the second direction D2, and the integrated structure of the first control electrode 52A of the fifth transistor and the second plate C22 of the second capacitor of the m-th stage shift register is located on the side of the integrated structure of the first control electrode 42A of the fourth transistor and the second plate C12 of the first capacitor closer to the (m+1)-th stage shift register. The integrated structure of the first control electrode 12A of the first transistor, the integrated structure of the first control electrode 32A of the third transistor and the first signal connection line L1, the integrated structure of the first control electrode 22A of the second transistor, the integrated structure of the first control electrode 72A of the seventh transistor and the second signal connection line L2, the integrated structure of the first control electrode 62A of the sixth transistor, and the integrated structure of the first control electrode 82A of the eighth transistor are located on the side away from the display area of ​​at least one of the integrated structures of the first control electrode 42A of the fourth transistor and the second plate C12 of the first capacitor, and the integrated structure of the first control electrode 52A of the fifth transistor and the second plate C22 of the second capacitor. The first control electrode 22A of the second transistor of the m-th stage shift register is located on the side of the integrated structure of the first control electrode 12A of the first transistor, the first control electrode 32A of the third transistor, and the first signal connection line L1, close to the side of the (m+1)-th stage shift register. The first control electrode 72A of the seventh transistor of the m-th stage shift register and the integrated structure of the second signal connection line L2 are located on the side of the first control electrode 22A of the second transistor close to the side of the (m+1)-th stage shift register. The first control electrode 62A of the sixth transistor of the m-th stage shift register is located on the side of the integrated structure of the first control electrode 72A of the seventh transistor and the second signal connection line L2, close to the side of the (m+1)-th stage shift register. The first control electrode 82A of the eighth transistor is located between the integrated structure of the first control electrode 72A of the seventh transistor and the second signal connection line L2 and the integrated structure of the first control electrode 52A of the fifth transistor and the second plate C22 of the second capacitor.

[0239] In an exemplary embodiment, the integral structure of the first control electrode 12A of the first transistor, the first control electrode 32A of the third transistor, and the first signal connection line L1 is strip-shaped and extends along the first direction D1.

[0240] In an exemplary embodiment, the shape of the first control electrode 22A of the second transistor can be a horizontally flipped “7” shape.

[0241] In an exemplary embodiment, the first control electrode 42A of the fourth transistor can be shaped like an "n" with its opening facing the display area, and the second electrode C12 of the first capacitor can be rectangular. The orthographic projection of the second electrode C12 of the first capacitor onto the substrate at least partially overlaps with the orthographic projection of the main body of the first electrode of the first capacitor onto the substrate, but there is no overlap between the orthographic projection of the second connection portion of the first electrode of the first capacitor onto the substrate. The integrated structure of the first control electrode 42A of the fourth transistor and the second electrode C12 of the first capacitor can be annular.

[0242] In an exemplary embodiment, the first control electrode 52A of the fifth transistor and the second electrode C22 of the second capacitor can be shaped like a comb with an opening facing the display area. The second electrode C22 of the second capacitor serves as the back of the comb and is rectangular in shape, while the first control electrode 52A of the fifth transistor serves as the teeth of the comb. The orthographic projection of the second electrode C22 of the second capacitor onto the substrate at least partially overlaps with the orthographic projection of the first electrode of the second capacitor onto the substrate.

[0243] In an exemplary embodiment, the first control electrode 62A of the sixth transistor is strip-shaped and extends along the first direction D1.

[0244] In an exemplary embodiment, the integral structure of the first control electrode 72A and the second signal connection line L2 of the seventh transistor is strip-shaped and extends along the first direction D1.

[0245] In an exemplary embodiment, the first control electrode 82A of the eighth transistor is strip-shaped and extends along the second direction D2.

[0246] In an exemplary embodiment, the second virtual structure DA2 can be block-shaped and can be located in the blank area of ​​the shift register.

[0247] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern includes: depositing a second insulating film and a semiconductor film on a substrate on which the aforementioned pattern is formed, and patterning the second insulating film and the semiconductor film by a patterning process to form a second insulating layer and a semiconductor layer pattern disposed on the second insulating layer, as shown in Figures 13 and 14. Figure 13 is a schematic diagram of the semiconductor layer pattern in Figure 8, and Figure 14 is a schematic diagram of the first conductive layer pattern after it is formed in Figure 8.

[0248] In an exemplary embodiment, the semiconductor layer pattern may include: an active pattern 11 of the first transistor to an active pattern 81 of the eighth transistor located in at least one level shift register, and a plurality of first virtual structures DA1.

[0249] In an exemplary embodiment, the active pattern 41 of the fourth transistor and the active pattern 51 of the fifth transistor are an integral structure, and the active pattern 61 of the sixth transistor and the active pattern 71 of the seventh transistor are an integral structure. The active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 81 of the eighth transistor, and the first virtual structure DA1 can be set individually.

[0250] In an exemplary embodiment, at least one of the active patterns of the first transistor 11, the second transistor 21, the third transistor 31, the sixth transistor 61, and the seventh transistor 71 may be strip-shaped and extend along the second direction D2. The active pattern 81 of the eighth transistor may be strip-shaped and extend along the first direction D1.

[0251] In an exemplary embodiment, the active pattern 41 of the fourth transistor may include a plurality of first active structures 410 arranged along a first direction D1, the first active structures 410 extending along a second direction D2. The active pattern 51 of the fifth transistor may include a plurality of second active structures 510 arranged along the first direction D1, the second active structures 510 extending along the second direction D2. At least one first active structure 410 and at least one second active structure 510 are of the same structure, and the number of second active structures is greater than or equal to the number of first active structures.

[0252] In an exemplary embodiment, at least one of the plurality of first virtual structures, DA1, is block-shaped. At least one of the plurality of first virtual structures, DA1, may be strip-shaped and extend along the second direction D2.

[0253] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 61-2 of the active pattern 61 of the sixth transistor may simultaneously serve as the first region 71-1 of the active pattern 71 of the seventh transistor. The first region 11-1 and the second region 11-2 of the active pattern 11 of the first transistor, the first region 21-1 and the second region 21-2 of the active pattern 21 of the second transistor, the first region 31-1 and the second region 31-2 of the active pattern 31 of the third transistor, the first region 41-1 and the second region 41-2 of the active pattern 41 of the fourth transistor, the first region 51-1 and the second region 51-2 of the active pattern 51 of the fifth transistor, the first region 61-1 of the active pattern 61 of the sixth transistor, the second region 71-2 of the active pattern 71 of the seventh transistor, and the first region 81-1 and the second region 81-2 of the active pattern 81 of the eighth transistor may be configured individually.

[0254] (4) Forming a third conductive layer pattern includes: depositing a third insulating film and a third conductive film on a substrate having the aforementioned pattern; and patterning the third insulating film and the third conductive film using a patterning process to form a third insulating layer pattern and a third conductive layer pattern located on the third insulating layer pattern, as shown in Figures 15 and 16. Figure 15 is a schematic diagram of the third conductive layer pattern in Figure 8, and Figure 16 is a schematic diagram of Figure 8 after the third conductive layer pattern has been formed. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0255] In an exemplary embodiment, the third conductive layer pattern may include: a second control electrode 12B of a first transistor, a second control electrode 22B of a second transistor, a second control electrode 32B of a third transistor, a second control electrode 42B of a fourth transistor, a second control electrode 52B of a fifth transistor, a second control electrode 62B of a sixth transistor, a second control electrode 72B of a seventh transistor, a second control electrode 82B of an eighth transistor, a first output line OUTL1, and a second output line OUTL2.

[0256] In an exemplary embodiment, the second control electrode 12B of the first transistor and the second control electrode 32B of the third transistor are integrally formed. The second control electrode 22B of the second transistor, the second control electrode 42B of the fourth transistor, the second control electrode 52B of the fifth transistor, the second control electrode 62B of the sixth transistor, the second control electrode 72B of the seventh transistor, and the second control electrode 82B of the eighth transistor are separately provided.

[0257] In an exemplary embodiment, the integral structure of the second control electrode 12B of the first transistor and the second control electrode 32B of the third transistor is strip-shaped and extends along the first direction D1. The orthographic projection of the integral structure of the second control electrode 12B of the first transistor and the second control electrode 32B of the third transistor on the substrate at least partially overlaps with the orthographic projection of the integral structure of the first control electrode of the first transistor and the first control electrode of the third transistor on the substrate.

[0258] In an exemplary embodiment, the second control electrode 22B of the second transistor may be strip-shaped and extend along the first direction D1. The orthographic projection of the second control electrode 22B of the second transistor on the substrate at least partially overlaps with the orthographic projection of the first control electrode of the second transistor on the substrate.

[0259] In an exemplary embodiment, the second control electrode 42B of the fourth transistor may be shaped like an "h" with its opening facing the display area. The orthographic projection of the second control electrode 42B of the fourth transistor onto the substrate at least partially overlaps with the orthographic projection of the integral structure of the first control electrode of the fourth transistor and the second plate of the first capacitor onto the substrate.

[0260] In an exemplary embodiment, the second control electrode 52B of the fifth transistor may be shaped like an "m" with its opening facing the display area. The orthographic projection of the second control electrode 52B of the fifth transistor onto the substrate at least partially overlaps with the orthographic projection of the integral structure of the first control electrode of the fifth transistor and the second plate of the second capacitor onto the substrate.

[0261] In an exemplary embodiment, the second control electrode 62B of the sixth transistor is strip-shaped and extends along the first direction D1. The orthographic projection of the second control electrode 62B of the sixth transistor on the substrate at least partially overlaps with the orthographic projection of the first control electrode of the sixth transistor on the substrate.

[0262] In an exemplary embodiment, the second control electrode 72B of the seventh transistor is strip-shaped and extends along the first direction D1. The orthographic projection of the second control electrode 72B of the seventh transistor on the substrate at least partially overlaps with the orthographic projection of the first control electrode of the seventh transistor on the substrate. The orthographic projection of the second control electrode 82B of the eighth transistor on the substrate at least partially overlaps with the orthographic projection of the first control electrode of the eighth transistor on the substrate.

[0263] In an exemplary embodiment, the second control electrode 12B of the first transistor is disposed across the active pattern of the first transistor, the second control electrode 22B of the second transistor is disposed across the active pattern of the second transistor, the second control electrode 32B of the third transistor is disposed across the active pattern of the third transistor, the second control electrode 42B of the fourth transistor is disposed across the active pattern of the fourth transistor, the second control electrode 52B of the fifth transistor is disposed across the active pattern of the fifth transistor, the second control electrode 62B of the sixth transistor is disposed across the active pattern of the sixth transistor, the second control electrode 72B of the seventh transistor is disposed across the active pattern of the seventh transistor, and the second control electrode 82B of the eighth transistor is disposed across the active pattern of the eighth transistor. That is, the extension direction of the second control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0264] (5) Forming a fourth insulating layer pattern includes: depositing a fourth insulating film on a substrate on which the aforementioned pattern has been formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer pattern covering the aforementioned structure. The fourth insulating layer has multiple via patterns, as shown in Figure 17. Figure 17 is a schematic diagram of the fourth insulating layer pattern formed in Figure 8.

[0265] In an exemplary embodiment, the plurality of via patterns may include: first vias V1 to thirty-fourth vias V34 and a plurality of virtual vias DV.

[0266] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the orthographic projection range of the first region of the first plate of the first capacitor on the substrate. The first insulating layer, the second insulating layer and the third insulating layer in the first via V1 are etched away to expose the surface of the first plate of the first capacitor. The first via V1 is configured to allow the first connection line of the subsequently formed second power line to be connected to the first plate of the first capacitor through the via.

[0267] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the first electrode of the second capacitor onto the substrate. The first insulating layer, the second insulating layer, and the third insulating layer within the second via V2 are etched away, exposing the surface of the first electrode of the second capacitor. The second via V2 is configured to allow the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to be connected to the first electrode of the second capacitor through the via.

[0268] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first control electrode of the first transistor (which is also the first control electrode of the third transistor) onto the substrate. The second and third insulating layers within the third via V3 are etched away, exposing the surface of the first control electrode of the first transistor (which is also the first control electrode of the third transistor). The third via V3 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the first control electrode of the first transistor (which is also the first control electrode of the third transistor) through the via.

[0269] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is within the range of the orthographic projection of the first signal connection line on the substrate. The second and third insulating layers within the fourth via V4 are etched away, exposing the surface of the first signal connection line. The fourth via V4 is configured to allow one of the subsequently formed third and fourth clock signal lines to be connected to the first signal connection line through the via.

[0270] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the substrate is within the range of the orthogonal projection of the first control electrode of the second transistor onto the substrate. The second and third insulating layers within the fifth via V5 are etched away, exposing the surface of the first control electrode of the second transistor. The fifth via V5 is configured to allow the second electrode of the subsequently formed first transistor (which is also the second electrode of the seventh transistor) to be connected to the first control electrode of the second transistor through the via.

[0271] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the first control electrode of the fourth transistor (which is also the second electrode of the first capacitor) onto the substrate. The second and third insulating layers within the sixth via V6 are etched away, exposing the surface of the first control electrode of the fourth transistor (which is also the second electrode of the first capacitor). The sixth via V6 is configured to allow a subsequently formed second connection electrode to be connected to the first control electrode of the fourth transistor (which is also the second electrode of the first capacitor) through the via.

[0272] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the substrate is located within the orthogonal projection of the first control electrode of the fifth transistor (which is also the second plate of the second capacitor) onto the substrate. The second and third insulating layers within the seventh via V7 are etched away, exposing the surface of the first control electrode of the fifth transistor (which is also the second plate of the second capacitor). The seventh via V7 is configured to allow the subsequently formed fourth connection electrode to be connected to the first control electrode of the fifth transistor (which is also the second plate of the second capacitor) through the via.

[0273] In an exemplary embodiment, the orthogonal projection of the eighth via V8 onto the substrate is within the range of the orthogonal projection of the first control electrode of the sixth transistor onto the substrate. The second and third insulating layers within the eighth via V8 are etched away, exposing the surface of the first control electrode of the sixth transistor. The eighth via V8 is configured to allow the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor) to be connected to the first control electrode of the sixth transistor through the via.

[0274] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the substrate is within the range of the orthogonal projection of the first control electrode of the seventh transistor onto the substrate. The second and third insulating layers within the ninth via V9 are etched away, exposing the surface of the first control electrode of the seventh transistor. The ninth via V9 is configured to allow a subsequently formed first connection electrode to be connected to the first control electrode of the seventh transistor through the via.

[0275] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the second signal connection line on the substrate. The second and third insulating layers within the tenth via V10 are etched away, exposing the surface of the second signal connection line. The tenth via V10 is configured to allow another signal line among the subsequently formed third and fourth clock signal lines to be connected to the second signal connection line through the via.

[0276] In an exemplary embodiment, the orthogonal projection of the eleventh via V11 onto the substrate is within the range of the orthogonal projection of the first control electrode of the eighth transistor onto the substrate. The second and third insulating layers within the eleventh via V11 are etched away, exposing the surface of the first control electrode of the eighth transistor. The eleventh via V11 is configured to allow a subsequently formed first power line to be connected to the first control electrode of the eighth transistor through the via.

[0277] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is located within the orthographic projection range of the first region of the first electrode plate of the first capacitor onto the substrate. The second insulating layer within the twelfth via V12 is etched away, exposing the surface of the first region of the active pattern of the first transistor. The twelfth via V12 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active pattern of the first transistor through the via.

[0278] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is within the orthographic projection of the second region of the active pattern of the first transistor onto the substrate. The third insulating layer within the thirteenth via V13 is etched away, exposing the surface of the second region of the active pattern of the first transistor. The thirteenth via V13 is configured to allow the second terminal of the subsequently formed first transistor (which is also the second terminal of the seventh transistor) to be connected to the second region of the active pattern of the first transistor through the via.

[0279] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate is within the orthographic projection of the first region of the active pattern of the second transistor onto the substrate. The third insulating layer within the fourteenth via V14 is etched away, exposing the surface of the first region of the active pattern of the second transistor. The fourteenth via V14 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the first region of the active pattern of the second transistor through the via.

[0280] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate is within the orthographic projection range of the second region of the active pattern of the second transistor onto the substrate. The third insulating layer within the fifteenth via V15 is etched away, exposing the surface of the second region of the active pattern of the second transistor. The fifteenth via V15 is configured to allow the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor) to be connected to the second region of the active pattern of the second transistor through the via.

[0281] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate is within the orthographic projection range of the first region of the active pattern of the third transistor onto the substrate. The third insulating layer within the sixteenth via V16 is etched away, exposing the surface of the first region of the active pattern of the third transistor. The sixteenth via V16 is configured to allow the first electrode of the subsequently formed third transistor to be connected to the first region of the active pattern of the third transistor through the via.

[0282] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the orthographic projection range of the second region of the active pattern of the third transistor onto the substrate. The third insulating layer within the seventeenth via V17 is etched away, exposing the surface of the second region of the active pattern of the third transistor. The seventeenth via V17 is configured to allow the second electrode of the subsequently formed third transistor (which is also the second electrode of the second transistor) to be connected to the second region of the active pattern of the third transistor through the via.

[0283] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 onto the substrate is within the orthographic projection range of the first region of the active pattern of the fourth transistor onto the substrate. The third insulating layer within the eighteenth via V18 is etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The eighteenth via V18 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0284] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the fourth transistor onto the substrate. The third insulating layer within the nineteenth via V19 is etched away, exposing the surface of the second region of the active pattern of the fourth transistor. The nineteenth via V19 is configured to allow the second terminal of the subsequently formed fourth transistor (which is also the second terminal of the fifth transistor) to be connected to the second region of the active pattern of the fourth transistor through the via.

[0285] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate is within the orthographic projection of the first region of the active pattern of the fifth transistor onto the substrate. The third insulating layer within the twentieth via V20 is etched away, exposing the surface of the first region of the active pattern of the fifth transistor. The twentieth via V20 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0286] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the fifth transistor onto the substrate. The third insulating layer within the 21st via V21 is etched away, exposing the surface of the second region of the active pattern of the fifth transistor. The 21st via V21 is configured to allow the second terminal of the subsequently formed fourth transistor (which is also the second terminal of the fifth transistor) to be connected to the second region of the active pattern of the fifth transistor through the via.

[0287] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate is within the orthographic projection of the first region of the active pattern of the sixth transistor onto the substrate. The third insulating layer within the 22nd via V22 is etched away, exposing the surface of the first region of the active pattern of the sixth transistor. The 22nd via V22 is configured to allow the first electrode of the subsequently formed sixth transistor to be connected to the first region of the active pattern of the sixth transistor through the via.

[0288] In an exemplary embodiment, the orthographic projection of the 23rd via V23 onto the substrate is within the orthographic projection range of the second region of the active pattern of the 7th transistor onto the substrate. The third insulating layer within the 23rd via V23 is etched away, exposing the surface of the second region of the active pattern of the 7th transistor. The 23rd via V23 is configured to allow the second terminal of the subsequently formed 7th transistor (which is also the second terminal of the 1st transistor) to be connected to the second region of the active pattern of the 7th transistor through the via.

[0289] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate is within the orthographic projection of the first region of the active pattern of the 8th transistor onto the substrate. The third insulating layer within the 24th via V24 is etched away, exposing the surface of the first region of the active pattern of the 8th transistor. The 24th via V24 is configured to allow the first electrode of the subsequently formed 8th transistor to be connected to the first region of the active pattern of the 8th transistor through the via.

[0290] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the 8th transistor onto the substrate. The third insulating layer within the 25th via V25 is etched away, exposing the surface of the first region of the active pattern of the 8th transistor. The 25th via V25 is configured to allow the second electrode of the subsequently formed 8th transistor to be connected to the second region of the active pattern of the 8th transistor through the via.

[0291] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate is located within the range of the orthographic projection of the second control electrode of the first transistor (which is also the second control electrode of the third transistor) onto the substrate. The surface of the 26th via V26 that exposes the second control electrode of the first transistor (which is also the second control electrode of the third transistor) is provided with respect to the surface of the 26th via V26. The 26th via V26 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the second control electrode of the first transistor (which is also the second control electrode of the third transistor) through the via.

[0292] In an exemplary embodiment, the orthographic projection of the 27th via V27 onto the substrate is within the range of the orthographic projection of the second control electrode of the second transistor onto the substrate. The 27th via V27 exposes the surface of the second control electrode of the second transistor. The 27th via V27 is configured to allow the second electrode of the subsequently formed first transistor (which is also the second electrode of the seventh transistor) to be connected to the second control electrode of the second transistor through the via.

[0293] In an exemplary embodiment, the orthogonal projection of the 28th via V28 onto the substrate is within the range of the orthogonal projection of the second control electrode of the fourth transistor onto the substrate. The 28th via V28 exposes the surface of the second control electrode of the fourth transistor. The 28th via V28 is configured to allow a subsequently formed second connection electrode to be connected to the second control electrode of the fourth transistor through the via.

[0294] In an exemplary embodiment, the orthographic projection of the 29th via V29 on the substrate is within the range of the orthographic projection of the second control electrode of the fifth transistor on the substrate. The 29th via V29 exposes the surface of the second control electrode of the fifth transistor. The 29th via V29 is configured to allow a subsequently formed fourth connection electrode to be connected to the second control electrode of the fifth transistor through the via.

[0295] In an exemplary embodiment, the orthogonal projection of the thirtieth via V30 onto the substrate is within the range of the orthogonal projection of the second control electrode of the sixth transistor onto the substrate. The thirtieth via V30 exposes the surface of the second control electrode of the sixth transistor. The thirtieth via V30 is configured to allow the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor) to be connected to the second control electrode of the sixth transistor through the via.

[0296] In an exemplary embodiment, the orthographic projection of the 31st via V31 on the substrate is within the range of the orthographic projection of the second control electrode of the 7th transistor on the substrate. The 31st via V31 exposes the surface of the second control electrode of the 7th transistor. The 31st via V31 is configured to connect the via to the second control electrode of the 8th transistor via a subsequently formed first connection electrode.

[0297] In an exemplary embodiment, the orthogonal projection of the 32nd via V32 onto the substrate is within the range of the orthogonal projection of the second control electrode of the 8th transistor onto the substrate. The 32nd via V32 exposes the surface of the second control electrode of the 8th transistor. The 32nd via V32 is configured to allow a subsequently formed first power line to be connected to the second control electrode of the 8th transistor through the via.

[0298] In an exemplary embodiment, the orthographic projection of the 33rd via V33 on the substrate is within the range of the orthographic projection of the first output line on the substrate. The 33rd via V33 exposes the surface of the first connection line. The 33rd via V33 is configured to allow the second terminal (also the second terminal of the fifth transistor) of the subsequently formed shift register of this stage and the first terminal of the first transistor of the next stage shift register to be connected to the first output line through the via.

[0299] In an exemplary embodiment, the orthographic projection of the 34th via V34 on the substrate is within the range of the orthographic projection of the second output line on the substrate. The 34th via V34 exposes the surface of the second output line. The 34th via V34 is configured to allow the second terminal of the subsequently formed fourth transistor (which is also the second terminal of the fifth transistor) to be connected to the second output line through the via.

[0300] In an exemplary embodiment, the plurality of virtual vias (DVs) include a first virtual via (DV1) and a second virtual via (DV2).

[0301] In an exemplary embodiment, the orthographic projection of the first virtual via DV1 on the substrate is within the range of the orthographic projection of the first virtual structure on the substrate, and the first virtual via DV1 exposes the surface of the first virtual structure.

[0302] In an exemplary embodiment, the orthographic projection of the second virtual via DV2 on the substrate is within the range of the orthographic projection of the second virtual structure on the substrate, and the second virtual via DV2 exposes the surface of the second virtual structure.

[0303] (6) Forming a fourth conductive layer pattern includes: depositing a fourth metal thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth metal thin film using a patterning process to form a fourth metal layer pattern, as shown in Figures 18 and 19. Figure 18 is a schematic diagram of the fourth conductive layer pattern in Figure 8, and Figure 19 is a schematic diagram of the fourth conductive layer pattern formed in Figure 8. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0304] In an exemplary embodiment, the fourth conductive layer pattern may include: an initial signal line STV, a first connection line CLK1A of a first clock signal line, a first connection line CLK2A of a second clock signal line, a first power line VL1, a first connection line VL2A of a second power line, a first connection line VL3A of a third power line, and a first electrode 13 and a second electrode 14 of a first transistor located in at least one level shift register to a first electrode 83 and a second electrode T84 of an eighth transistor, a first connection electrode E1, a second connection electrode E2, a third connection electrode E3, and a fourth connection electrode E4.

[0305] In an exemplary embodiment, at least a portion of at least one of the following signal lines extends along the second direction D2: initial signal line STV, first connection line CLK1A of the first clock signal line, first connection line CLK2A of the second clock signal line, first power line VL1, first connection line VL2A of the second power line, and first connection line VL3A of the third power line.

[0306] In an exemplary embodiment, the initial signal line STV, the first connection line CLK1A of the first clock signal line, the first connection line CLK2A of the second clock signal line, the first connection line VL3A of the third power line, the first power line VL1, and the first connection line VL2A of the second power line are arranged sequentially in the direction close to the display area.

[0307] In an exemplary embodiment, the initial signal line STV, the first connection line CLK1A of the first clock signal line, the first connection line CLK2A of the second clock signal line, and the first connection line VL3A of the third power line are located on the side of the first and second poles of at least one transistor that are away from the display area.

[0308] In an exemplary embodiment, the first power line VL1 is located between at least one electrode of the first pole 13 and the second pole 14 of the first transistor, the first pole 23 and the second pole 24 of the second transistor, the first pole 33 and the second pole 34 of the third transistor, the first pole 63 of the sixth transistor, the second pole 74 of the seventh transistor, and at least one electrode of the first pole 43 and the second pole 44 of the fourth transistor, the first pole 53 and the second pole 54 of the fifth transistor, and the second pole 84 of the eighth transistor.

[0309] In an exemplary embodiment, the first connection line VL2A of the second power line is located on the side of at least one electrode of the first pole 43 and the second pole 44 of the fourth transistor, the first pole 53 and the second pole 54 of the fifth transistor, and the second pole 84 of the eighth transistor, close to the display area.

[0310] In an exemplary embodiment, the first electrode 13 of the first transistor is provided separately. The first electrode 13 of the first transistor has a zigzag shape and extends at least partially along the second direction D2. The first electrode 13 of the first transistor of at least one level shift register is connected to the first region of the active pattern of the first transistor through the twelfth via V12 of the shift register of this level, and is connected to the first output line in the previous level shift register through the thirty-third via of the previous level shift register.

[0311] In an exemplary embodiment, the second electrode 14 of the first transistor and the second electrode 74 of the seventh transistor are an integral structure. The integral structure of the second electrode 14 of the first transistor and the second electrode 74 of the seventh transistor is strip-shaped and extends along the second direction D2. The integral structure of the second electrode 14 of the first transistor and the second electrode 74 of the seventh transistor is connected to the first control electrode of the second transistor through a fifth via, to the second region of the active pattern of the first transistor through a thirteenth via, to the second region of the active pattern of the seventh transistor through a twenty-third via, and to the second control electrode of the second transistor through a twenty-seventh via.

[0312] In an exemplary embodiment, the first electrode 23 of the second transistor is provided separately. The first electrode 23 of the second transistor is strip-shaped and extends along the second direction D2. The first electrode 23 of the second transistor is connected to the first control electrode of the first transistor (which is also the first control electrode of the third transistor) through a third via V3, connected to the first region of the active pattern of the second transistor through a fourteenth via, and connected to the second control electrode of the first transistor (which is also the second control electrode of the third transistor) through a twenty-sixth via V26.

[0313] In an exemplary embodiment, the second electrode 24 of the second transistor and the second electrode 34 of the third transistor are a single, integrated structure. This single, integrated structure is shaped like an "F" flipped 180 degrees to the right. The second electrode 24 of the second transistor and the second electrode 34 of the third transistor are connected to the first control electrode of the sixth transistor via an eighth via, to the second region of the active pattern of the second transistor via a fifteenth via, and to the second region of the active pattern of the third transistor via a seventeenth via.

[0314] In an exemplary embodiment, the first electrode 33 of the third transistor is integrally formed with the first power line VL1. The first electrode 33 of the third transistor may be strip-shaped and extend along the first direction D1. The first electrode 33 of the third transistor is connected to the first region of the active pattern of the third transistor through a sixteenth via.

[0315] In an exemplary embodiment, the first electrode 43 of the fourth transistor and the first connection line VL2A of the second power line are integrally formed. The first electrode 43 of the fourth transistor may be strip-shaped and extend along the first direction D1. The first electrode 43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through the eighteenth via.

[0316] In an exemplary embodiment, the second electrode 44 of the fourth transistor (which is also the second electrode 54 of the fifth transistor) may at least partially be "F" shaped. The second electrode 44 of the fourth transistor (which is also the second electrode 54 of the fifth transistor) is connected to the first plate of the second capacitor through a second via, to the second region of the active pattern of the fourth transistor through a nineteenth via, to the second region of the active pattern of the fifth transistor through a twenty-first via, to the first output line through a thirty-third via, and to the second output line through a thirty-fourth via.

[0317] In an exemplary embodiment, the first electrode 53 of the fifth transistor may be shaped like an "n" with its opening facing the display area. The first electrode 53 of the fifth transistor is connected to the first region of the active pattern of the fifth transistor through a twentieth via.

[0318] In an exemplary embodiment, the first electrode 63 of the sixth transistor and the first connection line VL3A of the third power line are integrally formed. The first electrode 63 of the sixth transistor may be strip-shaped and extend along the first direction D1. The first electrode 63 of the sixth transistor is connected to the first region of the active pattern of the sixth transistor through a twenty-second via.

[0319] In an exemplary embodiment, the first electrode 83 of the eighth transistor is provided separately. The first electrode 83 of the eighth transistor is strip-shaped and extends along the second direction D2. The first electrode 83 of the eighth transistor is connected to the first region of the active pattern of the eighth transistor through a twenty-fourth via.

[0320] In an exemplary embodiment, the second electrode 84 of the eighth transistor is separately disposed. The second electrode 84 of the eighth transistor is strip-shaped and extends along the second direction D2. The second electrode 84 of the eighth transistor is connected to the second region of the active pattern of the eighth transistor through a twenty-fifth via.

[0321] In an exemplary embodiment, a first connection electrode E1 is provided separately. The first connection electrode E1 is strip-shaped and extends along the second direction D2. The first connection electrode E1 is connected to the first control electrode of the seventh transistor through a ninth via and to the second control electrode of the eighth transistor through a thirty-first via.

[0322] In an exemplary embodiment, the second connection electrode E2 is provided separately. The second connection electrode E2 is strip-shaped and extends along the second direction D2. The second connection electrode E2 is connected to the first control electrode of the fourth transistor (which is also the second plate of the first capacitor) through the sixth via, and to the second control electrode of the fourth transistor through the twenty-eighth via.

[0323] In an exemplary embodiment, the third connection electrode E3 is provided separately. The third connection electrode E3 is strip-shaped and extends along the second direction D2. The third connection electrode E3 is connected to the first control electrode of the fifth transistor (which is also the second plate of the second capacitor) through the seventh via, and to the second control electrode of the fifth transistor through the twenty-ninth via.

[0324] In an exemplary embodiment, the fourth connection electrode E4 is provided separately. The fourth connection electrode E4 is strip-shaped and extends along the second direction D2. The fourth connection electrode E4 is connected to the first control electrode of the fifth transistor (which is also the second plate of the second capacitor) through the seventh via, and to the second control electrode of the fifth transistor through the twenty-ninth via.

[0325] In an exemplary embodiment, the first connection line VL2A of the second power line is connected to the first plate of the first capacitor through a first via.

[0326] In an exemplary embodiment, the first connection line VL3A of the third power line is connected to at least one first virtual structure through a first virtual via.

[0327] In an exemplary embodiment, the first connection line of one of the third and fourth clock signal lines is connected to a first signal connection line in at least one level shift register via a fourth via. The first connection line of the other of the third and fourth clock signal lines is connected to a second signal connection line in at least one level shift register via a tenth via.

[0328] In an exemplary embodiment, the first power line VL1 is connected to the first control electrode of the eighth transistor through the eleventh via and to the second control electrode of the eighth transistor through the thirty-second via.

[0329] (7) Forming a planarization layer pattern includes: depositing a fifth insulating film and a planarization film on a substrate on which the aforementioned pattern has been formed, and patterning the fifth insulating film and the planarization film through a patterning process to form a fifth insulating layer pattern and a planarization layer pattern covering the aforementioned structure. The planarization layer pattern has multiple via patterns, as shown in Figure 20. Figure 20 is a schematic diagram of the planarization layer pattern formed in Figure 8.

[0330] In an exemplary embodiment, the plurality of via patterns may include: the thirty-fifth via V35 to the thirty-ninth via V39.

[0331] In an exemplary embodiment, the orthographic projection of the 35th via V35 on the substrate is within the range of the orthographic projection of the first connection line of the third clock signal line on the substrate. The fifth insulating layer within the 35th via V35 is etched away, exposing the surface of the first connection line of the third clock signal line. The 35th via V35 is configured to allow the second connection line of the subsequently formed third clock signal line to be connected to the first connection line of the third clock signal line through the via.

[0332] In an exemplary embodiment, the orthographic projection of the 36th via V36 on the substrate is within the range of the orthographic projection of the first connection line of the fourth clock signal line on the substrate. The fifth insulating layer within the 36th via V36 is etched away, exposing the surface of the first connection line of the fourth clock signal line. The 36th via V36 is configured to allow the second connection line of the subsequently formed fourth clock signal line to be connected to the first connection line of the fourth clock signal line through the via.

[0333] In an exemplary embodiment, the orthographic projection of the 37th via V37 on the substrate is within the range of the orthographic projection of the first connection line of the third power line on the substrate. The fifth insulating layer within the 37th via V37 is etched away, exposing the surface of the first connection line of the third power line. The 37th via V37 is configured to allow the second connection line of the subsequently formed third power line to be connected to the first connection line of the third power line through the via.

[0334] In an exemplary embodiment, the orthographic projection of the 38th via V38 on the substrate is within the range of the orthographic projection of the first connection line of the second power line on the substrate. The fifth insulating layer in the 38th via V38 is etched away, exposing the surface of the first connection line of the second power line. The 38th via V38 is configured to allow the second connection line of the subsequently formed second power line to be connected to the first connection line of the second power line through the via.

[0335] In an exemplary embodiment, the orthographic projection of the 39th via V39 onto the substrate is within the range of the orthographic projection of the first electrode of the fifth transistor onto the substrate. The fifth insulating layer within the 39th via V39 is etched away, exposing the surface of the first electrode of the fifth transistor. The 39th via V39 is configured to allow one of the subsequently formed first clock signal lines and second clock signal lines to be connected to the first electrode of the fifth transistor through the via.

[0336] (8) Forming a fifth conductive layer pattern includes: depositing a fifth metal thin film on the substrate on which the aforementioned pattern is formed, and patterning the fifth metal thin film using a patterning process to form a fifth metal layer pattern, as shown in Figures 21 and 22. Figure 21 is a schematic diagram of the fifth conductive layer pattern in Figure 8, and Figure 22 is a schematic diagram of the fifth conductive layer pattern formed in Figure 8. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0337] In an exemplary embodiment, the fourth conductive layer pattern may include: a second connection line CLK3B of the third clock signal line, a second connection line CLK4B of the fourth clock signal line, a first clock signal line CLK1, a second clock signal line CLK2, a second connection line VL2B of the second power line, and a second connection line VL3B of the third power line.

[0338] In an exemplary embodiment, at least a portion of at least one of the following signal lines extends along the second direction D2: the second connection line CLK3B of the third clock signal line, the second connection line CLK4B of the fourth clock signal line, the first clock signal line CLK1, the second clock signal line CLK2, the second connection line VL2B of the second power line, and the second connection line VL3B of the third power line.

[0339] In an exemplary embodiment, the second connection line CLK3B of the third clock signal line, the second connection line CLK4B of the fourth clock signal line, the second connection line VL3B of the third power line, the first clock signal line CLK1, the second clock signal line CLK2, and the second connection line VL2B of the second power line are arranged sequentially in the direction close to the display area.

[0340] In an exemplary embodiment, the orthographic projection of the second connection line CLK3B of the third clock signal line on the substrate at least partially overlaps with the orthographic projection of the first connection line of the third clock signal line on the substrate. The second connection line CLK3B of the third clock signal line is connected to the first connection line of the third clock signal line through a thirty-fifth via.

[0341] In an exemplary embodiment, the orthographic projection of the second connection line CLK4B of the fourth clock signal line on the substrate at least partially overlaps with the orthographic projection of the first connection line of the fourth clock signal line on the substrate. The second connection line CLK3B of the fourth clock signal line is connected to the first connection line of the fourth clock signal line through a thirty-sixth via.

[0342] In an exemplary embodiment, the orthographic projection of the second connection line VL3B of the third power line on the substrate at least partially overlaps with the orthographic projection of the first connection line of the third power line on the substrate. The second connection line VL3B of the third power line is connected to the first connection line of the third power line through a thirty-seventh via.

[0343] In an exemplary embodiment, the orthographic projection of the second connection line VL2B of the second power line on the substrate at least partially overlaps with the orthographic projection of the first connection line of the second power line on the substrate. The second connection line VL2B of the second power line is connected to the first connection line of the second power line through a thirty-eighth via.

[0344] In an exemplary embodiment, the first clock signal line CLK1 is connected to the first terminal of the fifth transistor of at least one level shift register through the thirty-ninth via of at least one level shift register.

[0345] In an exemplary embodiment, the second clock signal line CLK2 is connected to the first terminal of the fifth transistor of at least one level shift register through the thirty-ninth via of at least one level shift register.

[0346] At this point, the circuit structure layer has been fabricated on the substrate.

[0347] In an exemplary embodiment, when the circuit structure layer includes a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer, the structure included in the first to third conductive layers is the same as the film layer structure in the display substrate provided in FIG8. The difference lies in the fourth, fifth, and sixth conductive layers. The fourth conductive layer includes an initial signal line, a first power line, and a fifth connection line of the second signal line. The fifth conductive layer may include a third connection line of at least one of the first clock signal line, a second clock signal line, and the sixth connection line of the second signal line. The sixth conductive layer may include a fourth connection line of at least one of the first clock signal line, a second clock signal line, and the seventh connection line of the second signal line. At this time, the circuit structure layer also includes: a first insulating layer located between the first conductive layer and the second conductive layer, a second insulating layer located between the second conductive layer and the semiconductor layer, a third insulating layer located between the semiconductor layer and the third conductive layer, a fourth insulating layer located between the third conductive layer and the fourth conductive layer, a fifth insulating layer located between the fourth conductive layer and the fifth conductive layer, and a sixth insulating layer located between the fifth conductive layer and the sixth conductive layer.

[0348] In an exemplary embodiment, the semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0349] In an exemplary embodiment, at least one of the first conductive layer, second conductive layer, third conductive layer, fourth conductive layer, fifth conductive layer and sixth conductive layer can be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0350] In an exemplary embodiment, at least one of the first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, fifth insulating layer and sixth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, multiple layers or composite layer.

[0351] In an exemplary embodiment, the planarization layer may be made of organic materials, such as resin.

[0352] The display substrate described in this embodiment can be used in display products of any resolution.

[0353] This disclosure also provides a display device, including: a display substrate provided in any of the embodiments.

[0354] In an exemplary embodiment, the display device can be any product or component with display function, such as a wearable device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0355] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0356] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0357] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate having a display area and a non-display area located at at least one side of the display area, the display substrate comprising: The substrate and a gate driving circuit and a clock signal line group disposed on the substrate and located in the non-display area, the clock signal line group including: multiple clock signal lines, the gate driving circuit including: multiple cascaded shift registers, at least one of the multiple cascaded shift registers being electrically connected to at least one of the multiple clock signal lines, and at least one of the multiple cascaded shift registers including: at least one output transistor; The orthographic projection of at least one of the multiple clock signal lines on the substrate at least partially overlaps with the orthographic projection of at least one output transistor of at least one stage of the multiple cascaded shift registers on the substrate. 2.The display substrate of claim 1, wherein, The at least one output transistor includes a fourth transistor and a fifth transistor, wherein the second terminals of the fourth transistor and the fifth transistor are electrically connected to a signal output terminal, and the first terminal of the fifth transistor is electrically connected to a first clock signal terminal. The plurality of clock signal lines include: a first clock signal line and a second clock signal line, wherein at least a portion of at least one of the first clock signal line and the second clock signal line extends along a second direction; The first clock signal terminal of at least one shift register is electrically connected to one of the first clock signal lines and the second clock signal line, and the first clock signal terminals of adjacent shift registers are connected to different clock signal lines; The orthographic projection of at least one of the first clock signal lines and the second clock signal line onto the substrate at least partially overlaps with the orthographic projection of at least one of the fourth and fifth transistors in at least one level shift register onto the substrate. 3.The display substrate of claim 2, wherein, The shift register at least one level further includes: a first transistor, a second transistor, a third transistor, and a seventh transistor, wherein the control electrode of the first transistor, the first electrode of the second transistor, and the control electrode of the third transistor are electrically connected to the second clock signal terminal, and the control electrode of the seventh transistor is electrically connected to the third clock signal terminal. The plurality of clock signal lines further includes: a third clock signal line and a fourth clock signal line, wherein at least a portion of at least one of the third clock signal line and the fourth clock signal line extends along a second direction; The second clock signal terminal of at least one stage shift register is electrically connected to one of the third and fourth clock signal lines, and the third clock signal terminal of at least one stage shift register is electrically connected to the other of the third and fourth clock signal lines. The second clock signal terminals of adjacent stages shift registers are connected to different signal lines, and the third clock signal terminals of adjacent stages shift registers are connected to different signal lines. The orthographic projection of at least one of the third and fourth clock signal lines onto the substrate is located on the side of the orthographic projection of at least one of the first and second clock signal lines onto the substrate that is away from the display area. 4.The display substrate of claim 3, further comprising: The power signal line group disposed on the substrate and located in the non-display area, at least one level shift register further includes: an eighth transistor, wherein the first electrode of the third transistor and the control electrode of the eighth transistor are respectively electrically connected to the first power supply terminal; The power signal line group includes: a first power line, at least a portion of which extends along a second direction, and a first power supply terminal of at least one shift register is electrically connected to the first power line; The orthographic projection of the first power line on the substrate lies between the orthographic projections of at least one of the first and second clock signal lines on the substrate and the orthographic projections of at least one of the third and fourth clock signal lines on the substrate, and at least partially overlaps with the orthographic projection of at least one transistor in at least one level shift register on the substrate. 5.The display substrate of claim 4, wherein, The first terminal of the fourth transistor in at least one shift register is electrically connected to the second power supply terminal; The power signal line group further includes: a second power line, at least a portion of which extends along a second direction, and the second power supply terminal of at least one shift register is electrically connected to the second power line; The orthographic projection of the second power line on the substrate is located on the side of the orthographic projection of at least one of the first clock signal line and the second clock signal line on the substrate that is closer to the display area. 6.The display substrate of claim 5, wherein, At least one shift register also includes: a sixth transistor, the first terminal of which is electrically connected to a third power supply terminal; The power signal line group further includes: a third power line, at least a portion of which extends along the second direction, and the third power supply terminal of at least one shift register is electrically connected to the third power line; The orthographic projection of the third power line onto the substrate lies between the orthographic projection of at least one of the third and fourth clock signal lines onto the substrate and the orthographic projection of the first power line onto the substrate. 7.The display substrate according to claim 3 or 6, wherein The first terminal of the first transistor in at least one shift register is electrically connected to the signal input terminal; The display substrate further includes: an initial signal line disposed on the substrate and located in the non-display area, the initial signal line extending at least partially along a second direction, and the signal input terminal of at least one shift register being electrically connected to the initial signal line; The orthographic projection of the initial signal line on the substrate is located on the side of the orthographic projection of at least one of the third and fourth clock signal lines on the substrate that is away from the display area. 8.The display substrate of claim 7, wherein, The signal lines connected to at least one shift register include: a first clock signal line, a second clock signal line, and a first power supply line; The signal lines connected to at least one shift register further include at least one of a first signal line and a second signal line, wherein the first signal line is a signal line among the third clock signal line, the fourth clock signal line, the second power supply line, and the third power supply line that at least partially overlaps with the orthogonal projection of at least one transistor in the at least one shift register on the substrate, and the second signal line is a signal line among the third clock signal line, the fourth clock signal line, the second power supply line, and the third power supply line that does not overlap with the orthogonal projection of at least one transistor in the at least one shift register on the substrate. 9.The display substrate of claim 8, further comprising: A circuit structure layer disposed on the substrate includes: a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; The first clock signal line, the second clock signal line, and the first signal line are located in the fifth conductive layer, and the first power line and the initial signal line are located in the fourth conductive layer. The second signal line includes: a first connecting line and a second connecting line that are interconnected, wherein the orthographic projection of the first connecting line on the substrate and the orthographic projection of the second connecting line on the substrate at least partially overlap; The first connection line of at least one second signal line is located in the fourth conductive layer, and the second connection line of at least one second signal line is located in the fifth conductive layer. 10.The display substrate of claim 8, further comprising: A circuit structure layer disposed on the substrate includes: a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer; The initial signal line and the first power line are located in the fourth conductive layer. At least one of the first clock signal line, the second clock signal line and the first signal line includes: a third connecting line and a fourth connecting line that are connected to each other. The orthographic projection of the third connecting line on the substrate and the orthographic projection of the fourth connecting line on the substrate at least partially overlap. The third connecting line of at least one signal line is located in the fifth conductive layer, and the fourth connecting line of at least one signal line is located in the sixth conductive layer. The second signal line includes: a fifth connecting line, a sixth connecting line, and a seventh connecting line that are interconnected. The orthographic projections of at least two of the fifth connecting lines, the sixth connecting line, and the seventh connecting line located on the same signal line on the substrate at least partially overlap. The fifth connecting line of at least one signal line is located in the fourth conductive layer, the sixth connecting line of at least one signal line is located in the fifth conductive layer, and the seventh connecting line of at least one signal line is located in the sixth conductive layer. 11.The display substrate according to claim 9 or 10, wherein At least one shift register includes: a plurality of transistors, at least one of the plurality of transistors being an N-type transistor, and at least one of the plurality of transistors including: a first control electrode and a second control electrode interconnected with each other; The first control electrode of at least one transistor is located on the side of the active pattern of at least one transistor close to the substrate, and the second control electrode of at least one transistor is located on the side of the active pattern of at least one transistor away from the substrate. The orthographic projection of the first control electrode of at least one transistor on the substrate and the orthographic projection of the second control electrode of at least one transistor on the substrate at least partially overlap. 12.The display substrate of claim 11, wherein, The first control electrode of at least one transistor is located in the second conductive layer, the second control electrode of at least one transistor is located in the third conductive layer, and the active pattern of at least one transistor is located in the semiconductor layer; The semiconductor layer is a metal oxide layer.

13. The display substrate of claim 11, further comprising: A plurality of first signal connection lines and a plurality of second signal connection lines, wherein at least a portion of at least one of the plurality of first signal connection lines extends along a first direction, and at least a portion of at least one of the plurality of second signal connection lines extends along the first direction, wherein the first direction and the second direction intersect. At least one first signal connection line is electrically connected to at least one electrode of the first control electrode and the second control electrode of the first transistor, at least one electrode of the control electrode and the second control electrode of the third transistor, and one of the signal lines of the third clock signal line and the fourth clock signal line, respectively; at least one second signal connection line is electrically connected to one electrode of the first control electrode and the second control electrode of the seventh transistor and the other signal line of the third clock signal line and the fourth clock signal line, respectively. At least one of the first signal connection line and the second signal connection line is located in the first conductive layer or the second conductive layer.

14. The display substrate of claim 11, further comprising: Multiple connection vias are disposed on the substrate and located in the non-display area; The number of connection vias exposing at least one first control electrode of a transistor is at least one, and the number of connection vias exposing at least one second control electrode of a transistor is at least one. 15.The display substrate of claim 14, wherein, At least one shift register further includes: a second capacitor, the first plate of the second capacitor being electrically connected to the control electrode of the fifth transistor, the second plate of the second capacitor being electrically connected to the signal output terminal, and the plurality of connection vias including: a first connection via, a second connection via, a third connection via, and a fourth connection via; The first and second connection vias expose the first control electrode of the fifth transistor, the second connection via is located on the side of the first connection via closer to the display area, the third and fourth connection vias expose the second control electrode of the fifth transistor, and the fourth connection via is located on the side of the third connection via closer to the display area; For at least one level shift register, the orthographic projections of the first and third connection vias onto the substrate are within the range of the orthographic projection of the second capacitor onto the substrate. 16.The display substrate of claim 15, wherein, The second control electrode of the fifth transistor includes: a first connection segment and a plurality of branch segments, the first connection segment extending along a second direction, at least one of the plurality of branch segments extending along a first direction, and at least one of the plurality of branch segments being located on the side of the first connection segment closer to the display area and electrically connected to the first connection segment; For at least one level shift register, the orthographic projection of the first connection segment onto the substrate is within the range of the orthographic projection of the second capacitor onto the substrate, the third connection via exposes the first connection segment, and the fourth connection via exposes one of the plurality of branch segments at an end away from the first connection segment. 17.The display substrate of claim 16, wherein, The second control electrode of the fifth transistor further includes: a second connection segment, the second connection segment extending along a second direction; The second connection segment is located on the side of the plurality of branch segments closest to the display area and is connected to at least one of the plurality of branch segments.

18. The display substrate of claim 11, further comprising: A plurality of first virtual structures, wherein at least one of the plurality of first virtual structures is disposed on the same layer as the active pattern of at least one transistor located in at least one level shift register; The distance between the orthographic projection of at least one of the plurality of first virtual structures on the substrate and the orthographic projection of at least one of the active patterns, first control electrode and second control electrode of at least one transistor located in at least one level shift register on the substrate is greater than 2 micrometers.

19. The display substrate of claim 18, wherein, The orthographic projection of at least one of the plurality of first virtual structures on the substrate at least partially overlaps with the orthographic projection of at least one of the third clock signal line, the fourth clock signal line, and the third power line on the substrate, and is electrically connected to at least one of the third clock signal line, the fourth clock signal line, and the third power line.

20. The display substrate of claim 18, further comprising: Multiple second virtual structures, wherein the orthographic projection of at least one of the multiple second virtual structures on the substrate does not overlap with the orthographic projection of the active pattern, first control electrode, second control electrode, first electrode and second electrode of at least one transistor in at least one level shift register, and the signal line connected to at least one level shift register on the substrate. The second virtual structure is located in at least one of the first conductive layer, the second conductive layer, and the third conductive layer.

21. The display substrate of claim 20, further comprising: Multiple virtual vias, at least one of which exposes at least one of the first and second virtual structures.

22. The display substrate of claim 9 or 10, wherein, The shift register at least one level also includes: multiple transistors, a first capacitor and a second capacitor. The first capacitor and the second capacitor include: a first plate and a second plate. The first plate of the first capacitor is electrically connected to the second power supply terminal. The second plate of the first capacitor is electrically connected to the control electrode of the fourth transistor. The first plate of the second capacitor is electrically connected to the signal output terminal. The second plate of the second capacitor is electrically connected to the control electrode of the fifth transistor. The first conductive layer includes at least: the first plate of the first capacitor and the first plate of the second capacitor located in at least one level shift register; The second conductive layer includes at least: the second plate of the first capacitor and the second plate of the second capacitor located in at least one level shift register; The fourth conductive layer includes at least: the first and second terminals of at least one transistor among a plurality of transistors located in at least one level shift register.

23. The display substrate of claim 3, wherein, The line width of at least one of the first clock signal line and the second clock signal line is greater than the line width of at least one of the third clock signal line and the fourth clock signal line.

24. The display substrate of claim 6, wherein, The line width of at least one of the first power line and the third power line is smaller than the line width of at least one of the first clock signal line and the second clock signal line; The line width of the second power line is greater than the line width of at least one of the first power line and the third power line. 25.The display substrate of claim 3, wherein, The line width of at least one of the first clock signal line and the second clock signal line is in the range of 10 micrometers to 100 micrometers; The linewidth of at least one of the third and fourth clock signal lines is in the range of 4 micrometers to 20 micrometers.

26. The display substrate of claim 3, wherein, The clock signal of at least one of the first clock signal line and the second clock signal line within one cycle includes: a first clock signal and a second clock signal; the clock signal of at least one of the third clock signal line and the fourth clock signal line within one cycle includes: a third clock signal and a fourth clock signal. The first clock signal and the third clock signal are positive voltage signals, and the second clock signal and the fourth clock signal are negative voltage signals; The voltage value of at least one of the first clock signal and the third clock signal is greater than 8 volts, and the voltage value of the third clock signal is greater than the voltage value of the first clock signal, the voltage value of the fourth clock signal is greater than -14 volts, and the voltage value of the second clock signal is greater than the voltage value of the fourth clock signal.

27. A display device comprising: The display substrate as described in any one of claims 1 to 26.

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