Semiconductor device and method for manufacturing semiconductor device

Abstract

[Problem] To appropriately define an alignment mark. [Solution] This semiconductor device is formed by laminating at least a first substrate and a second substrate. The arrangement of the first substrate and the second substrate in a first direction and a second direction intersecting the first direction is defined by an alignment mark, and the first substrate and the second substrate are laminated in a third direction intersecting the first direction and the second direction. At least the second substrate is formed by laminating a plurality of layers, and the alignment mark is formed by laminating at least two layers among the plurality of layers.

Description

Semiconductor device and method for manufacturing a semiconductor device

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Semiconductor devices may be formed by stacking a plurality of semiconductor substrates depending on the purpose and manufacturing method. In order to join the elements disposed on each of the plurality of semiconductor substrates in a form that appropriately electrically connects them, for example, it is necessary to appropriately position and join them so that metal wirings and the like disposed on the respective surfaces of the plurality of semiconductor substrates are connected. In this positioning, an alignment mark having a predetermined pattern may be used. The alignment mark is formed so as to have a predetermined shape on each of the substrates to be stacked. In the stacking process, the joining position of the semiconductor device can be determined by adjusting the position so that the predetermined shapes appropriately overlap each other or form other appropriate shapes.

[0003] On the other hand, when there are a plurality of semiconductor layers in the substrate to be stacked, if an alignment mark is disposed in one of the layers, there will be no wirings or the like in the region where the alignment mark is defined in the other layers, and due to the difference in material from other wirings or the like in this region, it may become a factor for the occurrence of warpage or the like. In order to avoid this, it is possible to dispose wirings or the like in other layers in this region, but there is a problem that the visibility of the pattern of the alignment mark is reduced due to the disposition of wirings or the like.

[0004] Japanese Patent Application Laid-Open No. 2021-158348

[0005] Therefore, one of the non-limiting problems to be solved by the embodiments of the present disclosure is to appropriately define an alignment mark. The problems to be solved by the embodiments of the present disclosure can also be, as some further non-limiting examples, problems corresponding to the effects described in the embodiments. That is, the problems corresponding to any at least one of the effects described in the description of the embodiments of the present disclosure can be the problems to be solved in the present disclosure.

[0006] According to one embodiment, the substrate is formed by stacking at least a first substrate and a second substrate. The first substrate and the second substrate are stacked in a third direction intersecting the first and second directions, with their arrangement defined in a first direction and a second direction intersecting the first direction by alignment marks. At least the second substrate is formed by stacking a plurality of layers, and the alignment marks are formed by stacking at least two of the plurality of layers.

[0007] The first substrate is provided with a first alignment mark, and the second substrate is provided with a second alignment mark. The shape of the first alignment mark and the shape of the second alignment mark may define at least the positions in the first and second directions for stacking the first and second substrates, and the shape of the second alignment mark may be formed by superimposing patterns arranged on each of the at least two layers stacked on the second substrate in the third direction.

[0008] The first alignment mark and the second alignment mark may be located at one or at least more different positions in the plane formed by the first and second directions on the first and second substrates, respectively.

[0009] The second alignment marks may be arranged in the same shape and position in each of the at least two layers.

[0010] The second alignment mark may have a shape that is positioned at least differently in each of the at least two layers.

[0011] The second alignment mark may be defined by the metals arranged in the at least two layers.

[0012] The aforementioned two layers may have dummy patterns placed in areas where the second alignment marks are not defined.

[0013] The first substrate may be formed by stacking multiple layers, and the shape of the first alignment mark may be formed by superimposing patterns located on each of at least two layers stacked on the first substrate in the third direction.

[0014] Each of the at least two layers may include a dummy pattern, and the shape of the second alignment mark may be defined by superimposing the dummy patterns placed in each of the at least two layers in the third direction.

[0015] The first substrate may be formed by stacking multiple layers, and the shape of the first alignment mark may be defined by superimposing dummy patterns placed on each of the at least two layers stacked on the first substrate in the third direction.

[0016] The shape formed by the superposition of the dummy patterns may be a circular pattern.

[0017] The shape formed by the superposition of the dummy patterns may be a rectangular pattern.

[0018] The size or shape of the dummy pattern may be the same in at least two of the layers.

[0019] The size or shape of the dummy pattern may differ in at least two of the layers.

[0020] The size of the dummy pattern may be larger than the size of the metal wiring pattern arranged in the at least two layers.

[0021] The dummy pattern may be positioned in the same location in at least part of two or more layers of the at least two layers.

[0022] The dummy pattern may be positioned in different locations in at least part of two or more layers of the at least two layers.

[0023] A semiconductor device according to one embodiment is formed by stacking at least a first substrate and a second substrate, and this semiconductor device is formed by the following method: A plurality of semiconductor layers are stacked, and alignment marks are formed by overlapping patterns formed in at least two of the plurality of semiconductor layers to generate the second substrate; and the first substrate and the second substrate are stacked in a third direction intersecting the first and second directions, with their arrangement in a first direction and a second direction intersecting the first direction defined by the alignment marks.

[0024] According to one embodiment, the semiconductor device is formed by stacking a plurality of semiconductor substrates using the alignment marks described in any of the above.

[0025] A schematic diagram showing an example of stacking of a semiconductor device according to one embodiment. A schematic diagram showing an example of stacking of a semiconductor device according to one embodiment. A schematic diagram showing an example of the definition of an alignment mark according to one embodiment. A schematic diagram showing an example of the definition of an alignment mark according to one embodiment. A schematic diagram showing an example of the definition of an alignment mark according to one embodiment. A schematic diagram showing an example of the definition of an alignment mark according to one embodiment. A schematic diagram showing an example of the definition of an alignment mark according to one embodiment. A schematic top view showing an example of the generation of the shape of an alignment mark according to one embodiment. A schematic top view showing an example of the generation of the shape of an alignment mark according to one embodiment. A schematic top view showing an example of the generation of the shape of an alignment mark according to one embodiment. A schematic top view showing an example of the generation of the shape of an alignment mark according to one embodiment. A schematic top view showing an example of the generation of the shape of an alignment mark according to one embodiment. A schematic diagram showing a cross-section of a substrate according to one embodiment. A schematic diagram showing a cross-section of a substrate according to one embodiment. A schematic diagram showing a cross-section of a substrate according to one embodiment. A schematic top view showing an example of the generation of the alignment mark shape according to one embodiment. A schematic top view showing an example of the generation of the alignment mark shape according to one embodiment. A diagram showing several examples of dummy patterns according to one embodiment, not limited to one embodiment. A schematic diagram showing the surrounding state where the dummy pattern according to one embodiment is placed. A schematic diagram showing the surrounding state where the dummy pattern according to one embodiment is placed. A diagram showing an example of the arrangement of a pattern according to one embodiment. A diagram showing an example of the arrangement of a pattern according to one embodiment. A diagram showing an example of the arrangement of a pattern according to one embodiment. A diagram showing an example of an alignment mark according to one embodiment. A diagram showing an example of an alignment mark according to one embodiment. A diagram showing an example of an alignment mark according to one embodiment. A diagram showing an example of an alignment mark according to one embodiment. A diagram showing an example of an alignment mark according to one embodiment. A diagram showing an example of an alignment mark according to one embodiment. A diagram showing an example of an alignment mark according to one embodiment.

[0026] The embodiments of this disclosure will now be described with reference to the drawings. The drawings are for illustrative purposes only, and the shape, size, or size ratio of each component in the actual device does not need to be exactly as shown in the drawings. Furthermore, the drawings are simplified, so any other components necessary for implementation should be appropriately provided in addition to those shown in the drawings.

[0027] This disclosure describes embodiments in the following order: 1. Example of a multilayer semiconductor 2. Overview of the definition of alignment marks 3. Generation of alignment mark shapes 4. Shape and arrangement of alignment marks

[0028] <1. Examples of multilayer semiconductors>

[0029] This section describes an example of a semiconductor device formed by stacking multiple semiconductor substrates produced by separate processes. While this disclosure provides an example of a solid-state imaging device as a non-limiting example, it should be noted that the embodiments of this disclosure are not limited to applications to other semiconductor devices, but are applicable to various semiconductor devices formed by stacking semiconductor substrates.

[0030] Furthermore, while we will describe a configuration in which two substrates are joined as an example that is not limited to this, please note that it can also be applied to joining substrates with three or more layers, similar to the above.

[0031] Furthermore, the use of alignment marks described in each embodiment of this disclosure can be implemented by any method. For example, it is possible to align the substrates to be joined using information acquired by an appropriate sensor after irradiation with an appropriate light source.

[0032] Figure 1 is a schematic diagram illustrating an example of a semiconductor device stacking according to one embodiment, using a solid-state imaging device as an example without limitation. The semiconductor device 1 is, for example, a semiconductor device manufactured by stacking a first substrate 10 and a second substrate 12, which are formed separately.

[0033] The directions in which the substrates constituting the first substrate 10 and the second substrate 12 extend are indicated by the first direction and the second direction intersecting the first direction. The third direction is the direction that intersects each of the first and second directions. These directions only need to be primary independent; for example, the third direction may intersect the first direction and the second direction perpendicular to the first direction at a right angle. The semiconductor device 1 can have a structure in which the first substrate 10 and the second substrate 12 are stacked in the third direction.

[0034] The first substrate 10 is equipped with an analog-to-digital converter (ADC), logic circuits, etc., for processing signals output based on the intensity of incident light at each pixel belonging to the second substrate 12. The signals output from the second substrate 12 are converted into digital signals by the ADC, and the digital signals output from the ADC may be appropriately processed by logic circuits, etc., for signal processing, image processing, etc.

[0035] The second substrate 12 includes, for example, a region that operates as a photoelectric conversion element forming a light-receiving pixel, an optical system that collects light incident on each photoelectric conversion element, and a pixel circuit that includes transistors, capacitors, etc., for processing signals based on carriers output from the photoelectric conversion elements.

[0036] Since the first substrate 10 and the second substrate 12 generally contain complex structures, it is often difficult to manufacture them as a single process. In such cases, the first substrate 10 and the second substrate 12 are formed by separate processes, and the semiconductor device 1 is formed by joining these first substrate 10 and second substrate 12 together, as shown in Figure 2.

[0037] The first substrate 10 and the second substrate 12 may be joined by a Chip-on-Chip (CoC) method, in which they are joined after dicing each of the first substrate 10 and the second substrate 12. The first substrate 10 and the second substrate 12 may also be joined by a Chip-on-Wafer (CoW) method, in which one of the first substrate 10 or the second substrate 12 is diced and then joined to the other wafer. Alternatively, the first substrate 10 and the second substrate 12 may be joined by a Wafer-on-Wafer (WoW) method, in which they are joined before dicing the first substrate 10 and the second substrate 12.

[0038] Furthermore, if the semiconductor device 1 is a stack of three or more layers, the semiconductor device 1 may be formed by joining multiple layers using any combination of the above joining methods. Also, the above is merely an example and is not limiting, and the embodiments described in this disclosure can be applied to other joining methods as long as they do not contradict each other.

[0039] In the manufacturing process of semiconductor device 1, the semiconductor manufacturing equipment needs to bond the wiring, such as metal, located on the first substrate 10 to the wiring, such as metal, located on the second substrate 12, so that they are properly electrically connected. That is, the first substrate 10 and the second substrate 12 need to be properly positioned in the first and second directions, and then stacked and bonded in the third direction.

[0040] Alignment marks are patterns used for alignment in the first and second directions during the bonding process described above. For example, alignment marks are placed on the first substrate 10 and the second substrate 12, respectively. The alignment marks on the first substrate 10 and the second substrate 12 define their positions in the first and second directions during bonding, and they are then stacked in the third direction.

[0041] The bonding can be realized by any method such as Through Silicon Via (TSV) that electrically bonds each substrate using via holes, directly bonding the metals formed on the surfaces of the respective substrates (or bonding by heat treatment after directly contacting them), or micro-bump bonding.

[0042] The first substrate 10 and the second substrate 12 are each formed having a plurality of semiconductor layers such as wiring. In the present disclosure, some embodiments will be used to explain the definition of the arrangement of alignment marks and the like in the case where at least one of the stacked semiconductor substrates is formed having a plurality of semiconductor layers.

[0043] <2. Outline of the definition of alignment marks>

[0044] FIG. 3 is a diagram schematically showing an example of the definition of alignment marks according to an embodiment. This figure is a diagram showing an outline of the arrangement of the region including the alignment marks when the first substrate 10 and the second substrate 12 are viewed from above.

[0045] When the semiconductor device 1 is an image sensor, as an example, pixels having a photoelectric conversion region may be formed on the second substrate 12, and a circuit, wiring, etc. for signal processing output from the pixels may be formed on the first substrate 10. Even when the semiconductor device 1 is not an image sensor, circuits, wirings, etc. may be similarly arranged on the first substrate 10 and the second substrate 12, respectively.

[0046] The first substrate 10 is provided with a pixel region 100 and a dummy region 102. The pixel region 100 is, for example, a region where wirings, circuit elements, etc. for processing signals output from pixels are arranged. The dummy region 102 is a region other than the pixel region 100, and is a region where dummy wirings, etc. are arranged to ensure flatness with the surface of the pixel region 100 where wirings, circuit elements, etc. are arranged.

[0047] The second substrate 12 includes a circuit region 120 and a dummy region 122. The circuit region 120 is, for example, a region where pixels (active pixels) that convert light into an analog signal are arranged. The dummy region 122 is a region other than the circuit region 120, and is a region where peripheral pixels (inactive pixels), dummy wirings, etc. are arranged so as to ensure flatness with the surface of the circuit region 120 where wirings, circuit elements, etc. are arranged.

[0048] The first alignment mark 20, which is an alignment mark provided on the first substrate 10, is arranged, for example, in the dummy region 102. The second alignment mark 22, which is an alignment mark provided on the second substrate 12, is arranged, for example, in the dummy region 122. The first alignment mark 20 and the second alignment mark 22 are preferably formed in a manner that can be distinguished from other dummy wirings in a region where dummy wirings are arranged.

[0049] The dummy wirings are preferably formed in the semiconductor layers in which wirings, etc. are arranged in the pixel region 100 and the circuit region 120 in order to flatten the respective semiconductor layers. Therefore, the alignment marks formed in the dummy region 102 and the dummy region 122 are also preferably arranged together with the dummy wirings in the semiconductor layer in which wirings, etc. are arranged. Furthermore, in order to ensure flatness, the arranged dummy wirings and alignment marks are preferably formed of the same material as the wirings, etc. arranged in the pixel region 100 of the same layer, for example, the same metal material.

[0050] The first alignment mark 20 and the second alignment mark 22 are arranged (defined) so that the wirings electrically connecting the first substrate 10 and the second substrate 12 can be adjusted to contact each other in the first direction and the second direction so that the first substrate 10 and the second substrate 12 are appropriately joined and laminated in the third direction.

[0051] While one first alignment mark 20 and one second alignment mark 22 may be defined on each substrate, it is more desirable to define multiple marks, as this can improve the accuracy of the bond. For example, as shown in the figure, two first alignment marks 20 and two second alignment marks 22 may be placed on the first substrate 10 and the second substrate 12, respectively.

[0052] In the semiconductor device manufacturing process, the semiconductor manufacturing equipment can stack the first substrate 10 and the second substrate 12, which are formed individually by separate processes, without misalignment in the first and second directions by referring to alignment marks.

[0053] Figure 4 shows an example of alignment marks according to one embodiment, not limited to this example. The dashed lines represent, for example, the regions in which each alignment mark is defined. The shaded areas indicate defined alignment marks, which, as described above, are formed by metals or the like that are placed in predetermined semiconductor layers on the first substrate 10 and the second substrate 12.

[0054] The first alignment mark 20 and the second alignment mark 22 have predetermined shapes, such as rectangular marks, defined in the areas indicated by the shaded sections. These shapes are not limited to these, and other examples will be described later.

[0055] Figure 5 shows an example of alignment marks in a stacked state according to one embodiment, which is not limited to this example. The semiconductor manufacturing apparatus stacks the first substrate 10 and the second substrate 12 by, for example, overlapping them so that the first alignment mark 20 and the second alignment mark 22 shown in Figure 4 are in the appropriate position.

[0056] For example, in the case of the alignment marks shown in Figure 4, as shown in Figure 5, the semiconductor manufacturing apparatus can appropriately position the first substrate 10 and the second substrate 12 in the first and second directions by controlling the alignment of the first alignment mark 20 and the second alignment mark 22 in the first direction, and by controlling the alignment so that the shape defined in the first alignment mark 20 is centered on the shape defined in the second alignment mark 22.

[0057] In the above, different marks were defined for the first alignment mark 20 and the second alignment mark 22, but this is not the only way to go. For example, the alignment marks could be defined as the shapes shown in the lower part of Figure 4 for both the first alignment mark 20 and the second alignment mark 22, and the semiconductor manufacturing equipment could achieve proper alignment by adjusting the first and second directions so that these marks overlap, that is, so that one does not extend beyond the other.

[0058] Figure 6 shows an example of alignment marks according to one embodiment, not limited to this example. As described above, multiple alignment marks may be defined on each substrate. For example, multiple first alignment marks 20 may be placed in the dummy area 102 of the first substrate 10, and multiple second alignment marks 22 may be placed in the dummy area 122 of the second substrate 12. The alignment marks placed at each position are arranged so as to overlap with corresponding alignment marks on other substrates, thereby appropriately controlling the alignment between the first substrate 10 and the second substrate 12.

[0059] Figure 7 shows an example of alignment marks in a stacked state according to one embodiment, not limited to this example. By aligning the first alignment mark 20 and the second alignment mark 22 shown in Figure 6, the semiconductor manufacturing equipment can control alignment with higher precision.

[0060] Figure 8 shows an example of alignment marks according to one embodiment, not limited to this example. As shown in this figure, even if one substrate is tilted relative to the other, the first and second directions on each substrate can be controlled to overlap at an appropriate angle, allowing them to be stacked in the same configuration as in Figure 7.

[0061] For example, if the second substrate 12 is tilted by a certain angle with respect to the first and second directions of the first substrate 10, the first' and second' directions corresponding to the first and second directions, respectively, of the second substrate 12 can be appropriately adjusted to the first and second directions. In other words, by using alignment marks, it is possible to align the directions of the first and second directions in the stacking of the first substrate 10 and the second substrate 12, and then align the positions of the first and second directions.

[0062] In the above, the alignment was set to the first and second directions on the first substrate 10. However, it is possible to arbitrarily select, through mounting, which of the first substrate 10 or the second substrate 12 is used as the reference for aligning the first and second directions, or whether the semiconductor manufacturing equipment designates predetermined directions as the first and second directions regardless of the inclination of the first substrate 10 or the second substrate 12.

[0063] While several non-limiting examples have been described using Figures 3 to 8, the arrangement of each region is shown as an example and is not limited to these figures. For example, dummy region 102 and dummy region 122 may be arranged to surround the first substrate 10 and the second substrate 12, respectively. Also, for example, the regions of dummy region 102 and dummy region 122 do not necessarily have to coincide and may be formed with different shapes or sizes.

[0064] <3. Generating the shape of alignment marks>

[0065] Assume that the second substrate 12 is formed by stacking multiple semiconductor layers. However, the first substrate 10 may also be formed by stacking multiple semiconductor layers. In this case, if alignment marks are placed only on a certain layer of the second substrate 12, it is possible to maintain flatness in the layer on which the alignment marks are placed, but flatness in the region on which the alignment marks are placed may not be guaranteed in other layers where the alignment marks are not placed. Therefore, in this disclosure, alignment marks are defined using multiple layers.

[0066] (First Embodiment)

[0067] The following explanation uses the case where the second substrate 12 is formed from a plurality of semiconductor layers and the second alignment mark 22 is defined by at least two of these semiconductor layers. However, the first alignment mark 20 may also be defined by at least two of the plurality of semiconductor layers forming the first substrate 10. Furthermore, the second alignment mark 22 may be formed by the overlapping of semiconductor layers depending on the shape of the patterns arranged in these at least two layers.

[0068] In other words, the alignment marks (first alignment mark 20 and / or second alignment mark 22) are defined, for example, by placing a pattern appropriately formed of metal in at least two of the multiple semiconductor layers, and stacking these at least two layers. Furthermore, in these at least two layers, the pattern may be placed in the dummy regions 102 and / or dummy regions 122 shown in Figure 3 in a manner that distinguishes it from dummy wiring placed in other regions of the region where the alignment marks are placed.

[0069] Figure 9 is a schematic top view showing an example of the generation of an alignment mark shape according to one embodiment. The second alignment mark 22 can be defined by superimposing patterns formed in multiple layers. The second alignment mark 22 may be defined, for example, by superimposing a pattern 22a located in the a-th layer forming the second substrate 12, a pattern 22b located in the b-th layer, and a pattern 22c located in the c-th layer.

[0070] Although the alignment marks are defined by three layers in the diagram, they may also be defined by a pattern arranged in at least two layers, such as two layers or four or more layers.

[0071] As shown in Figure 9, the second alignment mark 22 is defined by forming each semiconductor layer such that the same pattern is located in the same position for the a-th, b-th, and c-th layers.

[0072] These a-th, b-th, and c-th layers may be at least two layers that are continuous in the third direction, or they may not all be formed so that they are directly in contact in the third direction. That is, the a-th and b-th layers may be formed continuously in the manufacturing process, or they may be formed with other layers in between.

[0073] In this way, by forming patterns of the same shape in at least two of the multiple layers that make up the second substrate 12, it becomes possible to define alignment marks as a clear pattern created by superimposing multiple identical patterns. Even with this shape, the flatness of each layer on which the pattern is placed can be improved.

[0074] (Second Embodiment)

[0075] Figure 10 is a schematic top view showing an example of the generation of the alignment mark shape according to one embodiment. The second alignment mark 22 may be formed, for example, by a pattern arranged in three layers, similar to the first embodiment described above.

[0076] As shown in this figure, the shape of the second alignment mark 22 may be defined by placing patterns of the same size and dimensions on each layer and overlapping these patterns.

[0077] Furthermore, as shown in Figures 11 and 12, the patterns arranged in each layer may be of different sizes, shapes, and arrangements, as long as the shape defined as the second alignment mark 22 is appropriate. For example, semiconductor manufacturing equipment can set the arrangement of patterns for each layer to better ensure flatness.

[0078] (Third embodiment)

[0079] In the second embodiment, the alignment mark shape was formed using different patterns in multiple layers, but it is possible to further subdivide this. By subdividing, the semiconductor manufacturing equipment can define the alignment mark to be sufficiently larger than other wiring and dummy wiring, thereby improving the flatness in each semiconductor layer and suppressing distortion of the semiconductor device as a whole.

[0080] Figure 13 is a schematic top view showing an example of the generation of the alignment mark shape according to one embodiment. As shown in this figure, each of patterns 22a, 22b, and 22c may be formed by dummy patterns shown by diagonal lines. The pattern of the second alignment mark 22 may be defined by combining these patterns.

[0081] The second alignment mark 22 forms an alignment mark pattern, similar to the embodiment described above, but depending on the arrangement of the dummy pattern in each layer, there may be some gaps or parts that extend beyond the alignment mark pattern. Overall, it is sufficient that the pattern is defined within the range that can be used as an alignment mark.

[0082] The range that can be used as alignment marks can be appropriately set depending on the manufacturing environment, such as the performance of the measuring device (image sensor, etc.) in the semiconductor manufacturing equipment, the wavelength of light used for measurement in the measuring device, and the signal processing (image processing) algorithm for determining positioning coordinates.

[0083] Thus, the shape of the alignment marks may be defined by placing dummy patterns in at least two layers and overlapping these layers in a third direction.

[0084] By using dummy patterns, it becomes possible to make each dummy pattern the same size as metal wiring placed on the same layer, while also making the size of the alignment marks (e.g., the width of the pattern) created by the overlapping patterns significantly larger than that of the metal wiring. As a result, accurate positioning by semiconductor manufacturing equipment can be achieved with greater precision, and the flatness of the surface in each layer can be maintained with greater accuracy.

[0085] For example, the alignment marks defined by superposition can be approximately 2.5 to 10 times, and more preferably 3 to 7 times, the width of the wiring used in the semiconductor device 1. By using these ratios, it is possible to adequately ensure the sensing accuracy (visibility) of the alignment marks in the sensor while appropriately maintaining flatness by arranging the alignment marks.

[0086] The placement of dummy patterns in each layer may be determined by a rule-based method based on defined alignment marks, or by optimization, including methods using a trained model. Furthermore, dummy patterns may be placed in different positions in each layer, or they may be placed in the same position in two or more layers.

[0087] <4. Shape and placement of alignment marks>

[0088] The shape and placement of alignment marks will be described using several non-limiting embodiments. First, the placement of alignment marks on the substrate and the surrounding area will be described.

[0089] (Fourth Embodiment)

[0090] Figure 14 is a schematic diagram showing an example of the AA cross-section of Figure 6. If semiconductor device 1 is a solid-state imaging device as an example of a semiconductor device that is not limited, the circuit region 120 can be, for example, a region where effective pixels are provided, and the dummy region 122 can be a region where ineffective pixels are provided or a region where no effective pixels are provided.

[0091] In the circuit region 120, the semiconductor device 1 may include, for example, an optical system such as a lens (not shown), a photoelectric conversion region (not shown), and wiring 124. In the dummy region 122, the semiconductor device 1 includes, for example, dummy wiring 126. The dummy wiring 126 is formed of a metal or the like, arranged to maintain the flatness of the surface of the stacked semiconductor layers.

[0092] Patterns 22a, 22b, and 22c, which define the second alignment mark 22 by superposition, can be placed in a dummy region 122, as an example, but are not limited to this example. These patterns are placed in some layers of the stacked semiconductor layers, as an example, but may be formed in all layers where the wiring 124 and dummy wiring 126 are placed.

[0093] The pattern defining the alignment marks may be, for example, a metal (Cu, Al, W) film of the same material as wiring 124 and / or dummy wiring 126, or a metal film of a different material. Furthermore, this pattern may be a metal film other than the Cu, Al, and W examples given above.

[0094] Of course, as shown in Figure 15, the patterns in each layer may be arranged by a set of dummy patterns.

[0095] (Fifth embodiment)

[0096] Figure 16 is a schematic diagram showing an example of a cross-section of a substrate according to another example. The patterns in each layer may be located in the circuit region 120, not limited to the dummy region 122. In this case as well, the second alignment mark 22 can be defined by the superposition of patterns 22a, 22b, and 22c, for example.

[0097] Similar to the embodiments described above, in order to maintain flatness, patterns made of the same material as the wiring may be formed in at least two of the multiple semiconductor layers forming the second substrate 12, including the wiring.

[0098] Not limited to solid-state imaging devices, even in general semiconductor devices, patterns may be placed in each layer in areas where wiring etc. is arranged, or in areas where no wiring etc. is arranged but dummy wiring etc. is arranged, and the second alignment mark 22 may be defined by the superposition of multiple patterns.

[0099] (Sixth Embodiment)

[0100] Next, we will explain how to generate the shape of the alignment mark using a dummy pattern. As an example, we will explain the case where the second alignment mark 22 is rectangular, but we are not limited to this, and the same method can be applied to circular shapes, etc. As mentioned above, especially in the case of circular shapes, etc., that have boundaries other than straight lines, it is desirable to define the shape of the alignment mark accurately by superimposing, but we are not limited to this, and deviations, chips, etc. in the shape of the alignment mark may occur within an acceptable range (within a range in which alignment in substrate stacking can be properly achieved).

[0101] As shown in Figure 13, the dummy patterns may be arranged differently in each layer, but the shape of the alignment marks can also be defined in various other ways.

[0102] Figure 17 is a schematic diagram showing an example of the generation of alignment mark shapes according to one embodiment. The dashed lines indicate the pattern placement areas in each layer, the dotted lines indicate the areas where the second alignment mark 22 is formed, and the shaded areas indicate dummy patterns.

[0103] As shown in the figure, the second alignment mark 22 may be defined by using the same set of dummy patterns for each alignment mark shape, shifting these sets of dummy patterns in the first and second directions, and overlapping these shifted patterns.

[0104] (Seventh Embodiment)

[0105] Figure 18 schematically shows an example of the generation of alignment mark shapes according to one embodiment. As shown in this figure, the dummy patterns may be arranged according to a predetermined regularity. By arranging them in this way, it becomes possible to more clearly define the boundaries of the alignment marks defined as the second alignment marks 22.

[0106] In addition to the arrangement shown in the figure, the dummy patterns may also be arranged in a two-dimensional array with appropriate pitches in the first and second directions, or in a staggered grid pattern.

[0107] As shown in Figures 17 and 18, the size or shape of the dummy pattern may be the same in at least two layers. Using the same dummy pattern simplifies the optimization calculation of the placement of the dummy pattern in each layer relative to the alignment marks.

[0108] Without being limited to this, the size and shape of the dummy pattern may differ in at least two layers.

[0109] Furthermore, in at least two of the semiconductor layers on which the dummy patterns are placed, at least one pair of dummy patterns may be positioned in the same first and second directions. Alternatively, in at least two of the semiconductor layers on which the dummy patterns are placed, the dummy patterns may be positioned in different first and second directions.

[0110] Furthermore, one aspect of this disclosure does not preclude the placement of some or all dummy patterns in the same position and shape and size in at least two layers.

[0111] (Eighth embodiment)

[0112] In the embodiments described above, the dummy pattern was formed in a rectangular shape, but is not limited to this. The dummy pattern can be in various shapes that can be implemented in wiring formed in a typical semiconductor process.

[0113] Figure 19 shows some, not limited, examples of dummy patterns according to one embodiment. As shown in this figure, the dummy patterns may be, for example, rectangular (square, rectangle), polygonal (including regular polygons and concave polygons, concave polygons including L-shaped and cross-shaped), or circular (elliptical). The width of these dummy patterns may be greater than the width of the wiring pattern formed in the semiconductor layer.

[0114] The width of the dummy pattern may be equal to or less than the width of the wiring pattern. By making the dummy pattern larger than the wiring pattern, clearer alignment marks can be defined. On the other hand, by making the dummy pattern equal to or less than the wiring pattern, it becomes possible to maintain the flatness of the semiconductor layer using a metal film equivalent to that of the wiring.

[0115] The semiconductor device 1 may have any of the shapes of dummy patterns placed on each layer, and in each substrate, multiple layers may be used as needed, and alignment marks may be defined by the overlapping of various dummy patterns.

[0116] (Ninth Embodiment)

[0117] Figure 20 is a schematic top view showing the surrounding area where a dummy pattern is placed according to one embodiment. This figure shows, for example, an example where pattern 22a is placed in the dummy region 122. The explanation uses pattern 22a, but is not limited to this, and the same applies to the placement of dummy patterns in each semiconductor layer.

[0118] The dummy wiring 126 is placed in an appropriate amount within an appropriate range of the dummy region 122 in order to maintain the flatness of the semiconductor layer. As shown in the figure, the dummy wiring 126 may be placed in a form that does not extend to the range of pattern 22a. Note that the dummy wiring 126 and the dummy pattern within pattern 22a may have the same shape and size.

[0119] In this way, by not including dummy wiring other than the dummy pattern that defines the alignment mark within the area of ​​pattern 22a, the visibility of the alignment mark can be improved.

[0120] (Tenth embodiment)

[0121] On the other hand, as shown in Figure 21, which schematically illustrates the surrounding conditions where the dummy pattern is placed, this does not rule out the possibility that the dummy wiring 126 is not placed at all inside the region where pattern 22a is formed. By placing the dummy wiring 126 inside the region where the alignment marks are defined, the flatness of each semiconductor layer can be better maintained.

[0122] In this case, to avoid affecting the definition of alignment marks, it is desirable that, for example, in the region where alignment marks are placed, the semiconductor layers are arranged in such a way that they do not overlap when the semiconductor layers are stacked in the third direction, or that they do not form patterns that could become alignment marks.

[0123] Similarly, even when pattern 22a is located in an area other than dummy area 122, dummy wiring that does not constitute alignment marks may be provided in the area of ​​pattern 22a.

[0124] (11th embodiment)

[0125] Next, we will explain the placement of alignment marks within a chip using several non-limiting examples. This can be similarly extended to stacking chips and wafers, or wafers and wafers, etc.

[0126] For example, when stacking chips and wafers, alignment marks can be placed in the area of ​​the wafer to be cut out as a chip so that the chips can be properly stacked. For example, when stacking wafers, alignment marks can be placed in the area of ​​both wafers to be cut out as chips so that they can be properly stacked.

[0127] Furthermore, although we will use the second alignment mark 22 as an example, the same applies to the first alignment mark 20 as well.

[0128] Figure 22 shows an example of the arrangement of patterns within a chip according to one embodiment. The second alignment marks 22 may be placed, for example, at the four corners of the chip on the second substrate 12.

[0129] Figure 23 shows an example of the arrangement of patterns within a chip according to one embodiment. The second alignment marks 22 may be placed at multiple locations on the second substrate 12, including the four corners of the chip. In this case, they do not necessarily have to be placed at the four corners of the chip, and can be placed at appropriate locations based on the circuit layout, etc.

[0130] Figure 24 shows an example of the arrangement of patterns within a chip according to one embodiment. Multiple second alignment marks 22 may be arranged inside the circuit region 120. In this case, as shown in the figure, they can also be arranged outside the circuit region 120 (including the dummy region 122).

[0131] If the semiconductor device 1 is, for example, a solid-state imaging device, it is also possible to place the second alignment mark 22 in the effective pixel region, which is the circuit region 120. Of course, it is also possible to place the second alignment mark 22 in the invalid pixel region.

[0132] Multiple alignment marks can be placed within the chip in this manner. Increasing the number of marks improves the accuracy of both misalignment prediction and misalignment prevention. Therefore, more alignment marks are generally better, but their number and placement can be determined as appropriate based on layout constraints and other factors.

[0133] (12th embodiment)

[0134] Alignment marks are formed on both the first substrate 10 and the second substrate 12, and the shapes formed as these alignment marks will be described using several non-limiting examples. Figures 25 to 32 show examples of alignment marks according to one embodiment. These figures demonstrate that by superimposing the first alignment mark 20 shown on the left and the second alignment mark 22 to form the figure on the right, it is possible to suppress misalignment of the stacking layers. The first alignment mark 20 and the second alignment mark 22 can also be interchanged in their respective embodiments.

[0135] Figure 25 shows a configuration for measuring the displacement in the first and second directions separately. By aligning the boundaries of the rectangles, it is possible to align the horizontal direction in the upper diagram and the vertical direction in the lower diagram. As a result, by using these two patterns together, it is possible to align the object in both the first and second directions.

[0136] Figure 26 shows an example in which deviations in the first and second directions can be measured more accurately using one alignment mark each. As shown in this example, one may be a surrounding bar, and the other may be formed by a rectangle or bars.

[0137] In addition, any combination that allows for appropriate position adjustment can be used, such as the windmill shape shown in Figure 27, the cross shape shown in Figure 28, the circle shape shown in Figure 29, the clover shape shown in Figure 30, the box shape shown in Figure 31, or the rice grain shape (asterisk shape) shown in Figure 32.

[0138] By defining these patterns as alignment marks, it becomes possible to prevent and suppress misalignment during lamination in the first and second directions.

[0139] Alignment marks can be formed in each semiconductor layer in the same way as wiring. For example, they can be manufactured using a process similar to that of general wiring formation methods, such as forming an insulating film on the upper surface of a substrate, forming a resist in a selective region on the upper surface of the insulating film, forming trenches in a selective region where a pattern (including dummy patterns) for forming alignment marks together with wiring is to be formed, forming a metallic material in these trenches, and etching the upper surface.

[0140] The semiconductor manufacturing apparatus can form alignment marks on the first substrate 10 and the second substrate 12, as well as on other stacked layers, by overlapping the semiconductor layers, and can use these formed alignment marks to position the semiconductors in the first and second directions.

[0141] The semiconductor device 1 can be configured as a device in which multiple semiconductor substrates are stacked by stacking them using alignment marks according to the above-described embodiment or a combination of embodiments. Furthermore, the semiconductor manufacturing apparatus can appropriately achieve positioning in the first and second directions using these alignment marks.

[0142] The embodiments of this disclosure can be applied to the manufacture of various semiconductor devices, including various solid-state imaging devices and display devices, as well as semiconductor devices themselves.

[0143] The embodiments described above may also take the following forms.

[0144] (1) A semiconductor device formed by stacking at least a first substrate and a second substrate, wherein the arrangement of the first substrate and the second substrate in a first direction and a second direction intersecting the first direction is defined by alignment marks, and the substrates are stacked in a third direction intersecting the first direction and the second direction, and at least the second substrate is formed by stacking a plurality of layers, and the alignment marks are formed by stacking at least two of the plurality of layers.

[0145] (2) The semiconductor device according to (1), wherein the first substrate has a first alignment mark, the second substrate has a second alignment mark, the shape of the first alignment mark and the shape of the second alignment mark define at least the positions in the first and second directions for stacking the first and second substrates, and the shape of the second alignment mark is formed by superimposing patterns arranged on each of the at least two layers stacked on the second substrate in the third direction.

[0146] (3) The semiconductor device according to (2), wherein the first alignment mark and the second alignment mark are each located at one or more different locations in the plane formed by the first direction and the second direction on the first substrate and the second substrate, respectively.

[0147] (4) The semiconductor device according to (2) or (3), wherein the second alignment marks are arranged in the same shape and position in each of the at least two layers.

[0148] (5) The semiconductor device according to (2) or (3), wherein the second alignment marks have shapes that are arranged in at least different shapes or positions in each of the at least two layers.

[0149] (6) The semiconductor device according to any one of (2) to (5), wherein the second alignment mark is defined by a metal arranged in the at least two layers.

[0150] (7) The semiconductor device according to any one of (2) to (6), wherein at least two layers have dummy patterns in areas where the second alignment marks are not defined.

[0151] (8) The semiconductor device according to any one of (2) to (7), wherein the first substrate is formed by stacking a plurality of layers, and the shape of the first alignment mark is formed by superimposing patterns arranged on each of at least two layers stacked on the first substrate in the third direction.

[0152] (9) The semiconductor device according to (2), wherein each of the at least two layers comprises a dummy pattern, and the shape of the second alignment mark is defined by superimposing the dummy patterns located in each of the at least two layers in the third direction.

[0153] (10) The semiconductor device according to (9), wherein the first substrate is formed by stacking a plurality of layers, and the shape of the first alignment mark is defined by superimposing dummy patterns located on each of the at least two layers stacked on the first substrate in the third direction.

[0154] (11) The semiconductor device according to (9) or (10), wherein the shape formed by the superposition of the dummy patterns is a circular pattern.

[0155] (12) The semiconductor device according to any one of (9) to (11), wherein the shape formed by the superposition of the dummy patterns is a rectangular pattern.

[0156] (13) The semiconductor device according to any one of (9) to (12), wherein the size or shape of the dummy pattern is the same in at least two layers.

[0157] (14) The semiconductor device according to any one of (9) to (12), wherein the size or shape of the dummy pattern differs in at least two layers.

[0158] (15) The semiconductor device according to any one of (9) to (14), wherein the size of the dummy pattern is greater than the size of the pattern of metal wiring arranged in the at least two layers.

[0159] (16) The semiconductor device according to any one of (9) to (15), wherein at least a portion of the dummy pattern is arranged in the same position in two or more layers of the at least two layers.

[0160] (17) The semiconductor device according to any one of (9) to (15), wherein the dummy pattern is located in different positions in at least a portion of two or more layers of the at least two layers.

[0161] (18) A method for manufacturing a semiconductor device, comprising stacking at least a first substrate and a second substrate, wherein the second substrate is generated by stacking a plurality of semiconductor layers and forming alignment marks by overlapping patterns formed in at least two of the plurality of semiconductor layers, and the first substrate and the second substrate are stacked in a third direction intersecting the first and second directions, with their arrangement in a first direction and a second direction intersecting the first direction defined by the alignment marks.

[0162] (19) A semiconductor device comprising multiple semiconductor substrates stacked using alignment marks described in any of (1) to (18).

[0163] (20) A method for manufacturing a semiconductor device, comprising stacking multiple semiconductor substrates using alignment marks described in any of (1) to (18).

[0164] The aspects of this disclosure are not limited to the embodiments described above, but include various conceivable variations, and the effects of this disclosure are not limited to those described above. The components in each embodiment may be appropriately combined and applied. That is, various additions, modifications, and partial deletions are possible, as long as they do not deviate from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0165] 1: Semiconductor device, 10: First substrate, 100: Pixel area, 102: Dummy area, 20: First alignment mark, 12: Second substrate, 120: Circuit area, 122: Dummy area, 124: Wiring, 126: Dummy wiring, 22: Second alignment mark, 22a, 22b, 22c: Pattern

Claims

1. A semiconductor device formed by stacking at least a first substrate and a second substrate, wherein the first substrate and the second substrate are stacked in a third direction intersecting the first direction, with their arrangement defined in a first direction and a second direction intersecting the first direction by alignment marks, and at least the second substrate is formed by stacking a plurality of layers, and the alignment marks are formed by stacking at least two of the plurality of layers.

2. The semiconductor device according to claim 1, wherein the first substrate is provided with a first alignment mark, the second substrate is provided with a second alignment mark, the shape of the first alignment mark and the shape of the second alignment mark define at least the positions in the first and second directions for stacking the first and second substrates, and the shape of the second alignment mark is formed by superimposing patterns arranged on each of the at least two layers stacked on the second substrate in the third direction.

3. The semiconductor device according to claim 2, wherein the first alignment mark and the second alignment mark are each located at one or at least more different locations in the plane formed by the first direction and the second direction on the first substrate and the second substrate, respectively.

4. The semiconductor device according to claim 2, wherein the second alignment marks are arranged in the same shape and position in each of the at least two layers.

5. The semiconductor device according to claim 2, wherein the second alignment marks have shapes that are arranged in at least different shapes or positions in each of the at least two layers.

6. The semiconductor device according to claim 2, wherein the second alignment mark is defined by a metal arranged in the at least two layers.

7. The semiconductor device according to claim 2, wherein at least two layers have dummy patterns arranged in areas where the second alignment marks are not defined.

8. The semiconductor device according to claim 2, wherein the first substrate is formed by stacking a plurality of layers, and the shape of the first alignment mark is formed by superimposing patterns disposed on each of at least two layers stacked on the first substrate in the third direction.

9. The semiconductor device according to claim 2, wherein each of the at least two layers comprises a dummy pattern, and the shape of the second alignment mark is defined by superimposing the dummy patterns, which are located in each of the at least two layers, in the third direction.

10. The semiconductor device according to claim 9, wherein the first substrate is formed by stacking a plurality of layers, and the shape of the first alignment mark is defined by superimposing dummy patterns disposed on each of the at least two layers stacked on the first substrate in the third direction.

11. The semiconductor device according to claim 9, wherein the shape formed by the superposition of the dummy patterns is a circular pattern.

12. The semiconductor device according to claim 9, wherein the shape formed by the superposition of the dummy patterns is a rectangular pattern.

13. The semiconductor device according to claim 9, wherein the size or shape of the dummy pattern is the same in at least two layers.

14. The semiconductor device according to claim 9, wherein the size or shape of the dummy pattern differs in at least two layers.

15. The semiconductor device according to claim 9, wherein the size of the dummy pattern is larger than the size of the pattern of metal wiring arranged in the at least two layers.

16. The semiconductor device according to claim 9, wherein at least a portion of the dummy pattern is arranged in the same position in two or more layers of the at least two layers.

17. The semiconductor device according to claim 9, wherein at least a portion of the dummy pattern is arranged in different positions in two or more layers of the at least two layers.

18. A method for manufacturing a semiconductor device, comprising stacking at least a first substrate and a second substrate, wherein the second substrate is generated by stacking a plurality of semiconductor layers and forming alignment marks by overlapping patterns formed in at least two of the plurality of semiconductor layers, and the first substrate and the second substrate are stacked in a third direction intersecting the first and second directions, with their arrangement in a first direction and a second direction intersecting the first direction defined by the alignment marks.

19. A semiconductor device comprising a plurality of semiconductor substrates stacked using the alignment marks described in claim 1.

20. A method for manufacturing a semiconductor device, comprising stacking a plurality of semiconductor substrates using the alignment marks described in claim 1.

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