Semiconductor device and manufacturing method therefor
By forming an electron trapping layer at the interface between the inner liner and the capacitor dielectric layer, interface electrons are trapped, solving the built-in electric field problem caused by the movement of interface electrons in ferroelectric memory, and improving the reliability and storage performance of the device.
WO2026103569A1PCT designated stage Publication Date: 2026-05-21WUXI CHINA RESOURCES MICROELECTRONICS
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Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- WUXI CHINA RESOURCES MICROELECTRONICS
- Filing Date
- 2025-11-04
- Publication Date
- 2026-05-21
AI Technical Summary
Technical Problem
In ferroelectric memories, the built-in electric field formed by the movement of electrons at the interface causes the coercive field of the ferroelectric dielectric to shift, resulting in an imprinting effect that affects the reliability of the device.
Method used
An electron trapping layer is formed at the interface between the inner liner and the capacitor dielectric layer. First and second electron trapping layers are formed by injecting metal ions to trap interface electrons and eliminate the built-in electric field formed by the movement of interface electrons.
Benefits of technology
It effectively reduces the imprinting effect and improves the reliability and storage performance of semiconductor devices.
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Smart Images
Figure CN2025132320_21052026_PF_FP_ABST
Abstract
Disclosed in the present application are a semiconductor device and a manufacturing method therefor. The manufacturing method comprises: forming a first electrode layer; forming a first liner layer on the first electrode layer; forming a capacitor dielectric layer on the first liner layer; forming a second liner layer on the capacitor dielectric layer; and forming a second electrode layer on the second liner layer, wherein a first electron capture layer is formed in a top region of the first liner layer, and a second electron capture layer is formed in a bottom region of the second liner layer, so as to capture interface electrons at an interface between the first liner layer and the capacitor dielectric layer and interface electrons at an interface between the second liner layer and the capacitor dielectric layer.
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