Device and method for protecting an integrated circuit from an EMI-induced overvoltage

Abstract

The invention relates to a device and a method for protecting an integrated circuit from an EMI-induced overvoltage.

Description

[0001] R. 409465

[0002] - 1 -

[0003] Description

[0004] title

[0005] Device and method for protecting an integrated circuit against an EMI-induced overvoltage

[0006] The invention relates to a device and a method for protecting an integrated circuit from an EMI-induced overvoltage.

[0007] State of the art

[0008] Protecting modern integrated circuits (ICs), especially in the low-voltage range (< 5V), from electrostatic discharge (ESD) presents a significant challenge. Conventional voltage-controlled ESD protection devices reach their limits due to various factors.

[0009] Advanced IC technologies are characterized by increasingly smaller safety margins between the maximum operating voltage and the breakdown voltage of the components to be protected. This complicates the use of voltage-controlled ESD protection mechanisms, as these must be very large to limit their voltage drop to values ​​below the breakdown voltage of the components being protected in the event of an ESD event, while simultaneously preventing them from triggering during operation and thus not impairing the function of the circuit components being protected. R. 409465

[0010] - 2 -

[0011] In some modern IC technologies, pn junctions with suitable breakdown voltages for ESD protection are not available.

[0012] PN junctions with low breakdown voltages exhibit greatly increased leakage currents due to tunneling effects, which can lead to increased power consumption and impairment of circuit function.

[0013] As an alternative to voltage-controlled ESD protection devices, dynamic, so-called slew-rate (dV / dt) triggered ESD cells have become established. These utilize the high rate of voltage rise during an ESD event to activate the protection mechanism. An example of such a dV / dt-triggered ESD cell is the widely used Merrill circuit (see Figure 1), which is most often used to protect power supply lines.

[0014] The Merrill circuit consists of an NMOS discharge transistor (MNO) that diverts the ESD current from the input (PAD_ESD) to the reference voltage (REF_ESD). MNO is controlled by an inverter (MP1 / MN1), which in turn is driven by an RC filter (R0, CO). The Miller capacitance of MNO, in combination with the RC filter, forms the slew rate trigger of the ESD cell. During an ESD event, the high slew rate of the voltage at the input (PAD_ESD) causes MNO to turn on. Under normal operating conditions, MNO remains off.

[0015] In this process, a leakage transistor (MNO) is controlled via an inverter (MP1 / MN1), which in turn is controlled by an RC filter (R0, CO).

[0016] Before an ESD event, the circuit is unpowered. CO is discharged and MNO is switched off. R. 409465

[0017] - 3 -

[0018] An ESD event at PAD_ESD leads to a voltage increase between PAD_ESD and REF_ESD. Since CO is initially discharged, the input signal at the inverter is "low" and its output, supported by the Miller capacitance of MNO, quickly switches to "high", thereby turning on MNO and diverting the ESD current to the REF_ESD terminal.

[0019] During the ESD event, the Merrill circuit is powered by the voltage drop across the transistor MNO.

[0020] The time constant of the RC filter (RO, CO) is dimensioned such that the capacitor is not yet charged, the input signal at the inverter is not yet "high", its output signal is not yet "low", and the transistor MNO is not yet switched off before the ESD current has decayed.

[0021] The Merrill circuit uses an RC filter-controlled inverter to switch the NMOS (MNO). While the integrated shutdown function via the inverter is advantageous, it requires a large RC filter (> 1 ps) to dissipate all the ESD current before it activates. Furthermore, the Merrill circuit suffers from a limited tripping speed. Specifically, this means that the gate of MNO cannot be charged quickly enough by the inverter and RC filter to dissipate very fast ESD pulses with minimal rise time. In such cases, a transient overvoltage between PAD_ESD and REF_ESD can occur, potentially damaging the circuit being protected. Another disadvantage of the Merrill circuit is the lack of a static trip that activates upon exceeding a certain overvoltage threshold, which can be important for protection against EMC-induced overvoltages during normal operation. R. 409465

[0022] - 4 -

[0023] An alternative dV / dt-triggered ESD cell uses a PMOS (MPO) to control MNO (see Figure 2). This circuit can operate with a smaller RC filter than the Merrill circuit. However, this circuit can also be falsely triggered by signals during normal operation if their voltage rise and slew rate are sufficiently high. Another problem is the potential deactivation of the ESD cell by capacitively coupled overvoltages in the CTRL_ESD control signal.

[0024] Unlike the Merrill circuit, here a PMOS transistor (MPO) controls the NMOS transistor (MNO). This circuit also uses an RC filter (RO, CO) to detect the rapid voltage change during an ESD event.

[0025] Before an ESD event, the circuit is without power. CO is discharged, MPO and MNO are switched off.

[0026] An ESD event at PAD_ESD leads to a voltage increase between PAD_ESD and REF_ESD. This voltage increase causes the voltage between PAD_ESD and REF_ESD to rise faster than CO charges via RO. This increases the voltage between the source and gate of MPO, causing MPO to turn on and, assisted by MNO's Miller capacitance, charge its gate. With its gate charged, MNO turns on and discharges the ESD current to REF_PAD.

[0027] As with the Merrill circuit, the ESD cell is powered during the ESD event by the voltage drop across transistor MNO. R. 409465

[0028] - 5 -

[0029] Compared to the Merrill circuit, the time constant of the RC filter (R0, CO) is significantly shorter, so the capacitor is already charged and the transistor MPO is switched off before the ESD current has dissipated. However, since the gate of MNO is still charged and only discharges slowly through resistor R1, MNO remains switched on until the ESD current has completely dissipated.

[0030] Despite these advantages, the circuit shown in Figure 2 still has disadvantages. For example, it is susceptible to false triggering due to rapid voltage changes during normal operation. Rapid signal changes that exceed the threshold voltage of MNO and MPO and exhibit a similarly high rise time to an ESD event can falsely activate the ESD cell.

[0031] To address this problem, some circuits use an additional NMOS transistor (MN1) that can short-circuit the gate of MNO, thus disabling MNO. MN1 is controlled by an external control signal (CTRL_ESD). However, this solution leads to increased complexity and an additional control signal. Furthermore, the limited tripping speed of the circuit, similar to the Merrill circuit, can lead to a transient overvoltage and damage to the protected circuit during very fast ESD pulses. Another problem is the potential capacitive coupling of the ESD-induced overvoltage into the CTRL_ESD control signal. This can cause MN1 to be erroneously switched on during an ESD event, disabling the ESD cell and preventing it from dissipating the ESD current, potentially damaging it. R. 409465

[0032] - 6 -

[0033] The ESD cell shown in Figure 3 attempts to solve the problem of capacitive coupling. Here, the gate of MN1 is decoupled from the external control signal CTRL_ESD via a resistor (R2) to reduce its susceptibility to capacitive coupling. Additionally, another transistor (MN2) is introduced, which shorts the gate of MN1 to REF_ESD in the event of an ESD event. MN2 is controlled by the gate voltage of MNO. This is intended to prevent MN1 from being activated during an ESD event and thus impairing the function of the ESD cell.

[0034] The examples described show that known dV / dt-triggered ESD protection circuits have various disadvantages, including:

[0035] • Incorrect shutdown during an ESD event: Some ESD protection circuits can be incorrectly deactivated during an ESD event, for example, due to capacitive coupling of overvoltages into control signals. This can lead to a loss of protection and damage the circuit.

[0036] • Limited tripping speed: Many circuits do not react quickly enough to very fast ESD pulses. The resulting transient voltage spikes can damage the components being protected.

[0037] • False triggering during normal operation: dV / dt-triggered ESD cells can be falsely triggered by rapid signal changes during normal operation, which can lead to unwanted power consumption and malfunctions. R. 409465

[0038] - 7 -

[0039] • Large RC filters: Some circuits require large RC filters to cover the entire ESD event. This increases the circuit's footprint.

[0040] • Complexity due to control connections: The use of control connections to disable the primary dynamic trigger increases the complexity of the circuit and requires additional control signals.

[0041] • Lack of EMI protection: Many modern ESD protection devices lack a static trigger mechanism that protects the circuit to be protected from EMI-induced overvoltages during normal operation when a certain overvoltage is exceeded.

[0042] In summary, there is a need for an ESD protection solution that is simultaneously fast, robust, reliable, and easy to integrate. It should protect against both ESD events and overvoltages during normal operation without impairing the functionality of the circuit. The present invention addresses these challenges and provides an improved ESD cell with the desired properties.

[0043] Document US 11 557895 B2 (Taiwan Semiconductor MFG Co. Ltd.) describes an ESD power clamping device (100). This includes an ESD detection circuit, a control circuit coupled to the ESD detection circuit, a field-effect transistor (FET) coupled to the control circuit, and an impedance element coupled to the FET. The FET includes a drain terminal connected to a first resistor. 409465

[0044] - 8 -

[0045] The supply node is coupled, as is a gate terminal coupled to the control circuit, a source terminal coupled to a second supply node via the impedance element, and a bulk terminal coupled to the second supply node.

[0046] German patent DE 102004041 831 A1 (Samsung Electronics Co. Ltd.) describes an integrated circuit device with an electrostatic discharge (ESD) protection cell for input / output (I / O) devices. The integrated circuit device includes an I / O ESD protection cell containing a voltage drop detection (VDD) ESD protection element inserted between an I / O contact point and a VDD line, a ground voltage (VSS) ESD protection element inserted between the I / O contact point and the VSS line, and a power limiting element inserted between the VDD line and the VSS line. The VDD ESD protection element, the power limiting element, and the VSS ESD protection element are arranged within the I / O ESD protection cell in such a way that they can be connected in a straight line or are arranged so that they partially overlap.

[0047] US 10026712 B2 (Texas Instruments Inc.) describes a protection circuit against electrostatic discharge (ESD). The protection circuit comprises a substrate with a semiconductor surface on which the ESD protection circuitry is implemented. A first ESD cell is connected in series with at least one second ESD cell. An active shunt transistor is connected electrically in parallel with either the first or the second ESD cell. The active shunt transistor includes a control node. A trigger circuit has a trigger input and a trigger output. The trigger output is coupled to the control node. R. 409465

[0048] - 9 -

[0049] Disclosure of the invention

[0050] The present invention offers decisive advantages over known ESD protection solutions.

[0051] The invention prevents the ESD cell from being switched off incorrectly during an ESD event, thus ensuring reliable protection even in the case of strong and fast ESD impulses.

[0052] The ESD cell reacts extremely quickly to ESD events, thus minimizing transient voltage spikes that could lead to damage to the protected components.

[0053] Under normal operating conditions, the ESD cell is not triggered by rapid signal changes, thus ensuring trouble-free operation of the circuit. The invention requires only a small RC filter, which reduces the area required on the chip and lowers integration costs.

[0054] The ESD cell features an integrated shutdown function, eliminating the need for a separate control terminal to deactivate the dynamic trigger. This simplifies the circuitry and reduces the number of external signals required.

[0055] The invention enables the simple integration of additional static triggers to protect the circuit from EMI-induced overvoltages during normal operation when a certain overvoltage threshold is exceeded. These static triggers do not affect the function of the primary dynamic ESD trigger.

[0056] Description R. 409465

[0057] - 10 -

[0058] Figure 4 shows an embodiment of the ESD cell according to the invention.

[0059] Resistor R2 and transistor MN2 form a protection circuit that prevents the ESD cell from being switched off incorrectly during an ESD event. Specifically, R2 and MN2 disable a potential shutdown signal at the gate of MN1, the shutdown transistor for the discharge transistor MNO. This ensures that MNO remains conductive throughout the entire ESD event and reliably dissipates the ESD current.

[0060] The capacitor at MPO increases the effective Miller capacitance of MNO. This allows for faster charging of the MNO gate and thus significantly faster triggering of the ESD cell. Transient voltage spikes that can occur during fast ESD pulses are thereby minimized.

[0061] MN1 is controlled via inverters MP3 / MN3 and MP4 / MN4, as well as the RC filter R0 / C0. The dimensions of MP4 and MN4 result in a high switching threshold for inverter MP4 / MN4. This necessitates a significant voltage rise between PAD_ESD and REF_ESD to switch off MN1 and switch on MNO. Under normal operating conditions, typical signal changes will not exceed this switching threshold, thus preventing false tripping.

[0062] Only a small RC filter (R0 / C0) is required. This is made possible by several factors: the decoupling of the gate of MN1 from the RC filter via R2, the inverters MP3 / MN3 and MP4 / MN4, the switching off of the gate of MN1 by MN2 during an ESD event, and the slow discharge of the gate of MNO via R1. The RC filter primarily serves to trigger the ESD cell, while the duration of the on-state is determined by the gate capacitance of MNO and R1.

[0063] By connecting R2 to the RC filter R0 / C0 via the inverters MP3 / MN3 and MP4 / MN4, an integrated shutdown function is implemented. This is R. 409465

[0064] - 11 -

[0065] The RC filter signal serves as a shutdown signal, thus eliminating the need for a separate control connection.

[0066] The circuit can optionally be extended with an additional trigger, coupled via an additional PMOS (e.g., MP10) and an additional NMOS (e.g., MN10). This additional trigger, activated upon exceeding a specific overvoltage, can intercept EMI-induced overvoltages without affecting the function of the primary dynamic (dV / dt) ESD trigger. The additional trigger can only switch the ESD cell on, not off.

[0067] The functionality with possible alternatives is as follows.

[0068] Initial state (before ESD event): All nets are discharged to 0V. MNO is switched off. A positive ESD pulse at PAD_ESD leads to a rapid voltage rise between PAD_ESD and REF_ESD. The capacitor at MPO couples this voltage rise directly to the gate of MNO. This causes MNO to switch on quickly and dissipates ESD current early. Simultaneously, CO begins to rise across R0.

[0069] to charge slowly. The "rc" signal initially remains low, which means

[0070] MP1 remains switched on and contributes to the gate bias of MNO. Inverter output "out4" goes high and "out3" goes low, so MN1 remains switched off and does not switch off the switched-on MNO. When the voltage of "rc" reaches the threshold voltages of MP1 and the inverter MP4 / MN4, MP1 switches off. "out4" goes low and "out3" goes high. As long as the gate voltage of MNO

[0071] However, if the threshold voltage of MN2 is exceeded, MN2 remains switched on and MN1 remains switched off. Thus, MNO remains conductive.

[0072] MNO and MN2 are only switched off when the gate of MNO is discharged through R1 to such an extent that the voltage is below its R. 409465

[0073] - 12 -

[0074] Threshold voltages drop. R1 is dimensioned so that this only happens after the ESD event has subsided.

[0075] The state of the static trigger (MP10, MN10) is during a

[0076] ESD event irrelevant. When switched on, MP10 and MN10 support the activation of MNO. When switched off, they have no influence on the function of the ESD cell during the ESD event.

[0077] Instead of MP10 and MN10, other measures can also be used for coupling an additional trigger, as long as they do not impair the function of the dynamic dV / dt trigger.

[0078] Normal operation (after application of the supply voltage): In normal operation, the circuit according to the invention reliably prevents false tripping and simultaneously offers optional EMI protection. PAD_ESD is at its operating voltage (vs. REF_ESD). CO and the signal "rc" are charged to the operating voltage. MP1 is off. "out4" is low, "out3" is high. Since there are no dynamic effects (as in the case of an ESD event), the gate of MNO is completely discharged via R1. Thus, both MNO and MN2 are off. Since the operating voltage is lower than the breakdown voltage of the Zener diode DO and the current mirror transistor MP12, no current flows through DO, MP12, and MP11. The gate of MN11 is discharged via R4, which switches off MN11 and MN10. At the same time, the gate of MP10 is discharged via R3, which also switches off MP10. Since both MN2 and MN10 are switched off, the gate of MN1 is biased via "out3" and R2.MN1 is thus switched on and actively keeps MNO switched off. To switch MNO on during normal operation without a static trigger, a significant voltage jump and a high slew rate at PAD_ESD are required. Only then can MP1 be switched on and enough current injected into the drain of MN1 to switch on MN2 and switch off MN1. Typical R. 409465.

[0079] - 13 -

[0080] Signal changes during normal operation are not sufficient for this, thus preventing false triggers.

[0081] The circuit with DO, MP12, MP11, MN10, MN11 , MP10, R3 and R4 represents only one example of an additional voltage-controlled trigger.

[0082] Alternative circuits based on different principles (e.g., current-controlled triggers) are also conceivable.

[0083] The switching threshold for the activation of MNO can be adapted to the specific requirements of the application by adjusting the dimensions of MP4, MN4, MN2 and R2.

[0084] Normal operation with EMI overvoltage and activated voltage-controlled trigger (OFF = 0V): The circuit is in normal operation. Additionally, the "OFF" terminal of the voltage-controlled trigger is at 0V, thus switching off MN12. If an EMI-induced overvoltage occurs between PAD_ESD and REF_ESD that exceeds the sum of the breakdown voltage of DO and the threshold voltage of MP12, a current flows through DO and MP12. This current is amplified by the MP12 / MP11 current mirror and switches on MP11. The amplified current through MP11 is significantly larger than the current through R4 and charges the "zd" network. This switches on both MN11 and MN10. MN10 discharges the gate of MN1, thus switching MN1 off. MN11, in conjunction with R3, acts as an inverter, simultaneously driving the gate of MP10 and switching MP10 on.MP10 charges the gate of MNO and switches MNO on, thereby dissipating the EMI-induced overvoltage.

[0085] The circuit described here, using a Zener diode and current mirror, is just one example. Other circuits based on different principles can also be used. It is important that the additional trigger does not impair the circuit's function during normal operation or ESD events. R. 409465

[0086] - 14 -

[0087] The trigger voltage of the voltage-controlled trigger can be adjusted by selecting the Zener diode DO. It is important to emphasize that the voltage-controlled trigger does not affect the dynamic trigger. In the event of an ESD event, the dynamic trigger is activated as described in Case 1 and dissipates the ESD current, regardless of the state of the voltage-controlled trigger.

[0088] Initial state (normal operation with voltage-controlled trigger disabled): The circuit is in normal operation. The "OFF" terminal of the voltage-controlled trigger is biased with a voltage > 2V, which turns on MN12. MN12 is rated higher than MP11. This allows MN12 to bias the gate of MN11 independently of any potential breakdown current across DO and MP12 that could be caused by an EMI-induced overvoltage. Consequently, MN11 and MN10 are switched off. The gate of MP10 is discharged through R3, which also turns MP10 off. The voltage-controlled trigger is thus disabled. If an EMI-induced overvoltage occurs, the voltage-controlled trigger will not activate because MN12 prevents the drive signal from being sent to MN11, and therefore also to MN10 and MP10. The "OFF" switch is used to deactivate the voltage-controlled trigger during certain tests, such as...an accelerated gate oxide screening test at increased supply voltages. This prevents potential interference with the test results due to the voltage-controlled trigger.

Claims

R. 409465 - 15 - Claims 1. ESD protection circuit, including: • an input (PAD_ESD) for receiving an ESD event; • an output (REF_ESD) for discharging the ESD current; • a leakage transistor (MNO) to conduct the ESD current from the input to the output; • a first branch comprising a capacitor (MPO) connected in parallel to the gate and drain of the leakage transistor (MNO) to increase the Miller capacitance of the leakage transistor and improve the tripping speed of the ESD protection circuit; • a second branch, encompassing: o an RC filter (R0, CO) to detect a rapid voltage change at the input; o a transistor (MP1) connected in parallel to the gate and drain of the leakage transistor (MNO) to charge the gate of the leakage transistor and turn on the leakage transistor; • encompassing a third branch: a first inverter (MP4, MN4), wherein the first inverter is dimensioned such that its switching threshold is greater than half the operating voltage in order to prevent false tripping during normal operation impede; R. 409465 - 16 - o a second inverter (MP3, MN3); o a shutdown transistor (MN1) that can control the leakage transistor (MNO); • a fourth branch comprising a transistor (MN2) connected to the gate of the shutdown transistor (MN1) to deactivate the shutdown transistor (MN1) during an ES D event; and • a resistor (R1) to discharge the gate of the leakage transistor (MNO).

2. ESD protection circuit according to claim 1, comprising: • a voltage-controlled trigger comprising a PMOS transistor (MP10) and an NMOS transistor (MN10) to activate the ESD protection circuit in the event of an EMI-induced overvoltage; • where the voltage-controlled trigger can only switch the ESD protection circuit on, but not off.

3. ESD protection circuit according to claim 2, comprising: • a shutdown terminal ("OFF") to deactivate the voltage-controlled trigger.

4. ESD protection circuit according to one of the preceding claims, characterized in that the third branch comprises a resistor (R2) which connects the gate of the shutdown transistor (MN1) to the output of the second inverter (MP3, MN3) to provide an integrated shutdown function.

5. ESD protection circuit according to claim 2 or 3, characterized in that the voltage-controlled trigger comprises a Zener diode (DO) and a current mirror (MP11, MP12) to respond to an overvoltage. R. 409465 - 17 - 6. ESD protection circuit according to one of the preceding claims, characterized in that the resistor R1 is dimensioned such that the gate of the leakage transistor is discharged after the ESD event has subsided.

7. Integrated circuit comprising an ESD protection circuit according to any of the preceding claims.

8. Method for protecting an integrated circuit against an ESD event, comprising at least the following steps: • Detecting a rapid voltage change between an input (PAD_ESD) and an output (REF_ESD) of the ESD protection circuit; • Coupling the voltage change to the gate of a leakage transistor (MNO) via a capacitor (MPO) and a transistor (MP1); • Switching on the leakage transistor (MNO) to drain an ESD current from the input to the output; • Maintaining the on-state of the leakage transistor (MNO) by a second transistor (MN2), which is activated when the gate voltage of MNO exceeds a threshold voltage; and • Discharging the gate of the leakage transistor (MNO) via a resistor (R1) to switch off the leakage transistor (MNO) after the ESD event has subsided.

9. The method of claim 8, comprising: • Controlling a first transistor (MN1) to deactivate the leakage transistor (MNO) via an inverter (MP4, MN4), wherein the inverter (MP4, MN4) has a switching threshold greater than half the operating voltage to prevent spurious tripping during normal operation.

10. Method for protecting an integrated circuit against an EMI-induced overvoltage comprising at least the following steps: R. 409465 - 18 - • Detection of an overvoltage between an input (PAD_ESD) and an output (REF_ESD) using a voltage-controlled trigger; • Activation of a PMOS transistor (MP10) and an NMOS transistor (MN10) by the voltage-controlled trigger; • Biasing the gate of a leakage transistor (MNO) by the PMOS transistor (MP10) to turn on the leakage transistor (MNO); and • Discharge of the overvoltage via the switched-on discharge transistor (MNO).

11. The method of claim 10, comprising: • Deactivating the voltage-controlled trigger by applying a voltage to a shutdown terminal ("OFF").

Images