Trimming configuration

Abstract

Herein is provided a semiconductor device (100), comprising a resonating element (110) having a top electrode layer (103), a dielectric layer (102) on top of the top electrode layer (103), and a trimming layer on top of the dielectric layer (102), wherein the top electrode layer (103) and the trimming layer are electrically connected via contact hole(s) (112). Herein is further provided a packaged semiconductor apparatus, comprising at least one semiconductor device (100) and a method for trimming a semiconductor device (100).

Description

[0001] TRIMMING CONFIGURATION

[0002] TECHNICAL FIELD

[0003] The present disclosure generally relates to the field of semiconductors. The disclosure relates particularly, though not exclusively, to trimming of semiconductor devices.

[0004] BACKGROUND

[0005] This section illustrates useful background information without admission of any technique described herein representative of the state of the art.

[0006] Semiconductor devices typically require trimming in order to adjust and correct their resonance frequency. Typically, trimming is performed by removing parts of the top electrode of the device. The characteristics of the device may be negatively impacted by the trimming process.

[0007] Ageing of materials implies changes of the original state of the materials. These changes can be, for instance, changes in material properties. In case the materials experiencing ageing changes are used in the context of semiconductors, the changes of material properties due to ageing may lead to changes in the semiconductor properties.

[0008] SUMMARY

[0009] The appended claims define the scope of protection. Any examples and technical descriptions of apparatuses, products and / or methods in the description and / or drawings not covered by the claims are presented not as embodiments of the invention but as background art or examples useful for understanding the invention. It is an object of certain embodiments of the present disclosure to provide a scheme to solve at least one of the problems related to the prior art, or at least to provide an alternative to existing technology. Accordingly, certain disclosed embodiments provide for an ingenious semiconductor device solving at least one of the problems related to the prior art.

[0010] According to a first example aspect of the present disclosure there is provided a semiconductor device, comprising a resonating element having a top electrode layer, a dielectric layer on top of the top electrode layer, and a trimming layer on top of the dielectric layer, wherein the top electrode layer and the trimming layer are electrically connected via contact hole(s).

[0011] In certain embodiments, the top electrode layer and the trimming layer are electrically connected via contact holes. In certain embodiments, the top electrode layer and the trimming layer are electrically connected via a contact hole or a plurality of contact holes. In certain embodiments, the top electrode (layer) is implemented by a layer of metal. In certain embodiments, the top electrode comprises (is of) metal. In certain embodiments, the top electrode is of gold, doped gold, or gold alloy. In certain embodiments, the top electrode (layer) is implemented by a layer of doped silicon, such as doped polysilicon or doped single-crystal silicon.

[0012] In certain embodiments, the top electrode layer is of high conductivity material, such as gold, molybdenum, or highly doped polysilicon. In certain embodiments, the top electrode layer is of gold, molybdenum, or highly doped polysilicon.

[0013] In certain embodiments, the top electrode layer is of high conductivity material. In certain embodiments, the high conductivity material is a high electrical conductivity material. In certain embodiments, the top electrode layer is of (high) (electrical) conductivity material having conductivity in the range of 104to 108S / m (Siemens per meter). In certain embodiments, the top electrode layer is of (highly) doped polysilicon having conductivity at least 10 000 S / m. In certain embodiments, the top electrode layer is of UHD doped polysilicon having conductivity in the range of 10 000 S / m to 200 000 S / m. In certain embodiments, the top electrode layer is of metal having conductivity less than 100 MS / m (wherein M is mega, 106). In certain embodiments, the top electrode layer is of metal having conductivity in the range of 5 to 70 MS / m.

[0014] In certain embodiments, the top electrode layer of the semiconductor device comprises a multilayer top electrode. In certain embodiments, the multilayer top electrode comprises alternating layers of different materials. In certain embodiments, the multilayer top electrode comprises metallic, semiconducting and / or insulating material layers. In certain embodiments, the multilayer top electrode comprises repeating interchanging material layers. In certain embodiments, the multilayer top electrode comprises gold, Au and / or platinum, Pt.

[0015] In certain embodiments, the dielectric layer is of insulating material. In certain embodiments, the dielectric layer is of insulating material, such as silicon dioxide. In certain embodiments, the dielectric layer is of silicon dioxide.

[0016] In certain embodiments, the trimming layer is of a high-density material. In certain embodiments, the trimming layer is of a high-density material having density above (or at least) 10 g / cm3. In certain embodiments, the trimming layer is of a material having linear temperature coefficient of resistance, TCR. In certain embodiments, the trimming layer is of a high-density material, such as gold or platinum. In certain embodiments, the trimming layer is of gold or platinum.

[0017] In certain embodiments, the trimming layer covers (the surface of) the resonating element (surface) partially. In certain embodiments, the trimming layer is patterned to cover the resonating element partially. In certain embodiments, the trimming layer is patterned to cover the resonating element only partially. In certain embodiments, the trimming layer is a patterned trimming layer.

[0018] In certain embodiments, the trimming layer is patterned to cover peripheral areas (edge areas, outer areas, non-central areas) of the resonating element. In certain embodiments, the trimming layer is patterned to cover the resonating element only partially, such as the trimming layer is patterned to cover peripheral areas of the resonating element. In certain embodiments, the trimming layer is patterned to run through the peripheral areas of the resonating element from one side to another side of the resonating element (in length direction of the resonating element). In certain embodiments, the trimming layer forms (is configured to form) a pathway for the charge carriers (across / through / along / in the resonating element). In certain embodiments, the trimming layer is arranged on the resonating element symmetrically (wherein the symmetry axis runs in either x or y direction / length or width direction).

[0019] In certain alternative embodiments, the trimming layer uniformly covers the resonating element. In certain embodiments, the trimming layer covers (essentially) the resonating element (cover the entire resonating element surface). In certain embodiments, the trimming layer is patterned by lithographic patterning and etching. In certain embodiments, the trimming layer is configured to enable trimming (modulating, adjusting) of the resonance frequency of the resonating element (of the semiconductor device). In certain embodiments, the trimming layer is for trimming the resonance frequency of the resonating element.

[0020] In certain embodiments, the resonating element (the semiconductor device) comprises at least two conductive material layers. In certain embodiments, the resonating element (the semiconductor device) comprises conductive material layers (the trimming layer and the top electrode layer).

[0021] In certain embodiments, the resonating element comprises at least one contact hole. In certain embodiments, the resonating element comprises a plurality of contact holes. What is herein disclosed for contacts holes applies also to a single contact hole. In certain embodiments, the contact holes are arranged within the trimming layer (at the areas of the resonating element having the trimming layer).

[0022] In certain embodiments, the top electrode layer and the trimming layer of the resonating element are electrically connected via contact holes. In certain embodiments, the top electrode layer and the trimming layer are electrically connected via contact holes (located) at the resonating element.

[0023] In certain embodiments, the contact hole(s) create (provide) an electrical connection between the trimming layer and the top electrode layer through the insulating layer. In certain embodiments, the contact hole(s) create (provide) an electrical connection between the trimming layer and the silicon layer, such as UHD doped silicon layer through the insulating layer, the top electrode layer and the piezoelectric layer.

[0024] In certain embodiments, the silicon layer and the trimming layer are electrically connected via contact holes. In certain embodiments, the silicon layer and the trimming layer are electrically connected via contact holes, to enable interdiffusion between the silicon layer and the trimming layer materials.

[0025] In certain embodiments, at least two material layers of the resonating element are electrically connected via contact holes. In certain embodiments, at least two conductive material layers of the resonating element are electrically connected via contact holes. In certain embodiments, the contact holes provide electric contact from one conductive layer to another conductive layer (and vice versa). In certain embodiments, the top electrode layer and the trimming layer are electrically connected via contact holes. In certain embodiments, the contact holes provide electric contact from the trimming layer to the top electrode layer (and vice versa).

[0026] In certain embodiments, the contact holes are configured to enable interdiffusion between the top electrode material and the trimming layer material (the conductive layers). In certain embodiments, atoms of the material layers diffuse from one layer to another via interdiffusion. In certain embodiments, the semiconductor apparatus comprises means to receive current (electrical flow, charge carriers) to the trimming layer. In certain embodiments, the interdiffusion is driven by the current applied in between the trimming layer and the top electrode layer.

[0027] In certain embodiments, the current (electrical flow, charge carriers) applied to the trimming layer heats the contact holes (and the trimming layer). In certain embodiments, said heating is Joule heating. In certain embodiments, said heating is laser heating. In certain embodiments, the heating of the contact holes provides (enables, initiates, is configured to provide) interdiffusion via the contact holes. In certain embodiments, the interdiffusion trims (adjusts, modulates) the resonance frequency of the resonating element.

[0028] In certain embodiments, the contact holes are connectable to current (voltage, electricity, electrical flow, charge carriers) to provide interdiffusion. In certain embodiments, the contact holes are connectable to current via electrical terminal(s). In certain embodiments, the contact holes are connectable to current via contact point(s).

[0029] In certain embodiments, the trimming layer and the top electrode layer are of a certain (electrical) potential each. In certain embodiments, the potential of the trimming layer increases (is configured to increase) to a higher potential due to voltage being applied into the trimming layer. In certain embodiments, the potential difference between the trimming layer and the top electrode layer increases (is configured to increase) due to voltage (current) being applied into the trimming layer. In certain embodiments, the voltage (current) applied between the trimming layer and the top electrode layer heats the contact holes. In certain embodiments, the (local) heating between the trimming layer and the top electrode layer drives (enables, provides) interdiffusion. In accordance with certain embodiments, the amount of local heating needed depends on the material(s) that interdiffuse (with one another, interdiffusion between the materials). High temperature promotes molecular interdiffusion. In certain embodiments, the temperature of interdiffusion is within the range of 200 °C to 700 °C. In certain embodiments, several factors drive the local heating between the trimming layer and the top electrode layer. In certain example embodiments, contact hole number, contact hole size, contact resistance, and applied potential drives the local heating.

[0030] In certain embodiments, the contact holes reach through at least one layer of material, thereby connecting the material layers above and below the said layer of material. In certain embodiments, the contact holes reach through at least the dielectric layer, thereby connecting the top electrode layer and the trimming layer. In certain embodiments, the contact holes reach through more than one layer of material, thereby connecting the material layers above and below the said layers of materials. In certain embodiments, the contact holes reach through a plurality of layers of material, thereby connecting the material layers above and below the said layers of materials. In certain embodiments, the contact holes (are configured to) provide an electrical and mechanical contact between the material layers.

[0031] In certain embodiments, the contact holes are arranged at peripheral areas (edge areas, outer areas, non-central areas) of the resonating element. In certain embodiments, the contact holes are arranged at central areas (at centre, width-wise central, lengthwise central) of the resonating element. In certain embodiments, the contact holes are arranged symmetrically within the resonating element (the axis of symmetry running in x-direction or y-direction / width-direction or length-direction).

[0032] In certain embodiments, the contact hole is a feedthrough (between said material layers). In certain embodiments, the (each) contact hole is in a shape of a cylinder (tube-like, pipelike). In certain embodiments, the contact hole has a (essentially) circular cross-section. In certain embodiments, the contact hole has another shaped cross-section than circular, such as square, rectangular, rounded corner square, rounded corner rectangular, elliptical, or triangular cross-section. In certain embodiments, the contact hole has a diameter of in the range of 1 pm to 10 pm, such as in the range of 2 pm to 4 pm.

[0033] In certain embodiments, the semiconductor device comprises contact points. In certain embodiments, the semiconductor device comprises contact points, coupled to through silicon vias connected to external (contact) pads. In certain embodiments, the semiconductor device comprises contact points, formed by through silicon vias connected via cap contact pads to external pads. In certain embodiments, the contact points are configured to provide electric (electrical) contact to / from outside of the semiconductor device. In certain embodiments, the contact points are configured to provide mechanical contact to the outside of the semiconductor device. In certain embodiments, the semiconductor device comprises a plurality of contact points. In certain embodiments, the semiconductor device comprises a plurality of external contact pads. In certain embodiments, the semiconductor device comprises a plurality of cap contact pads. In certain embodiments, the semiconductor device comprises an equal number of contact points, external contact pads and cap contact pads.

[0034] In certain embodiments, the semiconductor device comprises three contact points. In certain embodiments, the semiconductor device comprises three external contact pads. In certain embodiments, the semiconductor device comprises three cap contact pads.

[0035] In certain embodiments, (two of) the contact points are connected to one anchoring point of the resonating element. In certain embodiments, (two of) the contact points are connected to two anchoring points of the resonating element. In certain embodiments, the contact points are connected to a plurality of different anchoring points of the resonating element. In certain embodiments, two of the contact points are for sensing (determining, measuring, detecting) a parameter of interest, and two of the contact points are for trimming of the semiconductor device. In certain embodiments, the two of the contact points used for sensing a parameter of interest are different contact points from the two of the contact points used for trimming the semiconductor device. In certain embodiments, two of the contact points are for sensing a parameter of interest, and two of the contact points is for providing mechanical and electric contact to the trimming layer. In certain embodiments, two of the contact points are for trimming the resonance frequency of the resonating element by providing mechanical and electric contact to the trimming layer. In certain embodiments, one of the contact points is used for both sensing the parameter of interest and for trimming.

[0036] In certain embodiments, the semiconductor device provides (is configured to provide) as an output resonance frequency (signals) that are indicative of a parameter of interest. In certain embodiments, the semiconductor provides as an output resonance frequency signal(s) and an amplitude of the resonance frequency that are indicative of a parameter of interest. In certain embodiments, the resonance frequency (and the amplitude) of the device is measured. In certain embodiments, the resonance frequency (and the amplitude) of the device is measured, which enables determining the parameter of interest. In certain embodiments, the sensing of the parameter of interest is provided by (is enabled by) sensing the resonance frequency of the semiconductor device. In certain embodiments, the parameter of interest is (provided, enabled) based on tracking (measuring, sensing, determining) the resonance frequency. In certain embodiments, the parameter of interest is (provided, enabled) based on tracking resonance frequency and the amplitude of the resonance frequency.

[0037] In certain embodiments, the parameter (measurement, value, unit) of interest is (high precision) timing. In certain embodiments, the parameter (measurement, value, unit) of interest is sensing of mass. In certain embodiments, the parameter (measurement, value, unit) of interest is sensing of gas. In certain embodiments, the parameter (measurement, value, unit) of interest is acceleration, or deceleration.

[0038] In certain embodiments, the trimming layer is coupled to two of the contact points. In certain embodiments, the trimming layer is coupled to the two of the contact points used for trimming the semiconductor device (resonance frequency). In certain embodiments, the resonating element is coupled to the two of the (three) contact points used for sensing a parameter of interest.

[0039] In certain embodiments, the electric contact (current, flow, charge carriers) are provided to the semiconductor device via a route, the route formed by through silicon vias (through the cap wafer) connected to pads. In certain embodiments, the electric contact (current, flow, charge carriers) are provided to the semiconductor device via a route, the route formed by contact points connected to cap contact pads, the cap contact pads coupled with through silicon vias connected to external pads.

[0040] In certain embodiments, the semiconductor device is fabricated on a substrate. In certain embodiments, the substrate is a silicon-on-insulator, SOI, wafer. In certain embodiments, the substrate is a cavity silicon-on-insulator, CSOI, wafer. In certain embodiments, the substrate is a silicon-on-insulator, SOI, substrate, or a cavity silicon-on-insulator, CSOI, substrate.

[0041] In certain embodiments, the substrate comprises a buried oxide layer, BOX. In certain embodiments, the buried oxide layer is between a handle wafer portion and a device wafer portion. In certain embodiments, the handle wafer portion and the device wafer portion comprise silicon. In certain embodiments, the substrate comprises a cavity. In certain embodiments, the substrate comprises a cavity underneath the resonating element.

[0042] In certain embodiments, the device wafer portion comprises silicon (a silicon layer). In certain embodiments, the device wafer portion comprises silicon, preferably doped silicon, such as ultra-heavily doped, UHD, silicon. In certain preferred embodiments, the silicon is of single-crystal silicon. In certain embodiments, the doping level of the silicon is above 1019 cm3. In certain embodiments, the doping level of the silicon is above 1O20cm3. In certain embodiments, the doped silicon is of N-type or P-type doping.

[0043] In certain embodiments, the device wafer portion comprises a piezoelectric layer. In certain embodiments, the device wafer portion comprises a piezoelectric layer on the silicon layer (silicon body) of the device wafer portion. In certain embodiments, the piezoelectric layer (material) is of aluminum nitride, AIN.

[0044] In certain embodiments, the device wafer portion comprises a silicon layer. In certain embodiments, the semiconductor device comprises a silicon layer, preferably UHD doped silicon layer, below (beneath, under) the top electrode layer (not excluding the (optional) piezoelectric layer in between the silicon layer and the top electrode layer). In certain embodiments, the top electrode, the dielectric layer and the trimming layer are arranged onto the silicon layer (of the device wafer portion). In certain embodiments, (the resonating element of) the semiconductor device comprises a silicon layer, a top electrode layer on top of the silicon layer, a dielectric layer on top of the top electrode layer, and a trimming layer on top of the dielectric layer. In certain embodiments, the silicon layer and the trimming layer are electrically connected via contact holes to enable interdiffusion between the silicon layer and the trimming layer (materials). In certain embodiments, the resonating element comprises contact holes in between the silicon layer and the trimming layer to enable interdiffusion between the silicon layer and the trimming layer.

[0045] In certain embodiments, the device wafer portion comprises a silicon layer, and a piezoelectric layer on top of the silicon layer. In certain embodiments, the top electrode, the dielectric layer and the trimming layer are arranged onto the device wafer portion (onto the piezoelectric layer of the device wafer portion). In certain embodiments, (the resonating element of) the semiconductor device comprises a silicon layer, a piezoelectric layer on top of the silicon layer, a top electrode layer on top of the piezoelectric layer, a dielectric layer on top of the top electrode layer, and a trimming layer on top of the dielectric layer.

[0046] In certain embodiments, (the resonating element of) the semiconductor device comprises a material stack, the material stack comprising the silicon layer (the bottom electrode), the piezoelectric layer on top of the silicon layer, a top electrode layer on top of the piezoelectric layer, a dielectric layer on top of the top electrode layer, and a trimming layer on top of the dielectric layer. In certain embodiments, the semiconductor device comprises a piezoelectric device.

[0047] In certain embodiments, the semiconductor device comprises a bottom electrode. In certain embodiments, the semiconductor device comprises a bottom electrode layer. In certain embodiments, the semiconductor device comprises a bottom electrode layer of silicon. In certain embodiments, the semiconductor device comprises a resonating element having two electrode layers. In certain embodiments, the semiconductor device comprises a resonating element having a top electrode layer and a bottom electrode layer. In certain embodiments, the silicon layer is configured to implement a bottom electrode of device. In certain embodiments, the silicon layer is a bottom electrode of the semiconductor device. In certain embodiments, the bottom electrode comprises silicon, preferably doped silicon, such as ultra-heavily doped, UHD, silicon. In certain preferred embodiments, the silicon is of single-crystal silicon. In certain embodiments, the bottom electrode (layer) is implemented by an UHD silicon layer (of the device wafer portion). In certain embodiments, the doping level of the silicon is above 1019cm-3. In certain embodiments, the doping level of the silicon is above 1O20cm-3. In certain embodiments, the doped silicon is of N-type or P-type doping.

[0048] In certain embodiments, the sealing ring encircles (is configured to encircle) the semiconductor device. In certain embodiments, the sealing ring is of gold.

[0049] In certain embodiments, the semiconductor device comprises a resonating (oscillating) element. In certain embodiments, the semiconductor device comprises a microelectromechanical systems, MEMS, resonator. In certain embodiments, the semiconductor device is a microelectromechanical systems, MEMS, resonator device. In certain embodiments, the semiconductor device is configured to operate in a megahertz frequency area. In certain embodiments, the semiconductor device is configured to operate at 32 MHz frequency.

[0050] In certain embodiments, the semiconductor device comprises at least one resonating element (resonator). In certain embodiments, the semiconductor device comprises a plurality of resonating elements. In certain embodiments, the resonating element comprises a plurality of resonating beam elements. In certain embodiments, each beam element is a sub-element of the device.

[0051] In certain embodiments, the resonating element comprises a plurality of beam elements having a length and a width. In certain embodiments, the plurality of beam elements are positioned adjacent to each other. In certain embodiments, adjacent beam elements are mechanically connected to each other by connection elements.

[0052] In certain embodiments, the device comprises a stacked beam resonator. In certain embodiments, the stacked beam resonator comprises a plurality of beam elements positioned side-by-side in a plane. In certain embodiments, the plurality of beam elements are positions adjacent to each other in a width direction thereof. In certain embodiments, the plurality of beam elements are positioned adjacent to each other in a width direction of the device. In certain embodiments, the beam elements are separated by trenches. In certain embodiments, the beam elements are connected to each other by connection elements.

[0053] In certain embodiments, the resonating element of the device comprises a plurality of beam elements, such as seven, nine, or eleven beam elements. In certain embodiments, said adjacent beam elements are mechanically connected to each other by connection elements. In certain embodiments, the beam elements of the device are arranged in a rectangular array configuration.

[0054] In certain embodiments, the resonating element is in a shape of a rectangle. In certain embodiments, the resonating element is in a shape of an elongated rectangle (beamshaped). In certain embodiments, the resonating element has an aspect ratio (ratio of length to width, when observed from above) different from 1. In certain embodiments, each beam element is in a shape of a (rectangular) beam. In certain embodiments, each beam element has an aspect ratio (ratio of length to width, when observed from above) different from 1. In certain embodiments, each beam element has a length-to-width aspect ratio of more than 1.

[0055] In certain embodiments, the resonating element has a length-to-width aspect ratio of less than 1. In certain embodiments, the resonating element is attached (supported, anchored, suspended) to a support structure. In certain embodiments, the resonating element is attached to a support structure from the outermost beam elements of the resonating element. In certain embodiments, the resonating element comprises at least one anchoring point configured to connect the resonating element to, and suspend the device to the support structure (from surrounding layers). In certain embodiments, the resonating element comprises two anchoring points configured to connect the device to, and suspend the device to the support structure (from surrounding layers). In certain embodiments the anchoring point(s) comprise portions of the silicon layer (bottom electrode), the piezoelectric layer, the top electrode, the dielectric layer and the trimming layer.

[0056] In certain embodiments, the resonating beam element(s) are longitudinally aligned within 25 degrees of a <100> crystal direction of silicon (of the bottom electrode). Within at least some embodiments the resonating beam element(s) are longitudinally aligned with a <100 crystal direction of the silicon (of the bottom electrode) such that a longitudinal axis of each resonating beam is within 25 degrees of the <100> crystal direction of the silicon (of the bottom electrode).

[0057] In certain embodiments, the semiconductor device is configured to resonate (operate, oscillate, vibrate) in an in-plane resonance mode. In certain embodiments, the semiconductor device is configured to operate (resonate) in an in-plane length-extensional, LE, resonance mode. In certain embodiments, the length extensional resonance mode is configured to resonate parallel to the length direction of the resonating element of the semiconductor device. In certain embodiments, the length extensional resonance mode is configured to resonate perpendicular to the width direction of the resonating element of the semiconductor device.

[0058] In certain embodiments, the semiconductor device is configured to resonate in a squareextensional, SE, resonance mode. In certain embodiments, the semiconductor device is configured to resonate in a width-extensional, WE, resonance mode.

[0059] In certain embodiments, the semiconductor device is configured to resonate in a out-of-plane resonance mode. In certain embodiments, the semiconductor device is configured to resonate in an out-of-plane flexural resonance mode.

[0060] In certain embodiments, the semiconductor device is configured to resonate in a collective resonance mode. In certain embodiments, each resonating beam element of the semiconductor device is configured to resonate in the (same) collective resonance mode. In certain embodiments, the semiconductor device is configured to resonate in a desired (main) resonance mode. In certain embodiments, each resonating beam element is configured to resonate in the (same) desired resonance mode.

[0061] According to a second example aspect of the present disclosure there is provided a packaged semiconductor apparatus, comprising at least one semiconductor device of the first aspect of any of its embodiments.

[0062] In certain embodiments, the packaged semiconductor apparatus comprises at least one semiconductor device. In certain embodiments, the packaged semiconductor apparatus comprises a plurality of semiconductor devices (such as two devices).

[0063] In certain embodiments, the packaged semiconductor apparatus comprises a cap wafer and the device wafer bonded together. In certain embodiments, the packaged semiconductor apparatus comprises a cap wafer and the device wafer bonded together via thermocompression bonding. In certain embodiments, the packaged semiconductor apparatus is a wafer-level packaged, WLP, apparatus. In certain embodiments, the packaged semiconductor apparatus comprises an enclosure (formed by the cap wafer and the device wafer bonded together).

[0064] In certain embodiments, the device wafer comprises the handle wafer portion and the device wafer portion (optionally separated from one another by a buried oxide layer, and / or a cavity (the cavity being at least underneath the resonating element)).

[0065] In certain embodiments, the cap wafer of the packaged semiconductor apparatus comprises a (at least one) recess. In certain embodiments, the recess is arranged on the cap wafer facing the enclosure (inside the enclosure, facing the resonating element). In certain embodiments, the recess is arranged at the vertical location of the resonating element (above the resonating element, when observed from above).

[0066] In certain embodiments, the cap wafer of the packaged semiconductor apparatus comprises a redistribution layer. In certain embodiments, the redistribution layer is arranged on the cap wafer facing the enclosure (inside the enclosure, facing the resonating element). In certain embodiments, the redistribution layer is of gold.

[0067] In certain embodiments, the cap wafer comprises a sealing ring. In certain embodiments, the packaged semiconductor apparatus is sealed by a sealing ring. In certain embodiments, the cap wafer and the device wafer are sealed together by a sealing ring. In certain embodiments, the sealing ring is formed of two counterparts, one being on the device wafer and one being on the cap wafer. In certain embodiments, the two counterparts of the sealing ring are configured to merge with each other upon bonding. In certain embodiments, the sealing ring is configured to provide a hermetical seal for the packaged semiconductor apparatus.

[0068] In certain embodiments, the sealing ring (of the device wafer) encircles the semiconductor device. In certain embodiments, the sealing ring is formed of the redistribution layer.

[0069] In certain embodiments, the cap wafer comprises cap contact pads (cap pads). In certain embodiments, the cap wafer comprises three cap contacts pads. In certain embodiments, the cap contact pads are coupled to the contact points of the semiconductor device (upon bonding). In certain embodiments, the cap contacts pads are configured to provide electric (and mechanical) contact to the semiconductor device. In certain embodiments, the through silicon vias are arranged through the cap wafer. In certain embodiments, the cap wafer comprises external pads (external contact pads). In certain embodiments, the cap wafer comprises three external pads. In certain embodiments, the external pads are coupled by through silicon vias (and the cap contact pads) to the contact points of the semiconductor device, respectively. In certain embodiments, the external pads are configured to provide electric (and mechanical) contact to / from outside into the semiconductor device.

[0070] According to a third example aspect of the present disclosure there is provided a method for trimming a semiconductor device, the method comprising providing a semiconductor device of the first aspect of any of its embodiments, and applying current to the contact holes to trim the resonance frequency of the semiconductor device.

[0071] In certain embodiments, applying current to the contact holes heats the contact holes (Joule heating, or laser heating). In certain embodiments, applying current to the contact holes initiates interdiffusion to trim the resonance frequency of the semiconductor device. In certain embodiments, atoms of material layers connected by the contact holes diffuse from one layer to another (between the layers) via interdiffusion. In certain embodiments, the (joule, laser) heating temperature depends on the contact resistance of the layer materials, the deposition method of the layer materials, the contact hole size and the contact hole number. By way of an example, a single small hole is easy to heat with a given electrical potential. The same electrical potential will not be effective on an array of large holes. In certain embodiments, the contact hole number and contact hole size are parameters of design and tuning for the semiconductor device.

[0072] In certain embodiments, the contact hole(s) are filled with the diffused materials. In certain embodiments, the contact hole(s) are filled with the diffused materials, such that a homogenous mixture of the diffused materials is formed. In certain embodiments, the contact hole(s) are filled with the (mixture of) interdiffused materials. In certain embodiments, the contact hole(s) are filled with atoms of material layers connected by the contact holes. In certain embodiments, the contact hole(s) are filled with a homogenous mixture of atoms of material layers connected by the contact holes. In certain embodiments, the contact hole(s) are completely diffused. In certain embodiments, the contact hole(s) are not completely diffused (“mixed”). In certain embodiments, the contact hole(s) are partially diffused. In certain embodiments, the interdiffusion is driven by (high) current applied in between the material layers connected by the contact holes. In certain embodiments, the current applied to heat the contact holes to a temperature within a range 200 ° to 700 °C. In certain embodiments, applying current to the contact holes comprises providing current via a route, the route formed by through silicon vias (through the cap wafer) connected to pads (cap contact pads and contact points), the pads being connected to the contact holes. In certain embodiments, applying current to the contact holes comprises providing current via a route, the route formed by external contact pads coupled to through silicon vias TSVs, the TSVs connected to cap contact pads, and the cap contact pads connected to contact points of the semiconductor device.

[0073] In accordance with certain embodiments, embodiments of the second and third aspect are provided, the embodiments comprising subject matter of any single embodiment presented in connection with the first aspect, or the embodiments comprising subject matter of any of the embodiments presented in connection with the first aspect combined with subject matter presented in any other embodiment or embodiments.

[0074] Different non-binding example aspects and embodiments have been illustrated in the foregoing. The embodiments in the foregoing are used merely to explain selected aspects or steps that may be utilized in different implementations. Some embodiments may be presented only with reference to certain example aspects. It should be appreciated that corresponding embodiments may apply to other example aspects as well. In particular, the embodiments described in the context of the first aspect are applicable to each further aspect. Any appropriate combinations of the embodiments may be formed.

[0075] BRIEF DESCRIPTION OF THE FIGURES

[0076] Some example embodiments will be described with reference to the accompanying figures, in which:

[0077] Fig. 1A schematically shows a semiconductor device in a side view according to an example embodiment;

[0078] Fig. 1 B schematically shows a multilayer top electrode in accordance with an example embodiment:

[0079] Fig. 2A schematically shows a semiconductor device in a top view a stacked beam resonating element according to an example embodiment;

[0080] Fig. 2B schematically shows a semiconductor device a top view having a resonating plate element according to an example embodiment;

[0081] Fig. 3 schematically shows a cap wafer of the packaged semiconductor device on side facing the resonating element in a top view according to an example embodiment; and Fig. 4 schematically shows a cap wafer of the packaged semiconductor device on side facing outside in a top view according to an example embodiment;

[0082] Fig. 5A schematically shows a semiconductor device in a top view according to another example embodiment;

[0083] Fig. 5B schematically shows a semiconductor device in a side view according to another example embodiment;

[0084] Fig. 5C schematically shows a semiconductor device in a side view according to yet another example embodiment; and

[0085] Fig. 6 schematically shows method steps for trimming a semiconductor device according to an example embodiment.

[0086] DETAILED DESCRIPTION

[0087] In the following description, like reference signs denote like elements or steps.

[0088] As used herein, the term a semiconductor apparatus refers to any kind of apparatus or device that may appear in a semiconductor industry, such as a chip, circuitry, microchip, microprocessor, filter, silicon chip, computer chip, resonator, sensor, accelerometer, gyroscope, actuator and process-control unit, vacuum tube or alike. In certain embodiments, the semiconductor apparatus has been packaged. In certain embodiments, the semiconductor apparatus comprises a MEMS device.

[0089] As used herein, the term resonating element is used to refer to a (silicon-based) element suspended to a supporting structure so as to be capable of resonating in a resonance mode. In certain embodiments, the resonating element is a piezoelectric resonating element, comprising a piezoelectric layer. In certain embodiments, the resonating element comprises piezoelectric actuation. In certain alternative embodiments, the resonating element comprises electrostatic actuation. In certain electrostatic actuation embodiments, the piezoelectric layer is omitted (from the material stack of the resonating element).

[0090] As used herein, the term packaged apparatus or chip means a single package, i.e. one physical entity that comprises a device (oscillator, resonator, a resonating element) having structure(s), such as resonating beam(s). According to certain embodiments, the packaged apparatus is a packaged semiconductor apparatus. According to certain embodiments, the packaged apparatus comprises a device wafer and a cap wafer bonded together to form the package. As used herein, the term die means the part that is diced from a ready fabricated silicon wafer in the dicing operation. In dicing, the dies are separated from each other using a special equipment. In the context of the instant disclosure, the term die forms a synonym to the term chip. Other synonyms to the terms chip and die is the term component.

[0091] The axes x, y and z are denoted to each Figure to illustrate the direction of observing. The axes are interrelated, meaning that each of the notations x, y or z are to be understood as the same x, y or z direction in all the Figures.

[0092] Fig. 1A schematically shows a semiconductor device 100 in a side view according to an example embodiment. In certain embodiments, the semiconductor device 100 comprises at least two conductive material layers. In certain embodiments, the semiconductor device comprises the trimming layer 101 and the top electrode layer 103.

[0093] In certain embodiments, the semiconductor device 100 comprises a resonating element 110 having a top electrode (layer) 103, a dielectric layer 102 on top of (on, on the surface of, deposited onto) the top electrode layer 103, and a trimming layer 101 on top of the dielectric layer 102. In other words, the semiconductor device 100 comprises a resonating element 110 comprising a trimming layer 101, a dielectric layer 102 beneath the trimming layer 101, and a top electrode layer 103 beneath the dielectric layer 102.

[0094] In certain embodiments, the top electrode layer 103 is of high conductivity material having conductivity in the range of 104to 108S / m. In certain embodiments, the top electrode layer 103 is of gold, molybdenum, or highly doped polysilicon. In certain embodiments, the highly doped polysilicon has a doping concentration of X. In certain embodiments, the top electrode layer 103 has a thickness in the range of 50 nm to 500 nm.

[0095] In certain embodiments, the dielectric layer 102 is of insulating material, such as silicon dioxide. In certain embodiments, the dielectric layer 102 is configured to passivate the top electrode layer 103.

[0096] In certain embodiments, the trimming layer 101 is of a high-density material having density at least 10 g / cm3In certain embodiments, the trimming layer 101 is of material having linear temperature coefficient of resistance, TCR. In certain embodiments, the trimming layer 101 is of gold or platinum. In certain embodiments, the trimming layer 101 is configured to enable trimming (modulating, adjusting) of the resonance frequency of the resonating element 110.

[0097] In certain embodiments, the semiconductor device 100 is fabricated on a substrate. In the embodiment shown in Fig. 1A, the substrate is a cavity silicon-on-insulator, CSOI, silicon wafer. In the embodiment shown in Fig. 1A, the substrate comprises a cavity 108 underneath the resonating element 110. In certain embodiments, the resonating element 110 is configured to resonate (vibrate, oscillate) within the cavity 108.

[0098] In the embodiment shown in Fig. 1A, the substrate comprises a buried oxide layer, BOX, 106 in between a handle wafer portion 107 and a device wafer portion 101, 102, 103, 104, 105. In certain embodiments, the device wafer portion comprises a silicon layer 105. In certain embodiments, the semiconductor device 100 (device wafer portion) comprises a bottom electrode layer. In certain embodiments, the silicon layer 105 is configured to implement a bottom electrode of the semiconductor device 100. In certain embodiments, the silicon layer 105 is preferably doped silicon, such as ultra-heavily doped, UHD, silicon. In certain embodiments, the bottom electrode (layer) is implemented by an UHD silicon layer (of the device wafer portion). In certain preferred embodiments, the silicon layer 105 is of single-crystal silicon. In certain embodiments, the doping level of the silicon layer 105 is above 1019cm-3, such as above 102° cm-3. In certain embodiments, the doped silicon is of N-type or P-type doping.

[0099] In certain embodiments, the device wafer portion comprises a piezoelectric layer 104 on the silicon layer 105. In certain embodiments, the piezoelectric layer 104 is arranged in between the silicon layer 105 and the top electrode layer 103. In certain embodiments, the piezoelectric layer 104 is of aluminum nitride, AIN.

[0100] In certain embodiments, the said top electrode layer 103, dielectric layer 102 and trimming layer 101 are arranged onto the piezoelectric layer 104. In certain embodiments, the resonating element 110 comprises a material stack comprising a silicon layer 105, a piezoelectric layer 104 on top of the silicon layer 105, a top electrode layer 103 on top of the piezoelectric layer 104, a dielectric layer 102 on top of the top electrode layer 103, and a trimming layer 101 on top of the dielectric layer 102. In other words, the resonating element 110 comprises a material stack comprising a trimming layer 101, a dielectric layer 102 beneath the trimming layer 101, a top electrode layer 103 beneath the dielectric layer 102, a piezoelectric layer 104 beneath the top electrode layer 103, and a silicon layer 105 beneath the piezoelectric layer 104.

[0101] As shown in Fig. 1A, in certain embodiments, the resonating element 110 is separated from the support structure by trenches 109. In certain embodiments, the semiconductor device 100 comprises contact points XIN, XOUT, XTRIM. In certain embodiments, the contact points XOUT is arranged at a location having a top electrode layer 103 and a trimming layer 101 on top of the top electrode layer 103 (the dielectric layer is omitted). Thereby XOUT allows electric current (charge carriers) to exit from the semiconductor device. In certain embodiments, the contact point XOUT is coupled (connected) to the silicon layer 105 by a silicon contact hole 111. As shown in Fig. 1A, in certain embodiments, the silicon contact hole 111 is filled with both top electrode material and trimming layer material. In certain alternative embodiments, the silicon contact hole 111 is filled with trimming layer material (not shown). The conductive material layer(s) (the trimming layer, the top electrode layer) allow the electric current (charge carriers) to move from the silicon layer 105 to the contact point XOUT.

[0102] In certain embodiments, the contact points XIN is arranged at a location having a top electrode layer 103 and a trimming layer 101 on top of the top electrode layer 103 (the dielectric layer is omitted). Thereby XIN allows electric current (charge carriers) to travel (enter) into the (layer(s) of) semiconductor device.

[0103] In certain embodiments, the contact point XTRIM is each arranged at a location having a top electrode layer 103, a dielectric layer 102 on top of the top electrode layer 103, and a trimming layer 101 on top of the dielectric layer 103. Thereby XTRIM allows electric current (charge carriers) to travel (enter and exit) only within (to) the trimming layer 101. The dielectric layer 102 prevents the electric current from entering the layer(s) beneath.

[0104] In certain embodiments, the resonating element 110 comprises contact holes 112. In certain embodiments, the contact holes 112 are metal contact holes (should not be confused with silicon contact holes 111). In certain embodiments, at least two conductive material layers of the resonating element 110 are connected (coupled) via contact holes 112. In certain embodiments, the contact holes provide electric contact from one conductive layer to another conductive layer (and vice versa). As shown in Fig. 1A, in certain embodiments, the top electrode layer 103 and the trimming layer 101 are electrically connected via contact holes 112. In certain embodiments, the contact holes 112 provide electric contact between the trimming layer 101 to the top electrode layer 103. In certain embodiments, the trimming layer material 101 is configured to reach to the top electrode layer 103 via the contact holes 112.

[0105] In certain embodiments, in case of the multilayer top electrode 103, the contact hole 112 may reach through all the layers. In certain embodiments, the contact hole reaches through at least some of the layers of the multilayer top electrode 103. In certain embodiments, upon heating, the materials of the multilayer top electrode 103 anneal. In certain embodiments, the annealing depth may vary, as mentioned.

[0106] In certain embodiments, the contact holes 112 are configured to enable interdiffusion between the top electrode material 103 and the trimming layer material 101 (the conductive layers). In certain embodiments, atoms of the material layers diffuse from one layer to another (between the layers) via interdiffusion (upon heating). In certain embodiments, the interdiffusion is a metal interdiffusion. In certain embodiments, the contact holes 112 are filled with atoms of material layers connected by the contact holes, such that the contact holes 112 are completely diffused. In certain embodiments, the layers 101, 103 are fully diffused, thereby forming (making) an alloy or an intermetallic.

[0107] In certain alternative embodiments, the contact holes 112 are partially diffused, such that the crystallization (granulation) of the contact holes 112 changes, without reaching complete diffusion. In certain embodiments, the layers 101, 103 are welded together with boundary overlap forming transition interface. In certain embodiments, the layer 101, 103 interfaces may remain at least partially intact (no complete, significant diffusion) but the crystallization (granulation) of the layer(s) 101, 103 may change. In accordance with certain embodiments, the morphology of the layer(s) 101, 103 is changed by crystallization.

[0108] In other words, in certain embodiments, the layers 101, 103 are locally mixed. In certain embodiments, this mixing may be partial or complete. In certain embodiments, the layers 101, 103 are mixed in the spots of the contact holes 112. In certain embodiments, the mixing (diffusion) is achieved by local heating. In certain embodiments, the heating is Joule heating, or laser heating.

[0109] In certain embodiments, once the heating reaches high enough temperature, local recrystallization and stress distribution occurs. In certain embodiments, as a result, the elasticity of the top electrode 101 changes. In certain embodiments, the interdiffusion is driven by (high) current applied in between the trimming layer 101 and the top electrode layer 103. In certain embodiments, the current applied to heat the contact holes to a temperature within the range 200 ° to 700 °C. The dielectric layer 102 in between the trimming layer 101 and the top electrode layer 103 prevents the current from transferring in between the layers 101, 103 at any (random) location. The contact holes 112 enable the current to transfer between the layers 101 , 103. In certain embodiments, the current applied to the trimming layer 101 heats the contact holes 112 by Joule heating. In certain embodiments, the heating of the contact holes 112 provides interdiffusion between the top electrode layer 103 and the trimming layer 101. In certain embodiments, the interdiffusion enables trimming the resonance frequency of the resonating element 110.

[0110] In certain embodiments, the contact holes 112 are connected to current via contact point(s) XTRIM. In certain embodiments, the top electrode layer 103 and the trimming layer 101 are of different potential. In certain embodiments, the top electrode layer 103 and the trimming layer 101 each have their individual contact points (as explained earlier). In certain embodiments, the potential difference between the trimming layer 101 and the top electrode layer 103 increases due to current (voltage, electricity) being applied into the trimming layer 101. In certain embodiments, the potential difference between the trimming layer 101 and the top electrode layer 103 drives interdiffusion to trim the resonance frequency of the resonating element 110 of the semiconductor device 100. In certain embodiments, the contact holes 112 enable using interdiffusion and Joule heating to modulate the density and / or spring of the resonating element 110 of the semiconductor device 100.

[0111] In certain embodiments, the (each) contact hole is in a shape of a cylinder, having a circular cross-section. In certain embodiments, the contact hole has a diameter of the circular crosssection in the range of 1 pm to 10 pm. By providing a small enough contact holes 112, the interdiffusion is enhanced.

[0112] Accordingly, there is provided a semiconductor device 100, comprising a resonating element 110 having a top electrode layer 103, a dielectric layer 102 on top of the top electrode layer 103, and a trimming layer 101 on top of the dielectric layer 102, wherein the top electrode layer 103 and the trimming layer 101 are electrically connected via contact holes 112. This enables trimming the resonance frequency of the device 100.

[0113] Fig. 1B schematically shows a multilayer top electrode 103. Herein, the multilayer top electrode refers to a top electrode layer having a plurality of material a plurality of material layers atop one another. In certain embodiments, the multilayer top electrode 103 may comprise metallic, such as gold or platinum, semiconducting and / or insulating material layers. In certain embodiments, the multilayer top electrode 103 comprises repeating interchanging material layers. As shown in the left-side embodiment of Fig. 1 B, in certain embodiments, the contact hole 112 reaches through the multilayer top electrode 103. In certain embodiments, the contact hole 112 reaches through all the material layers of the multilayer top electrode 103. In certain embodiments, the material layers of the multilayer top electrode 103 participate into the interdiffusion.

[0114] As shown in the right-side embodiment of Fig. 1B, in certain embodiments, the contact hole 112 reaches into the multilayer top electrode 103. In certain embodiments, the contact hole 112 does not reach all the way through the multilayer top electrode. In certain embodiments, the depth of the contact hole 112 may vary.

[0115] Fig. 2A schematically shows a semiconductor device 100 in a top view having a stacked beam resonating element according to an example embodiment. As shown in Fig. 2A, in certain embodiments, the trimming layer 101 is patterned to cover the resonating element 110 only partially. In certain embodiments, the trimming layer 101 is patterned to cover peripheral areas of the resonating element 110 along the length dimension of the resonating element. In certain embodiments, the trimming layer 101 is arranged on the resonating element 110 symmetrically (wherein the symmetry axis runs in either x direction of the resonating element).

[0116] As shown in Fig. 2A, in certain embodiments, the semiconductor device 100 comprises contact points XIN, XOUT, XTRIM. In certain embodiments, the contact points XIN, XOUT, XTRIM are coupled to through silicon vias, the through silicon vias being connected pads (through silicon vias and pads shown in Figs. 3 and 4). In certain embodiments, the contact points XIN, XOUT are configured to provide electric and mechanical contact from / to the semiconductor device 100. In certain embodiments, two of the contact points XIN, XOUT are for sensing a parameter of interest, and two of the contact points XIN, XTRIM is for (enabling) trimming of the resonating element 110. In accordance with certain embodiments, the contact point XIN is used for both sensing the parameter of interest and for trimming. In certain embodiments, when the contact hole 112 connects to the top electrode layer, the electric current is applied between XTRIM and XIN.

[0117] As used herein, the parameter of interest is used to refer to a parameter for which the semiconductor device 100 is designed (configured) to provide. The semiconductor device provides as an output resonance frequency signal(s) that are indicative of a parameter of interest. In certain embodiments, the parameter of interest is (high precision) timing, sensing of mass sensing of gas, sensing of acceleration, or deceleration. In certain embodiments, the sensing of parameter of interest is provided by sensing (tracking, measuring) of frequency (and amplitude) of the resonance (vibration). In certain embodiments, the sensing of parameter of interest is provided by sensing of the change in frequency (and the amplitude) of the resonance.

[0118] In certain embodiments, the charge carriers (electric current) are configured to enter the trimming layer 101 via contact point XTRIM. Thus, the semiconductor device 100 comprises an ‘extra’ contact point XTRIM (in addition to the contact points XIN, XOUT). In certain embodiments, the trimming layer 101 is coupled to the two of the contact points XIN , XTRIM used for trimming the semiconductor device.

[0119] In certain embodiments, the trimming layer 101 is coupled to the contact point XTRIM via a XTRIM trace 202. In certain embodiments, the XTRIM trace 202 is of the same material as the trimming layer 101. In certain embodiments, the resonating element 110 is coupled to a contact point XIN via a XIN trace 204. In certain embodiments, the XIN trace 204 is of same material as the top electrode layer 103. As shown in Fig. 2A, in certain embodiments, the XTRIM trace 202 and the XIN trace 204 are routed via different anchoring points 208 of the resonating element 110. As shown in Fig. 2A, in certain embodiments, the contact point XOUT is coupled to the silicon layer 105 via silicon contact holes 111.

[0120] In certain embodiments, the contact holes 112 are arranged at zone of low strain of the resonating element 110. In certain embodiments, the contact holes 112 are arranged at peripheral areas of the resonating element. In certain embodiments, the contact holes 112 are arranged symmetrically within the resonating element (wherein the axis of symmetry running in x-direction of the resonating element 110). In certain embodiments, current and interdiffusion modulate the local strain (maximise the modulation of density) to tune the resonance frequency of the resonating element 110.

[0121] In certain embodiments, the sealing ring 201 encircles the semiconductor device 100. In certain embodiments, the sealing ring 201 is of gold.

[0122] As shown in Fig. 2A, in certain embodiments, the resonating element 110 comprises a plurality of resonating beam elements 206. In certain embodiments, the resonating element 110 comprises a plurality of beam elements 206 positioned adjacent to each other, mechanically connected to each other by connection elements and separated by trenches 207. In certain embodiments, the device 100 comprises a stacked beam resonator (ladderlike configuration), comprising a plurality of beam elements 206 positioned side-by-side in a plane. In certain embodiments, the resonating element 110 is attached to a support structure from the outermost beam elements of the resonating element via at least one anchoring point 208. The embodiment shown in Fig. 2A comprises two anchoring points 208. In certain embodiments, the anchoring points 208 are configured to connect the device 100 to, and suspend the device 100 to the support structure.

[0123] In certain embodiments, the semiconductor device 100 is configured to resonate in an inplane length-extensional, LE, resonance mode, configured to resonate parallel to the length direction (shown in Fig. 2A as x-direction) of the resonating element 110 of the semiconductor device 100. In certain embodiments, each resonating beam element 206 of the resonating element 110 of the semiconductor device 100 is configured to resonate in the (same) collective resonance mode. In certain embodiments, the semiconductor device comprises a microelectromechanical systems, MEMS, resonator.

[0124] In certain embodiments, such as shown in Fig. 2A, the contact holes 112 are arranged in horizontal lines within the resonating element. In certain embodiments, the contact holes 112 are arranged in horizontal lines along (aligning with) the x-direction (x-axis) of the resonating element 110. This enables changing the frequency of each part or portion of the resonating element 110, such as the resonating beam element 206, in the same way. Fig.

[0125] 2B schematically shows a semiconductor device having a resonating plate element 206’ in a top view according to an example embodiment. Fig. 2B shows otherwise an analogous device in comparison to Fig. 2A, except for the type of the resonating element 110.

[0126] In certain embodiments, the resonating element 110 comprises one resonating element. In certain embodiments, the resonating element 110 comprises a resonating plate element 206’. In certain embodiments, the resonating plate element 206’ is separated from the support structure by an external trench 207’. In certain embodiments, the resonating plate element 206’ is attached to the support structure via (at least) one anchoring point 208.

[0127] In certain embodiments, the contact holes 112 are arranged at peripheral areas of the resonating element 110. In certain embodiments, the trimming layer 101 is arranged to at the peripheral areas of resonating element 110. In certain embodiments, the trimming layer 101 is arranged in all sides (at peripheral areas) of the (rectangular) resonating element 110. In certain embodiments, the trimming layer 101 is arranged in both opposite sides (ends) of the (rectangular) resonating element 110. In certain embodiments, the trimming layer 101 is arranged on the same (or similar) areas of the resonating element 110 as the contact holes 112. In certain embodiments, where the resonating element 110 comprises trimming layer 101, there are also contact holes 112.

[0128] In certain alternative embodiments, the trimming layer 101 is arranged to cover (most of the) resonating element 206’ uniformly.

[0129] Fig. 3 schematically shows a cap wafer of the packaged semiconductor device on a side facing the resonating element 110 (facing the enclosure) in a top view according to an example embodiment. Fig. 4 schematically shows a cap wafer of the packaged semiconductor device on a side facing outside of the packaged apparatus in a top view according to an example embodiment. Fig. 4 depicts the packaged apparatus from above.

[0130] Accordingly, there is provided a packaged semiconductor apparatus, comprising at least one semiconductor device 100 of the first aspect or any of its embodiments. In certain embodiments, the packaged semiconductor apparatus is a wafer-level packaged, WLP, apparatus, wherein a cap wafer and the device wafer are bonded together via thermocompression bonding. In certain embodiments, the packaged semiconductor apparatus comprises an enclosure, formed by the cap wafer and the device wafer bonded together. Referring also to Fig. 1A, in certain embodiments, the device wafer comprises the handle wafer portion 107 and the device wafer portion 101, 102, 103, 104, 105. In certain embodiments, the handle wafer portion 107 and the device wafer portion 101, 102, 103, 104, 105 are separated from one another by a buried oxide layer 106. In certain embodiments, a cavity 108 is arranged in between the handle wafer portion 107 and the device wafer portion 101, 102, 103, 104, 105 (the cavity being at least underneath the resonating element 110).

[0131] In certain embodiments, the packaged semiconductor apparatus comprises at least one semiconductor device 100. In certain embodiments, the packaged semiconductor apparatus comprises a plurality of semiconductor devices 100. In certain embodiments, the semiconductor device(s) 100 recite in the enclosure. In certain embodiments, the enclosure is in vacuum.

[0132] As shown in Fig. 3, in certain embodiments, the cap wafer of the packaged semiconductor apparatus comprises a recess 302. In certain embodiments, the recess 302 is arranged on the cap wafer inside the enclosure, and facing the resonating element 110 (on the inner surface of the cap wafer). In certain embodiments, the recess 302 is arranged vertically above the resonating element 110 (the resonating element 110 being arranged on the device wafer). In certain embodiments, the recess 302 is a thinner material portion (etched cavity-type) than the rest of the cap wafer. In certain embodiments, the recess allows space for the resonating element 110 within the enclosure.

[0133] In certain embodiments, the cap wafer comprises a sealing ring 20T for bonding the cap wafer and the device wafer (the device wafer comprising also a sealing ring 201). In certain embodiments, the sealing ring 20T is arranged on the cap wafer inside the enclosure, and facing the resonating element 110 (on the inner surface of the cap wafer). In certain embodiments, the sealing ring is formed of two counterparts 201 and 201’, one being on the device wafer (sealing ring 201) and one being on the cap wafer (sealing ring 201’). In certain embodiments, the two counterparts 201, 201’ of the sealing ring are configured to merge with each other upon bonding. In certain embodiments, the sealing rings 201, 20T is of gold. In these embodiments, the bonding is Au-Au thermocompression bonding. In certain embodiments, the sealing ring 201, 201’ is configured to provide a hermetical seal for the packaged semiconductor apparatus.

[0134] In certain embodiments, the cap wafer comprises cap contact pads XIN-CAP, XOUT-CAP, XTRIM-CAP (on the inner surface of the cap wafer). In certain embodiments, the cap contact pads XIN-CAP, XOUT-CAP, XTRIM-CAP are arranged on the cap wafer inside the enclosure (facing the resonating element 110), as shown in Fig. 3.

[0135] In certain embodiments, the cap wafer comprises external contact pads XIN-EXT, XOUT-EXT, XTRIM-EXT (on the outer surface of the cap wafer). In certain embodiments, the external contact pads XIN-EXT, XOUT-EXT, XTRIM-EXT are arranged on the external surface of the packaged semiconductor apparatus, as shown in Fig. 4.

[0136] In certain embodiments, the external contact pads XIN-EXT, XOUT-EXT, XTRIM-EXT are coupled by through silicon vias 301 (through the cap wafer) to the cap contact pads XIN-CAP, XOUT-CAP, XTRIM-CAP of the semiconductor device 100. In certain embodiments, the external contact pads XIN-EXT, XOUT-EXT, XTRIM-EXT are configured to provide electric and mechanical contact from outside into the semiconductor device (through the cap wafer). In certain embodiments, the cap contact pads XIN-CAP, XOUT-CAP, XTRIM-CAP are configured to provide electric and mechanical contact from the cap wafer to the semiconductor device.

[0137] In certain embodiments, the cap contact pads XIN-CAP, XOUT-CAP, XTRIM are coupled to the contact points XIN, XOUT, XTRIM (within the enclosure). In certain embodiments, the cap contact pads XIN-CAP, XOUT-CAP, XTRIM-CAP are configured to contact the contact points XIN, XOUT, XTRIM upon bonding. In certain embodiments, the cap contact pads XIN-CAP, XOUT-CAP, XTRIM-CAP and the contact points XIN, XOUT, XTRIM are arranged vertically atop each other (corresponding locations on the device wafer and the cap wafer such that each of them touch the respective counterpart once the package is formed by bonding).

[0138] In certain embodiments, the contact points XIN, XOUT, XTRIM are coupled to through silicon vias 301, the through silicon vias 301 being formed between the cap contact pads XIN-CAP, XOUT-CAP, XTRIM-CAP and the external contact pads XIN-EXT, XOUT-EXT, XTRIM-EXT. In certain embodiments, the electrical contact to the semiconductor device 100 is provided from external contact pads XIN-EXT, XOUT-EXT, XTRIM-EXT via though silicon vias 301 to the cap contact pads XIN-CAP, XOUT-CAP, XTRIM-CAP and thereafter to the contact points XIN, XOUT, XTRIM.

[0139] In certain embodiments, the external contact pads XIN-EXT, XOUT-EXT, XTRIM-EXT enable wirebonding and / or soldering of the packaged semiconductor device. In certain embodiments, the external contact pads XIN-EXT, XOUT-EXT, are wirebonded to measure (detect, sense, determine) the resonance frequency for providing the parameter of interest. In certain embodiments, the external contact pad XTRIM-EXT is wirebonded to trim the semiconductor device 100.

[0140] In certain embodiments, the cap wafer of the packaged semiconductor apparatus comprises a redistribution layer, wherein the redistribution layer is arranged on the cap wafer inside the enclosure and facing the resonating element (inner surface of the cap wafer). In certain embodiments, the redistribution layer is of gold. In certain embodiments, the redistribution layer is patterned to form the sealing ring 20T and the cap contact pads XIN-CAP, XOUT-CAP, XTRIM-CAP on the cap wafer (on the inner surface of the cap wafer).

[0141] Fig. 5A schematically shows a semiconductor device 100 in a top view according to another example embodiment. Fig. 5A shows a semiconductor device 100 similar as shown in Fig.

[0142] 2A, but with certain alternative embodiments. As shown in Fig. 5A, in certain embodiments, the XTRIM trace 202 and the XIN trace 204 are routed via the same anchoring point 208 of the resonating element 110. In certain embodiments, one anchoring point 208 is used for XTRIM trace 202 and the XIN trace 204 routing.

[0143] In certain embodiments, the contact holes 112 are arranged at zone of high strain of the resonating element 110. In certain embodiments, the contact holes 112 are arranged at central area (non-peripheral) of the resonating element 110. In certain embodiments, the contact holes 112 are arranged in horizontal lines along the (central) x-axis of the resonating element 110. As shown in Fig. 5A, the contact holes 112 are arranged at the centre of each beam element 206 of the resonating element 110. In certain embodiments, the contact holes 112 are arranged symmetrically within the resonating element 110 (the axis of symmetry running in y-direction in the middle of the resonating element 110). In certain embodiments, current and interdiffusion modulate the local strain (maximise the modulation of spring) to tune the resonance frequency of the resonating element 110.

[0144] As shown in Fig. 5A, in certain embodiments, the trimming layer 101 uniformly covers the resonating element 110. In certain embodiments, the trimming layer 101 covers essentially the entire resonating element 110.

[0145] Fig. 5B schematically shows a semiconductor device 100 in a side view according to another example embodiment. Fig. 5B shows a semiconductor device 100 similar as shown in Fig. 1A, but with certain alternative embodiments.

[0146] In certain alternative embodiments, the resonating element 110 comprises UHD contact holes 112 (should not be confused with silicon contact holes 111). As shown in Fig. 5B, in certain embodiments, the trimming layer 101 and an UHD silicon layer 105 of the resonating element 110 are connected (coupled) via UHD contact holes 112. In certain embodiments, the contact holes provide electric contact from one conductive layer to the UHD silicon layer 105 (and vice versa). In certain embodiments, the doping level of the UHD silicon is above 1019cm-3, such as above 102° cm-3.

[0147] In certain embodiments, the UHD contact holes 112 are etched through the piezoelectric layer 104 (and through the top electrode layer 103, the dielectric layer 102, and the trimming layer 101) to reach the UHD silicon layer 105. In certain embodiments, the UHD contact holes 112 are filled with the trimming layer 101 material and the top electrode layer 103 material. In certain embodiments, the UHD contact holes 112 are filled such that the top electrode layer 103 material is beneath the trimming layer 101 material. In certain embodiments, the top electrode layer 103 material is in contact with (reaches) the UHD silicon layer 105. In certain embodiments, dielectric layer 102 material is patterned around the UHD contact hole 112 such that it disconnects the top electrode layer 103 material inside the UHD contact hole 112 from the actual top electrode layer 103. In certain embodiments, the trimming layer 101 is connected to the top electrode layer 103 material inside the UHD contact hole 112 via an etched gap in the dielectric layer 102. This is shown in Fig. 5B. In certain embodiments, the UHD contact holes 112 are configured to enable interdiffusion between the UHD silicon layer 105, the top electrode layer 103 and the trimming layer material 101. In certain embodiments, atoms of the material layers diffuse between the layers via interdiffusion (upon heating).

[0148] Fig. 5C schematically shows a semiconductor device 100 in a side view according to yet another example embodiment. Fig. 5C shows a semiconductor device 100 similar as shown in Fig. 1 A and Fig. 5B, but with certain yet alternative embodiments.

[0149] As shown in Fig. 5C, in certain embodiments, the trimming layer 101 and an UHD silicon layer 105 are connected via UHD contact holes 112. In certain embodiments, the UHD contact holes 112 are etched through the piezoelectric layer 104 (and through the top electrode layer 103, the dielectric layer 102, and the trimming layer 101) to reach the UHD silicon layer 105. In certain embodiments, the UHD contact holes 112 are filled with the trimming layer 101 material. In certain embodiments, the trimming layer 101 material is in contact with (reaches) the UHD silicon layer 105. In certain embodiments, dielectric layer 102 material is patterned around the UHD contact hole 112 such that it disconnects the trimming layer 101 material inside the UHD contact hole 112 from the top electrode layer 103. This is shown in Fig. 5C. In certain embodiments, the UHD contact holes 112 are configured to enable interdiffusion between the UHD silicon layer 105 and the trimming layer material 101. In certain embodiments, when the contact hole 112 connects to the silicon layer 105, the electric current is applied between XTRIM and XOUT.

[0150] Fig. 6 schematically shows method steps for trimming a semiconductor device according to an example embodiment. There is provided a method fortrimming a semiconductor device, the method comprising providing a semiconductor device of the first aspect of any of its embodiments 601, and applying current to the contact holes 602, to trim the resonance frequency of the semiconductor device 603.

[0151] In certain embodiments, applying current to contact holes 602 comprises applying current to a contact point XTRIM. In certain embodiments, applying current to the contact holes 602 heats the contact holes (Joule heating). In certain embodiments, applying current to the contact holes 602 initiates interdiffusion to trim the resonance frequency of the semiconductor device 603. In certain embodiments, atoms of material layers connected by the contact holes diffuse between the layers via interdiffusion. In certain embodiments, the interdiffusion is driven by temperature increase of the contact holes. In certain embodiments, the temperature increase of the contact holes is provided by current being applied in between the material layers connected by the contact holes. In certain embodiments, the selectively initiated interdiffusion creates frequency differences to trim the resonance frequency of the semiconductor device 603.

[0152] In certain embodiments, applying current to the contact holes 602 comprises providing current via a route. In certain embodiments, said route is formed by external contact pads coupled to TSVs, the TSVs connected to cap contact pads, and the cap contact pads connected to contact points of the semiconductor device. In certain embodiments, the contact points of the semiconductor device are coupled to the contact holes.

[0153] Without limiting the scope and the interpretation of the patent claims, certain technical effects of one or more of the example embodiments disclosed herein are listed in the following. A technical effect is avoiding frequency drift of the semiconductor device.

[0154] Typically, when resonators are trimmed prior to packaging, the characteristics of the device may be negatively impacted. Namely, the resonance frequency of the device may change after wafer packaging. By way of example, the trimming may be performed precisely to target prior to packaging, but then the resonance frequency shifts after the packaging (in particular, after wafer bonding). Thus, a technical effect of the instant solution is providing means to correct the shifted resonance frequency after device packaging.

[0155] Additionally, further harmful frequency drift may be caused by trimming prior to packaging of the semiconductor device. By way of an example, trimming the frequency of the device via Ion Beam Trimming (IBT) before packaging may cause such harmful frequency drift. Thus, a technical effect is enabling trimming of the resonator device post wafer level packaging (WLP), and thereby causing little to no impact on the characteristics, such as electrical characteristics of the device.

[0156] A further technical effect is avoiding or reducing top electrode material reflowing issues due to passivating the top electrode material by the dielectric layer. Similarly, a further technical effect is avoiding or reducing top electrode material ageing due to passivating the top electrode material by the dielectric layer.

[0157] A further technical effect is reducing the top electrode material needed. Namely, the top electrode metal thickness is preferably kept to minimal thickness. In certain embodiments, a top electrode thickness in the range of 50 nm to 500nm is preferred. This alleviates possible ageing and / or reflow problems of the top electrode material layer. The top electrode material layer does not need to be high density (to the contrary, when top electrode material layer is also trimming material layer, the top electrode material layer should be high density and significant thickness for trimming purposes). This enables more flexibility in the design of the device.

[0158] A further technical effect is allowing decoupling of trimming layer and top electrode layer functions. Conventionally, if same material layer is used both for top electrode and for trimming, this particular material must meet the requirements of both simultaneously. Namely, in accordance with certain embodiments of the present disclosure, the trimming layer does not need to be highly conductive, thick or cover most of the resonating element area. This enables more flexibility in the design of the device.

[0159] In accordance with certain embodiments, a further technical effect is providing a more positive temperature coefficient of frequency, TCF, for the semiconductor device. In certain embodiments, the dielectric layer enables tuning of TCF. By varying the thickness of the dielectric layer, preferably a dielectric layer of SiC>2, the TCF of the device can be tuned.

[0160] A further technical effect is enabling varying the heating of the contact hole(s), such as via a laser, to control the elasticity of the top electrode. This has an effect on the resonator spring. Thereby, a further technical effect is controlling the resonator spring.

[0161] A further technical effect is enabling clean trimming process, so-called zero-debris trimming. A further technical effect is improved frequency stability control, provided by the interdiffused contact holes. Specifically, the contact holes having different grain size and / or breaking the continuity of the layer(s) in x- and y-directions enable providing improved frequency stability control.

[0162] Various embodiments have been presented. It should be appreciated that in this document, words comprise, include, and contain are each used as open-ended expressions with no intended exclusivity.

[0163] The foregoing description has provided by way of non-limiting examples of particular implementations and embodiments a full and informative description of the best mode presently contemplated by the inventors for carrying out the invention. It is however clear to a person skilled in the art that the invention is not restricted to details of the embodiments presented in the foregoing, but that it can be implemented in other embodiments using equivalent means or in different combinations of embodiments without deviating from the characteristics of the invention. Furthermore, some of the features of the afore-disclosed example embodiments may be used to advantage without the corresponding use of other features. As such, the foregoing description shall be considered as merely illustrative of the principles of the present invention, and not in limitation thereof. Hence, the scope of the invention is only restricted by the appended patent claims.

Claims

CLAIMS1. A semiconductor device (100), comprisinga resonating element (110) having a top electrode layer (103), a dielectric layer (102) on top of the top electrode layer (103), and a trimming layer (101) on top of the dielectric layer (102),wherein the top electrode layer (103) and the trimming layer (101) are electrically connected via contact hole(s) (112).

2. The semiconductor device (100) of claim 1, wherein the contact hole(s) (112) are configured to enable interdiffusion between the top electrode layer (103) material and the trimming layer (101) material.

3. The semiconductor device (100) of claim 1 or 2, wherein the top electrode layer (103) is of high conductivity material having conductivity in the range of 104to 108S / m.

4. The semiconductor device (100) of any preceding claim, wherein the trimming layer (101) is of a high-density material having density at least 10 g / cm3.

5. The semiconductor device (100) of any preceding claim, wherein the trimming layer (101) is patterned to cover the resonating element (110) only partially, such as the trimming layer (101) is patterned to cover peripheral areas of the resonating element (110).

6. The semiconductor device (100) of any of claims 1-4, wherein the trimming layer (101) uniformly covers the resonating element (110).

7. The semiconductor device (100) of any preceding claim, comprising a silicon layer (105), preferably UHD doped silicon layer, below the top electrode layer (103).

8. The semiconductor device (100) of claim 8, wherein the silicon layer and the trimming layer (101) are electrically connected via contact hole(s) (112) to enable interdiffusion between the silicon layer (105) and the trimming layer (101) materials.

9. The semiconductor device (100) of any preceding claim, comprising contact points XIN, XOUT, XTRIM, coupled to through silicon vias connected to external pads XIN-EXT, XOUT-EXT, XTRIM-EXT.

10. The semiconductor device (100) of claim 10, wherein two of the contact points XIN, XOUT are for sensing a parameter of interest, and two of the contact points XIN, XTRIM are for providing mechanical and electric contact to the trimming layer (101).

11. The semiconductor device (100) of claim 10 or 11, wherein two of the contact points XTRIM, XIN are for trimming the resonance frequency of the resonating element (110) by providing mechanical and electric contact to the trimming layer (101).

12. The semiconductor device (100) of any preceding claim, wherein the top electrode layer (103) of the semiconductor device (100) comprises a multilayer top electrode.

13. The semiconductor device (100) of any preceding claim, wherein the semiconductor device (100) is a microelectromechanical systems, MEMS, resonator device.

14. A packaged semiconductor apparatus, comprising at least one semiconductor device (100) according to any of claims 1-13.

15. A method for trimming a semiconductor device (100), the method comprising providing a semiconductor device (100) according to any of claims 1-13; and applying current to the contact hole(s) (112) to trim the resonance frequency of the semiconductor device (100).

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