Quantum control interface for external compute resources

Abstract

This disclosure provides a quantum control system designed to enable low-latency, high-performance communication between quantum processors and classical computing resources. The system integrates optical interconnects, high-speed PCIe-based interfaces and flexible data packet structures to support Quantum Error Correction (QEC), gate calibration, and real-time optimization. The architecture allows independent scaling of quantum and classical resources, promoting adaptability and high-throughput performance.

Description

Attorney Docket No. 68667WO01QUANTUM CONTROL INTERFACE FOR EXTERNAL COMPUTE RESOURCESCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 720,325 entitled “QUANTUM CONTROL INTERFACE FOR EXTERNAL COMPUTE RESOURCES” filed November 14, 2024, and U.S. Patent Application 19 / 257,012 entitled “QUANTUM CONTROL INTERFACE FOR EXTERNAL COMPUTE RESOURCES” filed July 1, 2025, which is hereby incorporated herein by reference in its entirety.Attorney Docket No. 68667WO01BACKGROUND

[0002] Limitations and disadvantages of traditional interfaces will become apparent to one of skill in the art, through comparison of such approaches with some aspects of the present method and system set forth in the remainder of this disclosure with reference to the drawings.Attorney Docket No. 68667WO01BRIEF SUMMARY

[0003] Systems and methods herein provide a quantum control interface for external compute resources, substantially as illustrated by and / or described in connection with at least one of the figures, as set forth more completely in the claims.Attorney Docket No. 68667WO01BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 illustrates an example system comprising a quantum control interface, in accordance with various example implementations of this disclosure.

[0005] FIG. 2 illustrates an example low-latency communication interface structure, in accordance with various example implementations of this disclosure.

[0006] FIG. 3 illustrates example data transfer protocol, in accordance with various example implementations of this disclosure.

[0007] FIG. 4 illustrates an example server comprising a quantum control interface, in accordance with various example implementations of this disclosure.

[0008] FIG. 5 illustrates an example communication from a quantum system to a classical resource to, in accordance with various example implementations of this disclosure.

[0009] FIG. 6 illustrates an example communication from a classical resource to a quantum system, in accordance with various example implementations of this disclosure.Attorney Docket No. 68667WO01DETAILED DESCRIPTION

[0010] The following discussion provides various examples that are non-limiting. The scope of the appended claims should not be limited to the particular examples disclosed. In the following discussion, the terms “example” and “e.g.” are non-limiting.

[0011] The figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. In addition, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of the examples discussed in the present disclosure. The same reference numerals in different figures denote the same elements.

[0012] The term “or” means any one or more of the items in the list joined by “or”. As an example, “x or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0013] The terms “comprises,” “comprising,” “includes,” and / or “including,” are “open ended” terms and specify the presence of stated features, but do not preclude the presence or addition of one or more other features.

[0014] The terms “first,” “second,” etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element discussed in this disclosure could be termed a second element without departing from the teachings of the present disclosure.

[0015] Unless specified otherwise, the term “coupled” may be used to describe two elements directly contacting each other or describe two elements indirectly connected by one or more other elements. For example, if element A is coupled to element B, then element A can be directly contacting element B or indirectly connected to element B by an intervening element C. Similarly, the terms “over” or “on” may be used to describe twoAttorney Docket No. 68667WQ01elements directly contacting each other or describe two elements indirectly connected by one or more other elements.

[0016] Quantum computing demands high-speed, low-latency classical computations to support operations such as error correction, calibration and optimization. Traditional data transfer interfaces, such as TCP / IP, introduce excessive latency, preventing realtime performance. A low-latency communication system connecting quantum control processors to classical resources is essential to ensure fast, accurate quantum processing.

[0017] The disclosed system introduces a Quantum Control Interface Card (QCIC), enabling high-speed, low-latency communication between quantum controllers and classical resources (e.g., CPUs, GPUs, FPGAs, ASICs). The QCIC supports bidirectional dataflow, pre-mapped memory buffers, and software-defined packet structures, ensuring adaptable data handling. The architecture scales independently across quantum control units and classical accelerators, ensuring performance remains uncompromised.

[0018] FIG. 1 illustrates an example system comprising a quantum control interface, in accordance with various example implementations of this disclosure. The system of FIG. 1 comprises a quantum control system (QCS) 101, an interface device 105 and a classical computation resource (OCR) 107. The system of FIG. 1 may be scalable to comprise a plurality of QCSs 101 and / or a plurality of OCRs 107.

[0019] QCS 101 may comprise one or more pulse generation circuits. Each pulse generation circuit may be configured to transfer a pulse signal to a quantum processing unit (QPU) 103 and acquire a state determination signal from a qubit of the QPU 103. The QPU 103 may comprise a plurality of qubits.

[0020] The classical computation resource (CCR) 107 may comprise one or more of a central processing (CPU), a graphics processing unit (GPU), a hardware accelerator, and associated memory 109. The hardware accelerator may comprise a field programmable gate arrays (FPGA) and / or an application-specific integrated circuit (ASIC). A GPU in the CCR 107 may be configured as a multi-instance GPU (MIG).Attorney Docket No. 68667WQ01

[0021] The interface device 105 of FIG. 1 is operably coupled to the QCS 101 and the CCR 107. The interface device 105 may comprise a field programmable gate arrays (FPGA) and / or an application-specific integrated circuit (ASIC). The interface device 105 may be configured to manage direct communication between the QCS 101 and the CCR 107, without involvement of software components in the CCR 107. As the latency of standard Ethernet interfaces is too high for such tasks, the disclosed system incorporates a low-latency communication interface to address this bottleneck.

[0022] Some calculations related to quantum computing (e.g., quantum error correction (QEC), quantum gate calibration, and optimization loops) may require the CCR 107 to perform specific computation tasks. For example, QEC comprises microsecondlevel syndrome decoding with teraflop-to-petaflop computing power, quantum gate calibration comprises reinforcement learning and Bayesian filtering to ensure high-fidelity gate performance, and optimization loops require quantum control parameters to be iteratively refined. For some quantum calculations, the data transferred from the QCS 101 comprises discriminated measurement data and / or an indication of measurement fidelity.

[0023] The CCR 107 may also be configured to transfer data to the QCS 101. For example, data destined for the QCS 101 may be transferred to a component interface of the interface device 105.

[0024] When the system comprises a plurality of QCSs 101 and / or a plurality of CCRs 107. Data may be transferred through the interface device 105, via a bus and / or a switch. The interface device 105 may also be configured to communicate with the CCR 105 and / or QCS 101 using time division multiple access (TDMA). The system architecture accommodates high-performance computing (HPC) clusters as part of the CCR 107 infrastructure, promoting scalability and enhanced processing capabilities.

[0025] When the quantum control system scales to multiple controllers and multiple pulse processors, each pulse processor may communicate and pass information and variables with each other pulse processor.

[0026] The interface device 105 and the CCR 107 may be elements of a single server. Alternatively, the CCR 107 may comprise the interface device 105.Attorney Docket No. 68667WQ01

[0027] FIG. 2 illustrates an example low-latency communication interface structure, in accordance with various example implementations of this disclosure.

[0028] The interface device 105 is connected to Peripheral Component Interconnect Express (PCIe) 207 on one end and an ultra-low latency, high bandwidth interface (e.g., optical) 203 on the other end.

[0029] The optical interface 203 may be directly connected to a PPU (Pulse Processing Unit) on the QCS 101. This allows low-latency data transfer in quantum realtime. The optical interface 203 may be connected to the QCS 101 , via and optical cable, through a transceiver. The QCS 101 and the interface device 105 may be implemented on FPGAs.

[0030] The optical interfaces input buffers 211 may move data bi-directionally (full duplex), and also asynchronously between the interface device 105 and the QCS 101. Since the rate of PCIe 207 may be faster than the optical interface 203, there may be cases where packets are sent faster from the server than what can be sent over the optical link 203. Therefore, optical interfaces input buffers 211 may hold packets in a FIFO queue, and those packets may be sent out as quickly as possible.

[0031] A data aggregation and manipulation block 215 receives chunks of packets from the PCIe 207 and aggregates them to a single packet. Aggregation into a single packet may be required since the QCS 101 may be a very time-wise deterministic system that cannot wait an unknown time for chunks to arrive. Thus, the packet may be received whole. The data aggregation and manipulation block 215 may use block 205 to understand the context of the packet / stream (e.g., understand the destination, populate the meta-data of the packet, etc.).

[0032] Like the input buffers 211 , the PCIe output buffer 219 may provide a backpressure mechanism. Because the rate of the PCIE 207 may be much faster than the interface device 105, packets may be aggregated faster than they can be processed.

[0033] Memory Management 223 may be used when memory on the server is not in contiguous addresses. The user may allocate memory on the user-space, which is a contiguous virtual memory space. However, the underlying physical memory is in units ofAttorney Docket No. 68667WO01'pages', and these pages may be scattered, as handled by the operating system, which may not be controlled. Therefore, the Memory Management block 223 keeps a linked list of DMA descriptors, which enables the interface device 105 to initiate PCIe transfers from the correct location on the server side, even if it is scattered across the physical memory.

[0034] The PCIe -> Control stream contexts block 205 may operate as a database that includes the information required for the interface device 105 to process the data. The PCIe -> Control stream contexts block 205 may comprise, for example, assigned stream-IDs, packet sizes, etc. and may provide the relevant information to the data-path.

[0035] The Control -> PCIe stream contexts block 209 may operate like the PCIe -> Control stream contexts block 205 but for the other direction.

[0036] The PCIe 207 may comprise an FPGA-based PCIe controller that allows high speed serial data transfer to / from the interface device 105 to / from CPU / GPU / FPGA via the server.

[0037] Like the input buffers 211, the optical interfaces output buffers 213 may provide a back-pressure mechanism. Since data may arrive asynchronously, the data may be at a higher rate than the rate in which packets can be processed. Therefore, a FIFO-based queue may keep packets pending to be processed.

[0038] The data manipulation & routing block 217 handles the incoming packets, parses them (e.g., extracts the stream-id) and can then interpret which context this packet belongs to. The data manipulation & routing block 217 can then route the packet to the correct memory buffer on the server.

[0039] Like the PCIe output buffer 219, the PCIe input buffer 221 may provide a back-pressure mechanism in case the PCIe 207 bus is too busy to handle packets from the interface device 105. The idea behind these back-pressure queues is to increase the maximum rate that the interface device 105 can handle as high as possible.

[0040] Like Memory Management 223, the Context Manager 225 extracts the PCIe bus addresses which are required to be used in the PCIe transaction. The user may define virtual buffers, which are then translated to physical pages, and from there mapped toAttorney Docket No. 68667WQ01PCIe bus addresses. These addresses may be stored in this database, which the FPGA uses to map them to a unique stream-id.

[0041] The interface device 105 (FIG 1) may comprise a Quantum Control Interface Card (QCIC) 201 configured to transfer software-defined packet structures that adapt to various data configurations, ensuring flexibility in handling diverse computational needs. The interface device 105 may support a range of high-performance communication protocols, including PCIe, NVLink, Compute Express Link (CXL), Remote Direct Memory Access (RDMA), optical link protocols, direct data exchange pathways with GPUs, InfiniBand, and RDMA over Converged Ethernet (RoCE).

[0042] The QCIC 201 may operate as a network interface card integrated with optical communication 203 capabilities, enabling high-speed data transmission and low-latency performance.

[0043] The QCIC 201 is configured to support direct communication management, which can be configured by the QCS or an independent third-party device. The QCIC 201 may process and rearrange data 215, 217 before transmitting it to the classical computing resource (CCR) via PCIe 207 or the QCS using the optical interface 203, ensuring optimized data handling. The QCIC 201 may validate that both the QCS and the CCR adhere to a common data transfer definition, maintaining synchronization and data integrity. The QCIC 201 may communicate with the CCR using Time Division Multiple Access (TDMA) and write data directly to cyclic buffers (within the CCR) from the PCIe input buffer 221 (of the QCIC 201 ), ensuring efficient data flow management.

[0044] The QCIC 201 may support advanced memory handling techniques, such as writing producer indices to the CCR and enabling nonsequential physical memory writes for flexible data placement. The QCIC interface device 201 may receive incoming data destined for the QCS via locally mapped buffers 219 within the QCIC 201. Upon receiving the data, the QCIC 201 may trigger notifications to an interface component 223, and permit asynchronous (or synchronous) data access, which may accelerate response times. The QCIC 201 may also pre-fetch data from CCR memory, ensuring a continuous data stream for real-time processing.Attorney Docket No. 68667WQ01

[0045] The QCIC 201 may support loading waveform data and extensive parameter tables to the QCS, facilitating high-speed data provisioning essential for quantum operations.

[0046] The QCIC 201 may support independent control of the QCS and CCR programs while maintaining dedicated data communication channels between these components. Control data and the QCS and CCR functions may be transmitted according to an intermediate representation or a multi-level intermediate representation (MLIR), ensuring compatibility across varied processing environments. Bandwidth between the QCS and the interface device may differ from the bandwidth between the interface device and the CCR, allowing adaptable performance tuning. For example, a management packet may be transmitted as 4KB page, while an inlined management packet may return to the QCS as a 32-bit payload.

[0047] The CCR is capable of initiating program execution on the QCS through the QCIC 201, enabling streamlined task delegation and execution. The QCIC 201 supports bidirectional data flow, facilitating both forward and reverse data transfers between QCS and CCR. This comprises direct data transfers to pre-allocated classical memory buffers and reverse data streams from CCR back to the QCS, achieved through direct memory writes or buffer mapping.

[0048] The QCIC 201 may leverage optical interconnects 203 to enable ultra-low-latency communication, supporting high-performance protocols like PCIe, NVLink, CXL, and RDMA to bypass traditional operating system delays. The QCIC 201 may employ software-defined packet formats, adaptable to real-time computational needs, ensuring flexible and efficient data handling. The QCIC 201 may support independent scaling of QCSs and CCRs, ensuring that increased performance demands can be met without bottlenecks. Additionally, the system offers multi-user support with secure, isolated data streams, enabling collaborative quantum-classical processing environments with data management and security measures.

[0049] FIG. 3 illustrates an example server 401 comprising a quantum control interface 106, in accordance with various example implementations of this disclosure.Attorney Docket No. 68667WQ01

[0050] An application for system admins 403 may be used to do a one-time sync of the communication channel (e.g., optical fiber) between the QCIC 105 and the QOP 101. The application for system admins 403 may also be used to upgrade the QCIC FW, etc. The tool communicates with the driver for QCIC access, and through network with the QCS 101 for syncing.

[0051] A kernel space driver 403 for the QCIC 105 may be in charge of the low-level interactions with the QCIC 105, as well as "pinning" the GPU / CPU memories 107 to make sure the physical pages are not swapped.

[0052] The classical computation part 107 runs the algorithm. Data is transferred from the QCIC 105 directly to its designated memory. For GPUs, the QCIC driver 405 may use the GPU Software APIs to map the GPU memory.

[0053] The driver 405 may configure the streams / packets and memory context on the QCIC 105, as well as FPGA specific configurations to sync the communication channel over network.

[0054] The user's application 407 links to a QCIC Software Development Kit (SDK). When the application starts, the hardware is configured via the driver 405 from the user's application 407.

[0055] Direct connection may be achieved between the adapter 105 and the QCS hardware 101 , with no software in between.

[0056] FIG. 4 illustrates an example communication from a quantum system to a classical resource to, in accordance with various example implementations of this disclosure.

[0057] The quantum control system 101 measures and acquires data from the quantum computer's qubits. The parameters are sent over an ultra-low latency physical interface towards the classical computation counterpart 107. Algorithm run on the fast classical computation unit 107 use the qubits' data as input of the algorithm. The physical link can be virtually separated into logical channels, allowing different handling for different types of data. Examples of qubit parameters may include the qubits' state, system properties, and / or signal properties like phase, amplitude, frequencies, noise, etc.Attorney Docket No. 68667WQ01

[0058] FIG. 5 illustrates an example communication from a classical resource to a quantum system, in accordance with various example implementations of this disclosure.

[0059] The results of the algorithm may be sent over an ultra-low latency physical interface towards the QCS 101. Algorithms produce results and / or parameters required to be sent to the QCS 101. Algorithm results may include new quantum-control parameters, new signal characteristics, error-corrected qubit state, etc. Results from the classical computation counterpart 107 may also be sent to devices other than the QCS 101.

[0060] As used herein the terms “circuits” and “circuitry” refer to physical electronic components (i.e. hardware) and any software and / or firmware (“code”) which may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code and may comprise a second “circuit” when executing a second one or more lines of code. As used herein, “and / or” means any one or more of the items in the list joined by “and / or”. As an example, “x and / or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, "x, y, and / or z” means any element of the seven-element set {(x), (y), (z), ( x, y), (x, z), (y, z), (x, y, z)}. As used herein, the term “exemplary” means serving as a non-limiting example, instance, or illustration. As used herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations. As used herein, circuitry is “operable” to perform a function whenever the circuitry comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled or not enabled e.g., by a user-configurable setting, factory trim, etc.). As used herein, the term "based on" means "based at least in part on." For example, "x based on y" means that "x" is based at least in part on "y" and may also be based on z, for example.

[0061] While the present method and / or system has been described with reference to certain implementations, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present method and / or system. In addition, many modifications may be madeAttorney Docket No. 68667WO01to adapt a particular situation or material to the teachings of the present disclosure without departing from its scope. Therefore, it is intended that the present method and / or system not be limited to the particular implementations disclosed, but that the present method and / or system will include all implementations falling within the scope of the appended claims.

Claims

Attorney Docket No. 68667WQ01CLAIMSWhat is claimed is:

1. A system comprising:a quantum control system (QCS) configured to transfer a pulse signal to a quantum processing unit (QPU) and acquire a state determination signal from a qubit of the QPU;a classical computation resource (CCR); andan interface device operably coupled to the QCS and the CCR, wherein the interface device is configured to manage direct communication between the QCS and the CCR, without involvement of software components in the CCR.

2. The system of claim 1 , wherein the QCS comprises a pulse generation circuit.

3. The system of claim 1 , wherein the system is scalable to comprise a plurality of QCSs.

4. The system in claim 1 , wherein data transferred from the QCS comprises discriminated measurement data and / or an indication of measurement fidelity.

5. The system of claim 1 , wherein the system is configured for quantum error correction (QEC) decoding and / or calibration.

6. The system of claim 1 , wherein the system is scalable to comprise a plurality of CCRs operably coupled to the interface device via a bus and / or a switch.

7. The system of claim 1 , wherein the CCR is configured to transfer data, destined for the QCS, to a component interface of the interface device.Attorney Docket No. 68667WQ018. The system of claim 1, wherein the CCR comprises one or more of a central processing (CPU), a graphics processing unit (GPU), a field programmable gate arrays (FPGA), an application-specific integrated circuit (ASIC), and a hardware accelerator.

9. The system of claim 1 , wherein the CCR comprises a GPU configured as a multiinstance GPU (MIG).

10. The system of claim 1 , wherein the interface device is configured to transfer a software-defined packet structure adaptable to varying data configurations.

11. The system of claim 1, wherein the interface device is configured to support at least one of a peripheral component interconnect express (PCIe) protocol, an NVLink protocol, a compute express link (CXL) protocol, a remote direct memory access (RDMA) protocol, an optical link protocol, a direct path for data exchange with a GPU, an InfiniBand protocol, and an RDMA over Converged Ethernet (RoCE) protocol.

12. The system of claim 1 , wherein the interface device comprises a network interface card (NIC).

13. The system of claim 1, wherein the interface device comprises a PCIe network interface card with optical links.

14. The system of claim 1, wherein the interface device is connected to a plurality of QCSs.

15. The system of claim 1 , wherein:the interface device is configured to aggregate data from a plurality of QCSs, and the interface device is configured to distributes data sent to the a plurality of QCSs.Attorney Docket No. 68667WQ0116. The system of claim 1, wherein the management of the direct communication by the interface device in configured by the QCS and / or a third-party device.

17. The system of claim 1 , wherein the interface device is configured to process and / or rearrange data prior to sending it to the CCR and / or the QCS.

18. The system in claim 1 , wherein the interface device is configured to validate that the QCS and the CCR communicate according to a common definition of transferred data.

19. The system in claim 1 , wherein the interface device is configured to communicate with the CCR according to time division multiple access (TDMA).

20. The system of claim 1 , wherein the interface device is configured to write data to a cyclic buffer of the CCR.

21. The system in claim 1 , the interface device is configured to write a producer index to the CCR.

22. The system in claim 1 , wherein the interface device is configured write to nonsequential physical addresses in memory on the CCR.

23. The system of claim 1 , wherein the interface device is configured to:receive data, destined for the QCS from CCR, via a local buffer mapped to an interface component,notify the interface component, andallow a-synchronous access to the data.

24. The system in claim 1 , wherein the interface device is configured to pre-fetch data from memory of the CCR.Attorney Docket No. 68667WQ0125. The system of claim 1 , wherein the CCR comprises the interface device.

26. The system of claim 1 , wherein the interface device is configured to load waveform data and / or large parameter tables to the QCS.

27. The system of claim 1, wherein a high-performance computation (HPC) cluster comprises the CCR.

28. The system of claim 1 , wherein the system is configured to communicate a control of the QCS and / or a CCR program, while the interface device communicates data to the QCS and / or the CCR.

29. The system of claim 1 , wherein a control of the QCS and / or a CCR program are communicated according to an intermediate representation.

30. The system of claim 1 , wherein a control of the QCS and / or a CCR program are communicated according to a multi-level intermediate representation (MLIR).

31. The system of claim 1 , wherein a bandwidth between the QCS and the interface device is different than a bandwidth between the interface device and the CCR.

32. The system of claim 1 , wherein the CCR is configured to initiate an execution of a program on the QCS, via the interface device.

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