Semiconductor device and method for producing same

Abstract

The present invention suppresses latch-up in an IGBT provided with an n-type emitter region and a p-type contact region in contact with a gate insulating film. In this semiconductor device, a semiconductor substrate has an n-type emitter region and a p-type contact region in contact with a gate insulating film on the side surface of a first trench. The semiconductor substrate has a p-type body region in contact with the gate insulating film on the side surface of the first trench below the emitter region and the contact region. The body region has a peak value in a p-type impurity concentration distribution in the depth direction. When a value obtained by integrating from the depth of the peak value to the depth of the lower end of the first trench in an n-type impurity concentration distribution in the depth direction in the semiconductor substrate is defined as a first n-type integrated value, the first n-type integrated value directly below the emitter region is higher than the average value of first n-type integrated values in semiconductor layers between trenches.

Description

Semiconductor Device and Method for Manufacturing the Same

[0001] (Cross-reference to Related Applications) This application is a related application of Japanese Patent Application No. 2024-200817 filed on November 18, 2024, claims priority based on this Japanese patent application, and incorporates all the contents described in this Japanese patent application as constituting this specification.

[0002] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

[0003] Japanese Patent Publication No. 2001-308328 (hereinafter referred to as Patent Document 1) discloses an insulated gate bipolar transistor. Hereinafter, the insulated gate bipolar transistor may be referred to as an IGBT (abbreviation for Insulated Gate Bipolar Transistor). In the IGBT of Patent Document 1, a p-type high-concentration region is provided below the p-type contact region. The p-type high-concentration region is formed so as not to contact the trench gate. By providing the p-type high-concentration region, the on state of the parasitic thyristor (that is, the latch-up of the IGBT) is suppressed.

[0004] In a trench gate type IGBT, a structure in which an n-type emitter region and a p-type contact region are provided adjacent to each other in a range contacting the gate insulating film is known. In the IGBT of this structure, since the p-type contact region contacts the gate insulating film, if a p-type high-concentration region is provided below the p-type contact region, the p-type high-concentration region contacts the gate insulating film. When the p-type high-concentration region contacts the gate insulating film, the gate threshold value of the IGBT becomes extremely high. Therefore, in the IGBT of this structure, it is difficult to adopt the technology of Patent Document 1. In this specification, a technology for suppressing latch-up is proposed in a trench gate type IGBT in which an n-type emitter region and a p-type contact region are provided adjacent to each other in a range contacting the gate insulating film.

[0005] The semiconductor device disclosed herein comprises a semiconductor substrate, a gate insulating film, a gate electrode, and an emitter electrode. The semiconductor substrate is a semiconductor substrate having a plurality of trenches on its upper surface, wherein the plurality of trenches on the upper surface extend elongated in a first direction. The gate insulating film covers the inner surface of the trenches. The gate electrode is disposed within the trenches and is insulated from the semiconductor substrate by the gate insulating film. The emitter electrode covers the upper surface. The plurality of trenches include a first trench and a second trench. The semiconductor layer between the first trench and the second trench is an inter-trench semiconductor layer. The semiconductor substrate has an emitter region, a contact region, a body region, a drift region, and a collector region. The emitter region is an n-type region provided within the inter-trench semiconductor layer, in contact with the emitter electrode, and in contact with the gate insulating film on the side surface of the first trench. The contact region is a p-type region located within the inter-trench semiconductor layer, in contact with the emitter electrode, in contact with the gate insulating film on the side surface of the first trench, and in contact with the emitter region in the first direction. The body region is located within the inter-trench semiconductor layer, in contact with the emitter region and the contact region from below, in contact with the gate insulating film on the side surface of the first trench below the emitter region and the contact region, and is a p-type region having a lower p-type impurity concentration than the contact region. The drift region is an n-type region located below the body region and in contact with the gate insulating film on the side surface of the first trench below the body region. The collector region is a p-type region located below the drift region. The body region has a peak value in the p-type impurity concentration distribution in the depth direction. In the n-type impurity concentration distribution in the depth direction within the semiconductor substrate, when the first n-type integral value is defined as the value obtained by integrating from the depth of the peak value to the depth of the lower end of the first trench, the first n-type integral value directly below the emitter region is higher than the average value of the first n-type integral value within the inter-trench semiconductor layer.

[0006] In this semiconductor device, the IGBT is composed of an emitter region, a contact region, a body region, a drift region, a collector region, a gate electrode, etc. In this semiconductor device, the first n-type integral value is high directly below the emitter region, making it difficult for hole current to flow directly below the emitter region. Therefore, when the IGBT turns off, the inflow of holes from the drift region into the emitter region is suppressed, and IGBT latch-up is suppressed. Furthermore, since the impurity concentration below the depth of the peak value of the body region has almost no effect on the gate threshold of the IGBT, the gate threshold can be set to an appropriate value even if the first n-type integral value is high directly below the emitter region.

[0007] Plan view of the semiconductor device of the embodiment. Cross-sectional perspective view of the semiconductor device. Cross-sectional view of the boundary between the IGBT region and the diode region. Cross-sectional view of the semiconductor device along the xz plane. Graph showing the impurity concentration distribution at positions A, B, and C in Figure 4. Cross-sectional view of the semiconductor device along the yz plane at a position including the emitter region. Cross-sectional view of the semiconductor device along the yz plane at a position including the contact region. Cross-sectional view of the semiconductor device along the yz plane at a position including the low-concentration contact region. Explanatory diagram of the method for manufacturing the semiconductor device. Explanatory diagram of the method for manufacturing the semiconductor device. Cross-sectional view of the semiconductor device along the xz plane Cross-sectional view of a semiconductor device along the xz plane. Cross-sectional view of a semiconductor device along the xz plane. Cross-sectional view of a semiconductor device along the xz plane. Cross-sectional view of a semiconductor device along the xz plane. Cross-sectional view of a semiconductor device along the xz plane. Explanatory diagram of a semiconductor device manufacturing method. Explanatory diagram of a semiconductor device manufacturing method. Explanatory diagram of the integral value directly below the emitter region. Explanatory diagram of the integral value in the inter-trench semiconductor layer. Explanatory diagram of the integral value directly below the contact region.

[0008] (Example 1) Figure 1 is a top view of the semiconductor device 10 of Example 1. The semiconductor device 10 has a semiconductor substrate 12. Hereinafter, the direction parallel to the upper surface 12a of the semiconductor substrate 12 will be referred to as the x-direction, the direction parallel to the upper surface 12a and perpendicular to the x-direction will be referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 will be referred to as the z-direction. The semiconductor substrate 12 is made of silicon. However, the semiconductor substrate 12 may be made of other semiconductor materials such as silicon carbide or gallium nitride. An emitter electrode 14 is provided in the center of the upper surface 12a of the semiconductor substrate 12. Multiple IGBT regions 20 and multiple diode regions 22 are provided in the area below the emitter electrode 14 of the semiconductor substrate 12. IGBTs are provided in the IGBT regions 20, and diodes are provided in the diode regions 22. The IGBT regions 20 and diode regions 22 are arranged alternately in the y-direction.

[0009] Figure 2 is a cross-sectional perspective view of the IGBT region 20. Note that the emitter electrode 14 is omitted in Figure 2. Figure 3 is a cross-sectional view of the boundary between the IGBT region 20 and the diode region 22. As shown in Figures 2 and 3, a plurality of trenches 30 are provided on the upper surface 12a of the semiconductor substrate 12 in both the IGBT region 20 and the diode region 22. Each trench 30 extends long in the x direction on the upper surface 12a. The plurality of trenches 30 are spaced apart in the y direction. A gate insulating film 32 and a gate electrode 34 are placed in each trench 30. The gate insulating film 32 covers the inner surface of the trench 30. The gate electrode 34 is insulated from the semiconductor substrate 12 by the gate insulating film 32. The upper surface of the gate electrode 34 is covered by an interlayer insulating film 36. The emitter electrode 14 covers the upper surface 12a of the semiconductor substrate 12 in both the IGBT region 20 and the diode region 22. The emitter electrode 14 is insulated from the gate electrode 34 by an interlayer insulating film 36. A collector electrode 16 is provided on the lower surface 12b of the semiconductor substrate 12. The collector electrode 16 covers the entire lower surface 12b. When the diode in the diode region 22 is operating, the emitter electrode 14 functions as the anode electrode and the collector electrode 16 functions as the cathode electrode.

[0010] As shown in Figure 2, within the IGBT region 20, the semiconductor substrate 12 has a plurality of emitter regions 40, a plurality of contact regions 42, and a plurality of low-concentration contact regions 44. The emitter regions 40 are n-type regions. The contact regions 42 are p-type regions. The low-concentration contact regions 44 are p-type regions having a lower p-type impurity concentration than the contact regions 42. The emitter regions 40, contact regions 42, and low-concentration contact regions 44 are located in the region sandwiched between two trenches 30 (hereinafter referred to as the inter-trench semiconductor layer). The emitter regions 40, contact regions 42, and low-concentration contact regions 44 are located in the surface layer near the upper surface 12a. Along the x-direction, these regions are periodically arranged in the order of emitter region 40, contact region 42, low-concentration contact region 44, contact region 42, and emitter region 40. Therefore, as shown in Figure 4, the contact region 42 is sandwiched between the emitter region 40 and the low-concentration contact region 44 in the x-direction. That is, in the x-direction, the emitter region 40 is in contact with the contact region 42, and the low-concentration contact region 44 is in contact with the contact region 42 from the opposite side of the emitter region 40.

[0011] As shown in Figure 2, the emitter region 40 extends long in the y direction and is in contact with the gate insulating film 32 on the side surface of each trench 30. As shown in Figure 4, the emitter region 40 is in contact with the emitter electrode 14 on its upper surface 12a. Because the n-type impurity concentration in the emitter region 40 is high, the emitter region 40 is in ohmic contact with the emitter electrode 14.

[0012] As shown in Figure 2, the contact region 42 extends long in the y direction and is in contact with the gate insulating film 32 on the side surface of each trench 30. As shown in Figure 4, the contact region 42 is in contact with the emitter electrode 14 on its upper surface 12a. Because the p-type impurity concentration in the contact region 42 is high, the contact region 42 is in ohmic contact with the emitter electrode 14.

[0013] As shown in Figure 2, the low-concentration contact region 44 extends long in the y-direction and is in contact with the gate insulating film 32 on the side surface of each trench 30. As shown in Figure 4, the low-concentration contact region 44 is in contact with the emitter electrode 14 on its upper surface 12a. Because the p-type impurity concentration of the low-concentration contact region 44 is low, the barrier at the interface between the low-concentration contact region 44 and the emitter electrode 14 is high. Therefore, almost no current flows at the interface between the low-concentration contact region 44 and the emitter electrode 14.

[0014] As shown in Figure 2, a p-type body region 46 is provided in the inter-trench semiconductor layer. The p-type impurity concentration in the body region 46 is approximately equal to that of the low-concentration contact region 44 and lower than that of the contact region 42. As shown in Figure 4, the body region 46 is distributed across the lower parts of the emitter region 40, the contact region 42, and the low-concentration contact region 44. The body region 46 is in contact with the emitter region 40, the contact region 42, and the low-concentration contact region 44 from below. Figures 6 to 8 show yz cross-sections at the respective locations of the emitter region 40, the contact region 42, and the low-concentration contact region 44. As shown in Figures 6 to 8, the body region 46 is in contact with the gate insulating film 32 on the lower side surfaces of the trenches 30 of the emitter region 40, the contact region 42, and the low-concentration contact region 44.

[0015] As shown in Figure 2, an intermediate n-type region 48 is provided in the inter-trench semiconductor layer. As shown in Figure 4, the intermediate n-type region 48 is in contact with the body region 46 from below. The intermediate n-type region 48 is distributed across the position directly below the emitter region 40, the position directly below the contact region 42, and the position directly below the low-concentration contact region 44. In this embodiment, the potential of the intermediate n-type region 48 is floating, but the intermediate n-type region 48 may be electrically connected to the emitter electrode 14. As shown in Figures 6 to 8, the intermediate n-type region 48 is in contact with the gate insulating film 32 on the side surface of the trench 30 below the body region 46. As shown in Figure 4, the intermediate n-type region 48 has a first intermediate n-type region 48a and a second intermediate n-type region 48b having a lower n-type impurity concentration than the first intermediate n-type region 48a. The n-type impurity concentration in the first intermediate n-type region 48a is lower than that of the emitter region 40 and higher than that of the second intermediate n-type region 48b. The n-type impurity concentration in the second intermediate n-type region 48b is lower than that of the first intermediate n-type region 48a and higher than that of the drift region 52, which will be described later. The first intermediate n-type region 48a is located directly below the emitter region 40. The second intermediate n-type region 48b is distributed from directly below the contact region 42 to directly below the low-concentration contact region 44. In the x-direction, the width of the first intermediate n-type region 48a is wider than that of the emitter region 40. In the x-direction, the emitter region 40 is located within the width range of the first intermediate n-type region 48a.

[0016] As shown in Figure 2, a lower body region 50 is provided in the inter-trench semiconductor layer. The lower body region 50 has a lower p-type impurity concentration than the body region 46. As shown in Figure 4, the lower body region 50 is in contact with the intermediate n-type region 48 from below. The lower body region 50 is distributed across the position directly below the emitter region 40, the position directly below the contact region 42, and the position directly below the low-concentration contact region 44. The lower body region 50 is separated from the body region 46 by the intermediate n-type region 48. As shown in Figures 6 to 8, the lower body region 50 is in contact with the gate insulating film 32 on the side surface of the trench 30 below the intermediate n-type region 48. As shown in Figure 4, the lower body region 50 has a first lower body region 50a and a second lower body region 50b having a higher p-type impurity concentration than the first lower body region 50a. The p-type impurity concentration in the second lower body region 50b is lower than that in the body region 46, but higher than that in the first lower body region 50a. The first lower body region 50a is located directly below the emitter region 40. The second lower body region 50b is distributed from directly below the contact region 42 to directly below the low-concentration contact region 44.

[0017] As shown in Figure 3, a p-type anode region 57 is provided in the trench semiconductor layer within the diode region 22. The anode region 57 is in ohmic contact with the emitter electrode 14. In addition, similar to the IGBT region 20, a body region 46, an intermediate n-type region 48, and a lower body region 50 are provided below the anode region 57 in the diode region 22. However, in other embodiments, the intermediate n-type region 48 is not provided in the diode region 22, and the region from the anode region 57 to the lower body region 50 may be composed of a continuous p-type region.

[0018] As shown in Figure 3, an n-type drift region 52 is provided below the lower body region 50. The drift region 52 has a lower n-type impurity concentration than the second intermediate n-type region 48b. The drift region 52 is distributed across the IGBT region 20 and the diode region 22. The drift region 52 is in contact with the lower body region 50 from below. The drift region 52 is in contact with the gate insulating film 32 at the side surface and bottom surface of the trench 30 below the lower body region 50.

[0019] As shown in Figure 3, an n-type buffer region 54 is provided below the drift region 52. The buffer region 54 has a higher n-type impurity concentration than the drift region 52. The buffer region 54 is distributed across the IGBT region 20 and the diode region 22. The buffer region 54 is in contact with the drift region 52 from below.

[0020] As shown in Figure 3, a p-type collector region 56 and an n-type cathode region 58 are provided below the buffer region 54. The collector region 56 is located within the IGBT region 20. The collector region 56 is in contact with the buffer region 54 from below. The collector region 56 is in ohmic contact with the collector electrode 16 at its lower surface 12b. The cathode region 58 has a higher n-type impurity concentration than the buffer region 54. The cathode region 58 is located within the diode region 22. The cathode region 58 is in contact with the buffer region 54 from below. The cathode region 58 is in ohmic contact with the collector electrode 16 at its lower surface 12b.

[0021] Next, the impurity concentration distribution in the emitter region 40, contact region 42, low-concentration contact region 44, body region 46, intermediate n-type region 48, lower body region 50, and drift region 52 will be described. Each graph in Figure 5 shows the impurity concentration distribution in the z direction at positions A, B, and C shown in Figure 4. Position A includes the emitter region 40, the first intermediate n-type region 48a, and the first lower body region 50a. Position B includes the contact region 42, the second intermediate n-type region 48b, and the second lower body region 50b. Position C includes the low-concentration contact region 44, the second intermediate n-type region 48b, and the second lower body region 50b. In each graph in Figure 5, the solid line represents the n-type impurity concentration, and the dashed line represents the p-type impurity concentration.

[0022] As shown in the graph at position A, the p-type impurity concentration is extremely low in the emitter region 40. As shown in the graph at position B, the p-type impurity concentration is extremely high in the contact region 42. As shown in the graph at position C, the p-type impurity concentration is lower in the low-concentration contact region 44 than in the contact region 42, and higher than in the emitter region 40. In all of positions A, B, and C, the p-type impurity concentration is distributed in a normal distribution within the body region 46, and a peak value P1 of the p-type impurity concentration is formed within the body region 46. The peak value P1 is approximately equal between positions A, B, and C. In Figure 5, depth D1 is the depth at which the peak value P1 is formed. Also in Figure 5, depth D2 is the depth of the lower end of the trench 30. Depths D1 and D2 are also shown in cross-sectional views such as Figure 4. As shown in Figure 5, in all of positions A, B, and C, the peak value P1 is the maximum value of the p-type impurity concentration in the depth range from depth D1 to depth D2. In other words, in the depth range from depth D1 to depth D2, below depth D1, the p-type impurity concentration is lower than the peak value P1. At all of positions A, B, and C, the p-type impurity concentration in the intermediate n-type region 48 is extremely low. At all of positions A, B, and C, a peak value of p-type impurity concentration is formed within the lower body region 50. The peak value P2a of p-type impurity concentration in the first lower body region 50a is lower than the peak value P2b of p-type impurity concentration in the second lower body region 50b. Also, peak values ​​P2a and P2b are lower than the peak value P1 in the body region 46. At all of positions A, B, and C, the p-type impurity concentration is extremely low within the drift region 52.

[0023] As shown in the graph for position A, the n-type impurity concentration is extremely high within the emitter region 40. As shown in the graphs for positions B and C, the n-type impurity concentration is extremely low within the contact region 42 and the low-concentration contact region 44. In all of positions A, B, and C, the n-type impurity concentration in the body region 46 is extremely low. In all of positions A, B, and C, a peak value of the n-type impurity concentration is formed within the intermediate n-type region 48. The peak value N1a of the n-type impurity concentration in the first intermediate n-type region 48a is higher than the peak value N1b of the n-type impurity concentration in the second intermediate n-type region 48b. In all of positions A, B, and C, the n-type impurity concentration in the lower body region 50 is extremely low. In all of positions A, B, and C, the n-type impurity concentration in the drift region 52 is extremely low. However, in the drift region 52, the p-type impurity concentration is even lower than the n-type impurity concentration, so the drift region 52 is a low-concentration n-type region. At positions A, B, and C, in the depth range from depth D1 to depth D2, the n-type impurity concentration is lower than the peak value P1 of the p-type impurity concentration within the body region 46.

[0024] In this specification, the value obtained by integrating the n-type impurity concentration from depth D1 to depth D2 is called the first n-type integral value, and the value obtained by integrating the p-type impurity concentration from depth D1 to depth D2 is called the first p-type integral value. Furthermore, in this specification, the value obtained by integrating the n-type impurity concentration from the upper end to the lower end of the intermediate n-type region 48 is called the second n-type integral value. Furthermore, in this specification, the value obtained by integrating the p-type impurity concentration from the upper end to the lower end of the lower body region 50 is called the second p-type integral value.

[0025] As described above, the n-type impurity concentration in the first intermediate n-type region 48a (e.g., peak value N1a) is higher than the n-type impurity concentration in the second intermediate n-type region 48b (e.g., peak value N1b). Therefore, the second n-type integral value in the first intermediate n-type region 48a is higher than the second n-type integral value in the second intermediate n-type region 48b. Consequently, the first n-type integral value at position A is higher than the first n-type integral value at position B. In other words, the first n-type integral value directly below the emitter region 40 is higher than the first n-type integral value directly below the contact region 42. Similarly, the first n-type integral value directly below the emitter region 40 is higher than the first n-type integral value directly below the low-concentration contact region 44. For this reason, the first n-type integral value directly below the emitter region 40 is higher than the average value of the first n-type integral values ​​in the inter-trench semiconductor layer.

[0026] As described above, the p-type impurity concentration in the second lower body region 50b (e.g., peak value P2b) is higher than the p-type impurity concentration in the first lower body region 50a (e.g., peak value P2a). Therefore, the second p-type integral value in the second lower body region 50b is higher than the second p-type integral value in the first lower body region 50a. Consequently, the first p-type integral value at position B is higher than the first p-type integral value at position A. In other words, the first p-type integral value directly below the contact region 42 is higher than the first p-type integral value directly below the emitter region 40.

[0027] Next, the operation of the IGBT will be explained. The IGBT is used with a collector electrode 16 having a higher potential than the emitter electrode 14. When the potential of the gate electrode 34 is raised to a potential higher than the gate threshold, a channel is formed in the body region 46 near the gate insulating film 32, and a channel is formed in the lower body region 50 near the gate insulating film 32. The channel formed in the body region 46 connects the emitter region 40 and the intermediate n-type region 48, and the channel formed in the lower body region 50 connects the intermediate n-type region 48 and the drift region 52. As a result, electrons flow from the emitter region 40 to the collector region 56 via the channel in the body region 46, the intermediate n-type region 48, and the channel in the lower body region 50, the drift region 52, and the buffer region 54. At the same time, holes flow from the collector region 56 to the drift region 52 via the buffer region 54. As a result, the electrical resistance of the drift region 52 decreases due to the conductivity modulation phenomenon, allowing electrons to pass through the drift region 52 with low loss. In this way, when the potential of the gate electrode 34 is increased, the IGBT turns on, and electrons flow from the emitter region 40 to the collector region 56.

[0028] Subsequently, when the potential of the gate electrode 34 is reduced to a potential lower than the gate threshold, the channels disappear in the body region 46 and the lower body region 50. As a result, the IGBT turns off and the flow of electrons stops. When the IGBT turns off, holes present in the drift region 52 flow to the contact region 42 via the lower body region 50, the intermediate n-type region 48, and the body region 46. At this time, if some holes flow into the emitter region 40, the parasitic thyristor (i.e., the thyristor composed of the collector region 56, the drift region 52, the body region 46, and the emitter region 40) turns on, causing a latch-up. However, as will be explained below, in this embodiment, the inflow of holes into the emitter region 40 is suppressed by the intermediate n-type region 48 and the lower body region 50. As shown in Figure 4, a first intermediate n-type region 48a and a first lower body region 50a are provided directly below the emitter region 40, and a second intermediate n-type region 48b and a second lower body region 50b are provided directly below the contact region 42. The n-type impurity concentration in the first intermediate n-type region 48a is higher than that in the second intermediate n-type region 48b. Therefore, the electrical resistance to holes is higher in the first intermediate n-type region 48a than in the second intermediate n-type region 48b. The p-type impurity concentration in the first lower body region 50a is lower than that in the second lower body region 50b. Therefore, the electrical resistance to holes is higher in the first lower body region 50a than in the second lower body region 50b. Consequently, the electrical resistance to holes is higher in the region directly below the emitter region 40 than in the region directly below the contact region 42. Therefore, when the IGBT turns off, as shown by the arrows in Figure 4, the holes flow through the area directly below the contact area 42, avoiding the area directly below the emitter area 40. The holes flowing through the area directly below the contact area 42 flow directly into the contact area 42, thus suppressing the inflow of holes into the emitter area 40. Consequently, latch-up is suppressed. In particular, since the width of the first intermediate n-type area 48a is wider than the width of the emitter area 40, the inflow of holes into the emitter area 40 is suppressed more effectively. Consequently, latch-up is suppressed more effectively.

[0029] Next, the operation of the diode within the diode region 22 shown in Figure 3 will be explained. When a potential higher than that of the collector electrode 16 is applied to the emitter electrode 14, the diode within the diode region 22 turns on. That is, electrons flow from the cathode region 58 to the anode region 57 via the buffer region 54, drift region 52, lower body region 50, intermediate n-type region 48, and body region 46. At the same time, holes flow from the anode region 57 to the drift region 52 via the body region 46, intermediate n-type region 48, and lower body region 50. As a result, the electrical resistance of the drift region 52 decreases due to the conductivity modulation phenomenon, so electrons can pass through the drift region 52 with low loss. Note that since the n-type impurity concentration in the intermediate n-type region 48 is not very high, holes and electrons flow through the intermediate n-type region 48. In this way, when a potential higher than that of the collector electrode 16 is applied to the emitter electrode 14, the diode turns on, and electrons flow from the cathode region 58 to the anode region 57.

[0030] Furthermore, as shown in Figure 3, a parasitic diode is formed at the boundary between the IGBT region 20 and the diode region 22 by the contact region 42 within the IGBT region 20 and the cathode region 58 within the diode region 22. Also, during diode operation, as shown by the arrows in Figure 3, electrons flow from the diode region 22 to the IGBT region 20 within the drift region 52. When the electrons that have flowed as shown by the arrows in Figure 3 flow into the contact region 42, holes flow from the contact region 42 to the drift region 52, and the parasitic diode turns on. When the parasitic diode turns on, the diode's characteristics become unstable, such as an increase in the diode's recovery loss. However, as will be explained below, in this embodiment, when the diode is on, the inflow of electrons from the drift region 52 to the contact region 42 is suppressed by the intermediate n-type region 48 and the lower body region 50. As shown in Figure 4, a first intermediate n-type region 48a and a first lower body region 50a are provided directly below the emitter region 40, and a second intermediate n-type region 48b and a second lower body region 50b are provided directly below the contact region 42. The second intermediate n-type region 48b, which has a low n-type impurity concentration, has higher electrical resistance to electrons than the first intermediate n-type region 48a, which has a high n-type impurity concentration. Similarly, the second lower body region 50b, which has a high p-type impurity concentration, has higher electrical resistance to electrons than the first lower body region 50a, which has a low p-type impurity concentration. Therefore, the region directly below the contact region 42 has higher electrical resistance to electrons than the region directly below the emitter region 40. For this reason, as shown by the arrows in Figure 3, electrons flowing into the IGBT region 20 avoid the region directly below the contact region 42 and flow through the region directly below the emitter region 40. Electrons flowing in the region directly below the emitter region 40 flow directly into the emitter region 40, thus suppressing the inflow of electrons into the contact region 42. Consequently, the turning on of the parasitic diode is suppressed. As a result, the diode's characteristics become stable.

[0031] Next, the gate threshold of the IGBT will be explained. As shown in Figure 5, in the semiconductor device 10, a peak value P1 of the p-type impurity concentration is provided within the body region 46, and the peak value P1 is the maximum value of the p-type impurity concentration in both the body region 46 and the lower body region 50. Therefore, the gate threshold of the IGBT is determined by the peak value P1. If the p-type impurity concentration and the n-type impurity concentration differ between positions A and B at the depth D1 where the peak value P1 is located, the timing of channel formation will change depending on the position, and the switching operation of the IGBT will become unstable. In contrast, in the semiconductor device 10, the difference in p-type impurity concentration between positions A and B at depth D1 is small, and the difference in n-type impurity concentration is also small. Furthermore, in the semiconductor device 10, in the depth range between depth D1 and depth D2 at the lower end of the trench 30 (i.e., below the depth D1 of the peak value P1), there is a difference in the n-type impurity concentration and the p-type impurity concentration between positions A and B, thereby suppressing IGBT latch-up. With this configuration, the difference in impurity concentration between position A and position B has almost no effect on the gate threshold, thus enabling stable switching operation of the IGBT while suppressing IGBT latch-up.

[0032] Next, the manufacturing method of the semiconductor device 10 of Example 1 will be described. Below, the steps for forming the emitter region 40 and the first intermediate n-type region 48a will be described. In the emitter region 40 formation step, as shown in Figure 9, a mask 90 (for example, a resist mask) having an opening 90a is formed on the upper surface 12a of the semiconductor substrate 12. Next, n-type impurities are injected into the semiconductor substrate 12 through the mask 90 to form the emitter region 40. Next, as shown in Figure 10, n-type impurities are injected into the semiconductor substrate 12 using the mask 90 used in the emitter region 40 formation step. Here, by injecting n-type impurities at a deeper position than in the emitter region 40 formation step, the first intermediate n-type region 48a is formed directly below the emitter region 40. According to this manufacturing method, the emitter region 40 and the first intermediate n-type region 48a can be efficiently formed. In the process of forming the first intermediate n-type region 48a, since the injection depth of the n-type impurities is deep, the n-type impurities that pass through the opening 90a diffuse in the x-direction inside the semiconductor substrate 12. Therefore, this manufacturing method makes it possible to form a first intermediate n-type region 48a that is wider in the x-direction than the emitter region 40. Alternatively, the first intermediate n-type region 48a may be formed first, and then the emitter region 40 may be formed.

[0033] In Example 1, a semiconductor device having an IGBT and a diode (a so-called RC-IGBT) was described, but the technology disclosed herein may also be applied to an IGBT without a diode.

[0034] (Example 2) In Example 2, as shown in Figure 11, the width of the first lower body region 50a in the x-direction is wider than the width of the emitter region 40, and the emitter region 40 is positioned within the width range of the first lower body region 50a. The other structural aspects of Example 2 are the same as those of Example 1. According to the configuration of Example 2, holes are less likely to flow into the emitter region 40, and IGBT latch-up can be effectively suppressed. However, in other embodiments, the width of either or both of the first intermediate n-type region 48a and the first lower body region 50a may be less than or equal to the width of the emitter region 40. Even in this case, the presence of the first intermediate n-type region 48a and the first lower body region 50a directly below the emitter region 40 can suppress latch-up.

[0035] (Example 3) In Example 1 described above, the n-type impurity concentration in the first intermediate n-type region 48a was higher than that in the second intermediate n-type region 48b, resulting in higher electrical resistance to holes directly below the emitter region 40 than directly below the contact region 42. Also in Example 1, the p-type impurity concentration in the first lower body region 50a was lower than that in the second lower body region 50b, resulting in higher electrical resistance to holes directly below the emitter region 40 than directly below the contact region 42. In contrast, in Example 3, as shown in Figure 12, a difference in electrical resistance to holes is provided by the thickness of the intermediate n-type region 48 and the lower body region 50. In Figure 12, the n-type impurity concentration in the intermediate n-type region 48 is approximately constant in the x and y directions, and the p-type impurity concentration in the lower body region 50 is approximately constant. In Figure 12, the distribution range of n-type impurities in the intermediate n-type region 48 in the z-direction is wider directly below the emitter region 40 than directly below the contact region 42 and the low-concentration contact region 44. Therefore, the thickness of the first intermediate n-type region 48a is greater than the thickness of the second intermediate n-type region 48b. As a result, the second n-type integral value is larger in the first intermediate n-type region 48a than in the second intermediate n-type region 48b. Therefore, the electrical resistance to holes in the intermediate n-type region 48 is higher directly below the emitter region 40 than directly below the contact region 42. Also in Figure 12, the distribution range of p-type impurities in the lower body region 50 in the z-direction is narrower directly below the emitter region 40 than directly below the contact region 42 and the low-concentration contact region 44. Therefore, the thickness of the first lower body region 50a is thinner than the thickness of the second lower body region 50b. As a result, the second p-type integral value is smaller in the first lower body region 50a than in the second lower body region 50b. Therefore, the electrical resistance to the holes in the lower body region 50 is higher directly below the emitter region 40 than directly below the contact region 42. Consequently, IGBT latch-up can be suppressed even with the configuration shown in Figure 12.

[0036] The emitter region 40 and the first intermediate n-type region 48a in Figure 12 may also be formed by ion implantation using a common mask, similar to Figures 9 and 10.

[0037] Furthermore, in Figure 12, the width of either or both of the first intermediate n-type region 48a and the first lower body region 50a may be set to be less than or equal to the width of the emitter region 40.

[0038] In Figures 1-12, the presence of a difference in concentration or thickness in the intermediate n-type region 48 resulted in the first n-type integral value directly beneath the emitter region 40 being greater than the average value of the first n-type integral value in the inter-trench semiconductor layer. However, other configurations may also result in the first n-type integral value directly beneath the emitter region 40 being greater than the average value of the first n-type integral value in the inter-trench semiconductor layer. Also, in Figures 1-12, the presence of a difference in concentration or thickness in the lower body region 50 resulted in the first p-type integral value directly beneath the contact region 42 being greater than the first p-type integral value directly beneath the emitter region 40. However, other configurations may also result in the first p-type integral value directly beneath the contact region 42 being greater than the first p-type integral value directly beneath the emitter region 40. Furthermore, in Figures 1 to 12, both a first configuration in which the first n-type integral value directly below the emitter region 40 is greater than the average value of the first n-type integral value in the inter-trench semiconductor layer, and a second configuration in which the first p-type integral value directly below the contact region 42 is greater than the first p-type integral value directly below the emitter region 40 were employed. However, only one of the first or second configurations may be employed. Other embodiments will be described below.

[0039] (Example 4) The semiconductor device of Example 4 shown in Figure 13 does not have a lower body region 50. Therefore, the drift region 52 is in contact with the intermediate n-type region 48 from below. The first intermediate n-type region 48a, which has a high n-type impurity concentration, is located directly below the emitter region 40, and the second intermediate n-type region 48b, which has a low n-type impurity concentration, is located directly below the contact region 42 and the low-concentration contact region 44. Even with this configuration, the electrical resistance to holes is high within the first intermediate n-type region 48a, so the inflow of holes into the emitter region 40 can be suppressed.

[0040] (Example 5) In the semiconductor device of Example 5 shown in Figure 14, two intermediate n-type regions 48 are provided with a gap between them vertically. A drift region 52 is interposed between the two intermediate n-type regions 48. The configuration of each intermediate n-type region 48 is the same as in Figure 13. Even with this configuration, the inflow of holes into the emitter region 40 can be suppressed.

[0041] (Example 6) The semiconductor device of Example 6 shown in Figure 15 does not have a lower body region 50. Therefore, the drift region 52 is in contact with the intermediate n-type region 48 from below. In addition, the first intermediate n-type region 48a, which is thicker, is located directly below the emitter region 40, and the second intermediate n-type region 48b, which is thinner, is located directly below the contact region 42 and the low-concentration contact region 44. The n-type impurity concentration is the same in the first intermediate n-type region 48a and the second intermediate n-type region 48b. Even with this configuration, the inflow of holes into the emitter region 40 can be suppressed. Note that in Figure 15, the first intermediate n-type region 48a protrudes above the second intermediate n-type region 48b, but as shown in Figure 16, the first intermediate n-type region 48a may protrude below the second intermediate n-type region 48b.

[0042] (Example 7) The semiconductor device of Example 7 shown in Figure 17 does not have a lower body region 50. Also, an intermediate n-type region 48 (i.e., an n-type region with a higher n-type impurity concentration than the drift region 52) is provided directly below the emitter region 40, and an intermediate n-type region 48 is not provided directly below the contact region 42 and the low-concentration contact region 44. Directly below the contact region 42 and the low-concentration contact region 44, the drift region 52 is in contact with the body region 46 from below. Directly below the emitter region 40, the drift region 52 is in contact with the intermediate n-type region 48 from below. In this structure, the n-type impurity concentration of the intermediate n-type region 48 is higher than the n-type impurity concentration of the drift region 52 which is located in the same depth range as the intermediate n-type region 48. Therefore, in the depth range of the intermediate n-type region 48, the electrical resistance to holes is higher in the intermediate n-type region 48 than in the drift region 52. In other words, the electrical resistance to holes is higher directly below the emitter region 40 than directly below the contact region 42. Therefore, the inflow of holes into the emitter region 40 can be suppressed.

[0043] (Example 8) The semiconductor device of Example 8 shown in Figure 18 does not have a lower body region 50. Furthermore, a first intermediate n-type region 48a with a high n-type impurity concentration is distributed from directly below the emitter region 40 to directly below the contact region 42. A second intermediate n-type region 48b with a low n-type impurity concentration is located directly below the low-concentration contact region 44. In this configuration, when the IGBT turns off, as shown by the arrows in Figure 18, holes in the drift region 52 flow to the contact region 42, passing directly below the low-concentration contact region 44. Since the emitter region 40 is located on the opposite side of the low-concentration contact region 44, with the contact region 42 in between, holes passing directly below the low-concentration contact region 44 flow into the contact region 42 and are less likely to flow into the emitter region 40. Therefore, even in the configuration of Figure 18, the inflow of holes into the emitter region 40 can be suppressed. Note that in Figure 18, a lower body region 50 may be provided below the intermediate n-type region 48.

[0044] (Embodiment 9) In the semiconductor device of Embodiment 9 shown in FIG. 19, the n-type impurity concentration in the intermediate n-type region 48 is uniformly distributed in the x and y directions. That is, there is no difference in the n-type impurity concentration in the intermediate n-type region 48 directly below the emitter region 40, directly below the contact region 42, and directly below the low-concentration contact region 44. Further, the lower body region 50 is configured in the same manner as in Embodiment 1. That is, a first lower body region 50a is disposed directly below the emitter region 40, and a second lower body region 50b having a p-type impurity concentration higher than that of the first lower body region 50a is disposed directly below the contact region 42 and directly below the low-concentration contact region 44. Even with this configuration, since the electrical resistance to holes is high within the first lower body region 50a, the inflow of holes into the emitter region 40 can be suppressed.

[0045] (Embodiment 10) In the semiconductor device of Embodiment 10 shown in FIG. 20, the n-type impurity concentration in the intermediate n-type region 48 is uniformly distributed in the x and y directions. Further, the lower body region 50 is provided directly below the contact region 42 and is not provided directly below the emitter region 40 and directly below the low-concentration contact region 44. Directly below the emitter region 40 and directly below the low-concentration contact region 44, the drift region 52 is in contact with the intermediate n-type region 48 from below. In this structure, since there is no lower body region 50 directly below the emitter region 40, the electrical resistance to holes is higher directly below the emitter region 40 than directly below the contact region 42. Therefore, the inflow of holes into the emitter region 40 can be suppressed.

[0046] In FIG. 20, the lower body region 50 is not provided directly below the low-concentration contact region 44, but as shown in FIG. 21, the lower body region 50 may be provided spanning from directly below the contact region 42 to directly below the low-concentration contact region 44. Even with this structure, directly below the emitter region 40, the electrical resistance to holes is higher than directly below the contact region 42. Therefore, the inflow of holes into the emitter region 40 can be suppressed.

[0047] Further, as shown in FIG. 22, the lower body region 50 provided directly below the contact region 42 may partially enter the intermediate n-type region 48.

[0048] (Embodiment 11) In the semiconductor device of Embodiment 11 shown in FIG. 23, it is provided within a depth range Rd where the lower body region 50 and the intermediate n-type region 48 overlap. Within the depth range Rd (that is, the entirety of the lower body region 50 and the intermediate n-type region 48), the n-type impurity concentration is uniformly distributed in the x-direction and the y-direction. Also, within the lower body region 50, the p-type impurity concentration is higher than within the intermediate n-type region 48. The lower body region 50 is provided directly below the contact region 42. The intermediate n-type region 48 is provided directly below the emitter region 40 and directly below the low-concentration contact region 44. The drift region 52 contacts the lower body region 50 and the intermediate n-type region 48 from below. In this structure, since the lower body region 50 does not exist directly below the emitter region 40, the electrical resistance to holes is higher directly below the emitter region 40 than directly below the contact region 42. Therefore, the inflow of holes into the emitter region 40 can be suppressed. Note that in FIG. 23, the lower body region 50 may be provided spanning from directly below the contact region 42 to directly below the low-concentration contact region 44.

[0049] (Example 12) The semiconductor device of Example 12 shown in Figure 24 does not have an intermediate n-type region. Also, a lower body region 50 is provided directly below the contact region 42. The lower body region 50 is in contact with the body region 46 from below. The lower body region 50 is not provided directly below the emitter region 40 or directly below the low-density contact region 44. Directly below the emitter region 40 and directly below the low-density contact region 44, a drift region 52 is in contact with the body region 46 from below. Also, the drift region 52 is in contact with the lower body region 50 from below. In this structure, since the lower body region 50 is not present directly below the emitter region 40, the electrical resistance to holes is higher directly below the emitter region 40 than directly below the contact region 42. Therefore, the inflow of holes into the emitter region 40 can be suppressed. In addition, in Figure 24, the lower body region 50 may be provided spanning from directly below the contact region 42 to directly below the low-concentration contact region 44.

[0050] (Example 13) In the semiconductor device of Example 13 shown in Figure 25, the n-type impurity concentration in the intermediate n-type region 48 is uniformly distributed in the x and y directions. Furthermore, there is no low-concentration contact region 44 in the inter-trench semiconductor layer, and the emitter region 40 and contact region 42 are alternately arranged in the x direction. A first lower body region 50a is located directly below the emitter region 40, and a second lower body region 50b, which has a higher p-type impurity concentration than the first lower body region 50a, is located directly below the contact region 42. In this configuration as well, the electrical resistance to holes is higher directly below the emitter region 40 than directly below the contact region 42. Therefore, the inflow of holes into the emitter region 40 can be suppressed.

[0051] In the semiconductor device manufacturing method of Example 13, the contact region 42 and the second lower body region 50b may be formed as shown in Figures 26 and 27. First, as shown in Figure 26, a mask 92 (for example, a resist mask) having an opening 92a is formed on the upper surface 12a of the semiconductor substrate 12. Next, p-type impurities are injected into the semiconductor substrate 12 through the mask 92 to form the contact region 42. Next, as shown in Figure 27, p-type impurities are injected into the semiconductor substrate 12 using the mask 92 used in the contact region 42 formation step. Here, by injecting p-type impurities at a deeper position than in the contact region 42 formation step, the second lower body region 50b is formed directly below the contact region 42. This manufacturing method allows for the efficient formation of the contact region 42 and the second lower body region 50b. Alternatively, the second lower body region 50b may be formed first, and then the contact region 42 may be formed.

[0052] In the above-described embodiments 1 to 13, as shown in Figure 2, the emitter region 40 and the contact region 42 were in contact with the gate insulating film 32 on both sides in the y-direction. However, either or both of the emitter region 40 and the contact region 42 may be separated in the y-direction. For example, in the inter-trench semiconductor layer between two trenches 30-1 and 30-2, the emitter region 40-1 and the emitter region 40-2 may be arranged separately in the y-direction, with the emitter region 40-1 in contact with the side surface of trench 30-1 and the emitter region 40-2 in contact with the side surface of trench 30-2. Alternatively, either or both of the emitter region 40 and the contact region 42 may be in contact with only one side surface of the two trenches. For example, in the inter-trench semiconductor layer between two trenches 30-1 and 30-2, an emitter region 40 and a contact region 42 are provided in the area in contact with the side surface of trench 30-1, but an emitter region 40 and a contact region 42 are not required to be provided in the area in contact with the side surface of trench 30-2.

[0053] Examples 1 to 8 and their variations (i.e., Figures 4, 11, 12, 13, 14, 15, 16, 17, and 18) are examples of structures in which the first n-type integral value directly below the emitter region is higher than the average value of the first n-type integral value in the inter-trench semiconductor layer. Examples 1 to 3, 9 to 13 and their variations (i.e., Figures 4, 11, 12, 19, 20, 21, 22, 23, 24, and 25) are examples of structures in which the first p-type integral value directly below the contact region is higher than the first p-type integral value directly below the emitter region. It is also possible to combine the above-described Examples 1 to 13 and their variations.

[0054] The technical items disclosed in this specification are listed below. Items A1 to A11 are characterized by n-type integral values, and items A12 to A19 are characterized by p-type integral values.

[0055] (Item A1) A semiconductor device comprising: a semiconductor substrate having a plurality of trenches on its upper surface, wherein the plurality of trenches on the upper surface extend elongated in a first direction; a gate insulating film covering the inner surface of the trenches; a gate electrode disposed within the trench and insulated from the semiconductor substrate by the gate insulating film; and an emitter electrode covering the upper surface, wherein the plurality of trenches include a first trench and a second trench, and the semiconductor layer between the first trench and the second trench is an inter-trench semiconductor layer, and the semiconductor substrate comprises: an n-type emitter region provided within the inter-trench semiconductor layer, in contact with the emitter electrode, and in contact with the gate insulating film on the side surface of the first trench; and a p-type contact region provided within the inter-trench semiconductor layer, in contact with the emitter electrode, in contact with the gate insulating film on the side surface of the first trench, and in contact with the emitter region in a first direction. A semiconductor device comprising: a p-type body region provided within the inter-trench semiconductor layer, in contact with the emitter region and the contact region from below, in contact with the gate insulating film on the side surface of the first trench below the emitter region and the contact region, and having a lower p-type impurity concentration than the contact region; an n-type drift region located below the body region and in contact with the gate insulating film on the side surface of the first trench below the body region; and a p-type collector region located below the drift region, wherein the body region has a peak value in the p-type impurity concentration distribution in the depth direction, and when the first n-type integral value is defined as the value obtained by integrating the n-type impurity concentration distribution in the depth direction within the semiconductor substrate from the depth of the peak value to the depth of the lower end of the first trench, the first n-type integral value directly below the emitter region is higher than the average value of the first n-type integral value within the inter-trench semiconductor layer. (Item A2) The semiconductor device according to Item A1, wherein the first n-type integral value directly below the emitter region is higher than the first n-type integral value directly below the contact region.(Item A3) The semiconductor device according to Item A1 or A2, wherein the semiconductor substrate is provided in the inter-trench semiconductor layer, is in contact with the body region from below, is distributed from a position directly below the emitter region to a position directly below the contact region, is in contact with the gate insulating film on the side surface of the first trench below the body region, and has an intermediate n-type region having a higher n-type impurity concentration than the drift region, and when the value obtained by integrating the n-type impurity concentration distribution in the depth direction within the semiconductor substrate from the depth of the upper end of the intermediate n-type region to the depth of the lower end of the intermediate n-type region is taken as the second n-type integral value, the intermediate n-type region has a first intermediate n-type region and a second intermediate n-type region having a second n-type integral value lower than the first intermediate n-type region, the first intermediate n-type region is located directly below the emitter region, and the second intermediate n-type region is located directly below the contact region. (Item A4) The semiconductor device according to Item A3, wherein the n-type impurity concentration in the first intermediate n-type region is higher than the n-type impurity concentration in the second intermediate n-type region. (Item A5) The semiconductor device according to Item A3 or A4, wherein the thickness of the first intermediate n-type region is greater than the thickness of the second intermediate n-type region. (Item A6) The semiconductor device according to any one of Items A3 to A5, wherein in the first direction, the width of the first intermediate n-type region is wider than the width of the emitter region, and in the first direction, the emitter region is located within the width range of the first intermediate n-type region. (Item A7) The semiconductor device according to any one of Items A3 to A6, wherein the semiconductor substrate is provided in the inter-trench semiconductor layer, is in contact with the intermediate n-type region from below, and has a p-type lower body region that is in contact with the gate insulating film on the side surface of the first trench below the intermediate n-type region.(Item A8) The semiconductor device according to Item A1 or A2, wherein the semiconductor substrate is provided in the inter-trench semiconductor layer, is in contact with the body region from below, is located directly below the emitter region, is in contact with the gate insulating film on the side surface of the first trench below the body region, and has an intermediate n-type region having a higher n-type impurity concentration than the drift region, and the drift region is in contact with the body region from below directly below the contact region. (Item A9) The semiconductor substrate is provided within the inter-trench semiconductor layer and has a p-type low-concentration contact region having a lower p-type impurity concentration than the contact region, the contact region is positioned between the emitter region and the low-concentration contact region in the first direction, the low-concentration contact region is in contact with the emitter electrode, is in contact with the gate insulating film on the side surface of the first trench, is in contact with the contact region in the first direction, the body region is in contact with the low-concentration contact region from below, the semiconductor substrate is provided within the inter-trench semiconductor layer and is distributed from a position directly below the emitter region to a position directly below the low-concentration contact region, is in contact with the body region from below, is in contact with the gate insulating film on the side surface of the first trench below the body region, and has an intermediate n-type region having a higher n-type impurity concentration than the drift region, The semiconductor device according to item A1, wherein, in the n-type impurity concentration distribution in the depth direction within the semiconductor substrate, when the value obtained by integrating from the depth of the upper end of the intermediate n-type region to the depth of the lower end of the intermediate n-type region is defined as the second n-type integral value, the intermediate n-type region comprises a first intermediate n-type region and a second intermediate n-type region having a second n-type integral value lower than that of the first intermediate n-type region, the first intermediate n-type region is distributed across a position directly below the emitter region to a position directly below the contact region, and the second intermediate n-type region is located directly below the low-concentration contact region.(Item A10) The semiconductor device according to any one of Items A1 to A9, wherein the semiconductor substrate has a diode region, the diode region has a p-type anode region in contact with the emitter electrode, the drift region is provided below the anode region, and the diode region is located below the drift region and has an n-type cathode region having a higher n-type impurity concentration than the drift region. (Item A11) A method for manufacturing a semiconductor device according to any one of Items A3 to A7, comprising the steps of: forming the emitter region by injecting n-type impurities into the upper surface of the semiconductor substrate via a mask; and forming the first intermediate n-type region by injecting n-type impurities into the upper surface of the semiconductor substrate via a mask. (Item A12) A semiconductor device according to any one of Items A1 to A10, wherein, in the p-type impurity concentration distribution in the depth direction within the semiconductor substrate, when the value obtained by integrating from the depth of the peak value to the depth of the lower end of the first trench is defined as the first p-type integral value, the first p-type integral value directly below the contact region is higher than the first p-type integral value directly below the emitter region.(Item A13) The semiconductor substrate has an intermediate n-type region that is in contact with the body region from below, is distributed from a position directly below the emitter region to a position directly below the contact region, is in contact with the gate insulating film on the side surface of the first trench on the lower side of the body region, and has an n-type impurity concentration higher than that of the drift region; and a p-type lower body region that is in contact with the intermediate n-type region from below, is distributed from a position directly below the emitter region to a position directly below the contact region, and is in contact with the gate insulating film on the side surface of the first trench on the lower side of the intermediate n-type region, and when the value obtained by integrating the p-type impurity concentration distribution in the depth direction within the semiconductor substrate from the depth of the upper end of the lower body region to the depth of the lower end of the lower body region is taken as the second p-type integral value, the lower body region has a first lower body region and a second lower body region that has a second p-type integral value higher than that of the first lower body region, and the first lower body region is located directly below the emitter region. A semiconductor device according to item A12, wherein the second lower body region is located directly below the contact region. (Item A14) A semiconductor device according to item A13, wherein the p-type impurity concentration of the second lower body region is higher than the p-type impurity concentration of the first lower body region. (Item A15) A semiconductor device according to item A13 or A14, wherein the thickness of the second lower body region is greater than the thickness of the first lower body region. (Item A16) A semiconductor device according to any one of items A13 to A15, wherein in the first direction, the width of the first lower body region is wider than the width of the emitter region, and in the first direction, the emitter region is located within the width range of the first lower body region.(Item A17) The semiconductor device according to Item A12, wherein the semiconductor substrate is in contact with the body region from below, is distributed from a position directly below the emitter region to a position directly below the contact region, is in contact with the gate insulating film on the side surface of the first trench on the lower side of the body region, and has an intermediate n-type region having a higher n-type impurity concentration than the drift region, and is in contact with the intermediate n-type region from below, is located directly below the contact region, and is in contact with the gate insulating film on the side surface of the first trench on the lower side of the intermediate n-type region, and the drift region is in contact with the intermediate n-type region from below directly below the emitter region. (Item A18) The semiconductor device according to any one of Items A12 to A17, wherein the semiconductor substrate has a diode region, the diode region has a p-type anode region in contact with the emitter electrode, the drift region is provided below the anode region, and the diode region is located below the drift region and has an n-type cathode region having a higher n-type impurity concentration than the drift region. (Item A19) A method for manufacturing a semiconductor device according to any one of Items A13 to A16, comprising the steps of: forming the contact region by injecting p-type impurities into the upper surface of the semiconductor substrate via a mask; and forming the second lower body region directly below the contact region by injecting p-type impurities into the upper surface of the semiconductor substrate via the mask.

[0056] Figures 28, 29, and 30 are schematic diagrams illustrating the integral value. In each figure, the left figure is a cross-sectional view perpendicular to the first direction, and the right figure is a cross-sectional view along the first direction.

[0057] In item A1, the first n-type integral value directly below the emitter region is the first n-type integral value in region R1 directly below the emitter region E (i.e., the region between the depth Dp of the peak value of the p-type impurity concentration in body region B and the depth Dt of the lower end of the first trench T1, and directly below the emitter region E), as illustrated in Figure 28. If the first n-type integral value changes with position within region R1 directly below the emitter region E, the average value of the first n-type integral value in region R1 can be adopted as the first n-type integral value directly below the emitter region E. Also, in each figure, the area between trenches T1 and T2 is the inter-trench semiconductor layer. In item A1, the average value of the first n-type integral in the inter-trench semiconductor layer is the average value of the first n-type integral in region R2 (i.e., the region between the depth Dp of the peak value of the p-type impurity concentration in body region B and the depth Dt of the lower end of the first trench T1, between the ends of each trench T1 and T2 in the first direction, and between the first trench T1 and the second trench T2 in the direction perpendicular to the first direction), as illustrated in Figure 29.

[0058] In item A1, the IGBT is composed of an emitter region, contact region, body region, drift region, collector region, gate electrode, etc. In item A1, the first n-type integral value is high directly below the emitter region, making it difficult for holes to flow directly below the emitter region. Therefore, when the IGBT turns off, the inflow of holes from the drift region into the emitter region is suppressed, and IGBT latch-up is suppressed. In addition, the impurity concentration below the depth of the peak value in the body region has almost no effect on the gate threshold of the IGBT, so even if the first n-type integral value is high directly below the emitter region, the gate threshold can be set to an appropriate value.

[0059] In addition, in item A1, the peak value may be the maximum value of the p-type impurity concentration in the range from the depth of the peak value to the depth of the lower end of the first trench. Furthermore, the peak value may be higher than the maximum value of the n-type impurity concentration in the range from the depth of the peak value to the depth of the lower end of the first trench.

[0060] In item A2, the first n-type integral value directly below the contact region is the first n-type integral value in region R3 directly below the contact region C (i.e., the region between the depth Dp of the peak value of the p-type impurity concentration in body region B and the depth Dt of the lower end of the first trench T1, and directly below the contact region C), as illustrated in Figure 30. If the first n-type integral value changes with position within region R3 directly below the contact region C, the average value of the first n-type integral value in region R3 can be adopted as the first n-type integral value directly below the contact region.

[0061] According to item A2, the first n-type integral value is low directly below the contact region, making it easier for holes to flow directly below the contact region. Therefore, when the IGBT turns off, holes in the drift region are more likely to flow into the contact region, avoiding the emitter region. As a result, the inflow of holes into the emitter region is more effectively suppressed, and IGBT latch-up is effectively suppressed.

[0062] According to item A3, by providing a first intermediate n-type region and a second intermediate n-type region with different second n-type integral values ​​directly below the emitter region and the contact region, a difference in the first n-type integral value can be created directly below the emitter region and directly below the contact region. Note that a drift region may be in contact with the lower surface of the intermediate n-type region, or a p-type region may exist between the intermediate n-type region and the drift region.

[0063] According to item A4, by creating a difference in the n-type impurity concentration within the intermediate n-type region, a difference in the second n-type integral value can be created within the intermediate n-type region.

[0064] According to item A5, by creating a difference in thickness within the intermediate n-type region, a difference in the second n-type integral value can be created within the intermediate n-type region.

[0065] According to item A6, when an IGBT is turned off, the inflow of holes into the emitter region can be suppressed more effectively.

[0066] According to item A7, the on-voltage of the IGBT can be reduced.

[0067] According to item A8, by providing an intermediate n-type region directly below the emitter region with a higher n-type impurity concentration than the drift region, the first n-type integral value directly below the emitter region can be increased.

[0068] In item A9, when the IGBT turns off, holes tend to flow directly beneath the low-concentration contact area. Since the contact area is adjacent to the low-concentration contact area, holes that pass directly beneath the low-concentration contact area tend to flow into the contact area. Therefore, the inflow of holes into the emitter area is suppressed.

[0069] According to item A10, the first n-type integral value directly below the emitter region is high. Therefore, when the diode in the diode region is turned on, electrons flow easily from the cathode region to the emitter region, and it is difficult for electrons to flow from the cathode region to the contact region. As a result, current does not easily flow through the parasitic diode between the contact region and the cathode region. This stabilizes the operation of the diode in the diode region.

[0070] According to item A11, the emitter region and the first intermediate n-type region can be formed using a common mask. Note that the process of forming the emitter region and the process of forming the first intermediate n-type region may be performed in either order.

[0071] In item A12, the first p-type integral value directly below the contact region is the first p-type integral value in region R3 directly below the contact region C as illustrated in Figure 30 (i.e., the region directly below the contact region C, between the depth Dp of the peak value of the p-type impurity concentration in body region B and the depth Dt of the lower end of the first trench T1). If the first p-type integral value changes with position within region R3 directly below the contact region C, the average value of the first p-type integral value in region R3 can be adopted as the first p-type integral value directly below the contact region C. Also, in item A12, the first p-type integral value directly below the emitter region is the first p-type integral value in region R1 directly below the emitter region E as illustrated in Figure 28 (i.e., the region directly below the emitter region E, between the depth Dp of the peak value of the p-type impurity concentration in body region B and the depth Dt of the lower end of the first trench T12). Furthermore, if the first p-type integral value changes with position within region R1 directly below the emitter region E, the average value of the first p-type integral value in region R1 can be used as the first p-type integral value directly below the emitter region.

[0072] In item A12, the first p-type integral value is low directly below the emitter region, making it difficult for holes to flow directly below the emitter region. Therefore, when the IGBT turns off, the inflow of holes from the drift region into the emitter region is suppressed, and IGBT latch-up is suppressed. Furthermore, since the impurity concentration below the depth of the peak value in the body region has almost no effect on the IGBT gate threshold, the gate threshold can be set to an appropriate value even if the first p-type integral value differs directly below the emitter region and directly below the contact region.

[0073] Furthermore, in item A12, the peak value may be the maximum value of the p-type impurity concentration in the range from the depth of the peak value to the depth of the lower end of the first trench. Also, the peak value may be higher than the maximum value of the n-type impurity concentration in the range from the depth of the peak value to the depth of the lower end of the first trench.

[0074] According to item A13, by providing a first lower body region and a second lower body region with different second p-type integral values ​​directly below the emitter region and the contact region, a difference in the first p-type integral value can be created between the area directly below the emitter region and the area directly below the contact region.

[0075] According to item A14, by creating a difference in the p-type impurity concentration within the lower body region, a difference in the second p-type integral value can be created within the lower body region.

[0076] According to item A15, by creating a difference in thickness within the lower body region, a difference in the second p-type integral value can be created within the lower body region.

[0077] According to item A16, when an IGBT is turned off, the inflow of holes into the emitter region can be suppressed more effectively.

[0078] According to item A17, by providing a lower body region directly below the contact region, the first p-type integral value directly below the contact region can be increased.

[0079] According to item A18, the first p-type integral value directly below the emitter region is low. Therefore, when the diode in the diode region is turned on, electrons flow easily from the cathode region to the emitter region, and it is difficult for electrons to flow from the cathode region to the contact region. As a result, current does not easily flow through the parasitic diode between the contact region and the cathode region. This stabilizes the operation of the diode in the diode region.

[0080] According to item A19, a common mask can be used to form the contact region and the second lower body region. Note that the process of forming the contact region and the process of forming the second lower body region may be performed in either order.

[0081] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness.

Claims

1. A semiconductor device comprising: a semiconductor substrate having a plurality of trenches (30) on its upper surface, wherein the plurality of trenches on the upper surface extend elongated in a first direction; a gate insulating film (32) covering the inner surface of the trenches; a gate electrode (34) disposed within the trench and insulated from the semiconductor substrate by the gate insulating film; and an emitter electrode (14) covering the upper surface, wherein the plurality of trenches comprises a first trench and a second trench, and the semiconductor layer between the first trench and the second trench is an inter-trench semiconductor layer, and the semiconductor substrate comprises: an n-type emitter region (40) provided within the inter-trench semiconductor layer, in contact with the emitter electrode, and in contact with the gate insulating film on the side surface of the first trench; and a p-type contact region (42) provided within the inter-trench semiconductor layer, in contact with the emitter electrode, in contact with the gate insulating film on the side surface of the first trench, and in contact with the emitter region in a first direction. A semiconductor device comprising: a p-type body region (46) provided within the inter-trench semiconductor layer, in contact with the emitter region and the contact region from below, in contact with the gate insulating film on the side surface of the first trench below the emitter region and the contact region, and having a lower p-type impurity concentration than the contact region; an n-type drift region (52) located below the body region and in contact with the gate insulating film on the side surface of the first trench below the body region; and a p-type collector region (56) located below the drift region, wherein the body region has a peak value in the p-type impurity concentration distribution in the depth direction, and when the first n-type integral value is defined as the value obtained by integrating from the depth of the peak value to the depth of the lower end of the first trench in the n-type impurity concentration distribution in the depth direction within the semiconductor substrate, the first n-type integral value directly below the emitter region is higher than the average value of the first n-type integral value within the inter-trench semiconductor layer.

2. The semiconductor device according to claim 1, wherein the first n-type integral value directly below the emitter region is higher than the first n-type integral value directly below the contact region.

3. The semiconductor device according to claim 1, wherein the semiconductor substrate is provided in the inter-trench semiconductor layer, is in contact with the body region from below, is distributed from a position directly below the emitter region to a position directly below the contact region, is in contact with the gate insulating film on the side surface of the first trench below the body region, and has an intermediate n-type region (48) having a higher n-type impurity concentration than the drift region, and when the value obtained by integrating the n-type impurity concentration distribution in the depth direction within the semiconductor substrate from the depth of the upper end of the intermediate n-type region to the depth of the lower end of the intermediate n-type region is taken as the second n-type integral value, the intermediate n-type region has a first intermediate n-type region (48a) and a second intermediate n-type region (48b) having a second n-type integral value lower than the first intermediate n-type region, the first intermediate n-type region is located directly below the emitter region, and the second intermediate n-type region is located directly below the contact region.

4. The semiconductor device according to claim 3, wherein the n-type impurity concentration in the first intermediate n-type region is higher than the n-type impurity concentration in the second intermediate n-type region.

5. The semiconductor device according to claim 3, wherein the thickness of the first intermediate n-type region is greater than the thickness of the second intermediate n-type region.

6. The semiconductor device according to any one of claims 3 to 5, wherein in the first direction, the width of the first intermediate n-type region is wider than the width of the emitter region, and in the first direction, the emitter region is arranged within the range of the width of the first intermediate n-type region.

7. The semiconductor device according to any one of claims 3 to 5, wherein the semiconductor substrate is provided in the inter-trench semiconductor layer and has a p-type lower body region (50) that is in contact with the gate insulating film on the side surface of the first trench below the intermediate n-type region.

8. The semiconductor device according to claim 1 or 2, wherein the semiconductor substrate is provided in the inter-trench semiconductor layer, is in contact with the body region from below, is located directly below the emitter region, is in contact with the gate insulating film on the side surface of the first trench below the body region, and has an intermediate n-type region having a higher n-type impurity concentration than the drift region, and the drift region is in contact with the body region from below directly below the contact region.

9. The semiconductor substrate is provided within the inter-trench semiconductor layer and has a p-type low-concentration contact region (44) having a lower p-type impurity concentration than the contact region, the contact region is positioned between the emitter region and the low-concentration contact region in the first direction, the low-concentration contact region is in contact with the emitter electrode, in contact with the gate insulating film on the side surface of the first trench, and in contact with the contact region in the first direction, the body region is in contact with the low-concentration contact region from below, the semiconductor substrate is provided within the inter-trench semiconductor layer and is distributed from a position directly below the emitter region to a position directly below the low-concentration contact region, is in contact with the body region from below, is in contact with the gate insulating film on the side surface of the first trench below the body region, and has an intermediate n-type region having a higher n-type impurity concentration than the drift region, The semiconductor device according to claim 1, wherein, in the n-type impurity concentration distribution in the depth direction within the semiconductor substrate, when the value obtained by integrating from the depth of the upper end of the intermediate n-type region to the depth of the lower end of the intermediate n-type region is defined as the second n-type integral value, the intermediate n-type region comprises a first intermediate n-type region and a second intermediate n-type region having a second n-type integral value lower than that of the first intermediate n-type region, the first intermediate n-type region is distributed across a position directly below the emitter region to a position directly below the contact region, and the second intermediate n-type region is located directly below the low-concentration contact region.

10. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor substrate has a diode region, the diode region has a p-type anode region in contact with the emitter electrode, the drift region is provided below the anode region, and the diode region is positioned below the drift region and has an n-type cathode region having a higher n-type impurity concentration than the drift region.

11. A method for manufacturing a semiconductor device according to any one of claims 3 to 5, comprising: a step of forming the emitter region by injecting n-type impurities into the upper surface of the semiconductor substrate via a mask; and a step of forming the first intermediate n-type region by injecting n-type impurities into the upper surface of the semiconductor substrate via a mask.

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