Power conversion device, signal generation method, and program

Abstract

This power conversion device is capable of stably generating a plurality of PWM signals.　The power conversion device (2) has a conversion circuit (3) that converts and outputs inputted power on the basis of a plurality of PWM signals (Sp), and a control circuit (7) that generates the plurality of PWM signals (Sp). The control circuit (7) performs a control parameter calculation process for calculating at least one of a value specifying a PWM period and a value specifying a duty cycle of each PWM signal (Sp) such that error between the value of the output voltage (Vout) and the value of a target voltage (Vtgt) approaches zero, and a control parameter update process for updating the value of the control parameter (20) for each PWM signal (Sp) stored in a memory unit (12) with the value calculated in the control parameter calculation process. The control circuit (7) starts the control parameter update process in response to the start of a PWM period of a PWM signal (Sp) and completes the control parameter update process before the start of the next PWM period.

Description

Power Conversion Device, Signal Generation Method, and Program

[0001] The present invention relates to a power conversion device, a signal generation method, and a program, and more particularly, to a power conversion device that converts and outputs input power by control in a pulse width modulation (PWM) method.

[0002] In a power conversion device such as a DC / DC converter, a technique for converting and outputting input power by a PWM signal is known (see Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2021-57257

[0004] Prior to the present application, the inventor of the present application considered developing a power conversion device that converts an input voltage into a DC voltage of a desired magnitude and outputs it by PWM control using a general-purpose microcontroller (MCU).

[0005] The power conversion device according to the prior study example by the inventor of the present application includes a transformer, an inverter circuit connected to the primary side of the transformer, a rectifier circuit connected to the secondary side of the transformer, and an MCU having a function of generating a plurality of PWM signals.

[0006] In the above power conversion device, the MCU performs feedback control to generate a plurality of PWM signals for individually driving a plurality of transistors constituting the inverter circuit so that the DC voltage (output voltage) output from the rectifier circuit matches the target voltage. That is, the MCU calculates and updates the value of a control parameter including at least one of the duty ratio of the PWM signal and one cycle of the PWM signal (hereinafter also referred to as the "PWM period") for each PWM signal so that the error between the output voltage and the target voltage is reduced. As a result, at least one of the duty ratio and the PWM period of each PWM signal is dynamically adjusted, and the output voltage of the power conversion device is controlled to match the target voltage.

[0007] In order to stabilize the output voltage in the above power conversion device, it is necessary that the timing at which the PWM period starts is synchronized among the respective PWM signals.

[0008] However, the inventors' research has revealed that even when the start timing of the PWM cycle is synchronized between each PWM signal, depending on the function of the MCU used as the control circuit, some of the multiple PWM signals may not be generated properly.

[0009] Specifically, it has become clear that when the timing of two processes being executed in the MCU overlaps, the MCU may not be able to properly perform one of the processes, resulting in some PWM signals not being generated. For example, when the period during which the MCU updates the control parameters of each PWM signal overlaps with the timing at which the MCU synchronizes each PWM signal (the start timing of the PWM cycle), some PWM signals may not be output.

[0010] This issue arises from the specifications of the MCU used as the control circuit. Specifically, in an MCU that has a function to enable control parameter updates after a setting reflection invalidation period has elapsed, which disables the updating of control parameters while PWM signals are being generated, if the setting reflection invalidation period and the timing for synchronizing each PWM signal coincide, the signal for synchronizing each PWM signal may not be output, and some PWM signals may not be generated properly.

[0011] The present invention aims to solve the above-mentioned problems and to enable the stable generation of multiple PWM signals in a power conversion device.

[0012] A power conversion device according to a typical embodiment of the present invention includes a conversion circuit that converts and outputs input power based on a plurality of PWM signals, and a control circuit that generates the plurality of PWM signals so that the output voltage of the conversion circuit approaches a target voltage, wherein the control circuit includes a voltage acquisition unit that acquires the value of the output voltage, a storage unit that stores control parameters for each PWM signal, including a value that specifies the PWM period which is one period of the PWM signal and a value that specifies the duty cycle of the PWM signal, and a decrease in the value that specifies the PWM period and the duty cycle of each PWM signal so that the error between the output voltage value acquired by the voltage acquisition unit and the target voltage value approaches zero The system includes a control parameter setting unit that performs a control parameter calculation process to calculate at least one of the PWM signals, a control parameter update process that updates the value of the control parameter for each PWM signal stored in the storage unit with the value calculated by the control parameter calculation process, and a PWM signal generation unit that generates the plurality of PWM signals based on the control parameters stored in the storage unit so that the timing of when the PWM cycles of the plurality of PWM signals start is synchronized, wherein the control parameter setting unit starts the control parameter update process in response to the start of the PWM cycle and completes the control parameter update process before the next PWM cycle starts.

[0013] According to one aspect of the present invention, it is possible to stably generate multiple PWM signals in a power conversion device.

[0014] This figure shows the configuration of a power supply device equipped with a power converter according to the embodiment. This figure shows an example of the circuit configuration of the power converter according to the embodiment. This figure shows the configuration of the control circuit according to the embodiment. This is a timing chart showing an example of a PWM signal. This flowchart shows an example of the flow of the PWM signal generation process in the power converter according to the embodiment.

[0015] 1. Outline of Embodiments First, a general overview of a typical embodiment of the invention disclosed in this application will be given. In the following description, as an example, reference numerals on the drawings corresponding to the components of the invention are indicated in parentheses.

[0016] [1] A power conversion device (2) according to a typical embodiment of the present invention includes a conversion circuit (3) that converts and outputs input power based on a plurality of PWM signals, and a control circuit (7) that generates the plurality of PWM signals so that the output voltage (Vout) of the conversion circuit approaches a target voltage (Vtgt), wherein the control circuit includes a voltage acquisition unit (10) that acquires the value of the output voltage, a storage unit (12) that stores control parameters (20_1 to 20_12) for each PWM signal, including a value (Ctc) that specifies the PWM period which is one period of the PWM signal and a value (Cdt1 to Cdt12) that specifies the duty cycle of the PWM signal, and the PWM period of each PWM signal so that the error between the value of the output voltage acquired by the voltage acquisition unit and the value of the target voltage approaches zero. The system includes a control parameter setting unit (11) that performs a control parameter calculation process to calculate at least one of a value that specifies a period and a value that specifies the duty cycle, and a control parameter update process that updates the value of the control parameter for each PWM signal stored in the storage unit with the value calculated by the control parameter calculation process, and a PWM signal generation unit (13) that generates the plurality of PWM signals based on the control parameters stored in the storage unit so that the timing of when the PWM cycles of the plurality of PWM signals start is synchronized, wherein the control parameter setting unit starts the control parameter update process in response to the start of the PWM cycle and completes the control parameter update process before the next PWM cycle starts.

[0017] [2] In the power conversion device described in [1] above, the PWM signal generation unit includes a first signal generation unit (14_1) that generates the PWM signal (Sp1) as a master, and a plurality of second signal generation units (14_2 to 14_12) that generate the PWM signals (Sp2 to Sp12) as slaves to the master, wherein the second signal generation unit starts the PWM period of the PWM signal as a slave in synchronization with the timing at which the PWM period of the PWM signal as a master starts, and the control parameter setting unit may start the control parameter update process after a predetermined time (Td) has elapsed since detecting the start of the PWM period of the PWM signal as a master.

[0018] [3] In the power conversion device described in [2] above, the first signal generation unit and the second signal generation unit each include a counter (15) for counting a clock signal, a comparison unit (16) for comparing the count value of the counter with a value that specifies the duty cycle included in the control parameters, and an output unit (17) for generating a binary signal according to the comparison result by the comparison unit and outputting it as the PWM signal. The counter clears the count value and restarts counting the clock signal when the count value reaches a value that specifies the PWM period included in the control parameters, and the control parameter setting unit may start the control parameter update process after a predetermined time has elapsed since detecting that the count value of the counter of the first signal generation unit has been cleared.

[0019] [4] A typical embodiment of the present invention is a method for generating a plurality of PWM signals using a microcontroller (7) to control a conversion circuit (3) that converts and outputs input power. In this method, the microcontroller has a storage unit (12) that stores control parameters for each PWM signal, including a value that specifies the PWM period, which is one period of the PWM signal, and a value that specifies the duty cycle of the PWM signal. The method includes: a first step (S1) in which the microcontroller acquires the output voltage value of the conversion circuit; a second step (S2) in which the microcontroller performs a control parameter calculation process to calculate at least one of a value that specifies the PWM period and a value that specifies the duty cycle of each PWM signal so that the error between the output voltage value acquired in the first step and the target voltage value approaches zero; a third step (S3 to S6) in which the microcontroller performs a control parameter update process to update the values ​​of the control parameters for each PWM signal stored in the storage unit with the values ​​calculated in the second step; and a fourth step (S7) in which the microcontroller generates a plurality of PWM signals whose timing of the start of the PWM period is synchronized based on the values ​​of the control parameters stored in the storage unit, wherein the third step includes a step (S3 to S6) in which the microcontroller starts the control parameter update process in response to the start of the PWM period and completes the control parameter update process before the next PWM period starts.

[0020] [5] A program according to a typical embodiment of the present invention is characterized in that it causes the microcontroller to execute each step in the signal generation method described in [4] above.

[0021] 2. Specific Examples of Embodiments Specific examples of embodiments of the present invention will be described below with reference to the figures.

[0022] <Embodiment> Figure 1 is a diagram showing the configuration of a power supply device 100 equipped with a power conversion device 2 according to an embodiment.

[0023] The power supply device 100 shown in Figure 1 is, for example, a device that generates DC power from AC power input from an external source and supplies it to a load. For example, the power supply device 100 is a charger, and is a fast charger for charging the battery of an electric vehicle.

[0024] The power supply device 100 includes an AC / DC converter 1 and a power converter 2 as modules for generating DC power. Although Figure 1 shows one set of AC / DC converter 1 and power converter 2, the power supply device 100 may have multiple sets of AC / DC converter 1 and power converter 2.

[0025] The AC / DC converter 1 is a circuit that converts alternating current (AC) power to direct current (DC) power. A smoothing capacitor Cin is connected to the output terminal of the AC / DC converter 1. For example, the AC / DC converter 1 generates and outputs a DC voltage Vin based on a three-phase AC voltage (e.g., 200V) input from an external source. Various known circuit configurations can be used for the AC / DC converter 1.

[0026] The power converter 2 is a circuit that converts and outputs the input power. The power converter 2 is, for example, a DC / DC converter that converts the input voltage Vin into an output voltage Vout of a predetermined magnitude and outputs it. For example, the power converter 2 generates an output voltage Vout of a predetermined magnitude within the range of 500V to 1000V.

[0027] As shown in Figure 1, the power converter 2 has a conversion circuit 3, a control circuit 7, and a pre-drive circuit 8.

[0028] The conversion circuit 3 is a circuit that converts and outputs input power based on a plurality of PWM signals Sp1 to Spn (where n is an integer of 2 or more). The conversion circuit 3 constitutes, for example, an isolated DC / DC converter. The conversion circuit 3 converts the input voltage Vin to an output voltage Vout of a predetermined magnitude based on the plurality of PWM signals Sp1 to Spn and outputs it. For example, the conversion circuit 3 has an inverter circuit 4, a transformer 5, and a rectifier circuit 6.

[0029] The control circuit 7 is a circuit that controls the drive of the conversion circuit 3. The control circuit 7 generates multiple PWM signals so that the output voltage Vout of the conversion circuit approaches the target voltage Vtgt. The detailed configuration of the control circuit 7 will be described later.

[0030] The pre-drive circuit 8 is a circuit that drives the conversion circuit 3 based on a plurality of PWM signals Sp1 to Spn generated by the control circuit 7. For example, the pre-drive circuit 8 generates and outputs binary drive signals Sd1 to Sdm that have sufficient power to drive the inverter circuit 4 of the conversion circuit 3, based on a plurality of PWM signals Sp1 to Spn generated by the control circuit 7.

[0031] Furthermore, if the inverter circuit 4 can be driven without power shortage by the PWM signals Sp1 to Spn generated by the control circuit 7, the pre-drive circuit 8 does not need to be provided.

[0032] Figure 2 shows an example of the circuit configuration of the power conversion device 2 according to the embodiment.

[0033] In this embodiment, the case in which the control circuit 7 generates 12 (n=12) PWM signals Sp1 to Sp12 and the pre-drive circuit 8 generates 6 (m=6) drive signals Sd1 to Sd6 is described, but the number of PWM signals to be generated can be changed in various ways depending on the configuration of the inverter circuit 4 to be driven. Also, in the following description, when the PWM signals Sp1 to Spn are not distinguished, they will be referred to as "PWM signal Sp".

[0034] As shown in Figure 2, the conversion circuit 3 constitutes, for example, a three-phase transformer. The transformer 5 has, for example, primary coils L1u, L1v, L1w connected in a star configuration (Y configuration) and secondary coils L2u, L2v, L2w connected in a star configuration. The combination of the connection methods for the primary coils and the secondary coils is not particularly limited.

[0035] The inverter circuit 4 is a circuit that drives the primary coils L1u, L1v, and L1w of the transformer 5. The inverter circuit 4 is, for example, a bridge circuit. Specifically, the inverter circuit 4 has a switching leg consisting of transistors Muu and Mlu that drives the primary coil L1u, a switching leg consisting of transistors Muv and Mlv that drives the primary coil L1v, and a switching leg consisting of transistors Muw and Mlw that drives the primary coil L1w.

[0036] For example, transistors Muu and Mlu are connected in series between the power line LNp and the ground line LG. Transistors Muv and Mlv are connected in series between the power line LNp and the ground line LG. Transistors Muw and Mlw are connected in series between the power line LNp and the ground line LG. Transistors Muu, Mlu, Muv, Mlv, Muw, and Mlw are power transistors such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors).

[0037] The inverter circuit 4 converts the input voltage Vin into an AC voltage and supplies it to the primary coils L1u, L1v, and L1w of the transformer 5 by switching the on / off state of transistors Muu, Mlu, Muv, Mlv, Muw, and Mlw according to the drive signals Sd1 to Sd6. In other words, the inverter circuit 4 functions as an AC / DC converter.

[0038] The rectifier circuit 6 is a circuit that converts an AC voltage to a DC voltage and outputs it. The rectifier circuit 6 is, for example, a full-wave rectifier circuit. Specifically, the rectifier circuit 6 has a diode bridge circuit consisting of a plurality of diodes Duu, Dlu, Duv, Dlv, Duw, Dlw and a smoothing capacitor Cout. The rectifier circuit 6 rectifies the AC voltage supplied from the secondary side coils L2u, L2v, L2w of the transformer 5 using the diode bridge circuit and smooths it with the smoothing capacitor Cout, thereby outputting an output voltage Vout between it and the output terminals Po1, Po2.

[0039] The pre-drive circuit 8 generates drive signals Sd1 to Sd6 based on PWM signals Sp1 to Sp12 generated by the control circuit 7. The pre-drive circuit 8 has logic circuits 80_1 to 80_6 that generate one drive signal from two PWM signals, for example. Logic circuit 80_1 generates drive signal Sd1 based on PWM signals Sp1 and Sp2. Logic circuit 80_2 generates drive signal Sd2 based on PWM signals Sp3 and Sp4. Logic circuit 80_3 generates drive signal Sd3 based on PWM signals Sp5 and Sp6. Logic circuit 80_4 generates drive signal Sd4 based on PWM signals Sp7 and Sp8. Logic circuit 80_5 generates drive signal Sd5 based on PWM signals Sp9 and Sp10. Logic circuit 80_6 generates drive signal Sd6 based on PWM signals Sp11 and Sp12.

[0040] Furthermore, as described above, if the control circuit 7 can generate drive signals Sd1 to Sd6 that have sufficient power to drive the transistors Muu, Mlu, Muv, Mlv, Muw, and Mlw that constitute the inverter circuit 4, then the pre-drive circuit 8 does not need to be provided.

[0041] Furthermore, the circuit configurations of the inverter circuit 4, transformer 5, and rectifier circuit 6 are not limited to the above example, and various known circuits can be used depending on the control method of the DC / DC converter.

[0042] The control circuit 7 is a program processing device having components (hardware elements) such as a processor such as a CPU (Central Processing Unit), various memories such as a ROM (Read Only Memory) and a RAM (Random Access Memory), a timer, a counter, an A / D conversion circuit, an input / output I / F circuit, and a clock generation circuit, etc., and each component is connected to each other via a bus or a dedicated line. The control circuit 7 is, for example, a MCU. The control circuit 7 has a rewritable non-volatile storage device such as a flash memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory) as a memory. For example, values such as the target voltage Vtgt described later can be rewritten to the non-volatile storage device.

[0043] In the present embodiment, the control circuit 7 is, for example, packaged as an IC (integrated circuit), but is not limited thereto. For example, the control circuit 7 and the pre-drive circuit 8 may be packaged together, or the control circuit 7, the pre-drive circuit 8, and the inverter circuit 4 may be packaged together.

[0044] The control circuit 7 has a function of generating a plurality of PWM signals Sp1 to Sp12 so that the output voltage Vout of the conversion circuit 3 approaches the target voltage Vtgt. Specifically, the control circuit 7 monitors the output voltage Vout and has a function of generating a plurality of PWM signals Sp1 to Sp12 for driving the transistors Muu, Mlu, Muv, Mlv, Muw, Mlw of the inverter circuit 4 so that the error between the output voltage Vout and the target voltage Vtgt approaches zero.

[0045] FIG. 3 is a diagram showing the configuration of the control circuit 7 according to the embodiment.

[0046] As shown in FIG. 3, the control circuit 7 includes, as functional blocks for realizing the above-described functions, for example, a voltage acquisition unit 10, a control parameter setting unit 11, a storage unit 12, and a PWM signal generation unit 13. These functional blocks are realized, for example, when a processor in the MCU as the control circuit 7 described above executes various operations according to a program stored in a memory and controls peripheral circuits such as a timer and a counter, an A / D conversion circuit, and an input / output I / F circuit. Note that some of these functional blocks may be realized by dedicated hardware circuits (such as logic circuits). Further, the control circuit 7 may have functional blocks for realizing other functions in addition to the above functions.

[0047] The voltage acquisition unit 10 is a functional unit that detects the output voltage Vout. The voltage acquisition unit 10 detects the value of the output voltage Vout, for example, by converting a voltage obtained by dividing the output voltage Vout input to the control circuit 7 through a resistor voltage division circuit or the like (not shown) into a digital signal by an A / D conversion circuit.

[0048] The storage unit 12 is a functional unit for storing data and the like necessary for overall control of the power conversion device 2 by the control circuit 7. For example, the storage unit 12 stores values of control parameters 20_1 to 20_12, which are data necessary for generating the PWM signals Sp1 to Sp12. In the following description, when the control parameters 20_1 to 20_12 are not distinguished from each other, they are denoted as "control parameter 20".

[0049] The control parameter 20 includes a value Ctc that specifies the PWM period, which is one period of the PWM signal Sp to be generated, and a value Cdtn that specifies the duty cycle of the PWM signal Sp to be generated. For example, the control parameter 20_1 for generating the PWM signal Sp1 includes a value Ctc that specifies the PWM period of the PWM signal Sp1 and a value Cdt1 that specifies the duty cycle of the PWM signal Sp1, and the control parameters 20_2 to 20_12 for generating the PWM signals Sp2 to Sp12 include a value Ctc that specifies the respective PWM period of the PWM signals Sp2 to Sp12 and values ​​Cdt2 to Cdt12 that specify the respective duty cycles of the PWM signals Sp2 to Sp12.

[0050] In this embodiment, the values ​​that specify the PWM period of each PWM signal Sp1 to Sp12 are common to all of them. For example, if the value of the PWM period of PWM signal Sp1 is changed, the PWM periods of the other PWM signals Sp2 to Sp12 are similarly changed to the same value as the PWM period of PWM signal Sp1.

[0051] The control parameter setting unit 11 is a functional unit that sets the values ​​of the control parameters 20. The control parameter setting unit 11 performs the following: a process to calculate at least one of the values ​​Ctc, which specifies the PWM period of each PWM signal Sp1 to Sp12, and the values ​​Cdt1 to Cdt12, which specify the duty cycle, so that the error between the value of the output voltage Vout detected by the voltage acquisition unit 10 and the value of the target voltage Vtgt approaches zero (hereinafter also referred to as the "control parameter calculation process") and a process to update the values ​​of the control parameters 20_1 to 20_12 for each PWM signal Sp1 to Sp12 stored in the storage unit 12 (hereinafter also referred to as the "control parameter update process").

[0052] The control parameter setting unit 11 performs a control parameter calculation process, for example, by using a known feedback control calculation (e.g., PI control calculation or PID control calculation) to calculate a voltage command value to make the error between the output voltage Vout and the target voltage Vtgt zero, and then uses a known calculation method (e.g., a known spatial vector transformation) to calculate at least one of the values ​​Cdt1 to Cdt12 that specify the duty cycle of the PWM signals Sp1 to Sp12 and the value Ctc that specifies the PWM period, based on the voltage command value. The control parameter setting unit 11 performs the control parameter calculation process periodically. For example, the control parameter calculation process is performed every PWM period.

[0053] The control parameter setting unit 11 sets the values ​​of the control parameters 20 calculated by the control parameter calculation process into the storage unit 12 through a control parameter update process, and updates them sequentially. Here, the control parameter update process is performed at predetermined timings, which will be described later.

[0054] The PWM signal generation unit 13 is a functional unit that generates PWM signals Sp1 to Sp12. The PWM signal generation unit 13 generates multiple PWM signals Sp1 to Sp12 based on control parameters 20_1 to 20_12 stored in the storage unit 12 so that the timing of the start of the PWM cycles of the multiple PWM signals Sp1 to Sp12 is synchronized.

[0055] For example, the PWM signal generation unit 13 includes a first signal generation unit 14_1 that generates a PWM signal Sp1 as a master, and a plurality of second signal generation units 14_2 to 14_12 that generate PWM signals Sp2 to Sp12 as slaves to the master.

[0056] The first signal generation unit 14_1 generates a PWM signal Sp1 based on the value of the control parameter 20_1 stored in the memory unit 12. That is, the first signal generation unit 14_1 generates and outputs a PWM signal Sp1 having a period corresponding to the value Ctc which specifies the PWM period of the control parameter 20_1, and a duty cycle corresponding to the value Cdt1 which specifies the duty cycle of the control parameter 20_1.

[0057] The second signal generation units 14_2 to 14_12 each generate PWM signals Sp2 to Sp12 based on the control parameters 20_2 to 20_12 stored in the memory unit 12. For example, the second signal generation unit 14_2 generates and outputs PWM signals Sp2, each having a period corresponding to the value Ctc that specifies the PWM period of the control parameter 20_2, and a duty cycle corresponding to the values ​​Cdt2 to Cdt12 that specify the duty cycle of the control parameters 20_2 to 20_12.

[0058] Here, the second signal generation units 14_2 to 14_12 start the PWM cycles of the slave PWM signals Sp2 to Sp12 in synchronization with the timing at which the PWM cycle of the master PWM signal Sp1 starts.

[0059] Specifically, the first signal generation unit 14_1 and the second signal generation unit 14_2 each include a counter (CNTR) 15, a comparison unit 16, and an output unit (OTPU) 17, respectively.

[0060] The counter 15 is a functional unit that counts the clock signal CLK. The clock signal CLK may be a binary signal generated inside the MCU 7 by a known clock generation circuit, or it may be a binary signal input from an external source.

[0061] The counter 15 of the first signal generation unit 14_1, acting as a master, for example counts the number of pulses of the clock signal CLK and updates the count value sequentially. When the count value reaches a value Ctc that specifies the PWM period included in the control parameter 20 stored in the storage unit 12, the counter 15 clears the count value and restarts counting the clock signal CLK.

[0062] Here, the count value of counter 15 corresponds to the carrier signal in PWM, and this carrier signal has a sawtooth waveform. Hereafter, the count value of counter 15 of the first signal generation unit 14_1 will be referred to as "count value CNT1", and the count values ​​of counter 15 of each of the second signal generation units 14_2 to 14_12 will be referred to as "count values ​​CNT2 to CNT12", respectively. Also, when count values ​​CNT1 to CNT2 are not distinguished, they will be referred to as "count value CNT".

[0063] The counters 15 of the second signal generation units 14_2 to 14_12, acting as slaves, start counting the clock signal CLK in synchronization with the counter 15 of the first signal generation unit 14_1, acting as a master. For example, the counters 15 of the second signal generation units 14_2 to 14_12 monitor the count value CNT1 of the counter 15 of the first signal generation unit 14_1, and when they detect that the count value CNT1 has been cleared, they clear their own count values ​​CNT2 to CNT12 and restart counting the clock signal CLK. This makes it possible to synchronize the timing at which the PWM cycle of PWM signals Sp2 to Sp12 starts with the timing at which the PWM cycle of PWM signal Sp1 starts.

[0064] The comparison unit 16 is a functional unit that compares the count values ​​CNT1 to CNT12 of the counter 15 with the values ​​Cdt1 to Cdt12 that specify the duty cycle of the control parameter 20. For example, the comparison unit 16 of the first signal generation unit 14_1 determines whether the count value CNT1 is greater than or equal to the duty cycle value Cdt1 and outputs the determination result. Similarly, the comparison unit 16 of the second signal generation unit 14_2 determines whether the count value CNT2 is greater than or equal to the duty cycle value Cdt2 and outputs the determination result. The comparison units 16 of the second signal generation units 14_3 to 14_12 output the determination result using a similar method.

[0065] Here, the values ​​Cdt1 to Cdt12 that specify the duty cycle correspond to the reference value (reference signal) in PWM, and this reference value is a constant value that is updated in accordance with the update of the control parameter 20.

[0066] The output unit 17 is a functional unit that generates a binary signal according to the comparison result by the comparison unit 16 and outputs it as PWM signals Sp1 to Sp12. For example, the output unit 17 of the first signal generation unit 14_1 sets the voltage of the PWM signal Sp1 to a first logic level (e.g., high level) when the count value CNT1 is lower than the value Cdt1 which specifies the duty cycle, and sets the voltage of the PWM signal Sp1 to a second logic level (e.g., low level) when the count value CNT1 is equal to or greater than the value Cdt1 which specifies the duty cycle. Similarly, the output unit 17 of the second signal generation unit 14_2 sets the voltage of the PWM signal Sp2 to a first logic level (e.g., high level) when the count value CNT2 is lower than the value Cdt2 which specifies the duty cycle, and sets the voltage of the PWM signal Sp2 to a second logic level (e.g., low level) when the count value CNT2 is equal to or greater than the value Cdt2 which specifies the duty cycle. The output units 17 of the second signal generation units 14_3 to 14_12 generate PWM signals Sp2 to Sp12 using a similar method.

[0067] Next, an example of the PWM signal Sp generated by the PWM signal generation unit 13 is shown.

[0068] Figure 4 is a timing chart showing an example of a PWM signal Sp according to the embodiment.

[0069] In Figure 4, the horizontal axis represents time. In Figure 4, the waveforms of count value CNT1, PWM signal Sp1, count value CNT2, and PWM signal Sp2 are shown side by side from the top to the bottom of the page. Figure 4 also shows PWM signals Sp1 and Sp2 for four periods, from the first PWM period T1 to the fourth PWM period T4.

[0070] For example, at time t0 in Figure 4, the PWM signal generation unit 13 starts generating the PWM signal Sp. At this time, the counters 15 and comparison units 16 in the first signal generation unit 14_1 and the second signal generation units 14_2 to 14_12 are assumed to already have the control parameters 20_1 to 20_12 (value Ctc specifying the PWM period and values ​​Cdt1 to Cdt12 specifying the duty cycle) stored in the storage unit 12 set, respectively.

[0071] First, at time t0, the count value CNT1 of the counter 15 of the first signal generation unit 14_1, which acts as the master, is cleared. Next, the counter 15 starts counting the clock signal CLK. This starts the first PWM period T1.

[0072] Meanwhile, each counter 15 of the second signal generation unit 14_2 to 14_12, acting as a slave, clears its own count values ​​CNT2 to CNT12 when it detects that the count value CNT1 has been cleared, and starts counting the clock signal CLK.

[0073] Each comparison unit 16 of the first signal generation unit 14_1 and the second signal generation units 14_2 to 14_12 compares the count value CNT of the counter 15 with the values ​​Cdt1 to Cdt12 that specify the duty cycle of each control parameter 20_1 to 20_12, and outputs a value indicating whether the count value CNT is greater than or equal to the value Cdt that specifies the duty cycle. Each output unit 17 of the first signal generation unit 14_1 and the second signal generation units 14_2 to 14_12 generates a binary signal with high level and low level determined based on the value output from the comparison unit 16 as the comparison result, and outputs it as PWM signals Sp1 to Sp12, respectively.

[0074] For example, as shown in Figure 4, the output unit 17 of the first signal generation unit 14_1 sets the PWM signal Sp1 to a high level during the period from time t0 to time t2 when the value specifying the duty cycle Cdt1 is greater than the count value CNT1 in the first PWM period T1, and sets the PWM signal Sp1 to a low level from time t2 onward when the count value CNT1 becomes greater than or equal to the value specifying the duty cycle Cdt1.

[0075] Similarly, as shown in Figure 4, the output unit 17 of the second signal generation unit 14_2 sets the PWM signal Sp2 to a high level during the period from time t0 to time t3 when the value specifying the duty cycle Cdt2 is greater than the count value CNT2 in the first PWM period T1, and sets the PWM signal Sp2 to a low level from time t3 onwards when the count value CNT2 becomes equal to or greater than the value specifying the duty cycle Cdt2.

[0076] Subsequently, at time t4, when the counter 15 of the first signal generation unit 14_1 finds that the count value CNT1 matches the value Ctc which specifies the PWM period of the control parameter 20_1, it clears the count value CNT1 and restarts counting the clock signal CLK. Also, each counter 15 of the second signal generation units 14_2 to 14_12 finds that the count values ​​CNT1 to CNT12 match the value Ctc which specifies the PWM period of the control parameters 20_2 to 20_12, and clears the count value CNT1. Then, each counter 15 of the second signal generation units 14_2 to 14_12 finds that the count value CNT1 has been cleared at time t4 and restarts counting the clock signal CLK. As a result, the first PWM period T1 ends and the next second PWM period T2 begins. In the third PWM period T3 and the fourth PWM period T4, following the second PWM period T2, the PWM signals Sp1 to Sp12 are generated using the same method as described above for the first PWM period T1.

[0077] Here, we will explain the timing at which the control parameter 20 is updated.

[0078] The control parameter setting unit 11 starts and completes the control parameter update process during the period from the start of one PWM cycle to the start of the next PWM cycle. Specifically, the control parameter setting unit 11 starts the control parameter update process in response to the start of one PWM cycle and completes the control parameter update process before the start of the next second PWM cycle T2. For example, in Figure 4, the control parameter setting unit 11 starts the control parameter update process during the period from the start of the first PWM cycle T1 (time t0) to the start of the next second PWM cycle T2 (time t4), and completes updating the control parameters 20_1 to 20_12 stored in the storage unit 12.

[0079] More specifically, the control parameter setting unit 11 starts the control parameter update process after a predetermined time Td has elapsed since detecting the start of the PWM cycle of the master PWM signal Sp1. Preferably, the control parameter setting unit 11 updates the control parameters 20 of each PWM signal stored in the storage unit 12 after a predetermined time Td has elapsed since detecting that the count value CNT1 of the counter 15 of the first signal generation unit 14_1 has been cleared.

[0080] For example, the control parameter setting unit 11 starts the control parameter update process using the timer interrupt function of the MCU. When the control parameter setting unit 11 detects that the count value CNT1 has been cleared, it starts the timer and starts measuring time t, and when the time t measured by the timer reaches a predetermined time Td (t ≥ Td), it executes the control parameter update process.

[0081] For example, in the first PWM period T1 shown in Figure 4, the control parameter setting unit 11 updates the control parameters 20_1 to 20_n of each PWM signal stored in the storage unit 12 at time t1, which is a predetermined time Td elapsed from time t0, when it detects that the count value CNT1 of the counter 15 of the first signal generation unit 14_1 has been cleared. Similarly, in the second PWM period T2 shown in Figure 4, the control parameter setting unit 11 updates the control parameters 20_1 to 20_n of each PWM signal stored in the storage unit 12 at time t5, which is a predetermined time Td elapsed from time t4, when it detects that the count value CNT1 of the counter 15 of the first signal generation unit 14_1 has been cleared.

[0082] Here, the predetermined time Td should be set considering the time required for the control parameter update process and the time from the start of one PWM cycle to the start of the next PWM cycle. In other words, the predetermined time Td should be set so that the control parameter update process is completed before the start of the next PWM cycle. For example, if the value specifying the PWM cycle is CTc, the predetermined time Td may be CTc / 100 < Td ≤ CTc / 10.

[0083] When a new PWM period begins, the first signal generation unit 14_1 and the second signal generation units 14_2 to 14_12 generate PWM signals Sp1 to Sp12 for the new PWM period using the control parameters 20_1 to 20_12 updated in the previous PWM period, in the manner described above. For example, in Figure 4, the PWM signals Sp1 to Sp12 for the third PWM period T3 are generated based on the control parameters 20_1 to 20_12 updated at time t5 in the second PWM period T2, which precedes the third PWM period T3.

[0084] Next, the process flow for generating PWM signals Sp1 to Sp12 in the power conversion device 2 according to the embodiment will be described.

[0085] Figure 5 is a flowchart showing an example of the process flow for generating PWM signals Sp1 to Sp12 in the power conversion device 2 according to the embodiment.

[0086] For example, when a three-phase AC voltage (200V) is supplied to the power supply device 100 from an external source, the AC / DC converter 1 generates an input voltage Vin and inputs it to the power converter 2. This starts up the power converter 2.

[0087] After the power converter 2 is started, the control circuit 7 first obtains the value of the output voltage Vout using the method described above (step S1). Next, the control circuit 7 performs a control parameter calculation process (step S2). Specifically, as described above, the control circuit 7 generates a value Ctc that specifies the PWM period and values ​​Cdt1 to Cdt12 that specify the duty cycle, which are the control parameters 20, for each of the PWM signals Sp1 to Sp12 to be generated, so that the output voltage Vout approaches the target voltage Vtgt.

[0088] The control circuit 7 determines whether or not it has detected the start of the PWM period (step S3). Specifically, as described above, the control circuit 7 determines whether or not it has detected that the count value CNT1 of the counter 15 of the first signal generation unit 14_1, which generates the PWM signal Sp1 as a master, has been cleared.

[0089] If the start of the PWM cycle has not been detected, that is, if the count value CNT1 has not been cleared (step S3: NO), the control circuit 7 waits until the start of the PWM cycle is detected.

[0090] If the start of the PWM cycle is detected, that is, if the count value CNT1 is cleared (Step S3: YES), the control circuit 7 starts measuring time t using the timer interrupt function described above (Step S4). Next, the control circuit 7 determines whether the measured time t has reached a predetermined time Td (Step S5). If the measured time t has not reached the predetermined time Td (Step S5: NO), the control circuit 7 continues measuring time t. On the other hand, if the measured time t has reached the predetermined time Td (Step S5: YES), the control circuit 7 executes the control parameter update process using the method described above (Step S6).

[0091] Subsequently, in response to the start of the next PWM cycle (clearing of the count value CNT1), the control circuit 7 reads the control parameters 20 updated in step S6 and generates PWM signals Sp1 to Sp12 for the next PWM cycle (step S7).

[0092] As the control circuit 7 repeatedly executes the above-described processes (steps S1 to S7), the control parameters 20 are updated with each PWM cycle, and PWM signals Sp1 to Sp12 corresponding to the updated control parameters 20 are periodically generated.

[0093] In the power converter 2 according to the embodiment described above, the control circuit 7 performs a control parameter calculation process to calculate at least one of a value Ctc that specifies the PWM period and values ​​Cdt1 to Cdt12 that specify the duty cycle for each PWM signal Sp1 to Sp12, so that the error between the value of the output voltage Vout and the value of the target voltage Vtgt approaches zero, and a control parameter update process to update the values ​​of the control parameters 20_1 to 20_12 for each PWM signal Sp1 to Sp12 stored in the storage unit 12 with the values ​​calculated by the control parameter calculation process. The control circuit 7 starts the control parameter update process in response to the start of the PWM period and completes the control parameter update process before the start of the next PWM period.

[0094] According to this, the timing for synchronously starting the PWM periods of multiple PWM signals Sp1 to Sp12 and the period during which the control parameter update process is performed can be reliably staggered. As a result, the MCU, which acts as the control circuit 7, will not fall into a state where it cannot perform either the PWM period synchronization process or the control parameter update process. This makes it possible to appropriately generate all PWM signals Sp1 to Sp12. Furthermore, since the update of control parameters 20_1 to 20_12 is completed before the start of the next PWM period, in the next PWM period, PWM signals Sp1 to Sp12 corresponding to the updated control parameters 20_1 to 20_12 can be appropriately generated. Thus, the power converter 2 according to this embodiment makes it possible to stably generate multiple PWM signals Sp1 to Sp12.

[0095] Furthermore, in the power converter 2, the control circuit 7 includes, as described above, a first signal generation unit 14_1 that generates a PWM signal Sp1 as a master, and a plurality of second signal generation units 14_2 to 14_12 that generate PWM signals Sp2 to Sp12 as slaves to the master. As described above, the second signal generation units 14_2 to 14_12 start the PWM cycles of the slave PWM signals Sp2 to Sp12 in synchronization with the timing at which the PWM cycle of the master PWM signal Sp1 starts. The control circuit 7 starts the control parameter update process after a predetermined time Td has elapsed since detecting the start of the PWM cycle of the master PWM signal Sp1. With this, since the control parameter update process is executed triggered by the detection of the start of the PWM cycle of the PWM signal Sp1, it becomes easy to stagger the timing of synchronously starting the PWM cycles of the plurality of PWM signals Sp1 to Sp12 and the period during which the control parameter update process is performed. Furthermore, by adjusting a predetermined time Td, it is possible to easily control the process to start updating control parameters at a desired timing after the start of the PWM cycle.

[0096] Furthermore, as described above, the first signal generation unit 14_1 and the second signal generation units 14_2 to 14_12 each include a counter 15, a comparison unit 16 that compares the count value CNT of the counter 15 with a value Cdt that specifies the duty cycle included in the control parameter 20, and an output unit 17 that generates a binary signal according to the comparison result by the comparison unit 16 and outputs it as a PWM signal. The control circuit 7 starts the control parameter update process after a predetermined time Td has elapsed since detecting that the count value CNT1 of the counter 15 of the first signal generation unit 14_1 has been cleared. This makes it easy to control the timing of starting the measurement of the predetermined time Td, that is, the timing of starting the control parameter update process.

[0097] <<Expansion of Embodiments>> The present invention has been described in detail above based on embodiments, but it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from its essence.

[0098] For example, in the above embodiment, the case where the conversion circuit 3 is an isolated DC / DC converter was shown, but the type of conversion circuit 3 is not limited to this. For example, the conversion circuit 3 may be any circuit equipped with a drive circuit such as an inverter circuit driven by a plurality of PWM signals, and the conversion circuit 3 may be an LLC converter and a dual active bridge (DAB) converter, in addition to general boost converters and buck converters.

[0099] 100...Power supply device, 1...AC / DC converter, 2...Power conversion device, 3...Conversion circuit, 4...Inverter circuit, 5...Transformer, 6...Rectifier circuit, 7...Control circuit, 8...Pre-drive circuit, 10...Voltage acquisition unit, 11...Control parameter setting unit, 12...Storage unit, 13...PWM signal generation unit, 14_1...First signal generation unit, 14_2 to 14_12...Second signal generation unit, 15...Counter, 16 ...comparison section, 17...output section, 20_1 to 20_12...control parameters, Cdt1 to Cdt12...values ​​specifying the duty cycle, Ctc...values ​​specifying the PWM period, CNT1 to CNT12...count values, Vin...input voltage, Vout...output voltage, Vtgt...target voltage, Td...predetermined time, Sd1 to Sd6...drive signals, Sp1 to Sp12...PWM signals, Po1, Po2...output terminals.

Claims

1. A conversion circuit that converts and outputs input power based on a plurality of PWM signals, and a control circuit that generates the plurality of PWM signals so that the output voltage of the conversion circuit approaches a target voltage, wherein the control circuit includes: a voltage acquisition unit that acquires the value of the output voltage; a storage unit that stores control parameters for each PWM signal, including a value that specifies the PWM period which is one period of the PWM signal and a value that specifies the duty cycle of the PWM signal; a control parameter setting unit that performs a control parameter calculation process that calculates at least one of the value that specifies the PWM period and the value that specifies the duty cycle for each PWM signal so that the error between the output voltage value acquired by the voltage acquisition unit and the target voltage value approaches zero; a control parameter update process that updates the value of the control parameter for each PWM signal stored in the storage unit with the value calculated by the control parameter calculation process; and a PWM signal generation unit that generates the plurality of PWM signals based on the control parameters stored in the storage unit so that the timing of when the PWM periods of the plurality of PWM signals start is synchronized. The power converter is configured such that the control parameter setting unit starts the control parameter update process in response to the start of the PWM cycle and completes the control parameter update process before the next PWM cycle starts.

2. The power converter according to claim 1, wherein the PWM signal generation unit includes a first signal generation unit that generates the PWM signal as a master, and a plurality of second signal generation units that generate the PWM signal as a slave to the master, the second signal generation unit starts the PWM period of the PWM signal as a slave in synchronization with the timing at which the PWM period of the PWM signal as a master starts, and the control parameter setting unit starts the control parameter update process after a predetermined time has elapsed since detecting the start of the PWM period of the PWM signal as a master.

3. A power conversion device according to claim 2, wherein the first signal generation unit and the second signal generation unit each include: a counter for counting a clock signal; a comparison unit for comparing the count value of the counter with a value specifying the duty cycle included in the control parameters; and an output unit for generating a binary signal according to the comparison result by the comparison unit and outputting it as the PWM signal, wherein the counter clears the count value and restarts counting the clock signal when the count value reaches a value specifying the PWM period included in the control parameters, and the control parameter setting unit starts the control parameter update process after a predetermined time has elapsed since detecting that the count value of the counter of the first signal generation unit has been cleared.

4. A signal generation method for generating a plurality of PWM signals by a microcontroller to control a conversion circuit that converts input power and outputs it, wherein the microcontroller has a storage unit that stores control parameters for each PWM signal, including a value that specifies the PWM period which is one period of the PWM signal and a value that specifies the duty cycle of the PWM signal, and the method includes: a first step in which the microcontroller obtains the output voltage value of the conversion circuit; a second step in which the microcontroller performs a control parameter calculation process to calculate at least one of the value that specifies the PWM period and the value that specifies the duty cycle for each PWM signal so that the error between the output voltage value detected in the first step and the target voltage value approaches zero; a third step in which the microcontroller performs a control parameter update process to update the value of the control parameter for each PWM signal stored in the storage unit with the value calculated in the second step; and a fourth step in which the microcontroller generates a plurality of PWM signals whose timing of the start of the PWM period is synchronized based on the value of the control parameter stored in the storage unit. The third step is a signal generation method comprising the step of the microcontroller starting the control parameter update process in response to the start of the PWM cycle and completing the control parameter update process before the next PWM cycle starts.

5. A program that causes the microcontroller to execute each step in the signal generation method described in claim 4.

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