Semiconductor package and method for manufacturing semiconductor package

Abstract

The present invention prevents defects caused by cracks in a Wafer Level Chip Scale Package (WLCSP).　This semiconductor package comprises a semiconductor substrate, an insulating film and back surface wiring, a guard ring, and a protective film. In this semiconductor package, the insulating film and the back surface wiring are formed in a wiring region on the back surface of the semiconductor substrate. Further, in the semiconductor package, the guard ring is formed around the back surface wiring. Moreover, in the semiconductor package, the protective film covers the guard ring, the insulating film, and the back surface wiring.

Description

Semiconductor Package and Method for Manufacturing the Same

[0001] The present technology relates to a semiconductor package. More specifically, it relates to a semiconductor package that performs rewiring and terminal formation at the wafer level, and a method for manufacturing the semiconductor package.

[0002] Conventionally, for the purpose of miniaturizing the package size, etc., WLCSPs (Wafer Level Chip Scale Packages) that perform rewiring and terminal formation at the wafer level have been used in various circuits. For example, a WLCSP has been proposed in which an insulating film and a wiring layer are formed in a wiring region on the back surface of a semiconductor substrate, and a groove is formed between a scribe line and the wiring region on the back surface thereof (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 1-309351

[0004] In the above-described conventional technology, by forming a groove between the scribe line and the insulating film or wiring layer, peeling of the insulating film is prevented. However, in the above-described conventional technology, if a crack occurs during singulation, there is a risk that the crack will reach the wiring region and cause defects in the circuits and elements within the wiring region.

[0005] The present technology has been created in view of such a situation, and aims to prevent defects due to cracks in WLCSPs. [[ID=十六]] [[ID=十七]]

[0006] The present technology has been made to solve the above-described problems, and a first aspect thereof is a semiconductor package including a semiconductor substrate, an insulating film and a back surface wiring formed in a wiring region on the back surface of the semiconductor substrate, a guard ring formed around the back surface wiring, and a protective film covering the guard ring, the insulating film, and the back surface wiring, and a method for manufacturing the same. This brings about an effect of suppressing the crack from reaching the wiring region.

[0007] Also, in this first aspect, the guard ring may be formed between the outer periphery of the semiconductor substrate and the wiring region. This brings about an effect of suppressing the crack from reaching the wiring region.

[0008] Furthermore, in this first aspect, an insulating film may be embedded in the guard ring. This results in the embedding occurring during the deposition of the insulating film.

[0009] Furthermore, in this first aspect, the protective film may be embedded in the guard ring. This improves the adhesion of the protective film.

[0010] Furthermore, in this first aspect, the wiring region may be engraved into the surface side of the semiconductor substrate, and the guard ring may be formed within the wiring region along the outer circumference of the wiring region. This results in an improved effect of suppressing crack propagation.

[0011] Furthermore, in this first aspect, an insulating film may be embedded in the guard ring. This results in the embedding occurring during the deposition of the insulating film.

[0012] Furthermore, in this first aspect, the back wiring may include a first back wiring routed on a first wiring layer and a second back wiring routed on a second wiring layer, and the protective film may include a first protective film covering the first back wiring and a second protective film covering the second back wiring. This results in an improvement in mounting density.

[0013] Furthermore, a second aspect of this technology is a semiconductor package comprising a semiconductor substrate including stacked silicon layers and wiring layers, a guard ring formed on the wiring layer, and a groove formed between the outer periphery of the semiconductor substrate and the guard ring when viewed from a direction perpendicular to the substrate plane of the semiconductor substrate, with one end reaching the silicon layer when viewed from a direction parallel to the substrate plane. This has the effect of suppressing the propagation of cracks from the side of the silicon layer.

[0014] Furthermore, in this second aspect, the other end of the groove may reach the surface of the wiring layer. This has the effect of suppressing the propagation of cracks from the side of the silicon layer.

[0015] Furthermore, in this second aspect, the other end of the groove may reach a predetermined position between the front and back surfaces of the wiring layer. This results in improved flatness of the semiconductor substrate surface.

[0016] Furthermore, in this second aspect, the other end of the groove may reach the surface of the silicon layer. This results in an improvement in the flatness of the semiconductor substrate surface.

[0017] Furthermore, in this second aspect, a predetermined embedding material with lower rigidity than silicon may be embedded in the groove. This results in an improved crack suppression effect compared to the case where no embedding is performed.

[0018] Furthermore, in this second aspect, bonding resin may be further embedded in the groove to bond the surface of the semiconductor substrate to the light-transmitting substrate. This has the effect of improving the bonding strength between the semiconductor substrate and the bonding resin.

[0019] Furthermore, in this second aspect, the device further comprises a light-transmitting substrate and a bonding resin that joins the surface of the semiconductor substrate to the light-transmitting substrate, and one end of the groove may reach the bonding resin. This provides the effect that flare is suppressed when the groove has light-shielding properties.

[0020] Furthermore, in this second aspect, the groove may include a first groove formed along the outer circumference of the semiconductor substrate and a second groove formed between the first groove and the guard ring. This has the effect of improving the probability of crack prevention.

[0021] Furthermore, in this second aspect, the semiconductor substrate may further comprise a light-transmitting substrate and a bonding resin that bonds a predetermined area on the surface of the semiconductor substrate surrounding the pixel area to the light-transmitting substrate. This provides the effect of creating a cavity.

[0022] This is an example of a cross-sectional view of a wafer in the first embodiment of this technology. This is an example of a top view of a wafer in the first embodiment of this technology. This is an example of an enlarged view of the top surface of a wafer in the first embodiment of this technology. This is a cross-sectional view illustrating the process up to the formation of a resist for creating through holes in the first embodiment of this technology. This is a cross-sectional view illustrating the process up to the formation of a resist while avoiding scribe lines and guard rings in the first embodiment of this technology. This is a diagram illustrating the process up to dicing in the first embodiment of this technology. This is a flowchart illustrating an example of the semiconductor package manufacturing process in the first embodiment of this technology. This is an example of a cross-sectional view of a wafer in the first embodiment of this technology when a guard ring is not embedded. This is an example of a cross-sectional view of a wafer in the first embodiment of this technology when a cavity is provided. This is an example of a cross-sectional view of a wafer in the first modified example of the first embodiment of this technology. This is a cross-sectional view illustrating the process up to the formation of a resist for creating through holes in the first modified example of the first embodiment of this technology. This is a cross-sectional view illustrating the process up to the formation of a resist while avoiding scribe lines and guard rings in the first modified example of the first embodiment of this technology. This is a cross-sectional view illustrating the process up to the formation of a protective film in a first modified example of the first embodiment of this technology. This is an example of a cross-sectional view of a wafer in a second modified example of the first embodiment of this technology. This is a cross-sectional view illustrating the process up to the formation of a resist for creating through holes in a second modified example of the first embodiment of this technology. This is a cross-sectional view illustrating the process up to the formation of a resist while avoiding scribe lines and guard rings in a second modified example of the first embodiment of this technology. This is a diagram illustrating the process up to dicing in a second modified example of the first embodiment of this technology. This is an example of a cross-sectional view of a wafer in a fourth modified example of the first embodiment of this technology. This is a cross-sectional view illustrating the process up to the formation of a resist for creating through holes in a fifth modified example of the first embodiment of this technology. This is a cross-sectional view illustrating the process up to the formation of a resist while avoiding scribe lines and guard rings in a fifth modified example of the first embodiment of this technology.This is a diagram illustrating the process up to dicing in the fifth modified example of the first embodiment of this technology. This is an example of a cross-sectional view of a semiconductor package in the second embodiment of this technology. This is a diagram illustrating the process up to filling the grooves in the second embodiment of this technology. This is a diagram illustrating the process up to bonding the light-transmitting substrate in the second embodiment of this technology. This is a diagram illustrating the process up to dicing in the second embodiment of this technology. This is an example of a cross-sectional view of a semiconductor package in the second embodiment of this technology when the grooves are not filled. This is an example of a cross-sectional view of a semiconductor package in the first modified example of the second embodiment of this technology. This is an example of a cross-sectional view of a semiconductor package in the second modified example of the second embodiment of this technology. This is an example of a cross-sectional view of a semiconductor package in the third modified example of the second embodiment of this technology. This is an example of a cross-sectional view of a semiconductor package in the fourth modified example of the second embodiment of this technology. This is an example of a cross-sectional view of a semiconductor package in the fifth modified example of the second embodiment of this technology. This is an example of a cross-sectional view of a semiconductor package in the sixth modified example of the second embodiment of this technology. This is a block diagram illustrating an example of a schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit.

[0023] The following describes the embodiments for implementing this technology (hereinafter referred to as "embodiments"). The description will proceed in the following order: 1. First embodiment (an example in which a guard ring is embedded in an insulating film and covered with a protective film) 2. Second embodiment (an example in which a guard ring is formed with one end reaching the silicon layer) 3. Application example to a mobile body

[0024] <1. First Embodiment> [Example of Wafer Configuration] Figure 1 is an example of a cross-sectional view of a wafer 100 in the first embodiment of this technology. A predetermined axis parallel to the plane of the wafer 100 is defined as the X-axis, and an axis perpendicular to that plane is defined as the Z-axis. An axis perpendicular to the X-axis and Z-axis is defined as the Y-axis. The figure shows a cross-sectional view from the Y-axis direction.

[0025] The wafer 100 comprises a light-transmitting substrate 110, a bonding resin 120, and a sensor substrate 130. The sensor substrate 130 is an example of a semiconductor substrate as described in the claims.

[0026] Of the two surfaces of the sensor substrate 130, the light-receiving surface is designated as the "front surface," and the surface opposite to it is designated as the "back surface." On the front surface of this sensor substrate 130, a predetermined pixel region 131 has multiple pixels arranged in an array, and an on-chip lens 132, a photodiode, and various transistors are arranged for each pixel. The pixels include active pixels that are not shielded from light and OPB (optical black) pixels that are shielded from light. Each active pixel generates a pixel signal by photoelectric conversion of incident light.

[0027] Furthermore, the sensor substrate 130 may have a DRAM (Dynamic Random Access Memory) and a signal processing circuit that performs signal processing on the pixel signals output from the pixel area 131.

[0028] The bonding resin 120 is an adhesive member for bonding the sensor substrate 130 and the light-transmitting substrate 110 in a region including at least the pixel region 131. For example, siloxane resins, acrylic resins, or epoxy resins can be used as the bonding resin 120. As the material for the bonding resin 120, a resin material with adjusted optical properties (refractive index, extinction coefficient, etc.) may be selected so that light can be received well in the pixel region 131. In particular, a material with a refractive index of about 0.5 to 3.0 can be used, but a refractive index close to that of the light-transmitting substrate 110 is even more preferable. In addition, a small extinction coefficient is preferable, and a coefficient close to 0 is even more preferable. Furthermore, the bonding resin 120 may contain fillers made of inorganic or organic materials to improve reliability. Also, in the figure, the bonding resin 120 is completely filled between the light-transmitting substrate 110 and the sensor substrate 130 in a cavity-less structure. However, as will be described later, a cavity structure in which the bonding resin 120 is provided only in a part of the outer periphery may also be used.

[0029] Glass is generally used as the light-transmitting substrate 110, but any transparent material that can transmit light is acceptable, and other transparent materials such as sapphire, quartz, or transparent organic substrates may be used depending on the application.

[0030] Furthermore, the wafer 100 includes a plurality of semiconductor packages 200. These semiconductor packages 200 are separated by cutting the wafer 100 along the scribe lines. In the figure, the regions from coordinates X1 to X2 and from coordinates X5 to X6 correspond to the scribe lines. The cut-out semiconductor packages 200 function as CMOS (Complementary Metal Oxide Semiconductor) image sensors. These CMOS image sensors are, for example, back-illuminated image sensors. However, the CMOS image sensors may also be front-illuminated.

[0031] On the back surface of the sensor substrate 130, a wedge-shaped groove is formed as a guard ring 152 along the outer circumference of the semiconductor package. On the back surface of the sensor substrate 130, in the wiring region surrounded by the guard ring 152, a recess is formed that is carved out on the surface side of the surrounding area (scribe lines, guard ring 152, etc.), and an insulating film 141 is deposited in this recess. In the figure, the region from coordinates X3 to X4 corresponds to the wiring region.

[0032] Furthermore, a predetermined number of through-holes are formed around the pixel area 131 on the back surface of the sensor substrate 130. An insulating film 141 is also deposited on the sides of these through-holes. In addition, the insulating film 141 is embedded in the guard ring 152. This guard ring 152 helps to prevent cracks from reaching the wiring area inside it.

[0033] Furthermore, back-side wiring 142 is formed on the insulating film 141 of the wiring region. Also, back-side wiring 142 is formed along the insulating film 141 within the through-hole. This forms the through-electrode 151.

[0034] Furthermore, as mentioned above, a recess is formed inside the guard ring 152, in other words, in the wiring area surrounded by the scribe line, which is carved out on the surface side compared to the surrounding area, and the back wiring 142 is routed in this recess. For this reason, the back wiring 142 is formed on the surface side (downward in the figure) of the scribe line.

[0035] Furthermore, a protective film 143, such as a solder mask, is formed on the back surface of the sensor substrate 130, inside the scribe lines. However, the protective film 143 is not formed in the areas where external terminals are formed, and the back surface wiring 142 is exposed in those areas. Also, the protective film 143 is embedded in the through-electrode 151.

[0036] As described above, pixels are arranged within the pixel region 131 on the surface of the sensor substrate 130, and an insulating film 141 and back wiring 142 are formed on the wiring region on the back surface of the sensor substrate 130. In addition, a guard ring 152 is formed around the back wiring 142 (between the outer periphery of the sensor substrate 130 and the wiring region after individualization). The guard ring 152, the insulating film 141 and the back wiring 142 are covered with a protective film 143.

[0037] Furthermore, in the configuration shown in the figure, only the sensor substrate 130, bonding resin 120, and light-transmitting substrate 110 are provided on the scribe line, and the insulating film 141 and protective film 143 are not formed. The semiconductor package 200 cut along this scribe line has wiring and terminals formed at the wafer level before being cut from the wafer 100. Such a semiconductor package 200 is called a WLCSP (Wafer Level Chip Scale Package).

[0038] Here, we consider a comparative example in which an insulating film 141 and a protective film 143 are further deposited on the scribe line. In this comparative example, during dicing, the blade tends to bite into the insulating film 141 and protective film 143, which are made of different materials from the sensor substrate 130, making chipping on the sides more likely.

[0039] In contrast, in the first embodiment illustrated in the figure, only the sensor substrate 130, bonding resin 120, and light-transmitting substrate 110 are provided on the scribe line, and the insulating film 141 and protective film 143 are removed from the scribe line during the manufacturing process. This structure minimizes the effects of chipping due to fragmentation. It also reduces the difficulty of the fragmentation process. Furthermore, since the protective film 143 is not processed on the scribe line, it is possible to prevent the protective film 143 from peeling off due to changes over time. This improves reliability.

[0040] Furthermore, in Patent Document 1, a groove is formed between the scribe line and the wiring area, and nothing is embedded in the groove. In contrast, in the same figure, a wedge-shaped groove is formed between the scribe line and the wiring area as a guard ring 152, an insulating film 141 is embedded in the guard ring 152, and the guard ring 152 and the like are covered with a protective film 143. With this structure, even if a crack occurs on the side surface of the sensor substrate 130 during individualization, the crack is stopped by the guard ring 152 and does not enter the wiring area. Therefore, the circuit in the wiring area is not destroyed by the crack, and no defects due to cracks occur, so a high yield can be achieved.

[0041] As described above, by minimizing the layered structure of the scribe lines and forming a guard ring 152 between the scribe lines and the wiring area, the crack size during fragmentation can be suppressed.

[0042] Furthermore, because it is covered with a protective film 143, the semiconductor package 200 (i.e., WLCSP) after individualization does not have any exposed wiring layers formed on the sensor substrate 130 around the chip. This makes it possible to suppress damage to the wiring layers when the edges come into contact during mounting or storage of the individualized semiconductor package 200.

[0043] Further, the wiring region is engraved on the front side (lower side) rather than the back side with a scribe line, and a wiring layer including the back surface wiring 142 is formed. Thus, since the wiring layer is formed in a portion deeper than the back surface of the sensor substrate 130, the thickness can be made smaller than that of a normal chip without performing digging. Also, the processing of the scribe line is minimized, and an improvement in chip strength can be expected.

[0044] Note that although the laminated structure of the scribe line and the structure of the guard ring 152 illustrated in the figure are applied to the CMOS image sensor, the present invention is not limited to this configuration and can be applied to semiconductor elements other than the CMOS image sensor, such as light emitting elements. The same applies to each modification of the first embodiment described later.

[0045] FIG. 2 is an example of a top view of the wafer 100 in the first embodiment of the present technology. The figure shows a top view seen from above with the light receiving surface side of the sensor substrate 130 facing downward. The wafer 100 is divided into a plurality of semiconductor packages 200 by vertical scribe lines from coordinate X1 to X2 and from coordinate X5 to X6 and horizontal scribe lines.

[0046] In the scribe line, the back surface of the sensor substrate 130 is exposed, and the region surrounded by the scribe line is covered with the protective film 143. Also, the back surface wiring 142 is exposed at the location where the external terminals are formed.

[0047] FIG. 3 is an example of an enlarged top view of the wafer in the first embodiment of the present technology. The alternate long and short dash line in the figure indicates the boundary of the guard ring 152 whose upper part is covered with the protective film 143. As illustrated in the figure, the guard ring 152 is formed along the scribe line on the inner side thereof.

[0048] [Method for manufacturing semiconductor package] Subsequently, a method for manufacturing the semiconductor package 200 will be described with reference to FIGS. 4 to 6.

[0049] First, as illustrated in Figure 4a, an on-chip lens 132 is formed on the surface of the sensor substrate 130 for each pixel, and a light-transmitting substrate 110 is bonded to the back surface of the sensor substrate 130 with bonding resin 120. Then, a resist 211, which serves as a mask during etching, is formed on the back surface of the sensor substrate 130 by photolithography. This resist 211 is formed while avoiding the areas where the guard ring 152 is formed and the wiring area from coordinates X3 to X4.

[0050] Then, as illustrated in figure b, grooves are formed as guard rings 152 in the unmasked areas by dry etching, and recesses are formed in the wiring areas. The depth of these recesses is preferably equal to or less than the thickness of the insulating film 141, for example, about 10 micrometers (μm).

[0051] Then, as illustrated in figure c, a resist 212 for creating through holes is formed. This resist 212 is formed while avoiding the areas where the through holes are to be formed.

[0052] Then, as illustrated in Figure 5a, through holes are formed on the back surface of the sensor substrate 130 by etching.

[0053] Then, as illustrated in figure b, an insulating film 141 is formed on the back surface of the sensor substrate 130 by CVD (Chemical Vapor Deposition). At this time, the insulating film 141 is embedded in the guard ring 152.

[0054] Then, as illustrated in figure c, a resist 213 is formed in the wiring region.

[0055] Then, as illustrated in Figure 6a, unnecessary insulating film 141 and resist 213 are removed by CMP (Chemical Mechanical Polishing) processing, except for the areas where backside wiring is to be formed.

[0056] Then, as illustrated in figure b, the insulating film 141 at the bottom of the through-hole is removed along with the resist 213 by full-surface etch-back.

[0057] Then, as illustrated in figure c, back surface wiring 142 is formed, and next a protective film 143 is deposited, avoiding the scribe lines. Finally, the semiconductor package 200 is cut out by dicing.

[0058] Figure 7 is a flowchart showing an example of the manufacturing process of a semiconductor package 200 in the first embodiment of this technology. An on-chip lens 132 is formed on the surface of the sensor substrate 130 for each pixel, and a light-transmitting substrate 110 is bonded to the back surface of the sensor substrate 130 with a bonding resin 120. Then, a resist 211 is formed on the back surface of the sensor substrate 130 by photolithography (step S901).

[0059] Then, grooves are formed as guard rings 152 in the unmasked areas by dry etching, and recesses are formed in the wiring areas (step S902). Then, resist 212 is formed for creating through holes (step S903).

[0060] Then, through holes are formed on the back surface of the sensor substrate 130 (step S904), and an insulating film 141 is deposited on the back surface by CVD (step S905). Then, a resist 213 is formed in the wiring region (step S906).

[0061] Then, by CMP processing, unnecessary insulating film 141 and resist 213 are removed except for the areas where back wiring is to be formed (step S907), and by full-surface etch-back, the insulating film 141 at the bottom of the through-hole is removed along with the resist 213 (step S908).

[0062] Then, back-side wiring 142 is formed, and next, a protective film 143 is deposited, avoiding the scribe lines. Then, the semiconductor package 200 is cut out by dicing (step S909). After step S909, various processes are performed as needed, and the semiconductor package manufacturing process is completed.

[0063] As illustrated in Figure 8, the insulating film 141 can be omitted from the guard ring 152, leaving it as a cavity. The structure shown in the figure can be applied to each of the first to fifth modifications of the first embodiment described later.

[0064] Furthermore, as illustrated in Figure 9, a cavity can be created by bonding the area around the pixel region 131 on the back surface to the light-transmitting substrate 110 using a bonding resin 120, thereby forming a space surrounded by the light-transmitting substrate 110, the bonding resin 120, and the sensor substrate 130. The structure shown in the figure can be applied to each of the first to fifth modifications of the first embodiment described later.

[0065] Thus, according to the first embodiment of this technology, the guard ring 152 is embedded in the insulating film 141 and the guard ring 152 and the like are covered with the protective film 143, which makes it possible to suppress cracks from reaching the wiring area during individualization. This makes it possible to prevent defects caused by cracks.

[0066] Furthermore, since the insulating film 141 and protective film 143 are removed from the scribe line during the manufacturing process, chipping during individual piece formation can be suppressed.

[0067] [First Modification] In the first embodiment described above, an insulating film 141 was embedded in the guard ring 152, but the configuration is not limited to this. The semiconductor package 200 in this first modification of the first embodiment differs from the first embodiment in that a protective film 143 is embedded in the guard ring 152.

[0068] Figure 10 is an example of a cross-sectional view of a wafer 100 in a first modified example of the first embodiment of the present technology. This wafer 100 in the first modified example of the first embodiment differs from the first embodiment in that a protective film 143 is embedded in the guard ring 152. This suppresses cracking and improves the adhesion of the protective film 143 to the peeling surface through an anchoring effect against the peeling of the protective film 143.

[0069] A method for manufacturing the semiconductor package 200 in a first modification of the first embodiment will be described with reference to Figures 11 to 13.

[0070] The steps illustrated in a, b, and c in Figure 11 and a and b in Figure 12 are the same as those in the first embodiment.

[0071] In the process illustrated in c in Figure 12, a resist 213 is formed in the wiring region. However, this resist 213 is thicker than that of the first embodiment and protrudes to the back side (upper side in the figure).

[0072] Then, as illustrated in Figure 13a, the CMP process removes unnecessary insulating film 141 and resist 213 from the scribe lines and other areas, except for the areas where back-side wiring is formed.

[0073] Then, as illustrated in figure b, the insulating film 141 at the bottom of the through hole and the insulating film 141 inside the guard ring 152 are removed by etch-back or dry etching using a resist.

[0074] Then, as illustrated in figure c, a protective film 143 is embedded in the guard ring 152, patterned by lithography, and made into a permanent film. This enhances the chipping prevention effect from the scribed area and the peeling suppression effect of the protective film 143. In addition, back surface wiring 142 is formed. After this, dicing is performed.

[0075] As described above, according to the first modification of the first embodiment of this technology, since the protective film 143 is embedded in the guard ring 152, defects due to cracks can be prevented and the adhesion of the protective film 143 can be improved.

[0076] [Second Modification] In the first embodiment described above, a guard ring 152 was formed along the scribe line on the back surface of the sensor substrate 130, but the configuration is not limited to this. The semiconductor package 200 in this second modification of the first embodiment differs from the first embodiment in that a guard ring 152 is formed along its outer circumference in a recessed wiring region on the surface side (lower side in the figure).

[0077] Figure 14 is an example of a cross-sectional view of a wafer 100 in a second modified example of the first embodiment of this technology. This wafer 100 in the second modified example of the first embodiment differs from the first embodiment in that a guard ring 152 is formed along the outer circumference of the recessed wiring region on the surface side. In addition, an insulating film 141 is embedded in the guard ring 152, similar to the first embodiment.

[0078] Since the wiring area is carved into the surface side (bottom side), the position Z2 of the upper end of the guard ring 152 is lower than the position Z1 on the back surface of the sensor substrate 130 in the Z-axis direction. By forming the guard ring 152 on the surface side of the sensor substrate 130 than the back surface, the area in which the crack size can be suppressed in the cross-sectional direction is expanded compared to the first embodiment, and the crack propagation suppression effect can be improved.

[0079] Referring to Figures 15 to 17, a method for manufacturing the semiconductor package 200 in a second modified example of the first embodiment will be described.

[0080] First, as illustrated in Figure 15a, a resist 211, which will serve as a mask during etching, is formed on the back surface of the sensor substrate 130 by photolithography. This resist 211 is formed while avoiding the wiring area from coordinates X3 to X4.

[0081] Then, as illustrated in figure b, a recess is formed in the unmasked wiring region.

[0082] Then, as illustrated in figure c, a resist 212 is formed for creating the through-hole and the guard ring 152. This resist 212 is formed while avoiding the areas where the through-hole is formed and the areas where the guard ring 152 is formed.

[0083] Then, as illustrated in Figure 16a, a guard ring 152 is formed along the outer circumference of the wiring area by dry etching, and through holes are also formed.

[0084] Then, as illustrated in figure b, the insulating film 141 is embedded in the guard ring 152. In this figure, the guard ring 152 is formed in the wiring region carved into the surface side (downward side) relative to the convex scribe line. As a result, cracks from the scribe that occur in the vertical direction during dicing can be prevented by the vertically extending guard ring 152, and the guard area is expanded. Therefore, the effect of suppressing crack propagation can be further improved.

[0085] Then, as illustrated in figure c, a resist 213 is formed in the wiring region. However, this resist 213 is thicker than that of the first embodiment and protrudes to the back side (upper side in the figure).

[0086] Then, as illustrated in Figure 17a, the CMP process removes unnecessary insulating film 141 and resist 213 from the scribe lines and other areas, except for the areas where back-side wiring is formed.

[0087] Then, as illustrated in figure b, the insulating film 141 at the bottom of the through hole is removed by etch-back or dry etching using a resist.

[0088] Then, as illustrated in figure c, back surface wiring 142 is formed, and next a protective film 143 is deposited, avoiding the scribe lines. Finally, the semiconductor package 200 is cut out by dicing.

[0089] Thus, according to the second modification of the first embodiment of this technology, since the guard ring 152 is formed on the surface side of the sensor substrate 130 rather than the back side, the crack propagation suppression effect can be improved.

[0090] [Fourth Modification] In the first embodiment described above, the wiring layer including the back surface wiring 142 was a single layer, but the wiring layer can also be made into a multilayer of two or more layers. The semiconductor package 200 in this fourth modification of the first embodiment differs from the first embodiment in that the wiring layer is multilayered.

[0091] Figure 18 is an example of a cross-sectional view of a wafer 100 in a fourth modification of the first embodiment of the present technology. Backside wiring 142-1 constituting the first wiring layer is formed on the insulating film 141. The backside wiring 142-1 is covered with an insulating protective film 143-1, and backside wiring 142-2 constituting the second wiring layer is formed on the back side of the protective film 143-1. Then, the backside wiring 142-2 is covered with the protective film 143-2. ​​By multi-layering the wiring layers in this way, the mounting density can be improved.

[0092] Note that the back-side wiring 142-1 and 142-2 are examples of the first and second back-side wiring described in the claims. Also, the protective films 143-1 and 143-2 are examples of the first and second protective films described in the claims.

[0093] However, a wedge-shaped region is provided along the outer circumference of the protective film 143-1 at the location indicated by the arrow, and the protective film 143-2 is embedded in that region. This structure suppresses delamination between the first and second layers and prevents delamination even when chipping occurs from the scribe line.

[0094] Furthermore, the structures of the first to third modifications of the first embodiment can be applied to the fourth modification of the first embodiment.

[0095] Thus, according to this fourth modification of the technology, the mounting density can be improved by making the wiring layers multilayered.

[0096] [Fifth Modification] In the first embodiment described above, the unnecessary insulating film 141 and resist 213 were removed by CMP processing, but the manufacturing method is not limited to this. The manufacturing method of the semiconductor package 200 in the fifth modification of the first embodiment of this technology differs from the first embodiment in that the unnecessary insulating film 141 and resist 213 are removed by dry etching.

[0097] Referring to Figures 19 to 21, a method for manufacturing the semiconductor package 200 in a fifth modified example of the first embodiment will be described.

[0098] The steps illustrated in a, b, and c in Figure 19 and a, b, and c in Figure 20 are the same as those in the first embodiment. However, the resist 213 in c in Figure 20 is thicker than that in the first embodiment and protrudes to the back side (upper side in the figure).

[0099] In Figure 21a, the unnecessary insulating film 141 and resist 213 are removed by dry etching, except for the areas where back-side wiring is formed. Note that dry etching is not the only method available; wet etching, for example, can also be used as long as it can remove the unnecessary insulating film 141 and other materials.

[0100] The steps illustrated in b and c in the figure are the same as those in the first embodiment.

[0101] Thus, according to the fifth modification of the first embodiment of this technology, CMP processing becomes unnecessary because the unwanted insulating film 141 and resist 213 are removed by dry etching or the like.

[0102] <2. Second Embodiment> In the first embodiment described above, a guard ring 152 was formed on the back surface of the sensor substrate 130, but it is also possible to form the guard ring 152 on the light-receiving side. The semiconductor package 200 in this second embodiment differs from the first embodiment in that a guard ring 152 is formed on the light-receiving side of the sensor substrate 130, and a groove is formed at one end that reaches the silicon layer.

[0103] Figure 22 is an example of a cross-sectional view of a semiconductor package 200 in a second embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200. In the figure, b shows a top view when observed from above with the light-receiving side facing upwards.

[0104] As illustrated in Figure a, the semiconductor package 200 in the second embodiment differs from the first embodiment in that grooves 160 are further formed. The sensor substrate 130 also includes a wiring layer 133 and a silicon layer 134. Backside wiring 142 and a protective film 143 are formed on the back surface of the silicon layer 134, and the wiring layer 133 is laminated on the surface of the silicon layer 134. Backside wiring 142, through electrodes 151 and solder balls 144 are also formed on the silicon layer 134. Note that the back surface of the semiconductor package 200 is not limited to a BGA (Ball Grid Array) structure having both backside wiring 142 and solder balls 144, as illustrated in the figure. It may also be an LGA (Land Grid Array) structure with no solder balls 142 on the back surface and lands with exposed backside wiring 142 arranged thereon.

[0105] Furthermore, a pixel region 131 is provided on the light-receiving surface of the wiring layer 133, and multiple pixels are arranged in an array.

[0106] Furthermore, the dashed line at b in the figure indicates the location where the guard ring 152 is formed. As illustrated in b in the figure, the guard ring 152 is formed around the pixel region 131 in the wiring layer 133.

[0107] Furthermore, the groove 160 is formed to surround the outer circumference of the guard ring 152. In other words, when viewed from the Z-axis direction perpendicular to the substrate surface of the sensor substrate 130, the groove 160 is formed between the outer circumference of the sensor substrate 130 and the guard ring 152. Also, as illustrated in figure a, when viewed from the Y-axis direction and X-axis direction parallel to the substrate surface of the sensor substrate 130, one end of the groove 160 reaches a predetermined position between the front and back surfaces of the silicon layer 134, and the other end reaches the surface of the wiring layer 133.

[0108] Furthermore, a predetermined embedding material with lower rigidity than silicon is embedded in the groove 160. This embedding material can be metal, insulating material, or resin.

[0109] Furthermore, the size (in other words, width) of the groove 160 in the X-axis and Y-axis directions is smaller than the width of the scribe line. For example, if the width of the scribe line is 50 to 150 micrometers (μm), the width of the groove 160 is set to 0.1 to 20 micrometers (μm). Also, the size (in other words, length) of the groove 160 in the Z-axis direction is set to a range of several micrometers (μm) to several tens of micrometers (μm), depending on the expected crack length.

[0110] During the individualization process or during pickup after individualization, cracks may occur originating from the side surface of the silicon layer 134. However, in figure a, a groove 160 is formed between the scribe line and the guard ring 152, with one end reaching the silicon layer 134. This groove 160 prevents cracks originating from the side surface of the silicon layer 134 from bypassing the guard ring 152 and propagating to the pixel area 131. As a result, a highly reliable CMOS image sensor can be realized. In figure a, the dotted arrow indicates the direction in which the crack propagates, and the white arrow indicates a crack that has stopped at the groove 160.

[0111] Furthermore, by embedding a material with lower rigidity than silicon in the groove 160, stress can be absorbed, and cracks during dicing and picking can be suppressed more effectively than when the material is not embedded.

[0112] Although the groove structure 160 illustrated in the figure is applied to a CMOS image sensor, it is not limited to this configuration and can be applied to semiconductor elements other than CMOS image sensors, such as light-emitting elements. The same applies to the various modifications of the second embodiment described later.

[0113] The method for manufacturing the semiconductor package 200 in the second embodiment will be described with reference to Figures 23 to 25.

[0114] As illustrated in Figure 23a, a guard ring 152 is formed on the wiring layer 133.

[0115] Then, as illustrated in figure b, the wiring layer 133 is processed by photolithography with a resist that serves as a mask during etching, and a groove 160 is formed between the scribe line and the guard ring 152. Then the resist is removed. The coordinates X2 and X5 in figure b are the coordinates of the right and left ends of the scribe line.

[0116] Then, as illustrated in figure c, the embedding material is embedded in the groove 160 by the CVD method, and the unnecessary embedding material is removed from the light-receiving surface by CMP processing.

[0117] Then, as illustrated in Figure 24a, a sensor upper structure such as an on-chip lens 132 is formed in the pixel region 131.

[0118] Then, as illustrated in figure b, the light-transmitting substrate 110 and the wiring layer 133 are bonded together by the bonding resin 120 in a wafer-level process.

[0119] Then, as illustrated in Figure 25a, back surface wiring 142, through electrodes 151, and solder balls 144 are formed.

[0120] Then, as illustrated in figure b, the wafer 100 is divided into individual pieces by the dicing blade 250 cutting from the back side.

[0121] As illustrated in Figure 26, the groove 160 can also be left hollow without being filled. The structure shown in the figure can be applied to each of the first to sixth modifications of the second embodiment described later.

[0122] Thus, according to the second embodiment of this technology, a groove 160 is formed between the outer circumference of the sensor substrate 130 and the guard ring 152, with one end reaching the silicon layer 134. This makes it possible to suppress the propagation of cracks from the side surface of the silicon layer 134.

[0123] [First Modification] In the second embodiment described above, a groove 160 was formed in which one end reached the silicon layer 134 and the other end reached the surface of the wiring layer 133, but the configuration is not limited to this. The semiconductor package 200 in the first modification of this second embodiment differs from the second embodiment in that the other end of the groove 160 reaches a predetermined position between the surface and back surface of the wiring layer 133.

[0124] Figure 27 is an example of a cross-sectional view of a semiconductor package 200 in a first modification of a second embodiment of the present technology. In this first modification of the second embodiment, one end of the groove 160 reaches the silicon layer 134, and the other end reaches a predetermined position between the front and back surfaces of the wiring layer 133. This improves the flatness of the surface of the wiring layer 133. This improvement in flatness suppresses the generation of voids in the bonding resin 120.

[0125] Thus, according to the first modification of the second embodiment of this technology, the other end of the groove 160 reaches a predetermined position between the front and back surfaces of the wiring layer 133, thereby improving the flatness of the surface of the wiring layer 133 and suppressing the generation of voids in the bonding resin 120.

[0126] [Second Modification] In the second embodiment described above, a groove 160 was formed in which one end reached the silicon layer 134 and the other end reached the surface of the wiring layer 133, but the configuration is not limited to this. The semiconductor package 200 in the second modification of this second embodiment differs from the second embodiment in that the other end of the groove 160 reaches the surface of the silicon layer 134.

[0127] Figure 28 is an example of a cross-sectional view of a semiconductor package 200 in a second modification of the second embodiment of the present technology. In this second modification of the second embodiment, one end of the groove 160 reaches a predetermined position between the front and back surfaces of the silicon layer 134, and the other end reaches the surface of the silicon layer 134. This improves the flatness of the surface of the wiring layer 133. This improvement in flatness suppresses the generation of voids in the bonding resin 120.

[0128] Thus, according to the second modification of the second embodiment of this technology, the other end of the groove 160 reaches the surface of the silicon layer 134, thereby improving the flatness of the surface of the wiring layer 133 and suppressing the generation of voids in the bonding resin 120.

[0129] [Third Modification] In the second embodiment described above, a filling material with lower rigidity than silicon was embedded in the groove 160, but the configuration is not limited to this. The semiconductor package 200 in this third modification of the second embodiment differs from the second embodiment in that bonding resin 120 is further embedded in the groove 160.

[0130] Figure 29 is an example of a cross-sectional view of a semiconductor package 200 in a third modification of the second embodiment of the present technology. In this third modification of the second embodiment, bonding resin 120 is further embedded in the groove 160. For example, let the Z coordinate of the surface of the wiring layer 133 be Z5, and the Z coordinate of one end of the groove 160 in the silicon layer 134 be Z3. Let the Z coordinate within the wiring layer 133 be Z4, and bonding resin 120 is embedded in the groove 160 from Z5 to Z4, and embedding material similar to that in the second embodiment is embedded from Z4 to Z3.

[0131] By further embedding the bonding resin 120 in the groove 160, the bonding strength between the bonding resin 120 and the sensor substrate 130 can be improved by the anchoring effect.

[0132] Thus, according to the third modification of the second embodiment of this technology, since the bonding resin 120 is further embedded in the groove 160, the bonding strength between the bonding resin 120 and the sensor substrate 130 can be improved.

[0133] [Fourth Modification] In the second embodiment described above, a groove 160 was formed in which one end reached the silicon layer 134 and the other end reached the surface of the wiring layer 133, but the configuration is not limited to this. The semiconductor package 200 in this fourth modification of the second embodiment differs from the second embodiment in that the other end of the groove 160 reaches the bonding resin 120.

[0134] Figure 30 is an example of a cross-sectional view of a semiconductor package 200 in a fourth modification of the second embodiment of this technology. In this fourth modification of the second embodiment, one end of the groove 160 reaches the silicon layer 134, and the other end reaches the bonding resin 120. The groove 160 is also made to have light-shielding properties. This makes it possible to suppress flare.

[0135] Thus, according to the fourth modification of the second embodiment of this technology, the other end of the groove 160 reaches the bonding resin 120, which can suppress flaring.

[0136] [Fifth Modification] In the second embodiment described above, a groove 160 was formed between the outer circumference of the sensor substrate 130 and the guard ring 152, but the configuration is not limited to this. The semiconductor package 200 in this fifth modification of the second embodiment differs from the second embodiment in that the groove is doubled.

[0137] Figure 31 is an example of a cross-sectional view of a semiconductor package 200 in a fifth modification of the second embodiment of the present technology. In this fifth modification of the second embodiment, grooves 161 and 162 are formed between the outer circumference of the sensor substrate 130 and the guard ring 152. Groove 161 is formed along the outer circumference of the sensor substrate 130, and groove 162 is formed between groove 161 and the guard ring 152. As illustrated in the figure, by making the grooves double, the probability of crack prevention can be further increased, and a more reliable element can be realized. Grooves 161 and 162 are examples of the first and second grooves described in the claims.

[0138] Furthermore, the grooves can be made three or more in number. Also, the first, second, third, and fourth modifications of the second embodiment can be applied to the fifth modification of the second embodiment.

[0139] Thus, according to the fifth modification of the second embodiment of this technology, by making the groove double, the probability of crack prevention is further increased, and a more reliable element can be realized.

[0140] [Sixth Modification] In the second embodiment described above, the bonding resin 120 was completely filled between the light-transmitting substrate 110 and the sensor substrate 130, resulting in a cavity-less structure. However, a cavity can also be provided. The semiconductor package 200 in this sixth modification of the second embodiment differs from the second embodiment in that a cavity is provided.

[0141] Figure 32 is an example of a cross-sectional view of a semiconductor package 200 in a sixth modification of the second embodiment of this technology. In this sixth modification of the second embodiment, the bonding resin 120 bonds a predetermined area on the surface of the sensor substrate 130 around the pixel area 131 to the light-transmitting substrate 110. By providing a cavity in this way, the difficulty of wafer-level processing can be reduced, and a low-cost and highly reliable device can be realized.

[0142] Furthermore, the sixth modification of the second embodiment can be applied to the first, second, third, fourth, and fifth modifications of the second embodiment, respectively.

[0143] Thus, according to the sixth modification of the second embodiment of this technology, a cavity is provided, making it possible to realize a low-cost and highly reliable element.

[0144] <3. Examples of Application to Mobile Devices> The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0145] Figure 33 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0146] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 33, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0147] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0148] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0149] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0150] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0151] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0152] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0153] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0154] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0155] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 33, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0156] Figure 34 shows an example of the installation position of the imaging unit 12031.

[0157] In Figure 34, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0158] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0159] Figure 34 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0160] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0161] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0162] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0163] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0164] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 12031 of the configuration described above. Specifically, the semiconductor package 200 in Figure 1 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, defects due to cracks can be prevented and yield can be improved.

[0165] The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology.

[0166] The effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0167] Furthermore, this technology can also take the following configurations: (1) A semiconductor package comprising a semiconductor substrate, an insulating film and back wiring formed on a wiring region on the back surface of the semiconductor substrate, a guard ring formed around the back wiring, and a protective film covering the guard ring, the insulating film, and the back wiring. (2) The semiconductor package according to (1), wherein the guard ring is formed between the outer periphery of the semiconductor substrate and the wiring region. (3) The semiconductor package according to (2), wherein an insulating film is embedded in the guard ring. (4) The semiconductor package according to (2), wherein the protective film is embedded in the guard ring. (5) The semiconductor package according to (1), wherein the wiring region is engraved on the surface side of the semiconductor substrate, and the guard ring is formed within the wiring region along the outer periphery of the wiring region. (6) The semiconductor package according to (5), wherein an insulating film is embedded in the guard ring. (7) The semiconductor package according to (1), wherein the back wiring includes a first back wiring routed on a first wiring layer and a second back wiring routed on a second wiring layer, and the protective film includes a first protective film covering the first back wiring and a second protective film covering the second back wiring. (8) A semiconductor package comprising a semiconductor substrate including a stacked silicon layer and a wiring layer, a guard ring formed on the wiring layer, and a groove formed between the outer periphery of the semiconductor substrate and the guard ring when viewed from a direction perpendicular to the substrate plane of the semiconductor substrate, with one end reaching the silicon layer when viewed from a direction parallel to the substrate plane. (9) The semiconductor package according to (8), wherein the other end of the groove reaches the surface of the wiring layer. (10) The semiconductor package according to (8), wherein the other end of the groove reaches a predetermined position between the surface and back of the wiring layer. (11) The semiconductor package according to (8), wherein the other end of the groove reaches the surface of the silicon layer. (12) The semiconductor package according to any one of (8) to (11), wherein a predetermined embedding material having lower rigidity than silicon is embedded in the groove. (13) The semiconductor package according to (12), wherein a bonding resin for bonding the surface of the semiconductor substrate and the light-transmitting substrate is further embedded in the groove.(14) The semiconductor package according to (8), further comprising a light-transmitting substrate and a bonding resin for bonding the surface of the semiconductor substrate to the light-transmitting substrate, wherein one end of the groove reaches the bonding resin. (15) The semiconductor package according to any one of (8) to (13), wherein the groove comprises a first groove formed along the outer circumference of the semiconductor substrate and a second groove formed between the first groove and the guard ring. (16) The semiconductor package according to any one of (8) to (15), further comprising a light-transmitting substrate and a bonding resin for bonding a predetermined region on the surface of the semiconductor substrate around a pixel region to the light-transmitting substrate. (17) A method for manufacturing a semiconductor package, comprising a guard ring formation step for forming a guard ring between a scribe line and a wiring region on the back surface of the semiconductor substrate; an insulating film deposition step for covering the wiring region with an insulating film; a removal step for removing the insulating film formed on the scribe line on the back surface of the semiconductor substrate; and a wiring step for forming back wiring in the wiring region. (18) The method for manufacturing a semiconductor package according to (17), wherein the insulating film is removed by chemical mechanical polishing in the removal procedure. (19) The method for manufacturing a semiconductor package according to (17), wherein the insulating film is removed by dry etching in the removal procedure.

[0168] 100 Wafer 110 Light-transmitting substrate 120 Bonding resin 130 Sensor substrate 131 Pixel area 132 On-chip lens 133 Wiring layer 134 Silicon layer 141 Insulating film 142, 142-1, 142-2 Backside wiring 143, 143-1, 143-2 Protective film 144 Solder ball 151 Through electrode 152 Guard ring 160, 161, 162 Groove 200 Semiconductor package 211, 212, 213 Resist 250 Dicing blade 12031 Imaging unit

Claims

1. A semiconductor package comprising: a semiconductor substrate; an insulating film and back wiring formed on a wiring region of the back surface of the semiconductor substrate; a guard ring formed around the back wiring; and a protective film covering the guard ring, the insulating film, and the back wiring.

2. The semiconductor package according to claim 1, wherein the guard ring is formed between the outer periphery of the semiconductor substrate and the wiring region.

3. The semiconductor package according to claim 2, wherein an insulating film is embedded in the guard ring.

4. The semiconductor package according to claim 2, wherein the protective film is embedded in the guard ring.

5. The semiconductor package according to claim 1, wherein the wiring region is engraved on the surface side of the semiconductor substrate, and the guard ring is formed within the wiring region along the outer circumference of the wiring region.

6. The semiconductor package according to claim 5, wherein an insulating film is embedded in the guard ring.

7. The semiconductor package according to claim 1, wherein the back wiring includes a first back wiring routed on a first wiring layer and a second back wiring routed on a second wiring layer, and the protective film includes a first protective film covering the first back wiring and a second protective film covering the second back wiring.

8. A semiconductor package comprising: a semiconductor substrate including stacked silicon layers and wiring layers; a guard ring formed in the wiring layer; and a groove formed between the outer periphery of the semiconductor substrate and the guard ring when viewed from a direction perpendicular to the substrate plane of the semiconductor substrate, with one end reaching the silicon layer when viewed from a direction parallel to the substrate plane.

9. The semiconductor package according to claim 8, wherein the other end of the groove reaches the surface of the wiring layer.

10. The semiconductor package according to claim 8, wherein the other end of the groove reaches a predetermined position between the front and back surfaces of the wiring layer.

11. The semiconductor package according to claim 8, wherein the other end of the groove reaches the surface of the silicon layer.

12. The semiconductor package according to claim 8, wherein a predetermined embedding material having lower rigidity than silicon is embedded in the groove.

13. The semiconductor package according to claim 12, wherein a bonding resin for bonding the surface of the semiconductor substrate and the light-transmitting substrate is further embedded in the groove.

14. The semiconductor package according to claim 8, further comprising a light-transmitting substrate and a bonding resin for bonding the surface of the semiconductor substrate to the light-transmitting substrate, wherein one end of the groove reaches the bonding resin.

15. The semiconductor package according to claim 8, wherein the groove includes a first groove formed along the outer circumference of the semiconductor substrate and a second groove formed between the first groove and the guard ring.

16. The semiconductor package according to claim 8, further comprising a light-transmitting substrate and a bonding resin for bonding a predetermined region on the surface of the semiconductor substrate surrounding a pixel region to the light-transmitting substrate.

17. A method for manufacturing a semiconductor package, comprising: a guard ring formation step for forming a guard ring between a scribe line and a wiring region on the back surface of a semiconductor substrate; an insulating film deposition step for covering the wiring region with an insulating film; a removal step for removing the insulating film formed on the scribe line on the back surface of the semiconductor substrate; and a wiring step for forming back surface wiring in the wiring region.

18. The method for manufacturing a semiconductor package according to claim 17, wherein the insulating film is removed by chemical mechanical polishing in the removal procedure.

19. The method for manufacturing a semiconductor package according to claim 17, wherein the insulating film is removed by dry etching in the removal procedure.

Images