Component built-in substrate

Abstract

A component built-in substrate 1A comprises: a plurality of unit substrates 10 to 30 stacked on each other with a plurality of adhesive layers 50 therebetween; and an electronic component 40. The unit substrates 10 to 30 include a double-sided substrate 10, an inner single-sided substrate 20, and an outer single-sided substrate 30. The outer single-sided substrate 30 is stacked on the inner single-sided substrate 20 located on the outermost side of the unit substrates 10 to 30 in the stacking direction. The electronic component 40 is arranged in an opening part 15 formed in a resin substrate 11 of the double-sided substrate 10. Surfaces of metal layers 12, 13, 22 of the inner single-sided substrate 20 and the double-sided substrate 10 are roughened, and an interval SO between wiring patterns 33 of a metal layer 32 of the outer single-sided substrate 30 and an interval SI between wiring patterns 23 of the metal layer 22 of the inner single-sided substrate 20 satisfy the following formula (1).　(1): SＯ ≤ SI x 0.85

Description

Component-integrated circuit board

[0001] The present invention relates to a component-embedded substrate. For designated countries where incorporation by reference is permitted, the contents described in Japanese Patent Application No. 2024-199910, filed in Japan on November 15, 2024, are incorporated herein by reference and constitute part of this specification.

[0002] As a technology that enables high integration of electronic components, component-embedded substrates, in which electronic components are embedded inside a multilayer printed circuit board, are known (see, for example, Patent Document 1).

[0003] The component-embedded substrate described in Patent Document 1 comprises an intermediate substrate, double-sided substrates arranged on the upper and lower layers of the intermediate substrate, and a single-sided substrate laminated on the double-sided substrate. The technology described in Patent Document 1 states that by housing electronic components in openings formed in the double-sided substrate, it is possible to reduce the number of insulating spacers and thus make the entire component-embedded substrate thinner.

[0004] Patent No. 5526276

[0005] Electronic components used in recent years in small, precision devices are required to be even smaller and more functional. Against this backdrop, component-embedded circuit boards require smaller components mounted on the surface. In order to mount small electronic components on the surface of a component-embedded circuit board, it is necessary to arrange a larger number of pads and wiring at a higher density on the outer single-sided circuit board.

[0006] On the other hand, the technology described in Patent Document 1 involves laminating multiple substrates with an adhesive and then thermocompressing this laminate to manufacture a component-embedded substrate. However, in this method, the adhesive flows along the surface direction of the substrate during thermocompression, causing the substrate to deform and stretch. In particular, substrates located on the outside of the component-embedded substrate tend to deform more easily during thermocompression than substrates located on the inside. Therefore, when manufacturing a component-embedded substrate with high-density pad and wiring arrangement using the technology described in Patent Document 1, there is a risk of poor conductivity between the outer and inner substrates due to the deformation of each unit substrate. Furthermore, there is a risk that unintended areas may be cut in subsequent processes, or that the position of components mounted on the surface may be misaligned. In particular, the narrower the spacing between wirings, the more likely even slight deformation of the substrate is to lead to the above problems.

[0007] The problem that this invention aims to solve is to provide a component-embedded substrate in which deformation of each unit substrate caused by thermocompression bonding is suppressed, and on which small electronic components can be mounted on the surface.

[0008] [1] Embodiment 1 of the present invention is a component-embedded substrate comprising a plurality of unit substrates laminated together via a plurality of adhesive layers, and an electronic component, wherein each unit substrate comprises an insulating layer and a metal layer, the unit substrate includes a double-sided substrate with the metal layer formed on both sides of the insulating layer, an inner single-sided substrate with the metal layer formed on one side of the insulating layer, and an outer single-sided substrate with the metal layer formed on one side of the insulating layer, the inner single-sided substrate is laminated on the double-sided substrate, the outer single-sided substrate is laminated on the inner single-sided substrate which is the outermost in the lamination direction of the unit substrates, the electronic component is arranged in an opening formed in the insulating layer of the double-sided substrate, the surfaces of the inner single-sided substrate and the metal layer of the double-sided substrate are roughened, and the spacing S between the wirings of the metal layer of the outer single-sided substrate Ｏ The spacing S between the wirings in the metal layer of the inner single-sided substrate. Ｉ However, it is a component-embedded circuit board that satisfies the following equation (1). S Ｏ ≤S Ｉ ×0.85 (1)

[0009] [2] Aspect 2 of the present invention is the component-embedded substrate of Aspect 1, wherein the width L of the wiring included in the metal layer of the inner single-sided substrate Ｏ and the width L of the wiring included in the metal layer of the outer single-sided substrate Ｉ may be a component-embedded substrate that satisfies the following formula (2). L Ｏ ≦ L Ｉ × 0.85 (2)

[0010] [3] Aspect 3 of the present invention is the component-embedded substrate of Aspect 1 or 2, wherein the inner single-sided substrate and the outer single-sided substrate are provided with conductive paste vias penetrating the insulating layer, and the diameter D of the conductive paste via of the outer single-sided substrate Ｏ and the diameter D of the conductive paste via of the inner single-sided substrate Ｉ may be a component-embedded substrate that satisfies the following formula (3). D Ｏ ≦ D Ｉ × 0.8 (3)

[0011] [4] Aspect 4 of the present invention is the component-embedded substrate of Aspect 3, wherein the thickness T of the insulating layer of the outer single-sided substrate Ｏ and the thickness T of the insulating layer of the outer single-sided substrate Ｉ may be a component-embedded substrate that satisfies the following formula (4). T Ｏ ≦ T Ｉ × 0.7 (4)

[0012] [5] Aspect 5 of the present invention is the component-embedded substrate of any one of Aspects 1 to 4, wherein the surface roughness Rz of the metal layer of the inner single-sided substrate and the metal layer of the double-sided substrate Ｉ and the surface roughness Rz of the metal layer of the outer single-sided substrate Ｏ may be a component-embedded substrate that satisfies the following formula (5). Rz Ｉ > Rz Ｏ (5)

[0013] [6] Aspect 6 of the present invention is the component-embedded substrate of any one of Aspects 1 to 5, and may be a component-embedded substrate including two or more of the electronic components, two or more of the double-sided substrates, and an intermediate substrate disposed between the two double-sided substrates via the adhesive layer.

[0014] [7] Aspect 7 of the present invention includes a first step of forming a metal layer on one surface of an insulating layer and preparing an outer single-sided substrate, a second step of forming a metal layer on one surface of the insulating layer, performing a roughening treatment on the surface of the metal layer, and preparing an inner single-sided substrate, and a third step of forming metal layers on both surfaces of the insulating layer, performing a roughening treatment on the surface of the metal layer, forming an opening in the insulating layer, and preparing a double-sided substrate. A fourth step of laminating the inner single-sided substrate on the double-sided substrate via an adhesive layer, laminating the outer single-sided substrate on the inner single-sided substrate via an adhesive layer, and thermocompression bonding the outer single-sided substrate, the inner single-sided substrate, and the double-sided substrate. The fourth step includes laminating the inner single-sided substrate and the double-sided substrate such that an electronic component is inserted into the opening of the double-sided substrate. It is a method for manufacturing a substrate with built-in electronic components.

[0015] [8] Aspect 8 of the present invention is a method for manufacturing a substrate with built-in components according to Aspect 7, and the second step may be a method for manufacturing a substrate with built-in components including mounting the electronic component on the inner single-sided substrate.

[0016] In the present invention, the surfaces of the metal layers provided on the inner single-sided substrate and the double-sided substrate are roughened. During the thermocompression bonding of the substrates, the roughened surface of the metal layer inhibits the flow of the adhesive applied on the metal layer, thereby suppressing the deformation of the inner single-sided substrate and the double-sided substrate. Therefore, in the substrate with built-in components of the present invention, the deformation of the substrate due to thermocompression bonding is suppressed, and each substrate is laminated with high positional accuracy. Also, in the present invention, the above formula (1) is satisfied, and the interval S between the wirings of the outer single-sided substrate Ｏ is less than or equal to the interval S between the wirings of the inner single-sided substrate Ｉ as follows. For this reason, it is possible to mount small electronic components on the surface of the substrate with built-in components of the present invention.

[0017] FIG. 1 is a cross-sectional view showing a component-embedded substrate in the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing the structure of the metal layers of the inner single-sided substrate and the double-sided substrate in the first embodiment of the present invention, and is an enlarged view of part II in FIG. 1. FIG. 3(a) is a plan view showing the wiring pattern of the outer single-sided substrate, and FIG. 3(b) is a plan view showing the wiring pattern of the inner single-sided substrate. FIG. 4 is a flowchart showing a method for manufacturing a component-embedded substrate in the first embodiment of the present invention. FIGS. 5(a) to 5(e) are cross-sectional views explaining the method for manufacturing the outer single-sided substrate in the first embodiment of the present invention step by step. FIGS. 6(a) and 6(b) are cross-sectional views showing the steps of the method for manufacturing the inner single-sided substrate in the first embodiment of the present invention. FIG. 6(a) is a cross-sectional view showing the roughening step of the inner single-sided substrate, and FIG. 6(b) is a cross-sectional view showing the step of mounting an electronic component on the inner single-sided substrate. FIGS. 7(a) to 7(f) are cross-sectional views explaining the method for forming the double-sided substrate in the first embodiment of the present invention step by step. FIG. 8 is a cross-sectional view showing the step of collectively thermocompression bonding each unit substrate in the method for manufacturing a component-embedded substrate in the first embodiment of the present invention. FIG. 9A is a cross-sectional view showing a component-embedded substrate in the second embodiment of the present invention. FIG. 9B is a cross-sectional view showing a first modification example of the component-embedded substrate in the second embodiment of the present invention. FIG. 9C is a cross-sectional view showing a second modification example of the component-embedded substrate in the second embodiment of the present invention. FIG. 10A is a cross-sectional view showing a third modification example of the component-embedded substrate in the second embodiment of the present invention. FIG. 10B is a cross-sectional view showing a fourth modification example of the component-embedded substrate in the second embodiment of the present invention. FIG. 10C is a cross-sectional view showing a fifth modification example of the component-embedded substrate in the second embodiment of the present invention. FIG. 10D is a cross-sectional view showing a sixth modification example of the component-embedded substrate in the second embodiment of the present invention.

[0018] Hereinafter, embodiments of the present invention will be described based on the drawings.

[0019] <<First Embodiment>> FIG. 1 is a cross-sectional view showing a component-embedded substrate 1A in the first embodiment.

[0020] The component-embedded substrate 1A of this embodiment is a multilayer wiring board that incorporates electronic components 40. The electronic components 40 are not particularly limited, but for example, they are IC chips. Because the component-embedded substrate 1A can be miniaturized and thinned, it can be used in medical devices such as wearable devices and implantable devices. However, the applications of the component-embedded substrate 1A are not particularly limited to the above applications, and the component-embedded substrate 1A may be used for applications other than medical devices.

[0021] The component-embedded substrate 1A comprises a double-sided substrate 10, inner single-sided substrates 20a to 20b, outer single-sided substrates 30a to 30b, and electronic components 40. The double-sided substrate 10, the inner single-sided substrates 20a to 20b, and the outer single-sided substrates 30a to 30b are laminated together via adhesive layers 50a to 50d. The adhesive layers 50a to 50d are not particularly limited, but are formed, for example, by curing an organic adhesive such as an epoxy or acrylic adhesive containing volatile components. Hereafter, the adhesive layers 50a to 50d will be collectively referred to as the adhesive layer 50.

[0022] The number of double-sided substrates, the number of inner single-sided substrates, the number of outer single-sided substrates, and the number of electronic components are not particularly limited and can be appropriately changed according to the design of the component-embedded substrate 1A. The double-sided substrate 10, the inner single-sided substrates 20a to 20b, and the outer single-sided substrates 30a to 30b correspond to examples of "unit substrates" in the embodiments of the present invention. Hereafter, the double-sided substrate 10, the inner single-sided substrates 20a to 20b, and the outer single-sided substrates 30a to 30b will be collectively referred to as a unit substrate as needed.

[0023] The double-sided substrate 10 comprises a resin substrate 11, metal layers 12 and 13, and vias 14. The resin substrate 11 corresponds to an example of an "insulating layer" in an embodiment of the present invention, and the metal layers 12 and 13 correspond to an example of a "metal layer" in an embodiment of the present invention.

[0024] The resin substrate 11 is made of an electrically insulating material such as a resin material. Specific examples of the resin constituting this resin substrate 11 include, for example, polyimide, polyolefin, and liquid crystal polymer (LCP).

[0025] The resin substrate 11 has an opening 15 that penetrates through the resin substrate 11 in the thickness direction. An electronic component 40 is housed in the opening 15.

[0026] A metal layer 12 is formed on one side of the resin substrate 11, and a metal layer 13 is formed on the other side. The metal layers 12 and 13 are made of a conductive material such as copper. Wiring patterns (not shown) are formed on the metal layers 12 and 13. The shape of the wiring patterns can be any shape. As will be described later, the surfaces 121 and 131 of the metal layers 12 and 13 are roughened (see Figure 8). In addition, an organic coating (not shown) may be provided on the surfaces 121 and 131 of the metal layers 12 and 13 to prevent oxidation of the roughened surface. The organic coating is made of an organic compound such as an imidazole compound. The organic coating is formed by immersing the surfaces 121 and 131 of the metal layers 12 and 13 in an aqueous solution mainly containing an organic compound.

[0027] The via 14 is an interlayer conductive passage that electrically connects the metal layer 12 and the metal layer 13 formed on both sides of the resin substrate 11. The via 14 is formed by filling the inside of a through hole that penetrates the resin substrate 11 in the thickness direction with copper by a plating process. The configuration of the via 14 is not particularly limited. For example, the via 14 may be a via formed by forming a copper layer on the inner wall surface of a through hole in the resin substrate 11. Alternatively, it may be formed by curing a conductive paste.

[0028] The inner single-sided substrate 20a comprises a resin substrate 21a, a metal layer 22a, and vias 24a. The resin substrate 21a is made of the same material as the resin substrate 11. The metal layer 22a is made of the same material as the metal layer 12. A wiring pattern 23a is formed on the metal layer 22a. The surface 221a of the metal layer 22a is roughened, similar to the surface 121 of the metal layer 12 (see Figure 8). On the inner single-sided substrate 20a, the metal layer 22a is formed on only one side of the resin substrate 21a.

[0029] The via 24a is an interlayer conductive passage that electrically connects the metal layer 22a of the inner single-sided substrate 20a and the metal layer 12 of the double-sided substrate. The via 24a is formed by curing a conductive paste that is filled into through holes penetrating the resin substrate 21a. Although not particularly limited, the metal particles contained in the via 24a are in contact with or bonded to each other, thereby electrically connecting the metal layer 22a and the metal layer 12.

[0030] The conductive paste constituting the via 24a includes, for example, at least one low-electrical-resistance metal particle selected from nickel, gold, silver, copper, aluminum, iron, etc., and at least one low-melting-point metal particle selected from tin, bismuth, indium, lead, etc. This conductive paste is composed of a paste made by mixing these metal particles with a binder component mainly composed of epoxy, acrylic, urethane, etc.

[0031] The conductive paste configured in this way has the characteristics of a metal sintering type, with a curing temperature of approximately 150°C to 200°C and a melting point of 260°C or higher after curing. For example, low-melting-point metal particles can melt at 200°C or below to form an alloy, and in particular, intermetallic compounds can be formed with copper, silver, etc. Therefore, the connection between via 24a and the metal layer 12, and the connection between via 24a and the metal layer 22a, will be alloyed by intermetallic compounds during the batch thermocompression bonding described later.

[0032] Furthermore, as a conductive paste, a paste formed by mixing low-electrical-resistance metal particles such as nickel with the binder component may be used. In this case, electrical connections are made in the conductive paste by contact between the metal particles. Alternatively, as a conductive paste, a nanopaste may be used in which fillers such as gold, silver, copper, and nickel with nano-level particle sizes are mixed with the binder component.

[0033] The inner single-sided substrate 20b comprises a resin substrate 21b, a metal layer 22b, vias 24b, and vias 25b. The resin substrate 21b is made of the same material as the resin substrate 11. The metal layer 22b is made of the same material as the metal layer 12. A wiring pattern 23b is formed on the metal layer 22b. The surface 221b of the metal layer 22b is roughened, similar to the surface 121 of the metal layer 12 (see Figure 8). On the inner single-sided substrate 20b, the metal layer 22b is formed on only one side of the resin substrate 21b.

[0034] Via 24b is an interlayer conductive passage that electrically connects the metal layer 22b of the inner single-sided substrate 20b and the metal layer 13 of the double-sided substrate. Via 24b is formed using the same material as via 24a and in the same manner as via 24a.

[0035] Via 25b electrically connects the metal layer 22b of the inner single-sided substrate 20b to the terminal 41 of the electronic component 40. Via 25b is made of the same material as via 24a and is formed in the same manner as via 24a.

[0036] As described above, the configurations of the inner single-sided substrate 20a and the inner single-sided substrate 20b are the same, except that the inner single-sided substrate 20b is provided with vias 25b for connecting to the electronic component 40. Hereafter, the inner single-sided substrate 20a and the inner single-sided substrate 20b will be collectively referred to as the inner single-sided substrate 20 as needed. Similarly, the metal layer 22a and the metal layer 22b will be collectively referred to as the metal layer 22, the wiring pattern 23a and the wiring pattern 23b will be collectively referred to as the wiring pattern 23, and the vias 24a and the vias 24b will be collectively referred to as the vias 24.

[0037] The outer single-sided substrate 30a comprises a resin substrate 31a, a metal layer 32a, and vias 34a. The outer single-sided substrate 30a is laminated on the inner single-sided substrate 20a via an adhesive layer 50a. The outer single-sided substrate 30a is located on the outermost side in the lamination direction of each unit substrate.

[0038] The resin substrate 31a is made of the same material as the resin substrate 11. The metal layer 32a is made of a conductive material such as copper. A wiring pattern 33a is formed on the metal layer 32a. In the outer single-sided substrate 30a, the metal layer 32a is formed on only one side of the resin substrate 31a.

[0039] Via 34a is an interlayer conductive passage that electrically connects the metal layer 32a of the outer single-sided substrate 30a and the metal layer 22a of the inner single-sided substrate. Via 34a is formed using the same material as via 24a and in the same manner as via 24a.

[0040] The outer single-sided substrate 30b comprises a resin substrate 31b, a metal layer 32b, and vias 34b. The outer single-sided substrate 30b is laminated on the inner single-sided substrate 20b via an adhesive layer 50d. The outer single-sided substrate 30b is located on the outermost side in the lamination direction of each unit substrate.

[0041] The resin substrate 31b is made of the same material as the resin substrate 11. The metal layer 32b is made of a conductive material such as copper. A wiring pattern 33b is formed on the metal layer 32b. In the outer single-sided substrate 30b, the metal layer 32b is formed on only one side of the resin substrate 31b.

[0042] Via 34b is an interlayer conductive passage that electrically connects the metal layer 32b of the outer single-sided substrate 30b and the metal layer 22b of the inner single-sided substrate. Via 34b is formed using the same material as via 24a and in the same manner as via 24a.

[0043] Hereafter, the outer single-sided substrate 30a and the outer single-sided substrate 30b will be collectively referred to as the outer single-sided substrate 30, as needed. Similarly, the metal layer 32a and the metal layer 32b will be collectively referred to as the metal layer 32, the wiring pattern 33a and the wiring pattern 33b will be collectively referred to as the wiring pattern 33, and the vias 34a and the vias 34b will be collectively referred to as the via 34.

[0044] Furthermore, other small electronic components 100 can be mounted on the outer single-sided substrate 30. While not particularly limited, examples of small electronic components 100 include those with a length and width of 0.05 mm to 5 mm and a thickness of 0.1 mm to 1 mm. While not particularly limited, a method for mounting the electronic components 100 on the outer single-sided substrate 30 is to connect the terminals 110 of the small electronic components 100 to the wiring pattern 33 using solder.

[0045] Figure 2 is a cross-sectional view showing the structure of the metal layer 22a of the inner single-sided substrate 20a in the first embodiment, and is an enlarged view of part II of Figure 1. Figure 3(a) is a plan view showing the wiring pattern 33 of the outer single-sided substrate 30, and Figure 3(b) is a plan view showing the wiring pattern 23 of the inner single-sided substrate 20.

[0046] In this embodiment, as shown in Figure 2, the surface 221a of the metal layer 22a of the inner single-sided substrate 20a is roughened. In this embodiment, the surface 121 of the metal layer 12 and the surface 131 of the metal layer 13 of the double-sided substrate 10, and the surface 221b of the metal layer 22b of the inner single-sided substrate 20b are similarly roughened. As a method for roughening the surfaces 121, 131 of the metal layers 12 and 13 and the surface 221 of the metal layer 22, for example, an etching method using an organic acid-based etching agent can be used to etch the surfaces 121, 131, and 221.

[0047] As described later, the component-embedded substrate 1A is manufactured by laminating a double-sided substrate 10, an inner single-sided substrate 20, and an outer single-sided substrate 30 via an adhesive 51 and then thermocompressing them (see Figure 8). In this embodiment, the surfaces 121 and 131 of the metal layers 12 and 13 of the double-sided substrate 10, and the surface 221 of the metal layer 22 of the inner single-sided substrate 20 are roughened. When thermocompressing, the movement of the adhesive on the surfaces 121, 131, and 221 of the metal layers 12, 13, and 222 in the planar direction (for example, the transverse direction of the paper in Figure 2) is inhibited by the roughened surfaces. This suppresses deformation of the substrate due to excessive flow of the adhesive during thermocompression. Therefore, it is possible to thermocompress each unit substrate while maintaining positional accuracy between them. Accordingly, in the component-embedded substrate 1A of this embodiment, each unit substrate is laminated with high positional accuracy. This makes it possible to make electrical contact between the metal layer 32 and the metal layer 22 of the inner single-sided substrate 20, even if the spacing between the wiring patterns 33 on the outer single-sided substrate 30 is narrowed or the diameter of the vias 34 is reduced.

[0048] Furthermore, the surface 321 (surfaces 321a, 321b) of the metal layer 32 of the outer single-sided substrate 30 is not roughened (see Figure 8). As a result, the surface roughness (maximum height roughness) Rz of the surfaces 121, 131 of the metal layers 12, 13 of the double-sided substrate and the surface 221 of the metal layer 22 of the inner single-sided substrate 20 is not roughened. Ｉ The surface roughness Rz of the surface 321 of the metal layer 32 of the outer single-sided substrate 30 Ｏ The following equation (5) is satisfied: Rz Ｉ > Rz Ｏ (5)

[0049] Surface roughness Rz of the surface 221 of the metal layer 22 of the inner single-sided substrate 20 Ｉ While not particularly limited, it is between 1.2 and 2.5 μm (1.2 μm ≤ Rz Ｉ (≤2.5 μm). Surface roughness Rz Ｉ If the surface roughness Rz is too low, as will be described later, when the individual unit substrates are stacked and heat-pressed during the manufacturing process of the component-embedded substrate 1A, the adhesive may flow over the surface of the metal layer. This may cause the outer single-sided substrate 30 to become deformed. On the other hand, the surface roughness Rz ＩIf the surface roughness Rz is too high, it may become difficult to spread the adhesive sufficiently across the surface of the metal layer during the manufacturing process of the component-embedded substrate 1A, potentially resulting in poor adhesion between substrates. Ｉ , Rz Ｏ This can be measured according to the JIS method (JIS B0601:2013).

[0050] In this embodiment, as shown in Figures 3(a) and 3(b), the spacing S between the wiring patterns 33 provided in the metal layer 32 of the outer single-sided substrate 30 Ｏ The spacing S between the wiring patterns 23 provided on the metal layer 22 of the inner single-sided substrate 20 Ｉ The following equation (1) is satisfied. Ｏ This represents the narrowest spacing between adjacent wiring patterns 33. Also, S Ｉ S represents the narrowest spacing between adjacent wiring patterns 23. For example, as shown in Figure 3(a), when the lands 331 of two wiring patterns 33 are adjacent, the distance between the lands 331 is S. Ｏ Similarly, as shown in Figure 3(b), when the lands 231 of two wiring patterns 23 are adjacent, the distance between the lands 231 is S. Ｉ This is the result. S Ｏ ≤0.85 × S Ｉ (1)

[0051] As described above, in the component-embedded substrate 1A of this embodiment, the surfaces 121 and 131 of the metal layers 12 and 13 of the double-sided substrate 10, and the surface 221 of the metal layer 22 of the inner single-sided substrate 20 are roughened, thereby suppressing deformation of the unit substrates caused by thermocompression bonding, and allowing each unit substrate to be stacked with high positional accuracy. Furthermore, by satisfying the above formula (1), the spacing between the wiring patterns 33 of the outer single-sided substrate 30 is relatively narrow. As a result, in the component-embedded substrate 1A of this embodiment, it is possible to mount small electronic components 100 on the surface.

[0052] In this embodiment, as shown in Figures 3(a) and 3(b), the width L of the wiring pattern 33 provided in the metal layer 32 of the outer single-sided substrate 30. Ｏ The width L of the wiring pattern 23 provided on the metal layer 22 of the inner single-sided substrate 20.Ｉ The following equation (2) is satisfied. Note that L Ｏ This represents the width of the narrowest wiring pattern 33 among the multiple existing wiring patterns 33. Also, L Ｉ This represents the width of the narrowest wiring pattern 23 among the multiple existing wiring patterns 23. Ｏ ≤ L Ｉ ×0.85 (2)

[0053] In this embodiment, by satisfying the above formula (2), the width of the wiring pattern 33 on the outer single-sided substrate 30 is relatively narrow. This makes it possible to mount small electronic components 100 on the surface of the outer single-sided substrate 30.

[0054] In this embodiment, as shown in Figures 3(a) and 3(b), the diameter D of the via 34 of the outer single-sided substrate 30 Ｏ And the diameter D of the via 24 on the inner single-sided substrate 20 Ｉ And satisfies the following equation (3). Note that D Ｏ This represents the diameter of the smallest via 34 among the multiple vias 34. Also, D Ｉ This represents the diameter of the smallest via 24 among the multiple vias 24. Ｏ ≤ D Ｉ ×0.8 (3)

[0055] In this embodiment, by satisfying the above formula (3), the diameter of the vias 34 on the outer single-sided substrate 30 is made relatively small. This makes it possible to mount small electronic components 100 on the surface of the outer single-sided substrate 30.

[0056] In this embodiment, as shown in Figure 1, the thickness T of the resin substrate 31 of the outer single-sided substrate 30 Ｏ The inner single-sided substrate 20 has a resin base material 21 with a thickness T Ｉ The following equation (4) is satisfied. Ｏ ≦T Ｉ ×0.7 (4)

[0057] In this embodiment, by satisfying the above formula (4), the thickness of the via 34 on the outer single-sided substrate 30 is reduced along with the thickness of the resin substrate 31. Therefore, even if the diameter of the via 34 is reduced, the aspect ratio of the via 34 can be made to be about the same as that of the via 24 on the inner single-sided substrate 20. Therefore, the decrease in strength due to the reduction in the diameter of the via 34 can be suppressed, and the connection reliability of the via 34 can be improved. In addition, the thinner the resin substrate, the more easily the substrate tends to deform due to the flow of the adhesive during heat compression bonding. Therefore, the component-embedded substrate 1A that satisfies the above formula (4) exhibits a remarkable effect of suppressing substrate deformation by roughening the surfaces 121, 131 of the metal layers 12, 13 and the surface 221 of the metal layer 22.

[0058] In this embodiment, the component-embedded substrate 1A contains only one electronic component 40, but the number of electronic components 40 is not particularly limited. For example, a plurality of openings 15 are formed in the double-sided substrate 10, and by housing an electronic component 40 in each opening 15, the component-embedded substrate 1A may contain multiple electronic components 40.

[0059] The manufacturing method of the component-embedded substrate 1A of this embodiment will be described below with reference to Figures 4 to 7(d). The component-embedded substrate 1A is formed by individually manufacturing each unit substrate 10, 20a to 20b, and 30a to 30b, and then stacking and thermocompressing them, as described below. Figure 4 is a flowchart showing the manufacturing method of the component-embedded substrate 1A in this embodiment.

[0060] In step S10 in Figure 4, the outer single-sided substrate 30 is manufactured. Figures 5(a) to 5(e) are cross-sectional views illustrating the manufacturing method of the outer single-sided substrate 30 and the inner single-sided substrate 20 in the first embodiment, step by step. Step S10 corresponds to an example of the "first step" in the embodiment of the present invention.

[0061] First, as shown in Figure 5(a), a single-sided CCL is prepared in which a metal layer 32 is formed on one side of a resin substrate 31. The single-sided CCL used here has a resin substrate 31 thickness that satisfies the above formula (4). Although not particularly limited, for example, a resin substrate 31 with a thickness of about 12 μm may be bonded to a metal layer 32 made of copper foil with a thickness of about 12 μm. As for this single-sided CCL, for example, one can be made by applying polyimide varnish to copper foil and curing the varnish using a known casting method.

[0062] As a single-sided CCL, a conductive layer may be formed by sputtering a seed layer on a polyimide film and growing copper by plating, or a conductive layer may be made by bonding rolled or electrolytic copper foil with a polyimide film using an adhesive. The resin substrate 31 does not necessarily have to be made of polyimide, and may be made of a plastic film such as a liquid crystal polymer as described above.

[0063] Next, as shown in Figure 5(b), an etching resist is formed on the metal layer 32 by photolithography or the like, and then etching is performed to form the wiring pattern 33. The wiring pattern 33 is formed to satisfy the above equations (1) and (2).

[0064] Next, as shown in Figure 5(c), the adhesive 51 and the resin film 36 are bonded together by heat and pressure in this order to the side of the resin substrate 31 opposite to the side on which the metal layer 32 is formed. While not particularly limited, a specific example of the adhesive 51 is, for example, an epoxy-based thermosetting film. A specific example of the resin film 36 is, for example, a polyimide resin film. A vacuum laminator is used to bond the films, and the adhesive 51 and the resin film 36 are bonded to the resin substrate 31 by heating and pressing the adhesive 51 at a temperature below its curing temperature in a reduced-pressure atmosphere. Note that instead of a film-type adhesive, a varnish-type adhesive may be used as the adhesive 51; in this case, the adhesive 51 is applied to the upper surface of the resin substrate 31.

[0065] Next, as shown in Figure 5(d), through-holes 301 are formed that penetrate the resin film 36, the adhesive 51, and the resin substrate 31. Specifically, the through-holes 301 are formed by irradiating the resin film 36 from the bottom in the figure with laser light. Alternatively, the through-holes 301 may be formed by drilling or chemical etching instead of laser processing. Desmearing may also be applied to the through-holes 301. The diameter of the through-holes 301 is adjusted so that the dimensions of the conductive paste 341, which will be described later, satisfy the above formula (3).

[0066] Next, as shown in Figure 5(e), the conductive paste 341 is filled into the through hole 301, and then the resin film 36 is peeled off the adhesive 51. As a result, the leading edge of the conductive paste 341 protrudes from the surface of the adhesive 51 by an amount equivalent to the thickness of the resin film 36. Specific methods for filling the through hole 301 with the conductive paste 341 include, for example, printing methods such as screen printing, spin coating, spray coating, dispensing, and lamination.

[0067] Figures 6(a) and 6(b) are cross-sectional views showing the method for forming the inner single-sided substrate 20 in the first embodiment. Figure 6(a) is a cross-sectional view showing the roughening process of the inner single-sided substrate 20, and Figure 6(b) is a cross-sectional view showing the mounting process of the electronic components 40 onto the inner single-sided substrate 20.

[0068] In step S20, the inner single-sided substrate 20 is manufactured. The inner single-sided substrate 20 is manufactured in the same manner as the outer single-sided substrate 30, except that the surface 221 of the metal layer 22 is subjected to a roughening treatment. Step S20 corresponds to an example of the "second step" in an embodiment of the present invention.

[0069] First, as shown in Figures 5(a) and 5(b), a wiring pattern 23 is formed on the metal layer 22 on the resin substrate 21 using a single-sided CCL. The single-sided CCL used is one in which the thickness of the resin substrate 21 satisfies formula (4) above. The wiring pattern 23 is formed to satisfy formulas (1) and (2) above. Furthermore, as shown in Figure 5(c), an adhesive 51 and a resin film 26 are laminated.

[0070] Next, as shown in Figure 6(a), the surface 221 of the metal layer 22 is subjected to a roughening treatment. Specifically, the surface 221 is roughened by etching with an organic acid-based etching agent. Alternatively, an organic film (not shown) may be formed on the surface 221 by immersing the roughened surface 121 in an aqueous solution mainly containing an organic compound.

[0071] Subsequently, as shown in Figures 5(d) to 5(e), through-holes 201 are formed that penetrate the adhesive 51 and the resin film 26, conductive paste 241 is filled into these holes, and finally the resin film 26 is peeled off to manufacture the inner single-sided substrate 20. The diameter of the through-holes 201 is adjusted so that the dimensions of the conductive paste 241 satisfy the above formula (3). Note that the surface 221 of the metal layer 22 is roughened at this point, but the roughened state of the surface 221 is not shown in Figures 5(d) to 5(e).

[0072] When manufacturing the inner single-sided substrate 20b on which the electronic component 40 is mounted, conductive paste 251 corresponding to the vias 25b connected to the terminals 41 of the electronic component 40 is formed, as shown in Figure 6(b). Furthermore, the terminals 41 of the electronic component 40 and the conductive paste 251 are aligned using an electronic component mounting machine, and heated at a temperature below the curing temperature of the adhesive 51 and the conductive paste 251. As a result, the electronic component 40 is mounted on the inner single-sided substrate 20b.

[0073] Figures 7(a) to 7(f) are cross-sectional views illustrating the manufacturing method of the double-sided substrate 10 in this embodiment, step by step.

[0074] In step S30, the double-sided substrate 10 is manufactured. Step S30 corresponds to an example of the "third step" in an embodiment of the present invention. First, as shown in Figure 7(a), a double-sided CCL is prepared, comprising a resin substrate 11 and metal layers 12 and 13 provided on both sides of the resin substrate 11. Although not particularly limited, a specific example of this double-sided CCL is one made by laminating copper foil about 12 μm thick to both sides of a polyimide film about 50 μm thick. Alternatively, a CCL made by the so-called casting method, in which polyimide varnish is applied to copper foil and the varnish is cured, may be used. Alternatively, a CCL made by forming a seed layer on a polyimide film and growing copper by plating may be used.

[0075] Next, as shown in Figure 7(b), through holes 101 are formed that penetrate the resin substrate 11 and the metal layers 12 and 13. Specifically, first, the metal layers 12 and 13 are etched to remove a portion of them, and then the removed portion is irradiated with laser light using a UV-YAG laser device to form through holes 101 in the resin substrate 11. Note that the etching treatment of the metal layers 12 and 13 before laser irradiation may be omitted. A carbon dioxide laser (CO2) may be used instead of a UV-YAG laser device. ２ Through holes 101 may be formed in the resin substrate 11 using a laser or excimer laser. Alternatively, through holes 101 may be formed in the resin substrate 11 by drilling or chemical etching. Desmear treatment may also be applied to the through holes 101.

[0076] Next, as shown in Figure 7(c), panel plating is applied to both sides of the CCL to grow copper plating within the through-hole 101, thereby forming vias 14 within the through-hole 101.

[0077] Next, as shown in Figure 7(d), an etching resist is formed on the metal layers 12 and 13 by photolithography or the like, and then etching is performed to form a wiring pattern. For this etching, an etchant mainly composed of ferric chloride or cupric chloride can be used. Alternatively, the wiring pattern on the metal layers 12 and 13 may be formed using a semi-additive method instead of using double-sided CCL.

[0078] Next, as shown in Figure 7(e), the surfaces 121 and 131 of the metal layers 12 and 13 are subjected to a roughening treatment. Specifically, the surfaces 121 and 131 are roughened by etching with an organic acid-based etching agent. Alternatively, an organic coating (not shown) may be formed on the surfaces 121 and 131 by immersing them in an aqueous solution mainly containing an organic compound.

[0079] Next, as shown in Figure 7(f), a UV-YAG laser device is used to irradiate the resin substrate 11 with laser light to form an opening 15 in the resin substrate 11. Alternatively, the opening 15 may be formed by punching using a mold.

[0080] Figure 8 is a cross-sectional view showing the process of collectively heat-pressing each unit substrate in the manufacturing method of the component-embedded substrate 1A in the first embodiment.

[0081] In step S40, as shown in Figure 8, the double-sided substrate 10, the inner single-sided substrates 20a and 20b, and the outer single-sided substrates 30a and 30b manufactured as described above are stacked, and these stacks are heat-pressed together. Step S40 corresponds to an example of the "fourth step" in an embodiment of the present invention.

[0082] Specifically, the electronic components 40 mounted on the inner single-sided substrate 20b are inserted into the opening 15 of the double-sided substrate 10, and the double-sided substrate 10 is sandwiched between the inner single-sided substrate 20a and the inner single-sided substrate 20b via adhesive 51. Furthermore, these three substrates are sandwiched between the outer single-sided substrate 30a and the outer single-sided substrate 30b via adhesive 51. In this way, the double-sided substrate 10, the inner single-sided substrates 20a and 20b, and the outer single-sided substrates 30a and 30b are stacked.

[0083] In this process, the conductive paste 241 of the inner single-sided substrate 20a is brought into contact with the metal layer 12 of the double-sided substrate 10, and the conductive paste 241 of the inner single-sided substrate 20b is brought into contact with the metal layer 13 of the double-sided substrate 10. In addition, the conductive paste 341 of the outer single-sided substrates 30a and 30b is brought into contact with the metal layers 22a and 22b of the inner single-sided substrates 20a and 20b.

[0084] Subsequently, using a vacuum press, the double-sided substrate 10, the inner single-sided substrates 20a and 20b, and the outer single-sided substrates 30a and 30b are heated and pressurized together in a reduced pressure atmosphere of 1 kPa or less to thermally bond them. As a result, the double-sided substrate 10, the inner single-sided substrates 20a and 20b, and the outer single-sided substrates 30a and 30b are integrated, completing the component-embedded substrate 1A as shown in Figure 1.

[0085] During thermocompression bonding, heating causes the adhesive 51 between the inner single-sided substrate 20 and the double-sided substrate 10 to flow, filling the gap between the electronic component 40 and the inner surface of the opening 15 in the double-sided substrate 10. On the other hand, the roughened surfaces 121 and 131 of the metal layers 12 and 13 of the double-sided substrate 10 prevent excessive flow of the adhesive 51 between the inner single-sided substrate 20 and the double-sided substrate 10. This suppresses deformation of the inner single-sided substrate 20 caused by the flow of the adhesive 51. Furthermore, the roughened surface 221 of the metal layer 22 of the inner single-sided substrate 20 prevents excessive flow of the adhesive 51 between the outer single-sided substrate 30 and the inner single-sided substrate 20. This suppresses deformation of the outer single-sided substrate 30 caused by the flow of the adhesive 51. Therefore, each unit substrate is thermocompressed while maintaining positional accuracy between the unit substrates.

[0086] The adhesive 51 between each substrate hardens through thermocompression bonding, forming adhesive layers 50a to 50d. Additionally, the conductive pastes 241, 251, and 341 harden through thermocompression bonding, forming vias 24a, 24b, 25b, 34a, and 34b.

[0087] <<Second Embodiment>> Figure 9A is a cross-sectional view of the component-embedded substrate 1B in the second embodiment. In the second embodiment, the component-embedded substrate 1B comprises two or more electronic components 40 and two or more double-sided substrates 10, and further comprises an intermediate substrate 60 provided between two double-sided substrates 10. In addition, in the second embodiment, the component-embedded substrate 1B may comprise three or more inner single-sided substrates 20. Except for the above, the configuration of the component-embedded substrate 1B in the second embodiment is the same as that of the component-embedded substrate 1A in the first embodiment. Hereinafter, only the differences between the component-embedded substrate 1B in the second embodiment and the first embodiment will be described, and parts that have the same configuration as in the first embodiment will be denoted by the same reference numerals and their description will be omitted.

[0088] As shown in Figure 9A, the component-embedded substrate 1B comprises two double-sided substrates 10, an intermediate substrate 60, two inner single-sided substrates 20, two outer single-sided substrates 30, and two electronic components 40a and 40b.

[0089] The intermediate substrate 60 comprises a resin substrate 61 and vias 62. It is made of the same material as the resin substrate 21. The vias 62 are interlayer conductive passages that electrically connect the metal layers 12 of the two double-sided substrates 10, which are located on both sides of the intermediate substrate 60. The vias 62 are formed by curing a conductive paste, similar to the vias 24a, etc. The intermediate substrate 60 is bonded to the two double-sided substrates 10 by an adhesive layer 50.

[0090] The intermediate substrate 60 is manufactured by applying adhesive to both sides of a resin substrate 61 by lamination or the like, and filling through holes formed in the resin substrate 61 by laser irradiation with conductive paste.

[0091] In the second embodiment, the component-embedded substrate 1B is manufactured by stacking and thermocompressing individually manufactured double-sided substrates 10, inner single-sided substrates 20, outer single-sided substrates 30, and intermediate substrates 60. When stacking each unit substrate, the intermediate substrate 60 is placed between two double-sided substrates 10. The two electronic components 40a and 40b are inserted into openings 15 of different double-sided substrates 10. At this time, the two electronic components 40a and 40b are inserted into the respective openings 15 in such a position that their terminals 41a and 41b face outwards from the component-embedded substrate 1. The adhesive interposed between each unit substrate hardens through thermocompression, and each unit substrate is integrated. Thus, the component-embedded substrate 1B is manufactured.

[0092] Figures 9B and 9C are cross-sectional views showing first and second modified examples of the component-embedded substrate 1B in the second embodiment, respectively.

[0093] The component-embedded substrate 1B shown in Figure 9B has a different orientation of the electronic component 40a compared to the configuration shown in Figure 9A. Specifically, the two electronic components 40 are arranged within each opening 15 in such a position that their respective terminals face in the same direction (downward in the figure). Furthermore, due to the different orientation of the electronic component 40a compared to the configuration shown in Figure 9A, the component-embedded substrate 1B includes three inner single-sided substrates 20a to 20c.

[0094] The component-embedded substrate 1B shown in Figure 9C has a different orientation of electronic components 40a and 40b compared to the configuration shown in Figure 9A. Specifically, the two electronic components 40a and 40b are arranged within each opening 15 in a position where their respective terminals face each other. Furthermore, due to the different orientation of the electronic components 40a and 40b compared to the configuration shown in Figure 9A, the component-embedded substrate 1B comprises four inner single-sided substrates 20.

[0095] Figures 10A to 10D are cross-sectional views showing the third to sixth modified examples of the component-embedded substrate 1B in the second embodiment, respectively.

[0096] The component-embedded substrates 1B shown in Figures 10A to 10D each comprise three double-sided substrates 10, three electronic components 40a to 40c, and two intermediate substrates 60. Furthermore, the component-embedded substrates 1B shown in Figures 10A to 10D also comprise three to five inner single-sided substrates 20, depending on the orientation of the electronic components 40a to 40c.

[0097] In the component-embedded substrate 1B of the second embodiment, the surfaces of the metal layers 12 and 13 of the double-sided substrate 10, and the surface of the metal layer 22 of the inner single-sided substrate 20 are both roughened. In addition, the spacing S between the wiring patterns of the metal layer 32 of the outer single-sided substrate 30 Ｏ The spacing S between the wiring patterns on the metal layer 22 of the inner single-sided substrate 20 Ｉ The above formula (1) is satisfied. Therefore, the component-embedded substrate 1B in the second embodiment can also have the small electronic component 100 mounted on its surface.

[0098] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit it. Therefore, each element disclosed in the above embodiments is intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0099] 1A, 1B...Component-embedded substrate 10, 10...Double-sided substrate 11...Resin substrate 12, 13...Metal layer 121, 131...Surface 14...Via 15...Opening 20, 20a-20b...Inner single-sided substrate 21...Resin substrate 22...Metal layer 23...Wiring pattern 24, 25...Via 30, 30a-30b...Outer single-sided substrate 31...Resin substrate 32...Metal layer 33...Wiring pattern 34...Via 40, 40a-40c...Electronic component 41...Terminal 50, 50a-50d...Adhesive layer 60...Intermediate layer 100...Small electronic component 110...Terminal

Claims

1. A component-embedded substrate comprising a plurality of unit substrates laminated together via a plurality of adhesive layers, and an electronic component, wherein each unit substrate comprises an insulating layer and a metal layer, the unit substrate includes a double-sided substrate with the metal layer formed on both sides of the insulating layer, an inner single-sided substrate with the metal layer formed on one side of the insulating layer, and an outer single-sided substrate with the metal layer formed on one side of the insulating layer, the inner single-sided substrate is laminated on the double-sided substrate, the outer single-sided substrate is laminated on the inner single-sided substrate located furthest out in the lamination direction of the unit substrates, the electronic component is arranged in an opening formed in the insulating layer of the double-sided substrate, the surfaces of the metal layer of the inner single-sided substrate and the double-sided substrate are roughened, and the spacing S between the wirings in the metal layer of the outer single-sided substrate Ｏ The spacing S between the wirings in the metal layer of the inner single-sided substrate. Ｉ However, a component-embedded circuit board that satisfies the following equation (1). S Ｏ ≤S Ｉ ×0.85 (1) 2. A component-embedded substrate according to claim 1, wherein the width L of the wiring provided in the metal layer of the outer single-sided substrate. Ｏ The width L of the wiring provided in the metal layer of the inner single-sided substrate. Ｉ However, a component-embedded circuit board that satisfies the following equation (2). L Ｏ ≤ L Ｉ ×0.85 (2) 3. The component-embedded substrate according to claim 1 or 2, wherein the inner single-sided substrate and the outer single-sided substrate are provided with conductive paste vias penetrating through the insulating layer, and the diameter D of the conductive paste via of the outer single-sided substrate Ｏ and the diameter D of the conductive paste via of the inner single-sided substrate Ｉ satisfy the following formula (3). D Ｏ ≦D Ｉ ×0.8 (3) 4. A component-embedded substrate according to claim 3, wherein the thickness T of the insulating layer of the outer single-sided substrate. Ｏ The thickness T of the insulating layer of the inner single-sided substrate. Ｉ However, a component-embedded circuit board that satisfies the following equation (4). Ｏ ≦T Ｉ ×0.7 (4) 5. A component-embedded substrate according to any one of claims 1 to 4, wherein the surface roughness Rz of the metal layer of the inner single-sided substrate and the metal layer of the double-sided substrate Ｉ The surface roughness Rz of the metal layer of the outer single-sided substrate Ｏ However, a component-embedded circuit board that satisfies the following equation (5). Rz Ｉ > Rz Ｏ (5) 6. A component-embedded substrate according to any one of claims 1 to 5, comprising: two or more electronic components; two or more double-sided substrates; and an intermediate substrate disposed between the two double-sided substrates via the adhesive layer.

7. A method for manufacturing an electronic component substrate, comprising: a first step of preparing an outer single-sided substrate by forming a metal layer on one side of an insulating layer; a second step of preparing an inner single-sided substrate by forming a metal layer on one side of an insulating layer and performing a surface roughening treatment on the surface of the metal layer; a third step of preparing a double-sided substrate by forming metal layers on both sides of an insulating layer, performing a surface roughening treatment on the surface of the metal layer and forming an opening in the insulating layer; and a fourth step of laminating the inner single-sided substrate onto the double-sided substrate via an adhesive layer, laminating the outer single-sided substrate onto the inner single-sided substrate via an adhesive layer, and thermocompressing the outer single-sided substrate, the inner single-sided substrate, and the double-sided substrate, wherein the fourth step includes laminating the inner single-sided substrate and the double-sided substrate so that an electronic component is inserted into the opening in the double-sided substrate.

8. A method for manufacturing a component-embedded substrate according to claim 7, wherein the second step includes mounting the electronic component on the inner single-sided substrate.

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