Silicon (110) substrate and method for processing silicon (110) substrate

Abstract

The present invention is a silicon (110) substrate characterized in that the silicon (110) substrate has an off angle, the off angle is greater than 0.23° and less than 0.5°, the silicon (110) substrate is an annealed substrate having a dopant concentration of 1E16 atoms / cm3 or less and subjected to a heat treatment at 1000°C or higher, and no protruding defects are detected. Thus, provided are a silicon (110) substrate in which the occurrences of minute protruding defects are suppressed, and a method for processing the silicon (110) substrate.

Description

Silicon (110) substrate and method for processing the silicon (110) substrate

[0001] The present invention relates to a silicon (110) substrate and a method for processing a silicon (110) substrate.

[0002] In contrast to the Fin structure currently used in logic ICs, GAA (Gate All Around) and CFET (Complete Field Effect Transistor), which further stacks NMOS and CMOS, have been proposed for the next generation and are being actively researched and developed. In this regard, the use of a silicon (hereinafter also referred to as Si) substrate with a plane orientation (110) is being considered as a method to improve hole mobility (Non-Patent Literature 1).

[0003] However, silicon (110) substrates have been criticized for having high surface roughness and haze (Non-Patent Literature 1). Here, haze is also called the degree of cloudiness of the surface, and it represents the surface roughness in terms of the degree of light scattering; the greater the haze, the rougher the surface. Furthermore, the most stable structure of the outermost surface of silicon (110) has only been confirmed relatively recently (Non-Patent Literature 2, 3).

[0004] Furthermore, according to Non-Patent Documents 2 and 3, the most stable structure, a 16x2 domain, undergoes a phase transition with temperature, and its structure changes in the range of 600 to 800°C as shown in Figure 2. In this temperature range, for example, hydrogen baking for growing silicon epitaxial layers (hereinafter simply referred to as epi, or epitaxial) and the subsequent silicon epitaxial layer exceed 1000°C, so it initially becomes a 1x1 structure, but a phase change occurs during cooling, and the surface structure also changes depending on the time spent passing through during cooling. Moreover, materials such as SiGe stacked in GAA and CFETs often use this temperature range, making it even more difficult to understand their surface structure.

[0005] This unique surface structure of the silicon (110) plane also affects the surface structure after etching. The step edges of the 16x2 surface structure are not monatomic structures like silicon (100), but have a step of two atoms. When the reaction system energy is low (equilibrium reaction), the reaction proceeds at the outermost surface atoms, resulting in a linear surface shape after etching surrounded by silicon (111), which is the first nearest neighbor. On the other hand, when the reaction system energy is high, atoms at the outermost surface and below participate in the reaction, resulting in a rectangular shape surrounded by silicon (111), which is the second nearest neighbor.

[0006] For silicon (110) with such a surface condition, Patent Document 1 discloses a method to reduce surface roughness by tilting the orientation during epitaxial growth. Patent Document 2 discloses the specification of the cooling rate and surface protection for the same epitaxial growth. Furthermore, Patent Document 3 discloses a method to reduce surface roughness in the same way by specifying the surface orientation during crystal growth rather than epitaxial growth. Patent Document 4 discloses polishing the epitaxial surface. Patent Document 5 also discloses a combination of Patent Documents 1 and 3.

[0007] Japan Society of Applied Physics, Industry-Academia Collaboration Committee on Crystal Growth, Processing and Evaluation of Semiconductors, 1st Workshop Meeting "Crystal Technology Supporting the Resurgence of Semiconductors," Yamada et al., "Fabrication of Si(110)-16×2 Single Domain Surface," Surface Science, 29(7), 401 (2008) Miyaji et al., "Observation of Si(110) Reconstructed Surfaces by Ultra-High Vacuum Non-Contact Atomic Microscope," Journal of the Japan Institute of Metals, 72(4), 290 (2008) Ueba, "Fundamentals of Epitaxial Growth - Strain, Diffusion, and Step Motion -," Journal of the Japan Society for Crystal Growth, 43(4), 213 (2016)

[0008] Japanese Patent Publication No. 2008-091887, Japanese Patent Publication No. 2006-100596, Japanese Patent Publication No. 2008-088045, Japanese Patent Publication No. 2014-239184, Japanese Patent Publication No. 2008-091891

[0009] As described above, the surface of the silicon (110) substrate has a very complex shape, and various methods have been disclosed to mitigate surface roughness. However, unlike the silicon (100) substrate, the silicon (110) substrate has a special structure in which the most stable structure is 16 × 2. As a result, there are unstable regions (expressed as disorder regions in Non-Patent Literature 2) adjacent to the most stable structure 16 × 2, and it has been found that hydrogen baking before epitaxial deposition generates minute protrusion-like defects from these areas.

[0010] The present invention has been made in view of the above-mentioned problems, and aims to provide a silicon (110) substrate in which the occurrence of minute protrusion-like defects is suppressed, and a method for processing the silicon (110) substrate.

[0011] To solve the above problems, the silicon (110) substrate of the present invention has an off-angle, which is greater than 0.23° and less than 0.5°, and the silicon (110) substrate has a dopant concentration of 1E16 atoms / cm³. ３ The following are annealed substrates that have undergone heat treatment at 1000°C or higher, and for which no protruding defects are detected.

[0012] With such a silicon (110) substrate, the occurrence of minute protrusion defects can be suppressed by limiting the off-angle, dopant concentration, and the heat treatment temperature of the annealing process.

[0013] Furthermore, the heat treatment of 1000°C or higher is preferably an annealing treatment.

[0014] This type of annealing process is preferable because it results in an annealed substrate in which no protruding defects are detected even after heat treatment.

[0015] Furthermore, the heat treatment at 1000°C or higher is an epitaxial treatment, and the dopant concentration of the epitaxial layer is 1E16 atoms / cm³. ３ The following is preferable:

[0016] With this dopant concentration for epitaxial treatment, the resulting epitaxial substrate is preferable because no protruding defects are detected even after heat treatment.

[0017] Furthermore, it is preferable that the dopant is of the p type.

[0018] With a p-type dopant at this concentration, no protrusion defects will be detected in the p-type epitaxial layer.

[0019] Furthermore, it is preferable that the dopant contains boron.

[0020] With dopant concentrations such as that of boron-containing dopants, it becomes more certain that no protrusion defects will be detected in the p-type epitaxial layer.

[0021] Furthermore, it is preferable that the dopant is of type n.

[0022] With an n-type dopant at this concentration, no protrusion defects will be detected in the n-type epitaxial layer.

[0023] Furthermore, it is preferable that the dopant contains at least one of phosphorus, arsenic, and antimony.

[0024] If the dopant contains at least one of phosphorus, arsenic, and antimony at such dopant concentrations, it becomes more certain that no protrusion defects will be detected in the n-type epitaxial layer.

[0025] Furthermore, it is preferable that the annealed substrate is cooled at a rate of 1000°C / min or more in the temperature range of 540 to 640°C after the heat treatment at 1000°C or higher.

[0026] If the annealed substrate is cooled at such a rate, the phase transition temperature will be passed through quickly during cooling, further suppressing the generation of minute protrusion-like defects.

[0027] Furthermore, the present invention relates to a silicon (110) substrate processing method which involves preparing a silicon (110) substrate having an off-angle greater than 0.23° and less than 0.5°, subjecting the silicon (110) substrate having the off-angle to a heat treatment of 1000°C or higher to produce an annealed substrate, and during the cooling in the heat treatment, cooling in the temperature range of 540 to 640°C at a rate of 1000°C / min or higher to ensure that no protruding defects are detected.

[0028] With this method of processing a silicon (110) substrate, the generation of minute protrusion defects can be suppressed by first limiting the off-angle, and furthermore, the generation of minute protrusion defects can be suppressed by rapidly passing through the phase transition temperature during cooling in the heat treatment.

[0029] Furthermore, it is preferable that the storage temperature of the annealed substrate after cooling be 540°C or lower and with a temperature variation of ±30°C or less.

[0030] By using such storage temperatures, the occurrence of minute protrusion-like defects during storage can be suppressed.

[0031] Furthermore, during the cooling process in the heat treatment, it is preferable to keep the temperature difference within the plane of the silicon (110) substrate within ±10°C when the average temperature within the plane of the silicon (110) substrate is in the range of 630°C to 750°C.

[0032] Such an in-plane temperature difference can suppress the generation of minute protrusion-like defects within the plane.

[0033] Furthermore, it is preferable that the heat treatment is an etching process that removes the native oxide film of the silicon (110) substrate using an etching gas, and that the pressure of the gas be 5 Torr or higher.

[0034] With this etching gas pressure, the evaporation of atoms during etching is suppressed due to the relatively high pressure, thus preventing the generation of minute protrusion-like defects caused by atomic evaporation.

[0035] Further, it is preferable that the heat treatment is an epitaxial process in which epitaxial growth is performed on the silicon (110) substrate using a gas, and the pressure of the gas is 5 Torr or less.

[0036] With such a gas pressure, since it is a relatively low pressure, the adhesion of atoms to the substrate surface can be suppressed to some extent, and the growth can be made not too fast, so that the generation of minute protrusion defects due to too fast growth can be suppressed.

[0037] Further, it is preferable that the gas contains nothing other than hydrogen and chlorine in addition to the atoms for the epitaxial process.

[0038] With such a gas species, growth can be performed in a state where there are no unnecessary atoms as much as possible, so that the generation of minute protrusion defects caused by unnecessary atoms can be suppressed.

[0039] Further, it is preferable that the flow rate of the gas (excluding inert gas) is 1000 sccm or less.

[0040] With such a gas flow rate, since it is a relatively low flow rate, the reactive species can be reduced, and the generation of minute protrusion defects due to too many reactive species can be suppressed.

[0041] In the case of the silicon (110) substrate of the present invention, by limiting the off-angle, dopant concentration, and heat treatment temperature of the applied annealing, the generation of minute protrusion defects is suppressed.

[0042] Also, in the case of the method for treating the silicon (110) substrate of the present invention, first, the generation of minute protrusion defects can be suppressed by limiting the off-angle, and further, the generation of minute protrusion defects can be suppressed by quickly passing through the phase transition temperature during cooling in the heat treatment.

[0043] This is a schematic diagram of the silicon (110) substrate of the present invention. This is a schematic diagram showing the relationship between the surface temperature and surface stability structure of the silicon (110) substrate. This is an image showing an example of surface structure and defects when hydrogen baked at atmospheric pressure. This is an image showing an example of surface structure and defects when hydrogen baking is performed for a long time to accelerate defect formation. This is a schematic diagram showing an example of defect formation on the surface. This is an image showing an example of the peripheral structure of a protruding defect. This is an image showing an example of the off-angle of silicon (110) and surface structure and defects. This is an image showing an example of the dopant concentration and p-type resistivity of silicon (110) and surface structure and defects.

[0044] The present invention will be described in detail below, but the present invention is not limited to these descriptions.

[0045] As mentioned above, there was a need to provide a silicon (110) substrate and a method for processing a silicon (110) substrate in which the occurrence of minute protrusion-like defects is suppressed.

[0046] As a result of diligent research into the above-mentioned problems, the inventors of the present invention discovered that the off-angle of the silicon (110) substrate is important, followed by the dopant concentration, the heat treatment temperature, and the cooling rate during the heat treatment, and thus completed the present invention.

[0047] That is, the silicon (110) substrate of the present invention has an off-angle, which is greater than 0.23° and less than 0.5°, and the silicon (110) substrate has a dopant concentration of 1E16 atoms / cm³. ３ The following are annealed substrates that have undergone heat treatment at 1000°C or higher, and for which no protruding defects are detected.

[0048] Furthermore, the present invention relates to a silicon (110) substrate processing method which involves preparing a silicon (110) substrate having an off-angle greater than 0.23° and less than 0.5°, subjecting the silicon (110) substrate having the off-angle to a heat treatment of 1000°C or higher to produce an annealed substrate, and during the cooling in the heat treatment, cooling in the temperature range of 540 to 640°C at a rate of 1000°C / min or higher to ensure that no protruding defects are detected.

[0049] The following explains the process that led to the completion of this invention.

[0050] Figure 1 is a schematic diagram of the silicon (110) substrate 1 of the present invention. In the silicon (110) substrate 1, a native oxide film 7 is usually formed on the surface of the surface stabilization structure 2.

[0051] Generally, before epitaxial growth, a high-temperature annealing treatment (hydrogen baking) is performed in a hydrogen atmosphere to remove the native oxide film 7 present on the surface of the silicon substrate. The temperature at this time is often in the range of approximately 1000°C or higher. This is because even a thin native oxide film of less than 1 nm can prevent the epitaxial growth of silicon due to the presence of an amorphous oxide layer.

[0052] Although this hydrogen bake temperature is sufficiently higher than the phase transition temperature of silicon (110) as described above, it may have an effect, unlike substrates such as silicon (100) which do not exhibit a phase transition temperature. Furthermore, as pointed out in Patent Document 2, the influence of the cooling process cannot be ignored. This is because the phase transition temperature of silicon (110) falls within the temperature range that is passed through during cooling.

[0053] In addition to surface roughness, as described in Patent Document 2, we investigated whether there were any other effects, and found that minute protrusion-like defects 6 were formed after hydrogen baking at 1080°C for 40 seconds (Figure 3). Figure 3 is an AFM image showing the surface structure after hydrogen baking at atmospheric pressure. The height is exaggerated, but the height is approximately 1 to 1.3 nm.

[0054] Therefore, in order to further accelerate the occurrence of defects, the hydrogen bake time was increased to 600 and 1800 seconds, and the same evaluation was performed. Figure 4 shows images of the surface structure; Figure 4(a) shows the result after a hydrogen bake time of 600 seconds, and Figure 4(b) shows the result after a hydrogen bake time of 1800 seconds. It was found that the longer the time, the more minute protrusion-like defects 6 there were. Furthermore, by increasing the field of view of the AFM and estimating the density, it was possible to quantify that more defects were generated as the bake time increased. Table 1 shows the hydrogen bake conditions and the estimated density of the minute protrusion-like defects that were generated.

[0055]

[0056] Furthermore, AFM imaging of this defect revealed the presence of shallower pits around the defect. From this, it was concluded that this protruding defect was formed by the aggregation of silicon atoms.

[0057] It is clear that the phase transition of the silicon (110) substrate is influencing the mechanism of occurrence of these protrusion defects. Non-patent document 2 describes a domain shape such as 16 × 2 on the silicon (110) surface, and states that unstable disorder regions (anomalous regions) in which pentagonal adatoms are randomly arranged tend to form between these domains.

[0058] Furthermore, Non-Patent Document 4 describes silicon (111), for which surface research is more advanced than that of silicon (110), stating that a phase transition occurs around 860°C, resulting in a 7×7 structure at low temperatures and a 1×1 structure at high temperatures. Around this phase transition temperature, the 7×7 structure appears only in the upper part near the step. This is attributed to the effect of elastic strain; the 7×7 structure is in a more compressed state compared to the 1×1 structure, and this strain can be relieved, causing the 7×7 structure to appear on the edge of the upper part of the step.

[0059] Furthermore, as a general principle, regarding the movement of atoms on step terraces, it is said that (1) atoms moving across terraces are more reactive the narrower the terrace width (because the distance the atom can move is shorter, in other words, the atom has more energy), and (2) atoms cannot move to other terraces due to the high energy barrier at the edge of the terrace.

[0060] Figure 5 attempts to schematically illustrate defect formation on this surface. Assuming that there are steps of 16×2 structures 3 at the ends between the terraces of two 1×1 structures 4, it is thought that atoms flow quickly on the terraces of the 1×1 structures 4, but cannot move at the terrace edges, so atoms accumulate at the terrace edges and defects are likely to be generated.

[0061] From theoretical analysis of the motion of these step terraces and the results of a series of hydrogen bakes, we were able to explain and infer for the first time that a phase transition occurs in silicon (110) over a relatively wide temperature range of 600°C to 800°C (Figure 2), and that atoms tend to accumulate at the terrace edges of silicon (110) and generate defects (Figure 5), which is the driving force behind the generation of the defects shown in Figures 3 and 4.

[0062] In fact, a more detailed analysis of the area around this protruding defect reveals that a depression has formed around the defect. Figure 6 is an image showing an example of the surrounding structure of a protruding defect. In both Figure 6(a) and Figure 6(b), which are under different conditions, a minute protruding defect 6 and a depression 5 around the protruding defect can be seen nearby. In other words, it can be seen that the minute protruding defect 6 was formed by the aggregation of surrounding atoms.

[0063] These defects are protrusions and are easily oxidized, so if left exposed to the air, they may be detected as oxide protrusions. Furthermore, if epitaxial growth is performed, the gas flow rate at these protrusions increases, which could cause them to enlarge and grow further.

[0064] Furthermore, in the case of deposited films, they may be detected as large protrusions due to the lens effect.

[0065] Furthermore, because this phenomenon is caused by migration on the silicon (110) surface, defects will grow even during the growth process, especially during epitaxial growth near the phase transition temperature (it can be easily inferred that this is particularly pronounced when growing at low temperatures, such as with SiGe or Ge).

[0066] To obtain a surface with fewer such protrusion defects, countermeasures are taken for the silicon (110) surface by dividing them into an etching process in which atoms are removed from the surface and a growth process in which atoms are adsorbed and diffused.

[0067] First, there is the etching process, such as the hydrogen baking process mentioned earlier, in which atoms are removed from the surface. For this process, uniform etching is crucial.

[0068] As a substrate, a large off-angle is used to suppress defect generation through the ES effect (Erlik-Schwebel effect: a wider terrace allows for greater atomic diffusion, thus suppressing step motion).

[0069] Furthermore, for etching (hydrogen baking) conditions, it is preferable to suppress atomic evaporation, and high pressure is desirable.

[0070] Regarding temperature, it is preferable to pass through the phase transition temperature region quickly. In particular, even if the surface is leveled at high temperatures, there is a high possibility of changes during cooling, making the cooling process especially important.

[0071] The temperature after cooling is also important; it is best to avoid leaving the wafers near the phase transition temperature for extended periods. For example, after removal from the processing unit, the wafers should be cooled to the lowest possible temperature and kept consistent between wafers. Temperature variations and fluctuations near the phase transition temperature will result in differences between wafers.

[0072] Furthermore, it is preferable to ensure that there is no difference in temperature between the center and edges of the wafer during cooling. In particular, when using a large-diameter substrate and high processing temperatures, if a temperature distribution occurs within the wafer surface, an in-plane temperature distribution will occur, especially near the phase transition temperature.

[0073] Next, there is the CVD process, which involves depositing atoms onto the surface, particularly the epitaxial process, which requires growth while maintaining crystallinity. Uniform growth is crucial for this process.

[0074] As with the substrate, a large off-angle can be used, similar to the etching process described above, to suppress the generation of growth defects through the ES effect.

[0075] Furthermore, regarding growth conditions, it is preferable to suppress the adhesion of atoms to the substrate surface so that growth is not too rapid, and low pressure is desirable.

[0076] Regarding temperature, it is preferable to quickly pass through the phase transition temperature region. Even if the epitaxial growth temperature is sufficiently higher than the phase transition temperature, there is a high possibility of changes during cooling, and cooling is particularly important. Furthermore, if the growth temperature overlaps with the phase transition temperature, additional consideration is required, and it is preferable to select a gas species without unwanted atoms and to reduce the gas flow rate (to reduce the number of reactive species).

[0077] Similar to the etching process described above, the temperature after cooling is also important. It is best to avoid leaving the wafers near the phase transition temperature for extended periods. For example, after removal from the processing equipment, the temperature should be kept as low as possible, and the temperature should not vary from wafer to wafer. Temperature variations and fluctuations near the phase transition temperature will result in differences between wafers.

[0078] Furthermore, similar to the etching process described above, it is preferable to ensure that there is no difference in temperature between the center and edges of the wafer during cooling. In particular, when using a large-diameter substrate and high processing temperatures, if a temperature distribution occurs within the wafer surface, an in-plane temperature distribution will occur, especially near the phase transition temperature.

[0079] Embodiments of the present invention will be described below with reference to the drawings.

[0080] Figure 7 shows an example image of the off-angle and surface structure / defects of silicon (110).

[0081] Regarding the effect of the off-angle on silicon (110) substrates, both etching and epitaxial growth show defects at angles of 0.217° and 0.224°, as shown in Figure 7, while defects are absent at 0.235°. Therefore, an off-angle greater than 0.23° is desirable. As for the upper limit of the off-angle, if it is less than 0.5°, the generation of minute protrusion-like defects can be suppressed.

[0082] Next, regarding etching conditions, it is preferable to suppress atomic evaporation, and high pressure is desirable. There are also constraints on temperature, but for example, when heat treatment is performed at 1000°C or higher, it is preferable to set the pressure to 5 Torr or higher. There is no particular upper limit to the etching pressure, but it can be, for example, 100 Torr or less. Here, 1 Torr is approximately 133.32 Pa in the International System of Units (SI).

[0083] Regarding temperature, it is preferable to quickly pass through the phase transition temperature region. In particular, even if the surface is leveled at high temperatures, there is a high possibility of changes during cooling, and cooling is especially important. By cooling in the temperature range of 540 to 640°C at a rate of 1000°C / min or more, the generation of even smaller protrusion-like defects can be suppressed even further. There is no particular upper limit to the cooling rate, but for example, it can be 2000°C / min or less.

[0084] The temperature after cooling is also important; it is best to avoid leaving the wafers near the phase transition temperature for extended periods. For example, the storage temperature after removal from the processing unit should be as low as possible, and the temperature should not vary from wafer to wafer. This can be achieved by storing the wafers at a temperature of 540°C or lower and controlling the temperature variation to within ±30°C. This suppresses the occurrence of differences between wafers due to temperature variations and fluctuations near the phase transition temperature, thereby preventing the generation of minute protrusion-like defects. The lower limit of the storage temperature is not particularly limited, but it can be, for example, 30°C or higher.

[0085] Furthermore, it is preferable to ensure that there is no difference in temperature between the center and edges of the wafer during cooling. When using a large-diameter substrate and high processing temperatures, temperature distribution occurs within the wafer surface, and especially near the phase transition temperature, this in-plane temperature distribution can lead to defect generation. Therefore, it is preferable to control the in-plane temperature distribution to within ±30°C to suppress defect generation. In particular, between approximately 630°C (the phase transition temperature) and 750°C, the temperature difference within the wafer surface can be kept within ±10°C to suppress the generation of minute protrusion-like defects within the wafer surface.

[0086] Next, regarding the conditions for epitaxial growth, it is preferable to suppress the adhesion of atoms to the substrate surface so that the growth is not too fast. Low pressure is desirable, and although there are constraints on temperature, for example, when heat treatment at 1000°C or higher is performed, it is preferable to keep the pressure at 5 Torr or less. The lower limit of the pressure for epitaxial growth is not particularly limited, but it can be, for example, 1 Torr or more.

[0087] Regarding temperature, it is preferable to quickly pass through the phase transition temperature region, similar to the etching conditions. Even if the epitaxial growth temperature is sufficiently higher than the phase transition temperature, there is a high possibility of changes during cooling, and cooling is particularly important. Cooling in the 540 to 640°C temperature range at a rate of 1000°C / min or higher can further suppress the generation of minute protrusion defects. There is no particular upper limit to the cooling rate, but for example, it can be set to 2000°C / min or less, similar to the etching conditions.

[0088] Furthermore, if the growth temperature overlaps with the phase transition temperature, additional consideration is required, and it is preferable to select a gas species that does not contain unwanted atoms. For example, as a gas for epitaxial processing, SiH ４ and GeH ４ While these are examples, it is preferable that the material does not contain any atoms other than hydrogen and chlorine, other than the atoms used for epitaxial treatment (Si and Ge).

[0089] Furthermore, if the growth temperature overlaps with the phase transition temperature, it is preferable to reduce the gas flow rate (to reduce the number of reactive species), and it is preferable to set the gas flow rate (excluding inert gas) to 1000 sccm or less. The lower limit of the gas flow rate is not particularly limited, but for example, it can be 100 sccm or more.

[0090] The temperature after cooling is also important. Similar to the conditions after etching, it is best to avoid leaving the wafers near the phase transition temperature for extended periods. For example, the storage temperature after removal from the processing unit should be as low as possible, and the temperature should not vary from wafer to wafer. Storage at a temperature of 540°C or lower, and controlling the temperature variation to within ±30°C, can suppress variations. This suppresses the occurrence of differences between wafers due to temperature variations and fluctuations near the phase transition temperature, thereby suppressing the generation of minute protrusion-like defects. There is no particular lower limit to the storage temperature, but it can be set to 30°C or higher, similar to the conditions after etching.

[0091] Furthermore, similar to the conditions after etching, it is preferable to ensure that there is no difference in temperature between the center and edges of the wafer during cooling. When using a large-diameter substrate and high processing temperatures, temperature distribution occurs within the wafer surface, and especially near the phase transition temperature, this in-plane distribution can lead to defect generation. Therefore, it is preferable to control the in-plane temperature distribution to within ±30°C to suppress defect generation. In particular, between approximately 630°C (the phase transition temperature) and 750°C, keeping the temperature difference within the wafer surface within ±10°C can suppress the generation of minute protrusion-like defects within the wafer surface.

[0092] The present invention will be specifically explained below with reference to three experimental examples, but this is not intended to limit the present invention.

[0093] [Experimental Example 1] A 300 mm (110) boron-doped single-crystal silicon substrate with a resistance of 10 Ω·cm was prepared. Substrates with off-angles of 0.217, 0.224, and 0.235° were prepared and annealed at a temperature of 1080°C for 600 seconds. The pressure at this time was 5 Torr. AFM measurements were then performed.

[0094] As a result, as shown in Figure 7, when the off-angle was 0.217°, defects occurred in the left-right direction of the paper, and when the off-angle was 0.224°, defects occurred from the upper left to the lower right of the paper. However, no defects were observed when the off-angle was 0.235°. Therefore, it was found that the off-angle should be greater than 0.23°.

[0095] [Experimental Example 2] A single-crystal silicon substrate with a diameter of 300 mm (110) boron doped and a resistance of 10 Ω·cm was prepared, and an off-angle of 0.235° was prepared. This substrate was annealed at a temperature of 1080°C for 600 seconds. The pressure at this time was 5 Torr. For cooling during the heat treatment, two conditions were used: cooling in the temperature range of 540 to 640°C at a rate of 1000°C / min, and cooling at a rate of 500°C / min. AFM measurements were then performed.

[0096] As a result, no minute protrusion-like defects were generated under any conditions. However, when the temperature was increased from 500 °C / min to 1000 °C / min, the surface roughness decreased, and the surface appeared smoother. Therefore, when the cooling rate can be adjusted, it is more preferable to set it at 1000 °C / min or higher.

[0097] [Experimental Example 3] A p-type silicon epitaxial substrate was prepared by epitaxially growing a p-type silicon substrate on a silicon (110) substrate with a diameter of 300 mm (off-angle: 0.235°) with a p-type boron dopant at different dopant concentrations. Each substrate was annealed (hydrogen bake) at 1080 °C for 45 seconds. The pressure at this time was 5 Torr, and AFM measurement was performed after the annealing treatment.

[0098] As a result, as shown in Fig. 8, no protrusion-like defects were detected when the dopant concentration was in the range of 5E14 to 1E16 atoms / cm ３ (p-type resistivity: 50 Ω·cm to 2 Ω·cm). On the other hand, on the substrate with a dopant concentration of 5E16 atoms / cm ３ , slightly protrusion-like objects 8 were observed. Although these protrusion-like objects 8 themselves may not be clearly defined as protrusion-like defects, it is considered that the risk of the occurrence of protrusion-like defects increases. Therefore, it is more preferable that the dopant concentration is 1E16 atoms / cm ３ or less (p-type resistivity: 2 Ω·cm or more). <​​​​​​​​​Therefore, the dopant concentration is preferably within the range shown in Figure 8, specifically a dopant concentration of 5E14 to 1E16 atoms / cm³. ３ It is preferable that this be the case.

[0102] In summary, the silicon (110) substrate of the present invention has an off-angle, which is greater than 0.23° and less than 0.5°, and the silicon (110) substrate has a dopant concentration of 1E16 atoms / cm³. ３ The following are annealed substrates that have undergone heat treatment at 1000°C or higher, and for which no protruding defects are detected.

[0103] With such a silicon (110) substrate, the occurrence of minute protrusion defects can be suppressed by limiting the off-angle, dopant concentration, and heat treatment temperature.

[0104] The upper limit of the heat treatment temperature is not particularly limited, but it is preferably below the melting point of silicon, 1420°C, and more preferably 1300°C or lower. Furthermore, depending on the capacity of the heat treatment apparatus, the temperature can be set to, for example, 1200°C or lower in order to reduce power consumption during heat treatment, although this is not particularly limited.

[0105] Furthermore, the heat treatment above 1000°C is not particularly limited, but annealing is preferred.

[0106] This type of annealing treatment is preferable because no protruding defects are detected even after heat treatment.

[0107] Furthermore, heat treatment above 1000°C is not particularly limited, but may be an epitaxial treatment. In addition, the dopant concentration of the epitaxial layer is not particularly limited, but 1E16 atoms / cm³. ３ The following is preferable:

[0108] With epitaxial treatment using such a dopant concentration, no protruding defects are detected even after heat treatment, making it more preferable.

[0109] Furthermore, the dopant is not particularly limited, but it is preferably of the p type.

[0110] With a p-type dopant at this concentration, no protrusion defects will be detected in the p-type epitaxial layer.

[0111] Furthermore, the p-type dopant is not particularly limited, but it is preferable that it contains boron.

[0112] With dopant concentrations such as that of boron-containing dopants, it becomes more certain that no protrusion defects will be detected in the p-type epitaxial layer.

[0113] Furthermore, while not specifically limited, the Dopant can be of type n.

[0114] With an n-type dopant at this concentration, no protrusion defects will be detected in the n-type epitaxial layer.

[0115] Furthermore, the n-type dopant is not particularly limited, but it is preferable that it contains at least one of phosphorus, arsenic, and antimony.

[0116] If the dopant contains at least one of phosphorus, arsenic, and antimony at such dopant concentrations, it becomes more certain that no protrusion defects will be detected in the n-type epitaxial layer.

[0117] Furthermore, it is preferable that the annealed substrate is heat-treated at 1000°C or higher, and then cooled at a rate of 1000°C / min or higher in the temperature range of 540 to 640°C.

[0118] If the annealed substrate is cooled at such a rate, the phase transition temperature will be passed through quickly during cooling, further suppressing the generation of minute protrusion-like defects.

[0119] The present invention encompasses the following embodiments: [1]: A silicon (110) substrate, wherein the silicon (110) substrate has an off-angle, which is greater than 0.23° and less than 0.5°, and the silicon (110) substrate has a dopant concentration of 1E16 atoms / cm³. ３A silicon (110) substrate characterized by being an annealed substrate subjected to a heat treatment of 1000°C or higher as described below, and in which no protruding defects are detected. [2]: The silicon (110) substrate according to [1] above, characterized in that the heat treatment of 1000°C or higher is an annealing treatment. [3]: The heat treatment of 1000°C or higher is an epitaxial treatment, and the dopant concentration of the epitaxial layer is 1E16 atoms / cm³. ３The silicon (110) substrate according to [1] above, characterized in that: [4]: ​​The silicon (110) substrate according to any one of [1] to [3] above, characterized in that the dopant is p-type. [5]: The silicon (110) substrate according to any one of [1] to [4] above, characterized in that the dopant contains boron. [6]: The silicon (110) substrate according to any one of [1] to [3] above, characterized in that the dopant is n-type. [7]: The silicon (110) substrate according to any one of [1] to [3] and [6] above, characterized in that the dopant contains at least one of phosphorus, arsenic, and antimony. [8]: The silicon (110) substrate according to any one of [1] to [7] above, characterized in that the annealed substrate is cooled at a rate of 1000°C / min or more in the temperature range of 540 to 640°C after the heat treatment of 1000°C or more. [9]: A method for processing a silicon (110) substrate, characterized in that a silicon (110) substrate having an off-angle greater than 0.23° and less than 0.5° is prepared, an annealed substrate is produced by subjecting the silicon (110) substrate having the off-angle to a heat treatment of 1000°C or higher, and during cooling in the heat treatment, the temperature range of 540 to 640°C is cooled at a rate of 1000°C / min or higher so that no protruding defects are detected.

[10] : The method for processing a silicon (110) substrate according to [9] above, characterized in that the storage temperature of the annealed substrate after cooling is 540°C or lower and the temperature variation is within ±30°C.

[11] : The method for processing a silicon (110) substrate according to [9] above or

[10] above, characterized in that during cooling in the heat treatment, the temperature difference within the plane of the silicon (110) substrate is kept within ±10°C when the average temperature within the plane of the silicon (110) substrate is in the range of 630°C to 750°C.

[12] : A method for processing a silicon (110) substrate according to any one of [9] to

[11] above, characterized in that the heat treatment is an etching treatment that removes the native oxide film of the silicon (110) substrate using an etching gas, and the pressure of the gas is 5 Torr or more.

[13] : A method for processing a silicon (110) substrate according to any one of [9] to

[11] above, characterized in that the heat treatment is an epitaxial treatment in which epitaxial growth is performed on the silicon (110) substrate using a gas, and the pressure of the gas is 5 Torr or less.

[14] : A method for processing a silicon (110) substrate according to

[13] above, characterized in that the gas does not contain anything other than hydrogen and chlorine other than atoms for the epitaxial treatment.

[15] : A method for processing a silicon (110) substrate according to

[13] or

[14] above, characterized in that the flow rate of the gas (excluding inert gas) is 1000 sccm or less.

[0120] It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that has substantially the same technical idea as described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention.

Claims

A silicon (110) substrate, The silicon (110) substrate has an off-angle, which is greater than 0.23° and less than 0.5°. The silicon (110) substrate has a dopant concentration of 1E16 atoms / cm³. ３ A silicon (110) substrate characterized by being an annealed substrate subjected to heat treatment at 1000°C or higher, and free from detectable protruding defects. 　 The silicon (110) substrate according to claim 1, characterized in that the heat treatment of 1000°C or higher is an annealing treatment. 　 The aforementioned heat treatment at 1000°C or higher is an epitaxial treatment, and the dopant concentration of the epitaxial layer is 1E16 atoms / cm³. ３ The silicon (110) substrate according to claim 1, characterized in that it is as follows. 　 The silicon (110) substrate according to any one of claims 1 to 3, characterized in that the dopant is of the p type. 　 The silicon (110) substrate according to claim 4, characterized in that the dopant contains boron. 　 The silicon (110) substrate according to any one of claims 1 to 3, characterized in that the dopant is n-type. 　 The silicon (110) substrate according to claim 6, characterized in that the dopant contains at least one of phosphorus, arsenic, and antimony. 　 The silicon (110) substrate according to any one of claims 1 to 3, characterized in that the annealed substrate is cooled at a rate of 1000°C / min or more in the temperature range of 540 to 640°C after the heat treatment of 1000°C or more. 　 A method for processing a silicon (110) substrate, Prepare a silicon (110) substrate with an off-angle greater than 0.23° and less than 0.5°. An annealed substrate is produced by subjecting the silicon (110) substrate having the aforementioned off-angle to a heat treatment of 1000°C or higher. During the cooling process in this heat treatment, the temperature range of 540 to 640°C is cooled at a rate of 1000°C / min or more. A method for processing a silicon (110) substrate, characterized in that no protruding defects are detected. 　 The method for processing a silicon (110) substrate according to claim 9, characterized in that the storage temperature of the annealed substrate after cooling is 540°C or less and the temperature variation is within ±30°C. 　 The method for processing a silicon (110) substrate according to claim 9, characterized in that, during cooling in the heat treatment, the temperature difference within the surface of the silicon (110) substrate is kept within ±10°C when the average temperature within the surface of the silicon (110) substrate is in the range of 630°C to 750°C. 　 The method for processing a silicon (110) substrate according to any one of claims 9 to 11, characterized in that the heat treatment is an etching treatment that removes the native oxide film of the silicon (110) substrate using an etching gas, and the pressure of the gas is 5 Torr or more. 　 The method for processing a silicon (110) substrate according to any one of claims 9 to 11, characterized in that the heat treatment is an epitaxial treatment in which epitaxial growth is performed on the silicon (110) substrate using a gas, and the pressure of the gas is 5 Torr or less. 　 The method for processing a silicon (110) substrate according to claim 13, characterized in that the gas does not contain anything other than hydrogen and chlorine, except for the atoms used for epitaxial processing. 　 The method for processing a silicon (110) substrate according to claim 13, characterized in that the flow rate of the gas (excluding inert gas) is 1000 sccm or less.

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