Pecvd HBN film engineering for inter metal dielectric in 3D semiconductor devices

Abstract

Embodiments described herein generally relate to semiconductor devices. More specifically, embodiments described herein relate to the production of films with high thermal conductivity and low dielectric constants for use in 3D semiconductor device packages. In at least one embodiment, a 3D integrated circuit is provided. The 3D integrated circuit includes at least one inter metal dielectric layer disposed between two metal interconnect layers. The inter metal dielectric layer includes a hexagonal boron nitride film having a dielectric constant of less than or about 5.0 and a specific conductivity of about 10 W / (mK) or greater. The 3D integrated circuit further includes a via disposed through the hexagonal boron nitride film, electrically connecting the two metal layers.

Description

PECVD HBN FILM ENGINEERING FOR INTER METAL DIELECTRIC IN 3D SEMICONDUCTOR DEVICESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims benefit of U.S. Provisional patent application Ser. No. 63 / 720,021, filed November 13, 2024, which is herein incorporated by reference in its entirety.Field

[0002] Embodiments of the present disclosure generally relate to semiconductor devices. More specifically, embodiments described herein relate to the production of films having high thermal conductivity and low dielectric constants for use in 3D semiconductor device packages.BACKGROUNDDescription of the Related Art

[0003] Ongoing trends in the development of semiconductor device technology have led to semiconductor components having reduced sizes and increased circuit densities. In accordance with demands for continued scaling of semiconductor devices while improving performance capabilities, these components and circuits are integrated into complex three-dimensional (3D) semiconductor device packages that facilitate a significant reduction in device footprint and enable shorter and faster connections between components. Such packages may integrate, for example, semiconductor chips and a plurality of other electronic components for mounting onto a circuit board of an electronic device.

[0004] 3D integrated circuits (3D-ICs) are a type of chip packaging done at the wafer level to streamline the manufacturing process. Using 3D-IC fabrication, multiple chips are vertically stacked in a single package to deliver higher performance and functionality in a smaller area. The chips are electrically connected to one another within the stack using holes through the chips called through silicon vias (TSVs) or monolithic internal vias. The verticalelectrical connection may generate a significant amount of heat during system operation, which can reduce the overall efficiency and longevity of the chip.

[0005] Thus, there is a need for materials for inter metal dielectric layers that have low dielectric constants and high thermal conductivities.SUMMARY

[0006] Embodiments of the present disclosure generally relate to semiconductor packaging. More specifically, embodiments described herein relate to the production of films having high thermal conductivity and low dielectric constants for use in 3D semiconductor device packages.

[0007] In at least one embodiment, a 3D integrated circuit is provided. The 3D integrated circuit includes at least one inter metal dielectric layer disposed between two metal interconnect layers. The inter metal dielectric layer includes a hexagonal boron nitride film having a dielectric constant of less than or about 5.0 and a specific conductivity of about 10 W / (mK) or greater. The 3D integrated circuit further includes a via disposed through the hexagonal boron nitride film, electrically connecting the two metal layers.

[0008] In at least one embodiment, a 3D stacked chip is provided. The 3D stacked chip includes two or more semiconductor chips and a bonding layer disposed between two of the two or more semiconductor chips. The bonding layer includes a hexagonal boron nitride film having a dielectric constant of about 5.0 or less and a specific conductivity of about 10 W / (mK) or greater. A through silicon via is disposed through the bonding layer and at least a portion of one of the two or more semiconductor chips, the through silicon via electrically connecting at least two of the two or more semiconductor chips.

[0009] In at least one embodiment, a method for modifying film characteristics is provided. The method includes positioning a substrate on a substrate support disposed within a processing chamber, depositing a hexagonal boron nitride (hBN) film, and treating the deposited hBN film. Depositing the hBN film includes, flowing a first one or more gases into the processing chamber, supplying a first plasma power from a first plasma sourceto form a first plasma from the first one or more gases, and depositing the hBN film on the substrate with the first plasma. Treating the hBN film includes, flowing a second one or more gases into the processing chamber, supplying a second plasma power from a second plasma source to form a second plasma from the second one or more gases, and tuning the second plasma to adjusting a lamella orientation of the deposited hBN film. Tuning the second plasma includes one or more of: forming horizontal lamella with an RF second plasma power of about 300 W to about 700 W and a H2 flow rate of about 0 seem to about 500 seem, and forming vertical lamella with an RF second plasma power of about 400 W to about 1 ,400 W and a H2 flow rate of about 1 ,000 seem to about 4,000 seem.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.

[0011] Figure 1 is a schematic cross-sectional view of a processing chamber, according to one or more embodiments of the present disclosure.

[0012] Figure 2 a schematic cross-sectional view of an integrated circuit, according to one or more embodiments of the present disclosure.

[0013] Figure 3A is a schematic cross-sectional view of a monolithic 3D integrated circuit, according to one or more embodiments of the present disclosure.

[0014] Figure 3B is a schematic cross-sectional view of a 3D stacked integrated circuit, according to one or more embodiments of the present disclosure.

[0015] Figure 4 is a flow diagram of a method for forming a hexagonal boron nitride film, according to one or more embodiments.

[0016] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0017] Embodiments described herein generally relate to semiconductor devices. More specifically, embodiments described herein relate to the production of films having high thermal conductivity and low dielectric constants for use in 3D semiconductor device packages. It has been discovered that the characteristics of hexagonal boron nitride (hBN) films may be tuned using the methods described herein to meet and exceed the required dielectric and thermal conductivity properties of both inter metal dielectric films and bonding films utilized in 3D integrated circuits. Methods disclosed herein generally include a tunable cyclic deposition and treatment process that produces highly ordered hBN films. Film characteristics such lamella orientation and crystallinity may be tuned by adjusting process conditions such as gas flow rate, plasma conditions, the plasma source, and treatment time during the deposition and treatment of the films.

[0018] At least some embodiments described herein implement a tunable cyclic deposition and treatment process to form highly ordered hBN films having dielectric constant of less than or about 4 and specific conductivity of about 10 W / (mK) to about 150 W / (mK) or greater. In at least one embodiment, the lamella orientation of the hBN film is tuned by altering the flow of H2, the plasma power, and / or treatment time during the treatment operation. In at least one embodiment, the crystallinity of the hBN film may be improved by adjusting the plasma conditions during the deposition and / or the treatment. In at least one embodiment, the crystallinity of the hBN film may be improved by adjusting the plasma source during the deposition and / or the treatment. At least some embodiments describe an inter metal dielectric layer that utilizes an hBN filmhaving a dielectric constant of less than or about 4 and a specific conductivity of about 10 W / (mK) to about 25 W / (mK). At least some embodiments describe a bonding layer that utilizes an hBN film having a dielectric constant of less than or about 4 and a specific conductivity of about 10 W / (mK) to about 25 W / (mK).

[0019] Embodiments described herein will be described below in reference to a Plasma Enhanced Chemical Vapor Deposition (PECVD) process that can be carried out using any suitable thin film deposition system. Examples of suitable systems include the CENTURA® systems which may use a DXZ® processing chamber, PRECISION 5000® systems, PRODUCER® systems, PRODUCER® GTTM systems, PRODUCER® XP PRECISION™ systems, PRODUCER® SETM systems, and TESSERACT® systems, which are commercially available from Applied Materials, Inc., of Santa Clara, Calif. Other tools capable of performing PECVD processes may also be adapted to benefit from the implementations described herein. In addition, any system enabling the PECVD processes described herein can be used to advantage. The apparatus description described herein is illustrative and should not be construed or interpreted as limiting the scope of the implementations described herein.

[0020] Figure 1 shows a cross-sectional view of an exemplary processing chamber 100 according to some embodiments of the present technology. Figure 1 provides an overview of a system incorporating one or more aspects of the present technology, and / or which may be specifically configured to perform one or more operations according to embodiments of the present technology. Additional details of processing chamber 100 or methods performed may be described further below. Processing chamber 100 may be utilized to form film layers according to some embodiments of the present technology, although it is to be understood that the methods may similarly be performed in any chamber within which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 coupled with the chamber body 102 and enclosing the substrate support 104 in a processing volume 120. A substrate 103 may be provided to the processingvolume 120 through an opening 126, which may be conventionally sealed for processing using a slit valve or door. The substrate 103 may be seated on a surface 105 of the substrate support during processing. The substrate support 104 may be rotatable, as indicated by the arrow 145, along an axis 147, where a shaft 144 of the substrate support 104 may be located. Alternatively, the substrate support 104 may be lifted up to rotate as necessary during a deposition process.

[0021] A plasma profile modulator 111 may be disposed in the processing chamber 100 to control plasma distribution across the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108 that may be disposed adjacent to the chamber body 102, and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106, or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-like member, and may be a ring electrode. The first electrode 108 may be a continuous loop around a circumference of the processing chamber 100 surrounding the processing volume 120, or may be discontinuous at selected locations if desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or a mesh electrode, or may be a plate electrode, such as, for example, a secondary gas distributor. In other embodiments, the processing chamber 100 may alternately, or additionally, include an inductive coil (not shown) surrounding the chamber body 102 or a lower portion of the lid assembly 106.

[0022] One or more isolators 110a, 110b, which may be a dielectric material such as a ceramic or metal oxide, for example aluminum oxide and / or aluminum nitride, may contact the first electrode 108 and separate the first electrode 108 electrically and thermally from a gas distributor 112 and from the chamber body 102. The gas distributor 112 may define apertures 118 for distributing process precursors into the processing volume 120. The gas distributor 112 may be coupled with a first source of electric power 142, such as an RF generator, RF power source, DC power source, pulsed DC power source, pulsed RF power source, low frequency (LF) RF power source, or any other power source thatmay be coupled with the processing chamber. In some embodiments, the first source of electric power 142 may be an RF power source.

[0023] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed of conductive and non-conductive components. For example, a body of the gas distributor 112 may be conductive while a face plate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by the first source of electric power 142 as shown in Figure 1 or the gas distributor 112 may be coupled with ground in some embodiments.

[0024] The first electrode 108 may be coupled with a first tuning circuit 128 that may control a ground pathway of the processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or include a variable capacitor or other circuit elements. The first tuning circuit 128 may be or include one or more inductors 132. The first tuning circuit 128 may be any circuit that enables variable or controllable impedance under the plasma conditions present in the processing volume 120 during processing. In some embodiments as illustrated, the first tuning circuit 128 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be coupled with the first electronic controller 134, which may afford a degree of closed-loop control of plasma conditions inside the processing volume 120.

[0025] A second electrode 122 may be coupled with the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or coupled with a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode122 may be a tuning electrode, and may be coupled with a second tuning circuit 136 by a conduit 146, for example a cable having a selected resistance, such as 50 ohms, for example, disposed in the shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor, and may be coupled with the second electronic controller 140 to provide further control over plasma conditions in the processing volume 120.

[0026] A third electrode 124, which may be a bias electrode and / or an electrostatic chucking electrode, may be coupled with the substrate support 104. The third electrode may be coupled with a second source of electric power 150 through a filter 148, which may be an impedance matching circuit. The second source of electric power 150 may be DC power, pulsed DC power, RF bias power, a pulsed RF source or bias power, LFRF source or bias power, or a combination of these or other power sources. In some embodiments, the second source of electric power 150 may be an RF bias power.

[0027] The lid assembly 106 and substrate support 104 of Figure 1 may be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber 100 may afford real-time control of plasma conditions in the processing volume 120. The substrate 103 may be disposed on the substrate support 104, and process gases may be flowed through the lid assembly 106 using an inlet 114 according to any desired flow plan. Gases may exit the processing chamber 100 through an outlet 152.

[0028] In some embodiments, electric power may be coupled with the gas distributor 112 to establish a plasma in the processing volume 120. In some embodiments, a plasma is established using an inductive coil (not shown) surrounding the chamber body 102 or a lower portion of the lid assembly 106. In other embodiments, the processing chamber 100 may alternately, or additionally, include a remote plasma source 116, such as an inductively coupled plasma (ICP) source or a microwave plasma source, that is configured to form a plasma. The substrate may be subjected to an electrical bias using the third electrode 124 in some embodiments.

[0029] Upon energizing a plasma in the processing volume 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. The electronic controllers 134, 140 may then be used to adjust the flow properties of the ground paths represented by the two tuning circuits 128 and 136. A set point may be delivered to the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of deposition rate and of plasma density uniformity from center to edge. In embodiments where the electronic controllers may both be variable capacitors, the electronic sensors may adjust the variable capacitors to maximize deposition rate and minimize thickness non-uniformity independently.

[0030] Each of the tuning circuits 128, 136 may have a variable impedance that may be adjusted using the respective electronic controllers 134, 140. Where the electronic controllers 134, 140 are variable capacitors, the capacitance range of each of the variable capacitors, and the inductances of the first inductor 132A and the second inductor 132B, may be chosen to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum in the capacitance range of each variable capacitor. Hence, when the capacitance of the first electronic controller 134 is at a minimum or maximum, impedance of the first tuning circuit 128 may be high, resulting in a plasma shape that has a minimum aerial or lateral coverage over the substrate support. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may grow to a maximum, effectively covering the entire working area of the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and aerial coverage of the substrate support may decline. The second electronic controller 140 may have a similar effect, increasing and decreasing aerial coverage of the plasma over the substrate support as the capacitance of the second electronic controller 140 may be changed.

[0031] The electronic sensors 130, 138 may be used to tune the respective circuits 128, 136 in a closed loop. A set point for current or voltage, depending on the type of sensor used, may be installed in each sensor, and the sensor may be provided with control software that determines an adjustment to each respective electronic controller 134, 140 to minimize deviation from the set point. Consequently, a plasma shape may be selected and dynamically controlled during processing. It is to be understood that, while the foregoing discussion is based on electronic controllers 134, 140, which may be variable capacitors, any electronic component with adjustable characteristic may be used to provide tuning circuits 128 and 136 with adjustable impedance.

[0032] Figure 2 is a schematic cross-sectional view of an integrated circuit 200, according to one or more embodiments of the present disclosure. The integrated circuit 200 includes a substrate 202 and devices 214 formed within the substrate 202. While only three devices 214 are shown any number of devices 214 may be formed in the substrate 202. An inter-layer dielectric (ILD) layer 204 (e.g. an insulating layer) is disposed over the substrate 202. Electrical contacts 216 are disposed through the ILD layer 204 and connect the devices 214 to the conductive features 212 of the first metal interconnect layer 206. A circuit 218 includes a plurality of metal interconnect layers 206 interposed between a plurality of inter metal dielectric layers (IMDL) 208. In at least some embodiments, the metal interconnect layers 206 are embedded within the IMDL 208. While only three metal interconnect layers 206 and two IMDL 208 are shown, it is contemplated that the integrated circuit 200 may include any number of metal interconnect layers 206 interposed between IMDL 208, such as two or more metal interconnect layers, five or more metal interconnect layers, ten or more metal interconnect layers, sixteen or more metal interconnect layers, or twenty or more metal interconnect layers. Vias 210 are disposed through the IMDL 208 and connect the conductive features 212 of different metal interconnect layers 206. During operation, the circuit 218, including the vias 210, generate heat, which dissipates through the IMDL 208.

[0033] In some embodiments, which can be combined with other embodiments, the IMDL 208 is a hexagonal boron nitride (hBN) film formedusing the methods described herein. The hBN film may have a thickness of about 25 nm to about 5 pm such as about 25 nm to about 1 pm, about 100 nm to about 1 pm, about 500 nm to about 1 pm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, or about 100 nm. In at least some embodiments, the hBN film may have a thickness of about 1 pm or greater, such as about 1 pm to about 5 pm, about 1 pm to about 3 pm, or about 1 pm to about 2 pm. The hBN film may be characterized by a dielectric constant of less than or about 5.0, and may be less than or about 4.5, less than or about 4, less than or about 3.9, less than or about 3.8, less than or about 3.75, less than or about 3.7, less than or about 3.6, less than or about 3.5, less than or about 3.4, less than or about 3.3, less than or about 3.25, less than or about 3.2, less than or about 3.1, less than or about 3.0, or less. The hBN film may have a specific conductivity of about 10 W / (mK) to about 150 W / (mK) or greater, such as about 10 W / (mK) to about 700 W / (mK), about 10 W / (mK) to about 500 W / (mK), about 10 W / (mK) to about 250 W / (mK), about 10 W / (mK) to about 150 W / (mK), about 10 W / (mK) to about 75 W / (mK), about 10 W / (mK) to about 50 W / (mK), about 10 W / (mK) to about 25 W / (mK), about 10 W / (mK) to about 20 W / (mK), about 15 W / (mK) to about 20 W / (mK), or about 18 W / (mK). In some embodiments, the hBN film may have a specific conductivity of about 20 W / (mK) or greater, about 50 W / (mK) or greater, about 100 W / (mK) or greater, about 150 W / (mK) or greater, about 200 W / (mK) or greater, or about 500 W / (mK) or greater. When measured at 4 MV / cm, the hBN film may have a may have a leakage of about 2E’5A / cm2or less.

[0034] Figure 3A is a schematic cross-sectional view of a monolithic 3D integrated circuit 300A, according to one or more embodiments of the present disclosure. The 3D integrated circuit 300A includes a substrate 202 and a plurality of circuits 218 interposed between a plurality of ILD layers 204. While only two circuits 218 and two ILD layers 204 are shown, it is contemplated that the 3D integrated circuit 300A may include any number of circuits 218 interposed between ILD layers 204, such as two or more circuits, five or more circuits, ten or more circuits, sixteen or more circuits, or twenty or more circuits. Each of the circuits 218 include a plurality of conductive features 212 formed in the IMDL 208 as detailed in Figure 1. The circuits 218 are connected by internalvias 302 that are disposed through the ILD layer 204. During operation, the circuits 218 and internal vias 320 generate heat, which dissipates through the IMDL 208.

[0035] Figure 3B is a schematic cross-sectional view of a stacked 3D integrated circuit 300B, according to one or more embodiments of the present disclosure. The 3D integrated circuit 300B includes a bonding layer 304 interposed between a plurality of semiconductor chips 306. While only two semiconductor chips 306 are shown it is contemplated that the stacked 3D integrated circuit 300B may include any number of semiconductor chips 306 with a bonding layer 304 therebetween, such as two or more, five or more, ten or more, sixteen or more, or twenty or more. The first semiconductor chip 308 includes a substrate 202 and a circuit 218. In at least some embodiments, the substrate 202 may be a silicon wafer. The bonding layer 304 is disposed, at least partially, on the metal interconnect layer 206 of the circuit 218 of the first semiconductor chip 308. The dielectric substrate 310 of the second semiconductor chip 312 is disposed on the bonding layer 304. In one or more embodiments, the dielectric substrate 310 is a silicon substrate. The circuits 218 of the first and second semiconductor chips 308 and 312 are connected by through silicon vias 314 that are disposed through the dielectric substrate 310 and the bonding layer 304.

[0036] In some embodiments, which can be combined with other embodiments, the bonding layer 304 is an hBN film formed using the methods described herein. The hBN film may have a thickness of about 5.0 nm to about 3.5 pm, such as about 10 nm to about 3.5 pm, about 10 nm to about 2.5 pm, about 10 nm to about 1.0 pm, about 1.0 pm to about 3.0 pm, about 1.5 pm to about 2.5 pm, or about 2.5 pm. The hBN film may be characterized by a dielectric constant of less than or about 4.0, and may be less than or about 3.95, less than or about 3.9, less than or about 3.8, less than or about 3.75, less than or about 3.7, less than or about 3.6, less than or about 3.5, less than or about 3.4, less than or about 3.3, less than or about 3.25, less than or about 3.2, less than or about 3.1, less than or about 3.0, or less. The hBN film may have a specific conductivity of about 10 W / (mK) to about 150 W / (mK) or greater,such as about 10 W / (mK) to about 700 W / (mK), about 10 W / (mK) to about 500 W / (mK), about 10 W / (mK) to about 250 W / (mK), about 10 W / (mK) to about 150 W / (mK), about 10 W / (mK) to about 20 W / (mK), about 15 W / (mK) to about 20 W / (mK), or about 18 W / (mK). In some embodiments, the hBN film may have a specific conductivity of about 20 W / (mK) or greater, about 50 W / (mK) or greater, about 100 W / (mK) or greater, about 150 W / (mK) or greater, about 200 W / (mK) or greater, or about 500 W / (mK) or greater. When measured at 4 MV / cm the hBN film may have a may have a leakage of about 2E’5A / cm2. The hBN film may have a bonding strength of about 2.0 J / m2or greater, such as about 2.1 J / m2to about 10 J / m2, about 4 J / m2to about 10 J / m2, about 4.0 J / m2or greater, about 8.0 J / m2or greater, about 10.0 J / m2or greater, or about 15.0 J / m2or greater.

[0037] Figure 4 is a flow diagram of a method 400 for forming an hBN film, according to one or more embodiments. The method 400 may be performed in any suitable process chamber, such as the process chamber 100 depicted in Figure 1. In some embodiments, the resulting hBN film may be an IMDL such as the IMDL 208 depicted in Figures 2-3 or a bonding layer such as the bonding layer 304 depicted in Figure 3B. While the method 400 is described in reference to the embodiments depicted in Figures 2 and 3, it is envisioned that the resultant hBN film may be used in other embodiments or combinations of embodiments that require a layer or film having high thermal conductivity and a dielectric constant of less than about 5.0.

[0038] One or more operations may be performed prior to the initiation of the method 400, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations.

[0039] Operation 402 includes providing a substrate into a processing chamber. The substrate is positioned on a support that is positioned at a predetermined distance from a gas distributor. In various embodiments, the predetermined distance can be about 200 mil to about 600 mil, such as about 400 mil.

[0040] Operation 404 includes depositing a layer of material onto the substrate. In one or more embodiments, a PECVD process is employed to deposit an hBN film. The deposited hBN film may have a hexagonal structure, a partially hexagonal structure, a partially amorphous structure, a partially cubic structure, or combinations thereof. In various embodiments, depositing the hBN film includes: flowing one or more precursor gases into the processing chamber, forming a plasma from the one or more precursor gases, and operating the processing chamber at a temperature of about 150 °C to about 550 °C, and a pressure of about 1 Torr to about 10 Torr for about 10 seconds (s), to deposit an hBN film having a thickness of about 0.5 angstroms to about 10 angstroms.

[0041] In at least some embodiments, which can be combined with other embodiments, the one or more precursor gases may include B2H6, nitrogen (N2), argon (Ar), and optionally hydrogen (H2). In some embodiments, the flow rate ratio of N2 to B2H6 may be greater than or about 100:1, such as greater than or about 200:1 , greater than or about 300:1 , greater than or about 400:1 , greater than or about 500:1 , greater than or about 600:1 , greater than or about 700: 1 , greater than or about 800: 1 , greater than or about 900: 1 , greater than or about 1 ,000: 1 , or higher. N2 may be provided into the processing chamber at a flow rate of greater than or about 500 seem, such as a rate of greater than or about 750 seem, greater than or about 1 ,000 seem, greater than or about 1 ,250 seem, greater than or about 1,500 seem, greater than or about 1,750 seem, greater than or about 2,000 seem, or higher. In some embodiments, the flow rate ratio of Ar to B2H6 may be greater than or about 50: 1 , such as greater than or about 100:1, greater than or about 200:1, greater than or about 250:1, greater than or about 300: 1 , greater than or about 400: 1 , or higher. Ar may be provided into the processing chamber at a flow rate of greater than or about 100 seem, such as a rate of greater than or about 200 seem, greater than or about 300 seem, greater than or about 400 seem, greater than or about 500 seem, or higher. In at least some embodiments, B2Hemay be provided at a low flow rate, such as a flow rate of about 10 seem or less and / or a flow rate ratio of B2H6 to any other of the one or more precursor gases of about 1 : 100 or less.

[0042] In at least some embodiments, H2 is optionally provided as one of the one or more precursor gases. In some embodiments, the flow rate ratio of H2 to B2H6 may be greater than or about 100:1, such as greater than or about 200: 1 , greater than or about 300: 1 , greater than or about 400: 1 , greater than or about 500:1 , greater than or about 600:1 , greater than or about 700:1 , greater than or about 800: 1 , greater than or about 900: 1 , greater than or about 1 ,000: 1 , or higher. H2 may be provided into the processing chamber at a flow rate of greater than or about 500 seem, such as a rate of greater than or about 750 seem, greater than or about 1,000 seem, greater than or about 1,250 seem, greater than or about 1,500 seem, greater than or about 1,750 seem, greater than or about 2,000 seem, or higher.

[0043] In at least some embodiments, operation 404 may be performed at substrate or substrate support temperatures of about 150 °C to about 550 °C. In some embodiments, the deposition may occur at temperatures of about 150 °C to about 500 °C, such as about 150 °C to about 400 °C, about 200 °C to about 400 °C, about 200 °C to about 350 °C, about 300 °C to about 500 °C, or about 250 °C to about 400 °C. In at least one embodiment, the deposition may occur at temperatures of less than or about 400 °C. The deposition may occur at pressures of about 1 Torr to about 10 Torr, such as less than or about 10 Torr, less than or about 9 Torr, less than or about 8 Torr, less than or about 7 Torr, less than or about 6 Torr, less than or about 5 Torr, less than or about 4 Torr, less than or about 3 Torr, less than about 2 Torr, or lower.

[0044] In at least some embodiments, the plasma may be generated using one or more plasma sources. Plasma sources may include but are not limited to a capacitively coupled plasma (CCP) source, a microwave plasma source, a remote ICP source, or combinations thereof. In some embodiments, which can be combined with other embodiments, a first plasma power may be used to generate and maintain the plasma. The first plasma power may be supplied by an RF generator, a high frequency RF (HFRF) power source, a pulsed RF power source, a low frequency RF (LFRF) power source, or combinations thereof. In at least some embodiments, the first plasma power used is a low plasma power, such as about 400 W or less. For example, in at least oneembodiment, the first plasma power used to generate a plasma is a HFRF power of about 150 W to about 400 W, such as about 200 W to about 400 W, about 250 W to about 350 W, 250 W to about 300 W, or about 250 W.

[0045] Operation 406 includes, treating the deposited material. In various embodiments, treating the deposited hBN film includes: flowing one or more gases into the processing chamber, forming a plasma from the one or more gases, and operating the processing chamber at a temperature of about 150 degrees Celsius to about 550 degrees Celsius, and a pressure of about 1 Torr to about 10 Torr for a predetermined amount of time, such as about 10 s.

[0046] In at least some embodiments, the one or more gases may include N2, Ar, and optionally H2. N2 may be provided into the processing chamber at a flow rate of greater than or about 500 seem, such as a rate of greater than or about 750 seem, greater than or about 1 ,000 seem, greater than or about 1 ,250 seem, greater than or about 1,500 seem, greater than or about 1,750 seem, greater than or about 2,000 seem, or higher. Ar may be provided into the processing chamber at a flow rate of greater than or about 100 seem, such as a rate of greater than or about 200 seem, greater than or about 300 seem, greater than or about 400 seem, greater than or about 500 seem, or higher. H2 may optionally be provided into the processing chamber at a flow rate of greater than or about 500 seem, such as a rate of greater than or about 750 seem, greater than or about 1,000 seem, greater than or about 1,250 seem, greater than or about 1,500 seem, greater than or about 1,750 seem, greater than or about 2,000 seem, or higher.

[0047] In at least some embodiments, the plasma may be generated using one or more plasma sources. Plasma sources may include but are not limited to a CCP source, a microwave plasma source, a remote ICP source, or combinations thereof. In some embodiments, the plasma source used in operation 406 is the same as the plasma source used in operation 404. In other embodiments, the plasma source used in operation 406 is different from the plasma source used in operation 404. In some embodiments, which can be combined with other embodiments, a second plasma power may be used to generate and maintain the plasma. In at least some embodiments, the secondplasma power used in operation 406 is higher than the first plasma power used in operation 404. In other embodiments, the second plasma power may be supplied by a different power source. In some embodiments, which can be combined with other embodiments, the second plasma power used to generate and maintain the plasma may be supplied by an RF generator, a high frequency RF (HFRF) power source, a pulsed RF power source, a low frequency RF (LFRF) power source, or combinations thereof. For example, in at least one embodiment, the second plasma power used to generate a plasma is a HFRF power of about 600 W to about 1 ,000 W, such as about 600 W to about 900 W, about 650 W to about 800 W, about 650 W to about 750 W, or about 700 W.

[0048] In at least some embodiments, operation 406 may be performed at substrate or substrate support temperatures of about 150 °C to about 550 °C. In some embodiments the treatment may occur at temperatures of about 150 °C to about 500 °C, such as about 150 °C to about 400 °C, about 200 °C to about 400 °C, about 200 °C to about 350 °C, about 300 °C to about 500 °C, or about 250 °C to about 400 °C. In at least one embodiment, the treatment may occur at temperatures of less than or about 400 °C. The treatment may occur at pressures of about 1 Torr to about 10 Torr, such as less than or about 10 Torr, less than or about 9 Torr, less than or about 8 Torr, less than or about 7 Torr, less than or about 6 Torr, less than or about 5 Torr, less than or about 4 Torr, less than or about 3 Torr, less than about 2 Torr, or lower. In at least one embodiment, the temperature and pressure during operation 406 are the same as the temperature and pressure during operation 404. In other embodiments, the temperature and pressure during operation 406 are different from the temperature and pressure during operation 404.

[0049] In one or more embodiments, which can be combined with other embodiments, operation 404 and 406 may be performed as a cyclic process, such that a first cycle includes a first deposition operation followed by a first treatment operation, a second cycle includes second deposition operation followed by a second treatment operation, a third cycle includes third deposition operation followed by a third treatment operation, and so on. Any number of cycles may be performed to reach the desired thickness of the hBN film. In oneor more embodiments, each deposition operation 404, deposits a layer of material having a thickness of about 0.5 angstroms to about 20 angstroms, such as about 0.5 angstroms to about 15 angstroms, about 0.5 angstroms to about 10 angstroms, about 2 angstroms to about 10 angstroms, or about 5 angstroms to about 10 angstroms. In at least one embodiment, the final hBN film is an IMDL, such as the IMDL 208, with a thickness of about 25 nm to about 5 pm. In at least one embodiment, the final hBN film is a bonding layer such as the bonding layer 304, with a thickness of about 5.0 nm to about 3.5 pm.

[0050] In at least one embodiment, of depositing and treating the hBN film, B2H6 and N2 are flowed at a ratio of N2 / B2H6 of about 1 ,000:1 , H2 is flowed at a ratio of H2 / B2H6 of about 1,000:1, and Ar is flowed at a ratio of Ar I B2H6 of about 250:1 into the processing chamber. The processing chamber is then operated at a temperature of about 350 °C, a pressure of about 6 Torr, and a HFRF power of about 250 W for about 10 s. The resulting film is then treated by flowing N2, H2, and Ar with a ratio of N2:H2:Ar of about 4:4:1 into the processing chamber. The processing chamber is operated a temperature of about 350 °C, a pressure of about 6 Torr, and a HFRF power of about 700 W for about 10 s.

[0051] In some embodiments, which can be combined with other embodiments, the lamella orientation and crystallinity of the hBN film may be tuned to achieve the desired hBN film characteristics by precisely controlling the deposition and treatment conditions. In some embodiments, hBN films with a highly ordered hexagonal structure may be deposited in operation 404 using a low flowrate of the precursor gas B2H6 and a low plasma power, which may slow the deposition rate of the layer of material resulting in a more uniformed structure with less defects within the layer of material. In at least some embodiments, a low flowrate of the precursor gas B2H6 may be a flow rate of about 10 seem or less and / or a flow rate ratio of B2H6 to any other of the one or more precursor gases of about 1:100 or less. A low plasma power may be a power of about 400 W or less, such as a power of about 200 W to about 400 W. Increasing the plasma power during operation 406 may densify and realign the hBN film to improve the mechanical strength of the layer of material on thesubstrate. At operation 406, some portions of the layer of material on the substrate may transition from an amorphous or cubic structure to a hexagonal structure, such that the layer of material may be characterized as a well-oriented layered structure of hexagonal boron nitride. With the material being realigned, the material may be more ordered, with fewer defects, and may reduce or eliminate diffusion of atoms or molecules through the layer.

[0052] In at least some embodiments, the lamella orientation may affect the dielectric properties, thermal conductivity properties, and stress of the deposited hBN films. The hBN films described herein are isotropic structures formed from 2D sheets disposed on a substrate. When the film is grown vertically (e.g., forming vertically aligned lamella), the volume change of the film happens predominantly out of plane, producing little to no stress on the substrate. By contrast, when the film is grown horizontally (e.g., forming horizontally aligned lamella), the volume change of the film is horizontal or in the same plane as the substrate, which produces a significant amount stress on the substrate. In some embodiments, the stress associated with forming horizontally aligned lamella may be reduced by adjusting the methods described herein, such as depositing a small amount of material non-continuously during operation 404. The empty space within the plane allows the hBN film to grow during the treatment operation 406 without adding stress or straining the substrate. In at least some embodiments, an hBN film with vertically aligned lamella may have a higher thermal conductivity than a disordered hBN film or an hBN film with horizontally aligned lamella.

[0053] In at least some embodiments, which can be combined with other embodiments, the lamella orientation may be tuned by altering or tuning the flow of H2, the plasma power, and / or treatment time during the treatment operation 406. As a non-limiting example, in some embodiments, vertically aligned, lamella may be formed using a high plasma power and a high H2 flowrate during the treatment operation. In contrast, in some embodiments, horizontally aligned, lamella may be formed using a moderate plasma power and a low H2 flowrate during the treatment operation.

[0054] In some embodiments, vertically aligned lamella may be preferentially formed by using a high plasma power of about 400 W to about 1400 W during the treatment operation 406, such as a plasma power of about 400 W to about 1200 W, about 500 W to about 1000 W, about 600 W to about 800 W, about 600 W to about 1200 W, or about 800 W to about 1200 W. In some embodiments, vertically aligned lamella may be preferentially formed by using a high H2 flow rate of about 1 ,000 seem to about 4,000 seem during the treatment operation 406, such as a H2 flow rate of about 1 ,000 seem to about 3,500 seem, about 1 ,000 seem to about 3,000 seem, about 1 ,000 seem to about 2,000 seem, or about 2,000 seem to about 4,000 seem. In some embodiments, vertically aligned lamella may be preferentially formed by using a Ar flow rate of about 500 seem to about 5,000 seem during the treatment operation 406, such as a Ar flow rate of about 500 seem to about 4,000 seem, about 500 seem to about 3,000 seem, about 1,000 seem to about 3,000 seem, or about 2,000 seem to about 5,000 seem. In at least one embodiment, which can be combined with other embodiments, vertically aligned lamella may be formed by treating an hBN film deposited using the methods described in operation 404. The treatment may include flowing H2 at a flow rate of about 1,000 seem to about 4,000 seem and Ar at a flow rate of about 500 seem to about 5,000 seem into a processing chamber and operating the processing chamber at a temperature of about 350 °C, a pressure of about 6 Torr, and a HFRF power of about 400 W to about 1 ,400 W for about 10 s. In at least one embodiment, the treatment includes, flowing H2 at a flow rate of about 2,000 seem and Ar at a flow rate of about 500 seem into a processing chamber and operating the processing chamber at a temperature of about 350 °C, a pressure of about 6 Torr, and a HFRF power of about 700 W for about 10 s.

[0055] In some embodiments, horizontally aligned lamella may be preferentially formed by using a moderate plasma power of about 300 W to about 700 W during the treatment operation 406, such as a plasma power of about 300 W to about 650 W, about 350 W to about 600 W, about 350 W to about 500 W, about 400 W to about 600 W, or about 400 W to about 500 W. In some embodiments, horizontally aligned lamella may be preferentially formed by using a low H2 flow rate of about 0 seem to about 500 seem during thetreatment operation 406, such as a H2 flow rate of about 0.1 seem to about 500 seem, about 1 seem to about 450 seem, about 1 seem to about 400 seem, or about 1 seem to about 200 seem. In some embodiments, horizontally aligned lamella may be preferentially formed by using an Ar flow rate of about 0 seem to about 1,000 seem during the treatment operation 406, such as an Ar flow rate of about 0.1 seem to about 1 ,000 seem, about 1 seem to about 900 seem, about 1 seem to about 700 seem, or about 1 seem to about 500 seem. In at least one embodiment, which can be combined with other embodiments, horizontally aligned lamella may be formed by treating an hBN film deposited using the methods described in operation 404. The treatment may include flowing H2 at a flow rate of about 0 seem to about 500 seem and Ar at a flow rate of about 0 seem to about 1,000 seem into a processing chamber and operating the processing chamber at a temperature of about 350 °C, a pressure of about 6 Torr, and a HFRF power of about 300 W to about 700 W for about 10 s. In at least one embodiment, the treatment includes, flowing H2 at a flow rate of about 0 seem and Ar at a flow rate of about 500 seem into a processing chamber and operating the processing chamber at a temperature of about 350 °C, a pressure of about 6 Torr, and a HFRF power of about 700 W for about 10 s.

[0056] In at least some embodiments, a randomized mixture of vertically and horizontally aligned lamella may be formed. As a non-limiting example, a random lamella orientation may be formed when a plasma power of about 100 W to about 700 W, a H2 flow rate of about 500 seem to about 1 ,000 seem, and an Ar flow rate of about 0 seem to about 5,000 seem are used during the treatment operation 406. As such, precise control of both the treatment plasma power and H2 flow rate is necessary to reliably produce the target lamella orientation.

[0057] In at least some embodiments, the final hNB film includes vertically aligned lamella, horizontally aligned lamella, or combinations thereof. In at least one embodiment, the final hBN film includes alternating domains of both vertically aligned lamella and horizontally aligned lamella. In at least one embodiment, the final hBN film may be an IMDL such as the IMDL 208 or a bonding layer such as the bonding layer 304 having vertically aligned lamella.

[0058] In at least some embodiments, the crystallinity of the hBN film may be improved by adjusting the plasma conditions or plasma source during the deposition operation 404 and / or the treatment operation 406. Improving the crystallinity includes reducing the amorphous phase in the hBN film and increasing the crystal domain size. Without being bound by theory, it is believed that increasing the crystallinity of the hBN film also increases the films thermal conductivity. However, films with high crystallinity may also substantially stress the substrate leading to an overall less efficient semiconductor. Thus, there is a need to carefully tune the characteristics of the hBN film to achieve the desired thermal conductivity while minimizing the stress placed on the substrate.

[0059] In at least some embodiments, the hBN film may have a stress of about -150 MPa to about 2,500 MPa, such as about -100 MPa to about 2,000 MPa, -100 MPa to about 1 ,000 MPa, -100 MPa to about 500 MPa, or -10 MPa to about 100 MPa. In at least some embodiments, the hBN film may have a positive stress of about 1 MPa to about 2,500 MPa, such as about 100 MPa to about 2,500 MPa, about 200 MPa to about 2,000 MPa, about 100 MPa to about 1 ,000 MPa, about 1 MPa to about 100 MPa, about 1 MPa to about 75 MPa, or about 10 MPa to about 50 MPa. In at least some embodiments, the hBN film may have a negative stress of about -150 MPa to about -1 MPa, such as about -150 MPa to about -5 MPa, about -150 MPa to about -10 MPa, about -150 MPa to about -20 MPa, about -150 MPa to about -50 MPa, or about -150 MPa to about -100 MPa. In at least some embodiments, the hBN film may have a crystallinity of about 100%. The percent crystallinity of the disclosed films may be measured using X-ray crystallography. In at least some embodiments, the hBN film may have a crystal size of about 5 nm to about 200 nm, such as about 5 nm to about 175 nm, about 10 nm to about 150 nm, about 20 nm to about 125 nm, about 20 nm to about 100 nm, or about 5 nm to about 50 nm. In other embodiments, the hBN film has a crystal size of about 3 nm to about 10 nm, such as about 4 nm, about 5 nm, about 6 nm, about 7 nm, about 8 nm, or about 9 nm.

[0060] In at least some embodiments, the crystallinity of the hBN film may be improved by tuning the plasma during the deposition operation 404 and / or the treatment operation 406. A bias may be applied during operation 404 and / or operation 406 using RF pulsing or LFRF to increase crystallinity. In at least one embodiment, which can be combined with other embodiments, the bias may be applied using an RF pulse with a frequency of about 500 Hz to about 5,000 Hz and a duty cycle of about 30% to about 90%. The frequency may be about 750 Hz to about 5,000 Hz, about 1,000 Hz to about 5,000 Hz, about 2,000 Hz to about 5,000 Hz, about 3,000 Hz to about 5,000 Hz, or about 500 Hz to about 3,000 Hz. The duty cycle may be about 35% to about 90%, about 35% to about 80%, about 40% to about 70%, about 50% to about 90%, or about 50% to about 70%. In another embodiment, which can be combined with other embodiments, the bias may be applied using a low frequency RF of less than or about 2 MHz, such as less than or about 1.75 MHz, less than or about 1.5 MHz, less than or about 1.25 MHz, less than or about 1 MHz, less than or about 0.75 MHz, less than or about 0.5 MHz, or less than or about 0.25 MHz.

[0061] Without being bound by theory, it is believed that the crystallinity of the film may be increased by slowing the deposition of the hBN film. As such, applying a bias with lower frequencies and lower duty cycles may result in a film with higher crystallinity. In at least some embodiments, decreasing the duty cycle of an RF pulse increases the randomness of the lamella orientation and decreases the roughness of the resulting hBN film. In at least some embodiments, increasing the duty cycle of an RF pulse increases the deposition rate of the hBN film. In at least some embodiments, increasing the low frequency RF bias increases the deposition rate and increases the roughness of the resulting hBN film. In at least some embodiments, altering the low frequency RF bias had little to no influence on the lamella orientation or crystal size of the resulting hBN film.

[0062] In at least some embodiments, the crystallinity of the hBN film may be tuned using a different plasma sources during the deposition operation 404 and / or the treatment operation 406. Plasma sources may include but are not limited to CCP sources, microwave sources, remote ICP sources, orcombinations thereof. In one or more embodiments, a microwave source or a remote ICP source may be used to form an hBN film having a large crystal domain. As a non-limiting example, in at least one embodiment, an hBN film produced using a microwave plasma source had a larger crystal domain than an hBN film produced using a CCP source when the processing conditions were otherwise similar. In one or more embodiments, one plasma source is used during the deposition operation 404 and a different plasma source is used during the treatment operation 406. The use of different plasma sources in operations 404 and 406 allows for the precise control of ion and radical bombardment. For example, in at least one embodiment, a remote ICP source may be used during operation 406 to form a plasma containing more radicals then ions.

[0063] Overall, the present disclosure provides methods and apparatuses to tune the thermal conductive and dielectric properties of hBN films, which may be used as inter metal dielectric layers or bonding layers in 3D integrated circuit. Methods disclosed herein generally include a cyclic deposition and treatment process that produces highly ordered hexagonal boron nitride films. The lamella orientation of the hBN films may be tuned by adjusting the flow of H2, the plasma power, and / or treatment time during the treatment operation. The crystallinity of the hBN films may be improved by adjusting the plasma conditions or plasma source during the deposition and / or the treatment. The methods disclosed herein may be used to carefully tune the characteristics of the hBN film to achieve the desired film thermal conductivity while minimizing the stress placed on the substrate.

[0064] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof. The present disclosure also contemplates that one or more aspects of the embodiments described herein may be substituted in for one or more of the other aspects described. The scope of the disclosure is determined by the claims that follow.

[0065] Certain embodiments and features have been described using a set of numerical upper limits and a set of numerical lower limits. It should beappreciated that ranges including the combination of any two values, e.g., the combination of any lower value with any upper value, the combination of any two lower values, and / or the combination of any two upper values are contemplated unless otherwise indicated. Certain lower limits, upper limits and ranges appear in one or more claims below.

Claims

What is claimed is:

1. A three-dimensional (3D) integrated circuit comprising:at least one inter metal dielectric layer disposed between two metal interconnect layers, the inter metal dielectric layer comprising;a hexagonal boron nitride film having a dielectric constant of about 5.0 or less and a specific conductivity of about 10 W / (mK) or greater; anda via disposed through the hexagonal boron nitride film, electrically connecting the two metal interconnect layers.

2. The 3D integrated circuit of claim 1 , wherein the hexagonal boron nitride film has a thickness of about 25 nm to about 1 pm.

3. The 3D integrated circuit of claim 1 , wherein the hexagonal boron nitride film has a leakage of about 2E’5A / cm2or less when measured at 4 MV / cm.

4. A 3D stacked chip comprising:two or more semiconductor chips;a bonding layer disposed between two of the two or more semiconductor chips, the bonding layer comprising a hexagonal boron nitride film having a dielectric constant of about 5.0 or less and a specific conductivity of about 10 W / (mK) or greater; anda through silicon via disposed through the bonding layer and at least a portion of one of the two or more semiconductor chips, the through silicon via electrically connecting at least two of the two or more semiconductor chips.

5. The 3D stacked chip of claim 4, wherein the hexagonal boron nitride film has a thickness of about 0.5 pm to about 3.5 pm.

6. The 3D stacked chip of claim 4, wherein the bonding layer is disposed between a metal interconnect layer of a first semiconductor chip of the two or more semiconductor chips and a dielectric substrate of a second semiconductor chip of the two or more semiconductor chips.

7. A method for modifying film characteristics comprising:positioning a substrate on a substrate support disposed within a processing chamber;depositing a hexagonal boron nitride (hBN) film, comprising:flowing a first one or more gases into the processing chamber; supplying a first plasma power from a first plasma source to form a first plasma from the first one or more gases; anddepositing the hBN film on the substrate with the first plasma; and treating the deposited hBN film, treating the hBN film comprising:flowing a second one or more gases into the processing chamber; supplying a second plasma power from a second plasma source to form a second plasma from the second one or more gases;tuning the second plasma to adjust a lamella orientation of the deposited hBN film comprising one or more of:forming horizontal lamella with an RF second plasma power of about 300 W to about 700 W and a H2 flow rate of about 0 seem to about 500 seem; andforming vertical lamella with an RF second plasma power of about 400 W to about 1 ,400 W and a H2 flow rate of about 1 ,000 seem to about 4,000 seem.

8. The method of claim 7, wherein the first one or more gases comprise one or more of B2H6, nitrogen, argon, or hydrogen.

9. The method of claim 7, wherein the second one or more gases comprise one or more of nitrogen, argon, or hydrogen.

10. The method of claim 7, further comprising treating the deposited hBN film with the second plasma for a predetermined amount of time to form a treated hBN film.

11. The method of claim 7, wherein the temperature of the substrate or the substrate support is about 150 °C to about 400 °C while depositing and treating the hexagonal boron nitride film.

12. The method of claim 7, wherein the first plasma source and the second plasma source are selected from the group consisting of a capacitively coupled plasma (CCP) source, a microwave source, a remote inductively coupled plasma (ICP) source, or combinations thereof.

13. The method of claim 12, wherein the first plasma source and the second plasma source are the same type of plasma source.

14. The method of claim 12, wherein the first plasma source and the second plasma source are different types of plasma sources.

15. The method of claim 7, wherein the second plasma source is a microwave source.

16. The method of claim 7, further comprising applying a bias while depositing the hexagonal boron nitride film or while treating the hexagonal boron nitride film.

17. The method of claim 16, wherein the bias is applied using an RF pulse with a frequency of about 500 Hz to about 5,000 Hz and a duty cycle of about 30% to about 90%.

18. The method of claim 16, wherein the bias is applied using a low frequency RF of about 2 MHz or less.

19. The method of claim 10, wherein the treated hBN film has a dielectric constant of about 5.0 or less and a specific conductivity of about 10 W / (mK) to about 25 W / (mK).

20. The method of claim 10, wherein the treated hBN film comprises vertically aligned lamella.

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