Encoding method, decoding method, and communication apparatus

Abstract

The present application relates to the technical field of communications, and provides an encoding method, a decoding method, and a communication apparatus. The encoding method comprises: determining an i-th information bit position set on the basis of an i-th bit position set and a reliability sequence, wherein i is an integer ranging from 1 to M, and M is an integer greater than 2; and performing polar code encoding on an information bit sequence on the basis of a union set of a first information bit position set to an M-th information bit position set, so as to obtain an encoded bit sequence. M information bit position sets are determined on the basis of M bit position sets, and a union set of the M information bit position sets is used as a final information bit position set. Some bit positions in the final information bit position set are determined in multiple steps, and a bit having the highest reliability is determined as an information bit in each step, thereby facilitating accurate selection of the bits having the highest reliability as information bits, and facilitating improvement of communication performance.

Description

An encoding method, a decoding method, and a communication device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411701791.0, filed on November 25, 2024, with the State Intellectual Property Office of the People's Republic of China, entitled "An Encoding Method, Decoding Method and Communication Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, and a communication device. Background Technology

[0004] In recent years, with the inclusion of polar codes in the 5th generation (5G) wireless communication standard, the design and construction of polar codes has become a hot topic in communication research. For example, when the number of bits in the encoded bit sequence (denoted by E) is not the same as the code length (denoted by N), rate matching needs to be introduced to adapt to the requirements of flexible code length. The code length can also be called the mother code length.

[0005] The introduction of rate matching may cause changes in the reliability order of information bits, resulting in the constructed coded bit sequence not achieving optimal performance, thus affecting communication quality. Summary of the Invention

[0006] This application provides an encoding method, a decoding method, and a communication device to improve communication quality.

[0007] Firstly, embodiments of this application provide an encoding method that can be applied to a first device. For example, the executing entity may be the first device, a component within the first device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the first device. For example, the first device may be a network device, a terminal device, or other device; this application does not limit the specific form of the first device. The execution is as follows:

[0008] Based on the set of i-th bit positions and the reliability sequence, determine the set of i-th information bit positions, where the set of i-th bit positions is used to indicate the frozen bits in the reliability sequence when determining the set of i-th information bit positions, i is an integer from 1 to M, and M is an integer greater than 2; based on the target set of information bit positions, encode the information bit sequence using polar codes to obtain the encoded bit sequence, where the target set of information bit positions is the union of the set of 1-th to the set of M-th information bit positions.

[0009] The set of i-th bit positions is also called the set of i-th frozen bit positions or the set of i-th pre-frozen bit positions.

[0010] The above scheme determines M information bit position sets based on M bit position sets, and takes the union of the M information bit position sets as the final information bit position set. Since it determines some bit positions in the final information bit position set in multiple steps, and each time it selects the bit with the highest reliability as the information bit, it helps to accurately select the bit with the highest reliability as the information bit, which can improve encoding and decoding performance (such as error correction performance), and thus help improve communication performance.

[0011] Secondly, embodiments of this application provide a decoding method that can be applied to a second device. For example, the executing entity may be the second device, a component within the second device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the second device. For example, the second device may be a network device, a terminal device, or other device; this application does not limit the specific form of the second device. The execution is as follows:

[0012] Based on the set of i-th bit positions and the reliability sequence, determine the set of i-th information bit positions, where the set of i-th bit positions is used to indicate the frozen bits in the reliability sequence when determining the set of i-th information bit positions, i is an integer from 1 to M, and M is an integer greater than 2; based on the target information bit position set, perform polar code decoding on the encoded bit sequence to obtain the information bit sequence, where the target information bit position set is the union of the set of 1-th information bit positions to the set of M-th information bit positions.

[0013] Based on the first or second aspect, one or more of the following implementation methods can be provided:

[0014] In one possible implementation, when i is greater than 1, the set of (i-1)th bit positions is a proper subset of the set of i-th bit positions.

[0015] The above scheme, because rate matching has a significant impact on the positions of bits with smaller sequence numbers in the reliability sequence, gradually expands the set of bit positions as the number of selected information bits increases. This helps to more accurately pre-freeze the positions of bits with different sequence numbers, thereby improving the reliability of information bits.

[0016] In one possible implementation, the number of bits in the set of the i-th bit positions is associated with at least one of E, N, or K; where E is the number of bits in the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, K is the number of bits in the information bit sequence, and E is less than N.

[0017] The above scheme configures the number of bits in the i-th bit position set based on at least one of E, N, or K. The different number of rate matching bits will affect the configuration of the number of bits in the i-th bit position set.

[0018] In one possible implementation, the set of i-th information bit positions is the T with the highest reliability in the reliability sequence, excluding the set of i-th bit positions and the sets of 1 to (i-1)-th information bit positions. i -T i-1 Each bit position, T i Associated with at least one of M, i, E, N, or K; where E is the number of bits in the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, K is the number of bits in the information bit sequence, T1 = 0, T M =K.

[0019] The above scheme selects the corresponding information bit position set based on different bit position sets, which helps to accurately pre-freeze bit positions of different sequence numbers in the reliability sequence, thereby improving the reliability of information bits.

[0020] In one possible implementation, when E / N≥P, T i Satisfy the following formula:

[0021] in, This indicates rounding up, where P is the preset bit threshold.

[0022] In the above scheme, when the rate matching method is puncturing and the number of punctures is small, the reliability of bit positions is less affected by rate matching. Based on the above formula, T is determined. i This helps in selecting reliable bits as information bits, thereby improving encoding and decoding performance, and ultimately improving communication performance.

[0023] In one possible implementation, when E / N ≥ P, the set of positions of the i-th bit includes the first set whose values ​​are less than N / 2. M+1-i The elements, or elements in the first set whose values ​​are less than NE, or elements in the first set whose values ​​are less than a first value, where the first value is N / 2. M+1-i The maximum value between E and NE, the elements in the first set consist of 0 to N-1; where E is the number of bits in the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, and P is the preset bit threshold.

[0024] The above scheme, when the rate matching method is puncturing and the number of punctures is small, determines the set of positions for the i-th bit based on the above method. Since the values ​​in the first set are less than N / 2... M+1-iThe reliability of the bit positions decreases successively as i increases, which helps to select reliable bit positions as information bit positions, thereby improving the encoding and decoding performance and further contributing to the improvement of communication performance.

[0025] In a possible implementation, E / N < P. When 5 / 8 ≤ E / N, When E / N < 5 / 8, Where, represents rounding up, and P is a preset bit threshold.

[0026] In the above scheme, when the rate matching method is puncturing and the number of punctures is large, determining T1 based on the above method helps to select reliable bit positions as information bit positions, thereby improving the encoding and decoding performance and further contributing to the improvement of communication performance.

[0027] In a possible implementation, E / N < P. When i is greater than 1, T i satisfies the following formula:

[0028] Where, represents rounding up, and P is a preset bit threshold.

[0029] In the above scheme, when the rate matching method is puncturing and the number of punctures is large, the reliability of the bit positions is greatly affected by the rate matching. Determining T i , helps to select reliable bit positions as information bit positions, thereby improving the encoding and decoding performance and further contributing to the improvement of communication performance.

[0030] In a possible implementation, when E / N < P, the first bit position set is the elements in the first set with values less than of the elements, the second bit position set is the elements in the first set with values less than N / 2, and the j-th bit position set includes the elements in the first set with values less than N / 2 + N / 2 M+2-j of the elements. The elements in the first set are composed of 0 to N - 1, 3 ≤ j ≤ M; where, E is the number of bits of the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, P is a preset bit threshold, represents rounding up.

[0031] In the above scheme, when the rate matching method is puncturing and the number of punctures is large, determining the i-th bit position set based on the above method. Since the bit positions in the first set with values less than N / 2 + N / 2 M+2-j have decreasing reliability as j increases, it helps to select reliable bit positions as information bit positions, thereby improving the encoding and decoding performance and further contributing to the improvement of communication performance.

[0032] In one possible implementation, T i Satisfy the following formula:

[0033] in, This indicates rounding up when 9 / 16 <= E / N. When E / N<9 / 16,

[0034] In the above scheme, when the rate matching method is shortened, T is determined based on the above method. i T i As i increases sequentially, it helps to select reliable bits as information bits, thereby improving encoding and decoding performance, and thus helping to improve communication performance.

[0035] In one possible implementation, the set of positions for the first bit is the set of elements in the first set whose values ​​are greater than or equal to E; when i is greater than 1, the set of positions for the i-th bit is the set of elements in the first set whose values ​​are less than N / 2. M+1-i The elements are either E or elements in the first set whose values ​​are greater than or equal to E; the elements in the first set consist of numbers from 0 to N-1; where E is the number of bits in the encoded bit sequence, and N is the encoding length corresponding to the information bit sequence. This indicates rounding up to the nearest integer.

[0036] In the above scheme, when the rate matching method is shortening, the set of positions of the i-th bit is determined based on the above method. Since the values ​​in the first set are less than N / 2 + N / 2... M+1-i The reliability of the bit position decreases as i increases, which helps to select reliable bits as information bits, thereby improving encoding and decoding performance, and thus helping to improve communication performance.

[0037] Thirdly, this application provides a communication device. The communication device has the functions to implement the first or second aspect described above. For example, the communication device includes modules, units, or means corresponding to the steps involved in the first or second aspect. These functions, units, or means can be implemented by software, hardware, or hardware executing corresponding software.

[0038] For example, the aforementioned communication device may be a first device, a component of the first device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software that can implement all or part of the functions of the first device.

[0039] For example, the aforementioned communication device may also be a second device, a component of the second device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software that can realize all or part of the functions of the second device.

[0040] In one possible design, the communication device includes a processing unit and a transceiver unit. The transceiver unit can be used to send and receive signals to enable communication between the communication device and other devices. The processing unit can be used to perform some internal operations of the communication device. The transceiver unit can be called an input / output unit, a communication unit, etc., and can be a transceiver; the processing unit can be a processor. When the communication device is a module (e.g., a chip) in a communication device, the transceiver unit can be an input / output interface, input / output circuit, or input / output pins, etc., and can also be called an interface, communication interface, or interface circuit, etc.; the processing unit can be a processor, processing circuit, or logic circuit, etc.

[0041] In another possible design, the communication device includes a processor and may further include a transceiver for transmitting and receiving signals. The processor executes program instructions to perform the methods in any possible design or implementation of the first or second aspect described above. The communication device may also include one or more memories coupled to the processor, which may store necessary computer programs or instructions for implementing the functions involved in the first or second aspect. The processor can execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the first or second aspect described above when the computer programs or instructions are executed.

[0042] In another possible design, the communication device includes a processor that can be coupled to a memory. The memory can store necessary computer programs or instructions for implementing the functions described in the first or second aspect above. The processor can execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the first or second aspect above, when the computer programs or instructions are executed.

[0043] In another possible design, the communication device includes a processor and an interface circuit, wherein the processor is used to communicate with other devices through the interface circuit and to perform the methods in any possible design or implementation of the first or second aspect described above.

[0044] Understandably, in the third aspect described above, the processor can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor or separated from it. In specific implementations, the memory can be integrated with the processor on the same chip or disposed on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0045] Fourthly, embodiments of this application provide a communication system, which includes the first device and the second device described above, wherein the first device is used to implement the method in any possible design or implementation of the first aspect, and the second device is used to implement the method in any possible design or implementation of the second aspect.

[0046] Fifthly, this application provides a chip system including a processor and potentially a memory, the processor being used to implement the methods described in the first or second aspect above. The chip system may be composed of chips or may include chips and other discrete devices. The memory is used to store data related to implementing any possible design in the first or second aspect, such as relationships, and the processor is used to implement the processing flow related to any possible design in the first or second aspect. No specific limitations are specified herein.

[0047] Sixthly, this application also provides a computer-readable storage medium, which may be a volatile storage medium or a non-volatile storage medium, wherein the computer-readable storage medium stores computer-readable instructions, which, when executed on a computer, cause the computer to perform the methods as described in the first or second aspect.

[0048] In a seventh aspect, this application provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the methods of the embodiments of the first or second aspect described above.

[0049] For the technical effects that can be achieved in the second to seventh aspects mentioned above, please refer to the description of the technical effects that can be achieved by the corresponding possible design schemes in the first aspect mentioned above. This application will not repeat them here. Attached Figure Description

[0050] Figure 1 is a schematic diagram of the architecture of a communication system;

[0051] Figure 2 is a schematic diagram of a processing flow for information sources and receivers;

[0052] Figure 3A is a schematic diagram of an 8×8 polarization transformation matrix;

[0053] Figure 3B is a schematic diagram of the SC decoding calculation process;

[0054] Figure 4 is a flowchart illustrating an encoding method and a decoding method provided in an embodiment of this application;

[0055] Figure 5 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0056] Figure 6 is a schematic diagram of another communication device provided in an embodiment of this application;

[0057] Figure 7 is a schematic diagram of another communication device provided in an embodiment of this application;

[0058] Figure 8 is a schematic diagram of a chip system provided in an embodiment of this application;

[0059] Figure 9 is a schematic diagram of another chip system provided in an embodiment of this application. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, a further detailed description of this application will be provided below in conjunction with the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. In the description of this application, unless otherwise stated, "multiple" means two or more (including two). Therefore, implementations of the device and method can be referred to mutually, and repeated details will not be repeated.

[0061] The technical solutions provided in this application can be applied to 5G systems, or to future communication systems or other similar communication systems. Furthermore, the technical solutions provided in this application can be applied to cellular links, public land mobile networks (PLMNs), machine-to-machine (M2M) networks, Internet of Things (IoT) networks, or other networks. They can also be applied to links between devices, such as device-to-device (D2D) links. D2D links can also be called sidelinks, which are also referred to as secondary links or auxiliary links. In this application, the above terms all refer to links established between devices of the same type, and their meanings are the same. The so-called "same type of devices" can be links between terminal devices, links between base stations, links between relay nodes, etc., and this application does not limit this.

[0062] Figure 1 is a schematic diagram of the architecture of the communication system 1000 used in an embodiment of this application. As shown in Figure 1, the communication system includes a wireless access network 100 and a core network 200. Optionally, the communication system 1000 may also include an Internet 300. The wireless access network 100 may include at least one wireless access network device (110a and 110b in Figure 1) and at least one terminal (120a-120j in Figure 1). The terminal is connected to the wireless access network device wirelessly, and the wireless access network device is connected to the core network wirelessly or via a wired connection. The core network device and the wireless access network device may be independent physical devices, or the functions of the core network device and the logical functions of the wireless access network device may be integrated on the same physical device, or a single physical device may integrate some of the functions of the core network device and some of the functions of the wireless access network device. Terminals and wireless access network devices can be interconnected via wired or wireless connections. Figure 1 is only a schematic diagram; the communication system may also include other network devices, such as wireless relay devices and wireless backhaul devices, which are not shown in Figure 1.

[0063] Wireless access network equipment can be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system; it can also be a module or unit that performs some of the functions of a base station. In some deployments, a gNB can include a central unit (CU) and a distributed unit (DU). The CU implements some of the functions of the gNB, and the DU implements some of the functions of the gNB. For example, the CU is responsible for handling non-real-time protocols and services. For example, it implements radio resource control (RRC), service data adaptation protocol (SDAP) functions, and packet data convergence protocol (PDCP) layer functions. The DU is responsible for handling physical layer protocols and real-time services. For example, it can implement the functions of the radio link control (RLC) layer, medium access control (MAC) layer, and physical (PHY) layer. The gNB can also include an active antenna unit (AAU). The AAU implements some physical layer processing functions, radio frequency processing, and related functions of the active antenna. Since the information in the RRC layer ultimately becomes the information in the PHY layer, or is transformed from the information in the PHY layer, in this architecture, higher-layer signaling (e.g., RRC layer signaling) can also be considered to be sent by the DU, or by the DU and AAU. It is understood that the network device can be one or more of the following: CU node, DU node, and AAU node. Furthermore, the CU can be a network device in the radio access network (RAN), or a network device in the core network (CN); this application does not limit this. Additionally, in the embodiments of this application, the network device provides services to the cell, and the terminal device communicates with the network device through the transmission resources (e.g., frequency domain resources, or spectrum resources) used by the cell. The cell can be the cell corresponding to network equipment (such as a base station). The cell can belong to a macro base station or to a base station corresponding to a small cell.For example, small cells can include: metro cells, micro cells, pico cells, femto cells, etc. Because small cells have small coverage areas and low transmission power, they can provide high-speed data transmission services. Furthermore, in other possible cases, the network device can be other devices that provide wireless communication functions for terminal devices. The embodiments of this application do not limit the specific technology or device form used in the network device. For example, in an open radio access network (ORAN) system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the CU (or CU-CP, CU-UP), DU, and RU units in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. For specific descriptions of the aforementioned protocol layers, please refer to the relevant technical specifications of the 3rd Generation Partnership Project (3GPP). The radio access network equipment can be a macro base station (as shown in Figure 1, 110a), a micro base station or an indoor station (as shown in Figure 1, 110b), or a relay node or donor node, etc. The embodiments of this application do not limit the specific technology or equipment form used in the radio access network equipment.

[0064] A terminal can also be referred to as a terminal device, user equipment (UE), mobile station, or mobile terminal (MT). Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, and smart cities. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, in-vehicle equipment, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, etc. The embodiments of this application do not limit the specific technologies or device forms used in the terminals.

[0065] Network devices and terminals can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can be deployed on aircraft, balloons, and satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminals.

[0066] The roles of network devices and terminals can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile network device. For terminals 120j that access the wireless access network 100 via 120i, drone 120i is a network device; however, for network device 110a, 120i is a terminal, meaning that 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol. In this case, relative to 110a, 120i is also a network device. Therefore, both network devices and terminals can be collectively referred to as communication devices. 110a and 110b in Figure 1 can be called communication devices with network device functions, and 120a-120j in Figure 1 can be called communication devices with terminal functions.

[0067] Communication between network devices and terminals, between network devices, and between terminals can be conducted using licensed spectrum, unlicensed spectrum, or both simultaneously. Communication can be conducted using spectrum below 6 GHz, spectrum above 6 GHz, or both simultaneously. The embodiments of this application do not limit the spectrum resources used for wireless communication.

[0068] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes network device functions. This control subsystem, including network device functions, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities. Similarly, the functions of the terminal can be executed by modules (such as chips or modems) within the terminal, or by a device that includes terminal functions.

[0069] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0070] (1) Channel coding and channel decoding

[0071] Figure 2 illustrates a processing flow diagram for the source and sink. As shown in Figure 2, the transmitting end (i.e., the source) obtains the bit sequence to be encoded (i.e., the information bit sequence) through source coding, and then performs channel coding on the information bit sequence to obtain the encoded bit sequence. Correspondingly, after the receiving end (i.e., the sink) obtains the modulation symbol sequence to be decoded, it performs channel decoding on the modulation symbol sequence to be decoded to obtain the information bit sequence, and then performs source recovery on the information bit sequence to obtain useful information.

[0072] Since source coding does not consider interference resistance, if the bit sequence output from source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output from source coding again, can improve communication reliability. Channel decoding is the inverse process of channel coding.

[0073] There are various channel coding methods, such as polar codes and low-density parity-check (LDPC) codes. Polar codes were chosen as the control channel coding method in the 5G standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity, and have the advantages of good decoding performance and low complexity. LDPC codes were chosen as the data channel coding method in the 5G standard. LDPC codes are linear block codes with a sparse parity-check matrix, which not only have good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure.

[0074] (2) Polar code encoding

[0075] Polar codes employ a coding strategy that utilizes a noiseless channel to transmit useful information, while using a noisy channel to transmit predetermined information or no information at all. A polar code is a linear block code, and its generator matrix is ​​G. N Its encoding process is as follows It is a binary row vector with a length of N (i.e., code length); and Defined as the Kronecker product of log₂N matrices F₂, x₁ N These are the encoded bits (also called codewords). With the generating matrix G N Multiplying them together yields the encoded bits; the process of multiplication is the encoding process.

[0076] During the encoding process of polar codes, A portion of the bits are used to carry information, called the information bit set, and the set of indices of these bits is denoted as A; the other portion of the bits are set to fixed values ​​agreed upon in advance by the receiver and the transmitter, called the fixed bit set or frozen bit set, and the set of its bit indices is denoted by the complement of A, denoted as A'. c These freeze bits are typically set to 0, but they can be set arbitrarily as long as the receiver and sender agree in advance.

[0077] Currently, in NR, the frozen bits and information bits of the polar code are determined based on the reliability sequence corresponding to the mother code length. The reliability sequence corresponding to the mother code length can be calculated offline to reduce the encoding complexity. The mother code length is an integer power of 2, which is the length of the bit sequence after polar code encoding; the mother code length can also be called the encoding length. Taking a mother code length of 8 as an example, assuming the first sequence is [0 1 2 4 3 5 6 7], it means that the reliability of the bits from high to low is: the bit corresponding to bit number 7, the bit corresponding to bit number 6, ..., the bit corresponding to bit number 1, and the bit corresponding to bit number 0. Here, a bit can be understood as a bit sub-channel. The bit number can be understood as the index or identifier of the bit. For example, when constructing a polar code with a master code length of 8 and an information length of 4, the bits corresponding to bit number 7, bit number 6, bit number 5, and bit number 3 are selected from the end to the beginning as information bits, while the bits corresponding to bit number 4, bit number 2, bit number 1, and bit number 0 are selected as frozen bits.

[0078] Figure 3A shows an 8×8 polarization transformation matrix. The left side can be understood as the encoding side, with bits on the left denoted by u. The right side can be understood as the encoding side (or codeword side), with bits on the right denoted by x. The process from left to right is the encoding process of the bit sequence to be encoded at the transmitting end. The information bits to be encoded are represented by the sequence u(0, 0, 0, 0, 0, 0, 1, 1). After the polarization transformation matrix, the encoded bits are represented by the sequence x(0, ​​1, 0, 1, 0, 1, 0, 1). Mapping x to a modulation symbol allows transmission through channel W. Bits corresponding to high channel reliability are used to map information bits, while bits corresponding to low channel reliability are used to map frozen bits. As shown in Figure 3A, {u0, u1, u2, u4} are frozen bits, i.e., the positions of frozen bits, and {u3, u5, u6, u7} are information bits, i.e., the positions of information bits. In this embodiment, information bits are also called information bits. Frozen bits are also called frozen bits.

[0079] Referring to Figure 3A, during the encoding process, two adjacent columns constitute a coding layer. The left column of bits represents the input bits of the coding layer, and the right column represents the output bits. For example, in the leftmost coding layer, the input bit sequence is (0, 0, 0, 0, 0, 0, 1, 1), and the output bit sequence is (0, 0, 0, 0, 0, 0, 0, 1). The operation symbols in the middle of the coding layer... This represents the XOR operation, specifically... express The bits in the current row and A single XOR operation between the bits in the row. The bits on the right represent the result of the operation. For example, in the leftmost coding layer, the first input bit (value 0) and the second input bit (value 0) are processed... The operation yields the first output ratio (5) polar code decoding.

[0080] There are several methods for decoding polar codes, such as successive cancellation (SC) decoding and successive cancellation list (SCL) decoding.

[0081] The SC decoding method involves calculating the LLR of each decoded bit based on the log likelihood ratio (LLR) sequence corresponding to the bit sequence to be decoded, and then making a bit-by-bit decision. When the decoded bit is an information bit, if the LLR of the decoded bit is greater than 0, then the decoded bit is 0; if the LLR of the decoded bit is less than 0, then the decoded bit is 1. When the decoded bit is a fixed bit, the decoding result is set to 0 regardless of the LLR value. Figure 3B is a schematic diagram of the SC decoding calculation process. Taking a decoded bit of 4 bits as an example, there are 8 calculation nodes in Figure 3B, including 4 F nodes and 4 G nodes. The F nodes and G nodes correspond to the F operation and the G operation, respectively. The operation of the F node requires the two LLR inputs on its right side, and the operation of the G node requires the two LLR inputs on its right side and the output of the previous stage as inputs. Only after the input items are calculated can the output be calculated. According to the above calculation rules, the decoded bits obtained by calculating sequentially from the right side in Figure 3B are ①→②→③→④, and the decoding is completed.

[0082] (3) Rate matching

[0083] Taking polar codes as an example, as mentioned above, the encoding length of a polar code is an integer power of 2. In practical applications, the required length may be a non-encoded length. In this case, it is necessary to remove some bits from the encoded bit sequence without transmitting them, or to repeatedly transmit some bits. This process is usually called rate matching. The rate matching methods will be further explained below in three categories.

[0084] Punching: Punching refers to directly creating holes in certain bit positions within the encoded bit sequence without transmitting them, thus generating bit sequences of arbitrary length. On the decoding side, since there is no information at the corresponding punctured positions, the LLR of the corresponding bit is set to 0.

[0085] Shortening: Shortening is another common rate-matching method. This method involves designing the polar code so that certain bit positions in the encoded bit sequence are fixed values, thus eliminating the need for transmission. On the decoding side, since the corresponding "shortened" positions are essentially known at the receiver (usually 0), the LLR of the corresponding bit is set to infinity.

[0086] Repetition: "Repetition" refers to obtaining a longer bit sequence by repeatedly sending a portion of the encoded bit sequence.

[0087] The introduction of rate matching may cause a change in the reliability order of information bits. That is, before rate matching, the selected K information bits are the K bits with the highest reliability. After rate matching, the reliability of one or more of these K information bits may decrease, causing the previously selected K information bits to no longer be the optimal K information bits after rate matching. This leads to a decrease in the performance of the constructed Polar code and thus affects the communication quality.

[0088] Based on this, this application provides an encoding method and a decoding method to improve communication quality when rate matching is achieved. Referring to Figure 4, an embodiment of the encoding and decoding method provided in this application is shown. The encoding method is applied to a first device, and the decoding method is applied to a second device. The first device can be a terminal device or a module (e.g., a chip) within a terminal device, or it can also be a network device or a module (e.g., a chip) within a network device. The second device can be a terminal device or a module (e.g., a chip) within a terminal device, or it can also be a network device or a module (e.g., a chip) within a network device. The following description uses the example of the first device executing the encoding method and the second device executing the decoding method. The execution is as follows:

[0089] Step 401: The first device acquires the information bit sequence.

[0090] The information bit sequence contains K bits, where K is an integer greater than 1. These K bits can be all payload bits, or they can contain both payload bits and a check bit. The information bit sequence can also be understood as the K information bits to be transmitted.

[0091] Step 402: The first device determines the set of locations of the i-th information bits based on the set of locations of the i-th bits and the reliability sequence.

[0092] The i-th bit position set is used to indicate the frozen bits in the reliability sequence when determining the i-th information bit position set, where i is an integer from 1 to M, and M is an integer greater than 2. Typically, the value of M is defined by the communication standard, such as 3 or 4, etc. This application does not specifically limit this value and can be flexibly adjusted according to the evolution of the communication standard. The M information bit position sets are determined sequentially, that is, the first information bit position set is determined based on the first bit position set and the reliability sequence, then the second information bit position set is determined based on the second bit position set and the reliability sequence, and so on, until finally the M-th information bit position set is determined based on the M-th bit position set and the reliability sequence.

[0093] The set of i-th bit positions is also called the set of i-th frozen bit positions or the set of i-th pre-frozen bit positions. The reliability sequence indicates the order of the reliability of the bits. For example, the reliability sequence S, where S = [0,1,2,4,8,16,32,3,5,9,6,17,10,18,12,33,20,34,24,36,7,11,40,19,13,48,14,21,35,26,37,25,22,38,41,28,42,49,44,50,15,52,23,56,27,39,29,43,30,45,51,46,53,54,57,58,60,31,47,55,59,61,62,63], shows that the reliability of the bits increases sequentially. For example, element 63 in sequence S has higher reliability than element 62.

[0094] The set of i-th bit positions is used to indicate the frozen bits in the reliability sequence when determining the set of i-th information bit positions. It can be understood that the frozen bits in the reliability sequence constitute the set of i-th bit positions, and the sequence obtained after excluding the set of i-th bit positions determines the set of i-th information bit positions. For example, the set of 1-th bit positions is {0,1,2,3,4,5,6,7}, and the reliability sequence is S as described above. The set of 1-th bit positions is determined by removing the elements in S corresponding to the set of 1-th bit positions from S.

[0095] When i is greater than 1, the set of (i-1)th bit positions is a proper subset of the set of ith bit positions. Based on this, when determining the frozen bits in the reliability sequence in stages, since speed matching has a significant impact on bit positions with smaller indices in the reliability sequence, gradually expanding the set of ith bit positions as the number of selected information bits increases helps to more accurately pre-freeze bit positions of different indices, thereby improving the reliability of information bits and enhancing communication performance. For example, the set of ith bit positions is {0,1,2,3,4,5,6,7}, and the set of ith bit positions is {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14}, where the set of ith bit positions is a proper subset of the set of ith bit positions.

[0096] In one possible implementation, the number of bits in the i-th bit position set is associated with at least one of E, N, or K; where E is the number of bits in the encoded bit sequence, N is the encoding length (or mother code length) corresponding to the information bit sequence, and K is the number of bits in the information bit sequence, with E less than N. N is the smallest integer power of 2 greater than or equal to E; for example, E = 252, N = 256. For example, E = 5, N = 8. Based on this, it is helpful to select reliable bits as information bits, thereby improving encoding and decoding performance, and thus helping to improve communication performance. For example, E is 60, N is 64, K is 21, and the number of bits in the first bit position set is N / 8, that is, 8 bits. For example, E is 60, N is 64, K is 21, and the number of bits in the first bit position set is E / 6, that is, 10 bits. For example, E is 60, N is 64, K is 21, and the number of bits in the first bit position set is NE, that is, 4 bits. The set of positions for the i-th bit can also be related to K. As K increases, the number of information bits that need to be selected increases, and the set of positions for the i-th bit can be reduced accordingly. For example, if E is 60, N is 64, and K is 21, the number of bits in the set of positions for the i-th bit is... That is, 6 bits. This is only an example and is not a specific limitation.

[0097] In one possible implementation, the set of i-th information bit positions is the T with the highest reliability in the reliability sequence, excluding the set of i-th bit positions and the sets of 1 to (i-1)-th information bit positions. i -T i-1 Each bit position Ti is associated with at least one of M, i, E, N, or K, T1 = 0, T M =K.

[0098] When performing step 402, the rate matching method can be determined first based on the value of K / E (which can also be represented by R, i.e., R = K / E). If K / E ≤ 7 / 16, the rate matching adopts the perforation method; if K / E > 7 / 16, the rate matching adopts the shortening method. The following explanation is based on different rate matching methods and describes different cases.

[0099] Scenario 1: Rate matching is done via punching, and the number of punches is relatively small.

[0100] When E / N ≥ P (i.e., the number of punctures is small), P is a preset bit threshold (this application does not specifically limit the value of P, and it can be flexibly set, such as 3 / 4, 7 / 8, 5 / 8, etc.). Since the generator matrix of the polar code is obtained according to the Kronecker product, P can be... At this point, the polar codes have exactly *a* codes of length *a*. The sub-blocks are punched or shortened, where 'a' indicates the number of sub-blocks with polar code rate matching, 2 b The length of the sub-block indicating rate matching. The set of i-th bit positions includes those in the first set whose values ​​are less than N / 2. M+1-i The elements, or elements in the first set whose values ​​are less than NE, or elements in the first set whose values ​​are less than a first value, where the first value is N / 2. M+1-i The maximum value between NE and NE, the elements in the first set consist of 0 to N-1. Furthermore, the first set described above can also be replaced by a natural order bit sequence [0,1,2,3,…,N-1] consisting of N sequence elements. T i Satisfy the following formula 1:

[0101] in, This indicates rounding up to the nearest integer.

[0102] The following M steps are used to obtain the information bits of the polar code, which are obtained sequentially. in, Let be the set of positions of the i-th bit. The union of the first i-1 information bit positions (i.e.) In addition to selecting T based on reliability, i -T i -1 bits are used as the set of the i-th information bits.

[0103] For example, P = 3 / 4, E = 60, N = 64, K = 21. E / N = 15 / 16, 15 / 16 > 3 / 4. The first set includes {0, 1, 2, 3, 4, 5, ..., N-1}. i is 1, M = 3, and the set at the i-th bit position includes values ​​in the first set less than N / 2. M+1-i Let's take the elements as an example to illustrate, 2 M+1-i =8, N / 2 M+1-i =8, It is 8 bits, where, It does not belong The most reliable T1 positions, if the reliability sequence is S = [0,1,2,4,8,16,32,3,5,9,6,17,10,18,12,33,20,34,24,36,7,11,40,19,13,48,14,21,35,26,37,25,22,38,41,28,42,49,44,50,15,52,23,56,27,39,29,43,30,45,51,46,53,54,57,58,60,31,47,55,59,61,62,63], remove We obtain S1 = [8,16,32,9,17,10,18,12,33,20,34,24,36,11,40,19,13,48,14,21,35,26,37,25,22,38,41,28,42,49,44,50,15,52,23,56,27,39,29,43,30,45,51,46,53,54,57,58,60,31,47,55,59,61,62,63]. When K = 21, T1 = 11.

[0104] When i is 2, M = 3, N / 2 M+1-i =16, It is 16 bits, where, in, for The proper subset of . It does not belong and The most reliable positions T2-T1 (i.e., 10) have a reliability sequence S (removed). We obtain S2 = [16,32,17,18,33,20,34,24,36,40,19,48,21,35,26,37,25,22,38,41,28,42,49,44,50,52,23,56,27,39,29,43,30,45,51,46,53,54,57,58,60,31,47,55,59,61,62,63], and remove... Get S3 = [16, 32, 17, 18, 33, 20, 34, 24, 36, 40, 19, 48, 21, 35, 26, 37, 25, 22, 38, 41, 28, 42, 49, 44, 50, 52, 23, 56, 27, 39, 29, 43, 30, 45, 51, 46, 53]. When K = 21, T2 = 21,

[0105] When i is 3, M = 3, N / 2 M+1-i = 32, is 32 bits, where, where, is a proper subset of. T3 = K = 21, does not belong to and the most reliable (T3 - T2) positions. When K = 21, T2 = 21, T3 - T2 = 0

[0106] Case 2: The rate matching method is puncturing and the number of puncturing is large

[0107] When E / N < P (that is, the number of puncturing is large), P is a preset bit threshold (the present application does not specifically limit the value of P, which can be flexibly set, such as 3 / 4). The set of the first bit positions is the elements in the first set whose values are less than The set of the second bit positions is the elements in the first set whose values are less than N / 2. The set of the jth bit positions includes the elements in the first set whose values are less than N / 2 + N / 2 M+2-j The elements in the first set are composed of 0 to N - 1, 3 ≤ j ≤ M. When 5 / 8 ≤ E / N, When E / N < 5 / 8, where, represents rounding up, and P is a preset bit threshold. When i is greater than 1, T i satisfies the following formula 2:

[0108] The following obtains the information bits of the polar code in M steps, and sequentially obtains where, is the set of the ith bit positions. Among and the union of the first i - 1 information bit positions (that is ), select T i -T i -1 bits as the set of the ith information bits.

[0109] For example, P = 3 / 4, E = 40, N = 64, K = 15. E / N = 5 / 8, 5 / 8 < 3 / 4. The first set includes {0, 1, 2, 3, 4, 5, ..., N-1}. i is 1, M = 3, and the first set is the set of positions of the first bit where the value is less than... Let's take the elements as an example to illustrate, It is 26 bits, of which, 5 / 8 = E / N It does not belong The most reliable T1 positions, if the reliability sequence is S = [0,1,2,4,8,16,32,3,5,9,6,17,10,18,12,33,20,34,24,36,7,11,40,19,13,48,14,21,35,26,37,25,22,38,41,28,42,49,44,50,15,52,23,56,27,39,29,43,30,45,51,46,53,54,57,58,60,31,47,55,59,61,62,63], remove We obtain S4 = [32,33,34,36,40,48,35,26,37,38,41,28,42,49,44,50,52,56,27,39,29,43,30,45,51,46,53,54,57,58,60,31,47,55,59,61,62,63]. When K = 15, T1 = 12.

[0110] When i is 2, M = 3, N / 2 = 32. It is 32 bits, where, in, for The proper subset of . It does not belong and The most reliable positions T2-T1 (i.e., 3) are represented by the reliability sequence S (removing the last three positions). We obtain S5 = [32,33,34,36,40,48,35,37,38,41,42,49,44,50,52,56,39,43,45,51,46,53,54,57,58,60,47,55,59,61,62,63], and remove... We get S6 = [32,33,34,36,40,48,35,37,38,41,42,49,44,50,52,56,39,43,45,51,46]. When K = 21, T2 = 15.

[0111] When i is 3, M = 3, N / 2 + N / 2 M+2-j =3N / 4=48, It is 48 bits, of which, in, for A proper subset of. T3 = K = 15, It does not belong and The most reliable T3-T2 positions, when K=15, T2=21, T3-T2=0

[0112] Scenario 3: Rate matching method is shortening

[0113] The first bit position set consists of elements in the first set whose values ​​are greater than or equal to E; when i is greater than 1, the i-th bit position set consists of elements in the first set whose values ​​are less than N / 2. M+1-i The elements of the set, and the elements in the first set whose values ​​are greater than or equal to E; the elements in the first set consist of 0 to N-1; in one possible implementation, T i The following formula 3 is satisfied:

[0114] Where 9 / 16 ≤ E / N, When E / N<9 / 16,

[0115] The following M steps are used to obtain the information bits of the polar code, which are obtained sequentially. in, Let be the set of positions of the i-th bit. The union of the first i-1 information bit positions (i.e.) In addition to selecting T based on reliability, i -T i-1 The set of bits is the i-th information bit.

[0116] For example, E = 40, N = 64, K = 20. The first set includes {0, 1, 2, 3, 4, 5, ..., N-1}. i is 1, M = 3. Taking the set of the first bit positions as elements in the first set whose values ​​are greater than or equal to E as an example, NE = 24. It is 24 bits, where, 5 / 8 = E / N, E / N > 9 / 16 It does not belong The most reliable T1 positions, if the reliability sequence is S = [0,1,2,4,8,16,32,3,5,9,6,17,10,18,12,33,20,34,24,36,7,11,40,19,13,48,14,21,35,26,37,25,22,38,41,28,42,49,44,50,15,52,23,56,27,39,29,43,30,45,51,46,53,54,57,58,60,31,47,55,59,61,62,63], remove We obtain S6 = [0,1,2,4,8,16,32,3,5,9,6,17,10,18,12,33,20,34,24,36,7,11,19,13,14,21,35,26,37,25,22,38,28,15,23,27,39,29,30,31]. When K = 20, T1 = 10.

[0117] When i is 2, M = 3, N / 2 M+1-i =16, NE=24, It is 40(16+24) bits, where, The union of [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] and [40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63]. for The proper subset of . It does not belong and The most reliable positions T2-T1 (i.e., 10) have a reliability sequence S (removed). We get S7 = [16,32,17,18,33,20,34,24,36,19,21,35,26,37,25,22,38,28,23,27,39,29,30,31], then remove... We get S8 = [16,32,17,18,33,20,34,24,36,19,21,35,26,37,25]. When K = 20, T2 = 20.

[0118] When i is 3, M = 3, N / 2 M+1-i =32, NE=24, It is 58 (32+24) bits, where, The union of [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,21,23,24,25,26,27,28,29,30,31] and [40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63]. for A proper subset of. T3 = K = 20, It does not belong and The most reliable (T3-T2) positions, when K=20, T2=20, T3-T2=0

[0119] In one possible implementation, in case three, when K / E > 3 / 4, T i =K, so that the information bits of the polar code can be obtained in multiple steps.

[0120] Step 403: Based on the target information bit position set, the information bit sequence is polar-coded to obtain the encoded bit sequence.

[0121] The target information bit position set is the union of the first to the Mth information bit position sets. For example, any information bit position set has no intersection with any other information bit position set; for instance, the first information bit position set has no intersection with the second information bit position set, and the first information bit position set has no intersection with the Mth information bit position set. For example, in case three above... 26, 37, 25). and There is no overlap.

[0122] For example, in the example of Case 1 above, the set of target information bit positions is: and The union of,

[0123] The encoding scheme described in steps 401 to 403 above can be executed independently. For example, the first device can send an air interface message to the second device, carrying parameters related to the encoded bit sequence in the air interface message. For instance, air interface information A, where air interface message A includes the encoded bit sequence, or air interface message A includes parameter A, where parameter A corresponds to the encoded bit sequence. Accordingly, the second device executes the decoding scheme. Furthermore, if the first device does not send the encoded bit sequence to the second device, the second device can also locally obtain the encoded bit sequence and execute the decoding scheme.

[0124] Step 404: The second device determines the set of locations of the i-th information bits based on the set of locations of the i-th bits and the reliability sequence.

[0125] Here, the i-th bit position set is used to indicate the frozen bits in the reliability sequence when determining the i-th information bit position set, where i is an integer from 1 to M, and M is an integer greater than 2. M is usually a value agreed upon by the communication standard, such as M being 3 or 4, etc. This application does not specifically limit it, and it can be flexibly adjusted according to the evolution of the communication standard.

[0126] When i is greater than 1, the set of (i-1)th bit positions is a proper subset of the set of ith bit positions. Based on this, determining the frozen bits in the reliability sequence in stages helps improve communication performance.

[0127] In one possible implementation, the number of bits in the set of the i-th bit positions is associated with at least one of E, N, or K.

[0128] In one possible implementation, the set of i-th information bit positions is the Ti-Ti-1 bit positions with the highest reliability in the reliability sequence, excluding the set of i-th bit positions and the sets of 1 to (i-1)-th information bit positions. Ti is associated with at least one of M, i, E, N or K, T1 = 0, and TM = K.

[0129] The second device determines the location set of the i-th information bit based on the location set of the i-th bit and the reliability sequence in the same way as the first device determines the location set of the i-th information bit based on the location set of the i-th bit and the reliability sequence in step 402 above. You can refer to the above description, and it will not be repeated here.

[0130] Step 405: The second device performs polar code decoding on the encoded bit sequence according to the target information bit position set to obtain the information bit sequence.

[0131] The target information bit position set is the union of the first information bit position set to the Mth information bit position set.

[0132] For example, decoding can be performed with reference to Figure 3B above to obtain the information bit sequence.

[0133] This application determines M information bit position sets based on M bit position sets, and takes the union of the M information bit position sets as the final information bit position set. Since the final information bit position set is determined in multiple steps and the bit with the highest reliability is selected as the information bit each time, it helps to accurately select the bit with the highest reliability as the information bit, which can improve encoding and decoding performance (e.g., error correction performance), and thus help improve communication performance.

[0134] The foregoing primarily describes the solutions provided by the embodiments of this application from the perspective of device interaction. It is understood that, in order to achieve the above functions, each device may include corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0135] The embodiments of this application can divide the device into functional units according to the above method examples. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0136] Figure 5 illustrates a possible exemplary block diagram of a communication device according to an embodiment of this application, when using integrated units. As shown in Figure 5, the communication device 500 may include a processing unit 501 and a transceiver unit 502. The processing unit 501 is used to control and manage the operation of the communication device 500. The transceiver unit 502 is used to support communication between the communication device 500 and other devices. Optionally, the transceiver unit 502 may include a receiving unit and / or a transmitting unit, respectively used to perform receiving and transmitting operations. Optionally, the communication device 500 may also include a storage unit for storing program code and / or data of the communication device 500. The transceiver unit may be referred to as an input / output unit, a communication unit, etc. The transceiver unit may be a transceiver. The processing unit may be a processor. When the communication device is a module (e.g., a chip) in a first device (or a second device), the transceiver unit may be an input / output interface, an input / output circuit, or input / output pins, etc. The transceiver unit may also be referred to as an interface, a communication interface, or an interface circuit, etc. The processing unit may be a processor, a processing circuit, or a logic circuit, etc.

[0137] The communication device can be the first device in the above embodiments, a component in the first device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software that can implement all or part of the functions of the first device.

[0138] For example, in one embodiment, processing unit 501 is used to determine the i-th information bit position set based on the i-th bit position set and the reliability sequence, wherein the i-th bit position set is used to indicate the frozen bits in the reliability sequence when determining the i-th information bit position set, i is an integer from 1 to M, and M is an integer greater than 2; based on the target information bit position set, polar code encoding is performed on the information bit sequence to obtain the encoded bit sequence, and the target information bit position set is the union of the first information bit position set to the M-th information bit position set. Transceiver unit 502 can transmit the encoded bit sequence.

[0139] In one possible implementation, when i is greater than 1, the set of (i-1)th bit positions is a proper subset of the set of i-th bit positions.

[0140] In one possible implementation, the number of bits in the set of the i-th bit positions is associated with at least one of E, N, or K; where E is the number of bits in the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, K is the number of bits in the information bit sequence, and E is less than N.

[0141] In one possible implementation, the set of i-th information bit positions is the T with the highest reliability in the reliability sequence, excluding the set of i-th bit positions and the sets of 1 to (i-1)-th information bit positions. i -Ti-1 a bit position, T i is related to at least one of M, i, E, N, or K; where E is the number of bits of the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, K is the number of bits of the information bit sequence, T1 = 0, T M = K.

[0142] In a possible implementation, when E / N ≥ P, T i satisfies the following formula:

[0143] where represents rounding up, and P is a preset bit threshold.

[0144] In a possible implementation, when E / N ≥ P, the set of the i-th bit positions includes elements in the first set with values less than N / 2 M+1-i or includes elements in the first set with values less than N - E, or includes elements in the first set with values less than a first value, the first value being the maximum value between N / 2 M+1-i and N - E; the elements in the first set consist of 0 to N - 1; where E is the number of bits of the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, and P is a preset bit threshold.

[0145] In a possible implementation, when E / N < P, when 5 / 8 ≤ E / N, when E / N < 5 / 8, where represents rounding up, and P is a preset bit threshold.

[0146] In a possible implementation, when E / N < P, when i is greater than 1, T i satisfies the following formula:

[0147] where represents rounding up, and P is a preset bit threshold.

[0148] In a possible implementation, when E / N < P, the set of the 1st bit position is the elements in the first set with values less than and the set of the 2nd bit position is the elements in the first set with values less than N / 2, and the set of the j-th bit position includes the elements in the first set with values less than N / 2 + N / 2 M+2-j ; the elements in the first set consist of 0 to N - 1, 3 ≤ j ≤ M; where E is the number of bits of the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, P is a preset bit threshold, represents rounding up.

[0149] In one possible implementation, T i Satisfy the following formula:

[0150] in, This indicates rounding up when 9 / 16 <= E / N. When E / N<9 / 16,

[0151] In one possible implementation, the set of positions for the first bit is the set of elements in the first set whose values ​​are greater than or equal to E; when i is greater than 1, the set of positions for the i-th bit is the set of elements in the first set whose values ​​are less than N / 2. M+1-i The elements are either E or elements in the first set whose values ​​are greater than or equal to E; the elements in the first set consist of numbers from 0 to N-1; where E is the number of bits in the encoded bit sequence, and N is the encoding length corresponding to the information bit sequence. This indicates rounding up to the nearest integer.

[0152] The communication device may also be the second device in the above embodiments, a component of the second device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software that can implement all or part of the functions of the second device.

[0153] For example, in one embodiment, the transceiver unit 502 can receive an encoded bit sequence; the processing unit 501 is used to determine the i-th information bit position set according to the i-th bit position set and the reliability sequence, wherein the i-th bit position set is used to indicate the frozen bits in the reliability sequence when determining the i-th information bit position set, i is an integer from 1 to M, and M is an integer greater than 2; according to the target information bit position set, the encoded bit sequence is polar-coded to obtain an information bit sequence, and the target information bit position set is the union of the first information bit position set to the M-th information bit position set.

[0154] In one possible implementation, when i is greater than 1, the set of (i-1)th bit positions is a proper subset of the set of i-th bit positions.

[0155] In one possible implementation, the number of bits in the set of the i-th bit positions is associated with at least one of E, N, or K; where E is the number of bits in the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, K is the number of bits in the information bit sequence, and E is less than N.

[0156] In one possible implementation, the set of i-th information bit positions is the T with the highest reliability in the reliability sequence, excluding the set of i-th bit positions and the sets of 1 to (i-1)-th information bit positions. i -T i-1 Each bit position, Ti associated with at least one of M, i, E, N, or K; where E is the number of bits of the encoded bit sequence, N is the encoded length corresponding to the information bit sequence, K is the number of bits of the information bit sequence, T1 = 0, T M = K.

[0157] In a possible implementation, when E / N ≥ P, T i satisfies the following formula:

[0158] where, represents rounding up, and P is a preset bit threshold.

[0159] In a possible implementation, when E / N ≥ P, the set of the i-th bit positions includes elements in the first set with values less than N / 2 M+1-i or includes elements in the first set with values less than N - E, or includes elements in the first set with values less than a first value, the first value being the maximum value between N / 2 M+1-i and N - E; the elements in the first set consist of 0 to N - 1; where E is the number of bits of the encoded bit sequence, N is the encoded length corresponding to the information bit sequence, and P is a preset bit threshold.

[0160] In a possible implementation, when E / N < P, when 5 / 8 ≤ E / N, when E / N < 5 / 8, where, represents rounding up, and P is a preset bit threshold.

[0161] In a possible implementation, when E / N < P, when i is greater than 1, T i satisfies the following formula:

[0162] where, represents rounding up, and P is a preset bit threshold.

[0163] In a possible implementation, when E / N < P, the set of the 1st bit positions is the elements in the first set with values less than of, the set of the 2nd bit positions is the elements in the first set with values less than N / 2, the set of the j-th bit positions includes the values in the first set less than N / 2 + N / 2 M+2-j of, the elements in the first set consist of 0 to N - 1, 3 ≤ j ≤ M; where E is the number of bits of the encoded bit sequence, N is the encoded length corresponding to the information bit sequence, P is a preset bit threshold, represents rounding up.

[0164] In a possible implementation, Ti Satisfy the following formula:

[0165] in, This indicates rounding up when 9 / 16 <= E / N. When E / N<9 / 16,

[0166] In one possible implementation, the set of positions for the first bit is the set of elements in the first set whose values ​​are greater than or equal to E; when i is greater than 1, the set of positions for the i-th bit is the set of elements in the first set whose values ​​are less than N / 2. M+1-i The elements are either E or elements in the first set whose values ​​are greater than or equal to E; the elements in the first set consist of numbers from 0 to N-1; where E is the number of bits in the encoded bit sequence, and N is the encoding length corresponding to the information bit sequence. This indicates rounding up to the nearest integer.

[0167] In one possible design, when the communication device 500 is a terminal device or a communication module within a terminal device, the function of the processing unit 501 can be implemented by one or more processors. Specifically, the processor may include a modem chip, or a system-on-a-chip (SoC) chip or a SIP chip containing a modem core. The function of the transceiver unit 502 can be implemented by transceiver circuitry.

[0168] In one possible design, when the communication device 500 is a circuit or chip responsible for communication functions in a terminal device, such as a modem chip or a system-on-a-chip (SoC) or SIP chip containing a modem core, the function of the processing unit 501 can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processor cores. The function of the transceiver unit 502 can be implemented by the interface circuitry or data transceiver circuitry on the aforementioned chip.

[0169] When the aforementioned communication device is a module applied in a base station, the base station module implements the functions of the base station in the above method embodiments. The base station module receives information from other modules (such as radio frequency modules or antennas) in the base station, which is information sent by the UE to the base station; or, the base station module sends information to other modules (such as radio frequency modules or antennas) in the base station, which is information sent by the base station to the UE. Here, the base station module can be the baseband chip of the base station, or it can be a DU or other modules, where the DU can be an O-DU under the O-RAN architecture.

[0170] Figure 6 is an exemplary block diagram of a communication device provided in an embodiment of this application. For example, the communication device 10 may include a chip system 110, a memory 120, a bus 130, a power management module 140, or a transceiver 150, etc.

[0171] The chip system 110 can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed through integrated logic circuits in the hardware of the chip system 110 or through software instructions.

[0172] As an example and not a limitation, chip system 110 may include circuitry or chips responsible for signal processing (such as a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip or system-in-package (SIP) chip containing a modem core).

[0173] Optionally, the chip system 110 may also include a memory (such as a cache) for storing instructions and data. In some embodiments, the memory in the chip system 110 is a cache memory. This memory can store instructions or data that the chip system 110 has just used or that are used repeatedly. If the chip system 110 needs to use the instruction or data again, it can directly retrieve it from the memory. This avoids repeated accesses, reduces the waiting time of the chip system 110, and thus improves the efficiency of the system.

[0174] In some embodiments, the chip system 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a SIM interface, and / or a USB interface, etc.

[0175] Memory 120 may include random access memory (RAM) and read-only memory (ROM). Memory 120 may store computer-readable, computer-executable code, including instructions that, when executed, cause the processor to perform the various functions described in this application.

[0176] Optionally, the code may include instructions for implementing various aspects of the embodiments of this application. The code may be stored in a non-transitory computer-readable medium such as system memory or other types of memory. In some cases, the code may not be directly executable by the chip system 110, but may enable a computer (e.g., at compile and execution time) to perform the functions described in this application. In some cases, memory 120 may in particular contain a basic I / O system that controls basic hardware or software operations, such as interaction with peripheral components or devices.

[0177] For example, the chip system 110 executes various functional applications and data processing of the communication device 10 by running instructions stored in the memory 120. For instance, when the communication device 10 transfers files with other devices (which may also be terminal devices or network devices), the chip system 110 of the communication device 10 can call the computer-executable program code stored in the memory 120 to implement the encoding or decoding methods provided in the embodiments of this application.

[0178] In addition, the memory 120 can be integrated into the chip system 110 or independent of the chip system 110.

[0179] Bus 130 may be a universal serial bus (USB) used to support communication between the various parts of the communication device 10.

[0180] The power management module 140 is used to receive charging input from the charger. Optionally, the power management module 140 can also supply power to the communication device 10 while charging it (e.g., the battery module of the communication device 10). By way of example and not limitation, the power management module 140 can also supply power to other devices besides the communication device 10.

[0181] Transceiver 150 can communicate bidirectionally via one or more antennas, wired links, or wireless links. For example, transceiver 150 can represent a wireless transceiver and can communicate bidirectionally with another wireless transceiver. Transceiver 150 may also include a modem for modulating packets and providing the modulated packets to the antenna for transmission, and for demodulating packets received from the antenna. Transceiver 150 may include a receiver and a transmitter, the receiver performing the function of receiving information and the transmitter performing the function of transmitting information.

[0182] In some cases, a wireless device may include a single antenna. However, in other cases, the device may have more than one antenna, such as antenna 1 and antenna 2 shown in FIG. 6, which may be capable of simultaneously transmitting or receiving multiple wireless transmissions. Exemplarily, antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in communication device 10 can be used to cover one or more communication frequency bands. Different antennas can also be multiplexed to improve antenna utilization. For example, antenna 1 can be multiplexed as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch. Communication device 10 can transfer files to other devices via wireless communication functions.

[0183] In one design, the communication device 10 may correspond to the first device in the above method embodiments. The communication device 10 may implement the steps or processes performed by the first device in the above method embodiments, wherein the transceiver 150 may be used to perform the transmission and reception related operations of the first device in the above method embodiments; and the chip system 110 may be used to perform the processing related operations of the first device in the above method embodiments.

[0184] In another design, the communication device 10 may correspond to the second device in the above method embodiments. The communication device 10 may implement the steps or processes performed by the second device in the above method embodiments, wherein the transceiver 150 may be used to perform the transmission and reception related operations of the second device in the above method embodiments; and the chip system 110 may be used to perform the processing related operations of the second device in the above method embodiments.

[0185] Under this design, the communication device 10 may include modules such as a short-range communication module 164, a sensor 161, a display 162, or a camera 163, as shown in Figure 6.

[0186] The short-range communication module 164 may include modules that support short-range communication, such as Wi-Fi and Bluetooth.

[0187] Sensor 161 may include pressure sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, distance sensors, proximity sensors, fingerprint sensors, temperature sensors, touch sensors, ambient light sensors, bone conduction sensors, etc.

[0188] Display 162 is used to display images, videos, etc. The display includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Miniled LED, a MicroLED, a Micro-OLED, a quantum dot light-emitting diode (QLED), etc. For example, in this embodiment, the display can be used to display the interface required by the communication device 10. Exemplarily, the communication device 10 implements display functions through a GPU, a display, and an application processor. The GPU is a microprocessor for image processing, connected to the display and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The chip system 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0189] Camera 163 is used to acquire images, videos, etc.

[0190] It is understood that the structure shown in Figure 6 does not constitute a specific limitation on the communication device 10. In some embodiments, the communication device 10 may also include more or fewer components than those shown in Figure 6, or combine some components, or split some components, or have different component arrangements, etc. Alternatively, some components shown in Figure 6 may be implemented in hardware, software, or a combination of software and hardware, and the communication device 10 may be based on the structure given in Figure 9 with or without additional components.

[0191] Figure 7 is a schematic block diagram of a communication device provided in an embodiment of this application. The communication device 20 may include a baseband unit 210, which can communicate with external devices via a cellular radio frequency (RF) transceiver 220 (e.g., if the communication device 20 is a terminal device, the baseband unit 210 can communicate with network devices via the cellular RF transceiver 220; or, if the communication device 20 is a network device, the baseband unit 210 can communicate with terminal devices and / or core network devices via the cellular RF transceiver 220).

[0192] Baseband unit 210 may include computer-readable medium / memory. Baseband unit 210 is responsible for general processing, including the execution of software stored on the computer-readable medium / memory. When executed by baseband unit 210, the software causes baseband unit 210 to perform the various functions described above. The computer-readable medium / memory may also be used to store data manipulated by baseband unit 210 during software execution.

[0193] The baseband unit 210 further includes a receiving unit 201, a management unit 202, and a transmitting unit 203. The management unit 202 includes the one or more sub-units shown in FIG. 7. The units within the management unit 202 may be stored in a computer-readable medium / memory and / or configured as hardware within the baseband unit 210. The receiving unit 201 and the transmitting unit 203 may be referred to as transceiver units.

[0194] Figure 8 is a schematic block diagram of the chip system provided in an embodiment of this application. The chip system 30 includes, but is not limited to, a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip or system-in-package (SIP) chip containing a modem core.

[0195] The chip system (or processing system) includes a processor 310, a memory 320, and an input / output interface 330.

[0196] The processor 310 can be a processing circuit in the chip system (including at least one processor, such as processor 311 and processor 312 as shown in FIG8). The processor 310 can be coupled to the memory 320, and call the instructions in the memory 320, so that the chip system can implement the methods and functions of the various embodiments of this application. The input / output interface 330 can be an input / output circuit in the chip system, which outputs the information processed by the chip system, or inputs the data or signaling information to be processed into the chip system for processing.

[0197] As one approach, the chip system is used to implement the operations performed by the first or second device in the various method embodiments described above.

[0198] For example, processor 310 is used to implement the processing-related operations performed by the first device or the second device in the above method embodiments, as described in the foregoing embodiments; input / output interface 330 is used to implement the sending and / or receiving-related operations performed by the first device or the second device in the above method embodiments, as described in the foregoing embodiments.

[0199] Figure 9 is a schematic block diagram of a chip system provided in an embodiment of this application. The chip system 40 (or processing system) includes an input / output interface 410 and logic circuitry 420. The input / output interface 410 can be an input / output circuit within the chip system, outputting processed information or inputting data or signaling information to be processed into the chip system for processing; details can be found in the descriptions of the foregoing embodiments. The logic circuitry 420 is used to execute the aforementioned communication method; details can also be found in the descriptions of the foregoing embodiments.

[0200] As one approach, the chip system is used to implement the operations performed by the first or second device in the various method embodiments described above.

[0201] For example, logic circuit 420 is used to implement processing-related operations performed by the first device or the second device in the above method embodiments; input / output interface 410 is used to implement sending and / or receiving-related operations performed by the first device or the second device in the above method embodiments.

[0202] This application also provides a computer-readable storage medium storing computer instructions for implementing the methods executed by the first device and / or the second device in the above-described method embodiments.

[0203] For example, when the computer program is executed by a computer, it enables the computer to implement the methods performed by the first device and / or the second device in the various embodiments of the above methods.

[0204] This application also provides a computer program product comprising instructions which, when executed by a computer, implement the methods performed by the first device and / or the second device in the above-described method embodiments.

[0205] This application also provides a communication system, including the aforementioned first device and second device.

[0206] The explanations and beneficial effects of the relevant contents in any of the devices provided above can be found in the corresponding method embodiments provided above, and will not be repeated here.

[0207] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, portable hard disks, compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a first device. Of course, the processor and storage medium can also exist as discrete components in an access network device or terminal.

[0208] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. A computer program is a set of instructions that directs each step of an action of an electronic computer or other device with message processing capabilities. It is typically written in a programming language and runs on a target architecture. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed, in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video optical disc; or it can be a semiconductor medium, such as a solid-state drive. The computer-readable storage medium can be volatile or non-volatile, or it can include both types of storage media.

[0209] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0210] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. In the textual description of this application, the character " / " generally indicates an "or" relationship between the preceding and following related objects; in the formulas of this application, the character " / " indicates a "division" relationship between the preceding and following related objects.

[0211] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

Claims

1. An encoding method characterized by, include: Based on the set of i-th bit positions and the reliability sequence, determine the set of i-th information bit positions, wherein the set of i-th bit positions is used to indicate the frozen bits in the reliability sequence when determining the set of i-th information bit positions, i is an integer from 1 to M, and M is an integer greater than 2; Based on the target information bit position set, the information bit sequence is polar-coded to obtain the encoded bit sequence. The target information bit position set is the union of the first information bit position set to the Mth information bit position set.

2. A decoding method, characterized in that, include: Based on the set of i-th bit positions and the reliability sequence, determine the set of i-th information bit positions, wherein the set of i-th bit positions is used to indicate the frozen bits in the reliability sequence when determining the set of i-th information bit positions, i is an integer from 1 to M, and M is an integer greater than 2; Based on the target information bit position set, the encoded bit sequence is decoded using polar codes to obtain the information bit sequence. The target information bit position set is the union of the first information bit position set to the Mth information bit position set.

3. The method according to claim 1 or 2, characterized in that, When i is greater than 1, the set of (i-1)th bit positions is a proper subset of the set of i-th bit positions.

4. The method according to any one of claims 1 to 3, characterized in that, The number of bits in the set of the i-th bit positions is associated with at least one of E, N, or K; Wherein, E is the number of bits in the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, K is the number of bits in the information bit sequence, and E is less than N.

5. The method according to any one of claims 1 to 4, characterized in that, The i-th information bit position set is the highest reliability T in the reliability sequence, excluding the i-th bit position set and the information bit position sets from the 1st to the (i-1)th information bit position sets. i -T i-1 Each bit position, the T i Associated with at least one of M, i, E, N, or K; wherein E is the number of bits in the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, K is the number of bits in the information bit sequence, T1 = 0, T M =K.

6. The method of claim 5, wherein, When E / N≥P, the T i The following formula is satisfied: Among them, the This indicates rounding up, where P is a preset bit threshold.

7. The method according to any one of claims 1-6, characterized in that, When E / N≥P, the set of the i-th bit positions includes the bits in the first set whose values ​​are less than N / 2. M+1-i The elements, or elements in the first set whose values ​​are less than NE, or elements in the first set whose values ​​are less than a first value, wherein the first value is N / 2. M+1-i The maximum value between NE and the first set consists of elements from 0 to N-1; Wherein, E is the number of bits in the encoded bit sequence, N is the encoding length corresponding to the information bit sequence, and P is a preset bit threshold.

8. The method of claim 5, wherein, E / N <P, When 5 / 8 < E / N, When E / N < 5 / 8, Among them, the This indicates rounding up, where P is a preset bit threshold.

9. The method of claim 5, wherein, E / N < P, when said i is greater than 1, said T i satisfies the following equation: Among them, the This indicates rounding up, where P is a preset bit threshold.

10. The method according to any one of claims 1-5, 8, and 9, characterized in that, When E / N < P, the first set of bit positions is the set of values less than The elements, the set of the 2nd bit positions are the elements in the first set whose values ​​are less than N / 2, and the set of the jth bit positions includes the elements in the first set whose values ​​are less than N / 2 + N / 2. M+2-j The elements of the first set consist of elements from 0 to N-1, where 3≤j≤M; Wherein, the E is the bit number of the encoding bit sequence, the N is the encoding length corresponding to the information bit sequence, the P is a preset bit threshold, and the This indicates rounding up to the nearest integer.

11. The method of claim 5, wherein, The T i satisfies the following equation: wherein the denotes rounding up, when 9 / 16 <= E / N, When E / N < 9 / 16, 12. The method according to any one of claims 1-5, 11, characterized in that, The set of the first bit positions is the elements in the first set whose value is greater than or equal to E; When i is greater than 1, the set of i-th bit positions is the set of values ​​in the first set that are less than N / 2. M+1-i The elements, or the elements in the first set whose values ​​are greater than or equal to E; The elements in the first set consist of numbers from 0 to N-1; wherein the E is the number of bits of the coded bit sequence, the N is the coding length corresponding to the information bit sequence, and the This indicates rounding up to the nearest integer.

13. A communications device, characterized by It includes a processor and an interface circuit, the processor being configured to communicate with other devices via the interface circuit and to perform the method of any one of claims 1, 3 to 12, or to perform the method of any one of claims 2 to 12.

14. A computer program product, characterised in that, The computer program product includes instructions that, when executed on a processor, cause the processor to perform the method of any one of claims 1, 3 to 12, or the method of any one of claims 2 to 12.

15. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, which, when executed by a communication device, implement the method of any one of claims 1, 3 to 12, or the method of any one of claims 2 to 12.

16. A communications device, characterized by comprising means or units for performing the method of any one of claims 1, 3-12.

17. A communications device, characterized by comprising means or units for performing the method of any one of claims 2-12.

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