Pixel driving circuit and driving method therefor, and display substrate

Abstract

A pixel driving circuit and a driving method therefor, and a display substrate. The pixel driving circuit comprises: an isolation sub-circuit, configured to connect or disconnect a third node (N3) and a fifth node (N5) under the control of a signal of a second scanning signal end (Gate2), and store the signals of a first node (N1) and the fifth node (N5); a first control sub-circuit, configured to provide a signal of a data signal end (Data) to the first node (N1) under the control of a signal of a first scanning signal end (Gate1); and second control sub-circuits, configured to separately provide a signal of at least one initial signal end (INIT1, INIT2, INIT3) to one node among a second node (N2), a fourth node (N4), the third node (N3), and the fifth node (N5) under the control of a signal of at least one reset signal end (Reset1, Reset2, Reset3).

Description

Pixel driving circuit and its driving method, display substrate Technical Field

[0001] This disclosure relates to, but is not limited to, the display field, specifically to a pixel driving circuit and its driving method, and a display substrate. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a pixel driving circuit and driving method thereof, and a display substrate.

[0005] In a first aspect, this disclosure provides a pixel driving circuit configured to drive a light-emitting device to emit light, comprising: a driving sub-circuit, an isolation sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit;

[0006] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node.

[0007] The isolation sub-circuit is electrically connected to the second scanning signal terminal, the first node, the third node, and the fifth node, respectively. It is configured to connect or disconnect the third node and the fifth node under the control of the signal at the second scanning signal terminal, and to store the voltage difference between the signals of the first node and the fifth node.

[0008] The first control sub-circuit is electrically connected to the first scan signal terminal, the data signal terminal, and the first node, respectively, and is configured to provide the data signal terminal to the first node under the control of the signal from the first scan signal terminal.

[0009] The second control sub-circuit is electrically connected to at least one reset signal terminal, at least one initial signal terminal, a second node, a fourth node, and one of the third and fifth nodes, respectively, and is configured to provide a signal from at least one initial signal terminal to one of the second node, the fourth node, and one of the third and fifth nodes, respectively, under the control of the signal from at least one reset signal terminal.

[0010] The third control sub-circuit is electrically connected to the light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively, and is configured to provide the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node under the control of the signal from the light-emitting signal terminal.

[0011] The light-emitting device is electrically connected to the fourth node and the second power supply terminal, respectively.

[0012] In an exemplary embodiment, it further includes: a fourth control sub-circuit;

[0013] When the second control sub-circuit is electrically connected to the fifth node, the fourth control sub-circuit is electrically connected to the first node and the first power supply terminal respectively, and is configured to store the voltage difference between the signals of the first node and the first power supply terminal.

[0014] When the second control sub-circuit is electrically connected to the third node, the fourth control sub-circuit is electrically connected to the fifth node and the second power supply terminal respectively, and is configured to store the voltage difference between the signals of the fifth node and the second power supply terminal.

[0015] In an exemplary embodiment, the isolation sub-circuit includes: a second transistor and a first capacitor, the first capacitor including: a first plate and a second plate;

[0016] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node.

[0017] The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the fifth node.

[0018] In an exemplary embodiment, the first control sub-circuit is also electrically connected to the fourth reset signal terminal and the reference signal terminal respectively, and is configured to provide the reference signal terminal to the first node under the control of the signal of the fourth reset signal terminal;

[0019] The first control sub-circuit includes: a fourth transistor and an eighth transistor;

[0020] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node.

[0021] The control terminal of the eighth transistor is electrically connected to the fourth reset signal terminal, the first terminal of the eighth transistor is electrically connected to the reference signal terminal, and the second terminal of the eighth transistor is electrically connected to the first node.

[0022] In an exemplary embodiment, the at least one reset signal terminal includes: a first reset signal terminal, a second reset signal terminal, and a third reset signal terminal; the at least one initial signal terminal includes: a first initial signal terminal, a second initial signal terminal, and a third initial signal terminal.

[0023] The second control sub-circuit is configured to provide a signal from a third initial signal terminal to a second node, a signal from a first initial signal terminal to one of the third and fifth nodes, and a signal from a second initial signal terminal to a fourth node;

[0024] When the second control sub-circuit is electrically connected to the fifth node, the second control sub-circuit includes: a first transistor, a seventh transistor, and a ninth transistor;

[0025] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the fifth node.

[0026] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0027] The control terminal of the ninth transistor is electrically connected to the third reset signal terminal, the first terminal of the ninth transistor is electrically connected to the third initial signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node.

[0028] In an exemplary embodiment, the at least one reset signal terminal includes: a first reset signal terminal, a second reset signal terminal, and a third reset signal terminal; the at least one initial signal terminal includes: a first initial signal terminal, a second initial signal terminal, and a third initial signal terminal.

[0029] The second control sub-circuit is configured to provide a signal from a third initial signal terminal to a second node, a signal from a first initial signal terminal to one of the third and fifth nodes, and a signal from a second initial signal terminal to a fourth node;

[0030] When the second control sub-circuit is electrically connected to the third node, the second control sub-circuit includes: a first transistor, a seventh transistor, and a ninth transistor;

[0031] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0032] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0033] The control terminal of the ninth transistor is electrically connected to the third reset signal terminal, the first terminal of the ninth transistor is electrically connected to the third initial signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node.

[0034] In an exemplary embodiment, the fourth control sub-circuit includes: a second capacitor, which includes: a first plate and a second plate;

[0035] When the second control sub-circuit is electrically connected to the fifth node, the first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.

[0036] When the second control sub-circuit is electrically connected to the third node, the first plate of the second capacitor is electrically connected to the fifth node, and the second plate of the second capacitor is electrically connected to the second power supply terminal.

[0037] In an exemplary embodiment, the first control sub-circuit is further electrically connected to a fourth reset signal terminal and a reference signal terminal, respectively. The at least one reset signal terminal includes a first reset signal terminal, a second reset signal terminal, and a third reset signal terminal. The at least one initial signal terminal includes a first initial signal terminal, a second initial signal terminal, and a third initial signal terminal. When the second control sub-circuit is electrically connected to the fifth node, the pixel driving circuit further includes a fourth control sub-circuit, wherein the driving sub-circuit includes a third transistor, the isolation sub-circuit includes a second transistor and a first capacitor, the first control sub-circuit includes a fourth transistor and an eighth transistor, the second control sub-circuit includes a first transistor, a seventh transistor, and a ninth transistor, and the third control sub-circuit includes a fifth transistor and a sixth transistor. The fourth control sub-circuit includes a second capacitor, and the first and second capacitors include a first electrode and a second electrode.

[0038] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the fifth node.

[0039] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node.

[0040] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0041] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node.

[0042] The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0043] The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0044] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0045] The control terminal of the eighth transistor is electrically connected to the fourth reset signal terminal, the first terminal of the eighth transistor is electrically connected to the data signal terminal, and the second terminal of the eighth transistor is electrically connected to the first node.

[0046] The control terminal of the ninth transistor is electrically connected to the third reset signal terminal, the first terminal of the ninth transistor is electrically connected to the third initial signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node.

[0047] The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the fifth node.

[0048] The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.

[0049] In an exemplary embodiment, for the same pixel driving circuit, the signal received by the first initial signal terminal is the same as the signal received by the second power supply terminal, and the signal received by the second reset signal terminal is the same as the signal received by the fourth reset signal terminal.

[0050] In at least one display frame, the duration of the time period in which the second reset signal terminal receives the valid level signal is the same as the duration of the time period in which the third reset signal terminal receives the valid level signal, and the duration of the time period in which the first reset signal terminal receives the valid level signal is the same as the duration of the time period in which the first scan signal terminal receives the valid level signal.

[0051] In an exemplary embodiment, for the same pixel driving circuit, the time period in which the signal of at least one of the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the fourth reset signal terminal, and the first scan signal terminal is an effective level signal is located within the time period in which the signal of the second scan signal terminal is an effective level signal.

[0052] The start time of the period in which the signal at the second reset signal terminal is at an effective level is earlier than the start time of the period in which the signal at the third reset signal terminal is at an effective level, and the end time of the period in which the signal at the second reset signal terminal is at an effective level is within the period in which the signal at the third reset signal terminal is at an effective level.

[0053] The start time of the period in which the signal at the first reset signal terminal is at an effective level is later than the start time of the period in which the signal at the second reset signal terminal is at an effective level, and earlier than the start time of the period in which the signal at the third reset signal terminal is at an effective level.

[0054] The time period during which the signal at the first scan signal terminal is at an effective level is after the time period during which the signal at the third reset signal terminal is at an effective level.

[0055] In an exemplary embodiment, the first control sub-circuit is further electrically connected to a fourth reset signal terminal and a reference signal terminal, respectively. The at least one reset signal terminal includes a first reset signal terminal, a second reset signal terminal, and a third reset signal terminal. The at least one initial signal terminal includes a first initial signal terminal, a second initial signal terminal, and a third initial signal terminal. When the second control sub-circuit is electrically connected to the third node, the pixel driving circuit further includes a fourth control sub-circuit, wherein the driving sub-circuit includes a third transistor, the isolation sub-circuit includes a second transistor and a first capacitor, the first control sub-circuit includes a fourth transistor and an eighth transistor, the second control sub-circuit includes a first transistor, a seventh transistor, and a ninth transistor, and the third control sub-circuit includes a fifth transistor and a sixth transistor. The fourth control sub-circuit includes a second capacitor, and the first and second capacitors include a first electrode and a second electrode.

[0056] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0057] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node.

[0058] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0059] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node.

[0060] The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0061] The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0062] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0063] The control terminal of the eighth transistor is electrically connected to the fourth reset signal terminal, the first terminal of the eighth transistor is electrically connected to the data signal terminal, and the second terminal of the eighth transistor is electrically connected to the first node.

[0064] The control terminal of the ninth transistor is electrically connected to the third reset signal terminal, the first terminal of the ninth transistor is electrically connected to the third initial signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node.

[0065] The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the fifth node.

[0066] The first plate of the second capacitor is electrically connected to the fifth node, and the second plate of the second capacitor is electrically connected to the second power supply terminal.

[0067] In an exemplary embodiment, for the same pixel driving circuit, the signal received by the first reset signal terminal and the signal received by the second reset signal terminal are the same.

[0068] In an exemplary embodiment, for the same pixel driving circuit, the time period in which the signal of at least one of the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the fourth reset signal terminal, and the first scan signal terminal is an effective level signal is located within the time period in which the signal of the second scan signal terminal is an effective level signal.

[0069] The time period in which the signal of at least one of the first reset signal terminal, the second reset signal terminal, and the third reset signal terminal is at an effective level is within the time period in which the signal of the fourth scan signal terminal is at an effective level, and the end time of the time period in which the signal of the first reset signal terminal is at an effective level is earlier than the start time of the time period in which the signal of the third reset signal terminal is at an effective level.

[0070] The time period during which the signal at the first scan signal terminal is at an effective level is after the time period during which the signal at the fourth scan signal terminal is at an effective level.

[0071] In an exemplary embodiment, for the same pixel driving circuit, the end time of the signal at the second scanning signal terminal being at an effective level is within the time period in which the signal at the light-emitting signal terminal is at an effective level, or the end time of the signal at the second scanning signal terminal being at an effective level is earlier than the start time of the time period in which the signal at the light-emitting signal terminal is at an effective level.

[0072] In an exemplary embodiment, at least one of the first to ninth transistors is an oxide transistor.

[0073] In a second aspect, this disclosure also provides a display substrate, including: a substrate and a plurality of the above-mentioned pixel driving circuits and a plurality of light-emitting devices arranged in an array on the substrate, wherein at least one of the plurality of light-emitting devices includes: an anode and a cathode, and at least one pixel driving circuit is electrically connected to the anode of at least one light-emitting device.

[0074] When the second control sub-circuit in the pixel driving circuit is electrically connected to the fifth node, the display substrate further includes: multiple first initial signal lines;

[0075] At least one of the plurality of first initial signal lines is electrically connected to a first initial signal terminal in at least one pixel driving circuit, and extends at least partially along the second direction;

[0076] At least one of the multiple first initial signal lines is electrically connected to the cathode of at least one light-emitting device.

[0077] In an exemplary embodiment, one of the plurality of first initial signal lines includes: a plurality of initial signal traces and a plurality of initial connection portions, wherein the plurality of initial signal traces and the plurality of initial connection portions are alternately arranged and interconnected with each other;

[0078] At least one of the plurality of initial signal traces extends at least partially along the second direction, and at least one of the plurality of initial connection portions extends at least partially along the second direction;

[0079] The display substrate further includes: a plurality of initial vias, at least one of the plurality of initial vias exposing at least one initial connection portion of a plurality of initial connection portions, and the cathode of at least one light-emitting device is connected to one of a plurality of first initial signal lines through at least one initial via;

[0080] At least one of the multiple initial connection portions has a linewidth along a first direction that is greater than the linewidth of at least one of the multiple initial signal traces along the first direction, and the first direction intersects with the second direction.

[0081] In an exemplary embodiment, it also includes: a plurality of initial connection lines;

[0082] At least one of the plurality of initial connection lines is electrically connected to the plurality of first initial signal lines and extends at least partially along the first direction.

[0083] In an exemplary embodiment, it further includes: multiple first power lines, and the pixel driving circuit includes: a first capacitor and a second capacitor;

[0084] At least one of the plurality of first power lines is electrically connected to a first power terminal in at least one pixel driving circuit, and extends at least partially along the second direction;

[0085] At least one of the multiple first power lines includes: a power main line and multiple power protrusions; the power main line is connected to the multiple power protrusions, and the multiple power protrusions are spaced apart;

[0086] The orthographic projection of at least one of the plurality of power supply protrusions on the substrate at least partially overlaps with the orthographic projection of at least one of the first and second capacitors in at least one pixel driving circuit on the substrate.

[0087] In an exemplary embodiment, the pixel driving circuit includes: a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor include: a first electrode plate and a second electrode plate;

[0088] The orthographic projection of the first capacitor on the substrate and the orthographic projection of the second capacitor on the substrate at least partially overlap, and at least one plate of the first capacitor and at least one plate of the second capacitor are the same plate.

[0089] In an exemplary embodiment, it further includes: multiple first scan signal lines, multiple second scan signal lines, multiple light emission signal lines, multiple first reset signal lines, multiple second reset signal lines, multiple third reset signal lines, and multiple fourth reset signal lines;

[0090] At least one of the following signals—a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of light emission signal lines, a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of third reset signal lines, and a plurality of fourth reset signal lines—extends at least partially along a first direction;

[0091] At least one of the plurality of first scan signal lines is electrically connected to the first scan signal terminal of at least one pixel driving circuit; at least one of the plurality of second scan signal lines is electrically connected to the second scan signal terminal of at least one pixel driving circuit; at least one of the plurality of light emission signal lines is electrically connected to the light emission signal terminal of at least one pixel driving circuit; at least one of the plurality of first reset signal lines is electrically connected to the first reset signal terminal of at least one pixel driving circuit; at least one of the plurality of second reset signal lines is electrically connected to the second reset signal terminal of at least one pixel driving circuit; at least one of the plurality of third reset signal lines is electrically connected to the third reset signal terminal of at least one pixel driving circuit; and at least one of the plurality of fourth reset signal lines is electrically connected to the fourth reset signal terminal of at least one pixel driving circuit.

[0092] The second reset signal line connected to the pixel driving circuit in row m is the same signal line as the fourth reset signal line connected to the pixel driving circuit in row (m-1).

[0093] The second reset signal line, the light emission signal line, the third reset signal line, the second scan signal line, the first scan signal line, the first reset signal line, and the fourth reset signal line connected to at least one pixel driving circuit are arranged sequentially along the second direction.

[0094] In an exemplary embodiment, it further includes: a plurality of second initial signal lines and a plurality of third initial signal lines;

[0095] At least one of the plurality of second initial signal lines is electrically connected to the second initial signal terminal of at least one pixel driving circuit, and extends at least partially along the first direction;

[0096] At least one of the plurality of third initial signal lines is electrically connected to the third initial signal terminal of at least one pixel driving circuit, and extends at least partially along the first direction;

[0097] The orthographic projection of the second initial signal line connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line on the substrate, and the orthographic projection of the third initial signal line connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the light emission signal line on the substrate.

[0098] In an exemplary embodiment, the system further includes: multiple first initial signal lines, multiple second initial signal lines, multiple third initial signal lines, multiple first scan signal lines, multiple second scan signal lines, multiple light emission signal lines, multiple first reset signal lines, multiple second reset signal lines, multiple third reset signal lines, multiple fourth reset signal lines, multiple data signal lines, multiple first power supply lines, and multiple reference signal lines. The pixel driving circuit includes: multiple transistors, a first capacitor, and a second capacitor. The first capacitor and the second capacitor include: a first electrode plate and a second electrode plate.

[0099] The display substrate further includes: a circuit structure layer disposed on the substrate, the circuit structure layer including: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate;

[0100] The first conductive layer includes at least: the second electrode of the first capacitor;

[0101] The semiconductor layer includes at least: an active pattern of at least one transistor among a plurality of transistors in at least one pixel driving circuit;

[0102] The second conductive layer includes at least: multiple first scan signal lines, multiple second scan signal lines, multiple light emission signal lines, multiple first reset signal lines, multiple second reset signal lines, multiple third reset signal lines, multiple fourth reset signal lines, the control electrode of at least one transistor of at least one pixel driving circuit, the first electrode of a first capacitor, and the first electrode of a second capacitor.

[0103] The third conductive layer includes at least: multiple second initial signal lines, multiple third initial signal lines, and the first and second terminals of at least one transistor of at least one pixel driving circuit, as well as the second plate of the second capacitor;

[0104] The fourth conductive layer includes at least: multiple data signal lines, multiple reference signal lines, multiple first power lines, and multiple first initial signal lines.

[0105] In an exemplary embodiment, it also includes: a plurality of initial connection lines;

[0106] Multiple initial connection lines are located in at least one of the first conductive layer, the second conductive layer, and the third conductive layer.

[0107] Thirdly, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit, the method comprising:

[0108] The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes;

[0109] The isolation sub-circuit, under the control of the signal at the second scanning signal terminal, connects or disconnects the third and fifth nodes, and stores the voltage difference between the signals of the first and fifth nodes;

[0110] The first control sub-circuit provides the data signal terminal signal to the first node under the control of the signal at the first scan signal terminal;

[0111] Under the control of at least one reset signal terminal, the second control sub-circuit provides at least one initial signal terminal signal to one of the second node, the fourth node, the third node, and the fifth node, respectively.

[0112] Under the control of the signal at the light-emitting signal terminal, the third control sub-circuit provides the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node.

[0113] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0114] Overview of the attached figures

[0115] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0116] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0117] Figure 2 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure.

[0118] Figure 3 shows the equivalent circuit diagram of the isolation sub-circuit;

[0119] Figure 4 is the equivalent circuit diagram of the first control sub-circuit;

[0120] Figure 5 shows the equivalent circuit diagram of the second control sub-circuit.

[0121] Figure 6 is the equivalent circuit diagram of the second control sub-circuit;

[0122] Figure 7 shows the equivalent circuit diagram of the fourth control sub-circuit.

[0123] Figure 8 shows the equivalent circuit diagram of the fourth control sub-circuit (II).

[0124] Figure 9 shows the equivalent circuit diagram of the driving sub-circuit and the third control sub-circuit;

[0125] Figure 10 is an equivalent circuit diagram of a pixel driving circuit;

[0126] Figure 11 is a timing diagram of the pixel driving circuit provided in Figure 10;

[0127] Figure 12 shows the equivalent circuit diagram of another pixel driving circuit;

[0128] Figure 13 is a timing diagram of the pixel driving circuit provided in Figure 12;

[0129] Figure 14 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0130] Figure 15 is a schematic diagram of the connection of the first initial signal line;

[0131] Figure 16 is a schematic diagram of the pattern of the first conductive layer;

[0132] Figure 17 is a schematic diagram of the semiconductor layer pattern;

[0133] Figure 18 is a schematic diagram after the semiconductor layer pattern has been formed;

[0134] Figure 19 is a schematic diagram of the pattern of the second conductive layer;

[0135] Figure 20 is a schematic diagram after the formation of the second conductive layer pattern;

[0136] Figure 21 is a schematic diagram after the formation of the third insulating layer pattern;

[0137] Figure 22 is a schematic diagram of the pattern of the third conductive layer;

[0138] Figure 23 is a schematic diagram after the formation of the third conductive layer pattern;

[0139] Figure 24 is a schematic diagram after the formation of the first planarization layer pattern;

[0140] Figure 25 is a schematic diagram of the pattern of the fourth conductive layer;

[0141] Figure 26 is a schematic diagram after the formation of the fourth conductive layer pattern;

[0142] Figure 27 is a schematic diagram after the formation of the second planarization layer pattern;

[0143] Figure 28 is a schematic diagram of the pattern of the fifth conductive layer;

[0144] Figure 29 is a schematic diagram after the formation of the fifth conductive layer pattern;

[0145] Figure 30 is a schematic diagram after the pixel definition layer pattern is formed.

[0146] Detailed Explanation

[0147] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0148] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0149] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0150] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0151] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0152] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0153] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0154] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0155] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0156] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0157] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0158] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0159] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0160] The pixel driving circuit is configured to drive a light-emitting device to emit light. The pixel driving circuit includes a driving transistor. The operation of the pixel driving circuit includes an emission stage, during which the light-emitting device emits light. During the emission stage, the gate electrode of the driving transistor in the pixel driving circuit is affected by the anode of the light-emitting device, causing signal instability at the gate electrode of the driving transistor and reducing the reliability of the pixel driving circuit.

[0161] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure, and Figure 2 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. As shown in Figures 1 and 2, an embodiment of this disclosure provides a pixel driving circuit configured to drive a light-emitting device L to emit light, including: a driving sub-circuit, an isolation sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit.

[0162] As shown in Figures 1 and 2, the driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2.

[0163] As shown in Figures 1 and 2, the isolation sub-circuit is electrically connected to the second scanning signal terminal Gate2, the first node N1, the third node N3, and the fifth node N5, respectively. It is configured to connect or disconnect the third node N3 and the fifth node N5 under the control of the signal of the second scanning signal terminal Gate2, and to store the voltage difference between the signals of the first node N1 and the fifth node N5.

[0164] As shown in Figures 1 and 2, the first control sub-circuit is electrically connected to the first scan signal terminal Gate1, the data signal terminal Data, and the first node N1, respectively, and is configured to provide the data signal terminal Data to the first node N1 under the control of the signal from the first scan signal terminal Gate1.

[0165] As shown in Figures 1 and 2, the second control subcircuit is electrically connected to at least one reset signal terminal, at least one initial signal terminal, one of the following nodes: second node N2, fourth node N4, third node N3, and fifth node N5. It is configured to provide a signal from at least one initial signal terminal to one of the following nodes, respectively, under the control of the signal from at least one reset signal terminal. Figure 1 illustrates the second control subcircuit with the fifth node N5 as an example, and Figure 2 illustrates the second control subcircuit with the third node N3 as an example.

[0166] As shown in Figures 1 and 2, the third control sub-circuit is electrically connected to the light-emitting signal terminal EM, the first power supply terminal VDD, the second node N2, the third node N3, and the fourth node N4, respectively. It is configured to provide the first power supply terminal VDD signal to the second node N2 and the third node N3 signal to the fourth node N4 under the control of the light-emitting signal terminal EM.

[0167] As shown in Figures 1 and 2, the light-emitting device L is electrically connected to the fourth node N4 and the second power supply terminal VSS, respectively.

[0168] In an exemplary embodiment, the first power supply terminal VDD continuously provides a high-level signal, and the second power supply terminal VSS continuously provides a low-level signal.

[0169] In an exemplary embodiment, the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0170] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0171] In an exemplary embodiment, the light-emitting device L may include a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). Exemplarily, the first electrode of the light-emitting device is electrically connected to the fourth node N4 in the pixel driving circuit, and the second electrode of the light-emitting device is electrically connected to the second power supply terminal VSS.

[0172] This disclosure, by setting an isolation sub-circuit, can disconnect the third node and the fifth node when the pixel driving circuit drives the light-emitting device to emit light, thereby reducing the influence of the fifth node on the first node through the third node when the light-emitting device emits light, ensuring the stability of the signal of the first node in the pixel driving circuit, and improving the reliability of the pixel driving circuit.

[0173] In an exemplary embodiment, as shown in FIG1, the pixel driving circuit may further include a fourth control sub-circuit. When the second control sub-circuit is electrically connected to the fifth node N5, the fourth control sub-circuit is electrically connected to the first node N1 and the first power supply terminal VDD, respectively, and is configured to store the voltage difference between the signals of the first node N1 and the first power supply terminal VDD.

[0174] In an exemplary embodiment, as shown in FIG2, the pixel driving circuit may further include a fourth control sub-circuit. When the second control sub-circuit is electrically connected to the third node N3, the fourth control sub-circuit is electrically connected to the fifth node N5 and the second power supply terminal VSS, respectively, and is configured to store the voltage difference between the signals of the fifth node N5 and the second power supply terminal VSS.

[0175] In an exemplary embodiment, FIG3 is an equivalent circuit diagram of the isolation sub-circuit. As shown in FIG3, the isolation sub-circuit includes a second transistor T2 and a first capacitor C1, wherein the first capacitor C1 includes a first plate and a second plate. FIG3 is illustrated using the second control sub-circuit and the fifth node N5 as an example.

[0176] As shown in Figure 3, the control terminal of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first terminal of the second transistor T2 is electrically connected to the fifth node N5, and the second terminal of the second transistor T2 is electrically connected to the third node N3; the first plate C11 of the first capacitor C1 is electrically connected to the first node N1, and the second plate C12 of the first capacitor C1 is electrically connected to the fifth node N5.

[0177] In an exemplary embodiment, as shown in Figures 1 and 2, the first control sub-circuit is also electrically connected to the fourth reset signal terminal Reset4 and the reference signal terminal REF, respectively, and is configured to provide the reference signal terminal REF to the first node N1 under the control of the signal of the fourth reset signal terminal Reset4.

[0178] In an exemplary embodiment, FIG4 is an equivalent circuit diagram of the first control sub-circuit. As shown in FIG4, the first control sub-circuit includes a fourth transistor T4 and an eighth transistor T8. FIG4 is illustrated using the second control sub-circuit and the fifth node N5 as an example.

[0179] As shown in Figure 4, the control terminal of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first terminal of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of the fourth transistor T4 is electrically connected to the first node N1; the control terminal of the eighth transistor T8 is electrically connected to the fourth reset signal terminal Reset4, the first terminal of the eighth transistor T8 is electrically connected to the reference signal terminal REF, and the second terminal of the eighth transistor T8 is electrically connected to the first node N1.

[0180] In an exemplary embodiment, as shown in Figures 1 and 2, at least one reset signal terminal includes: a first reset signal terminal Reset1, a second reset signal terminal Reset2, and a third reset signal terminal Reset3; and at least one initial signal terminal includes: a first initial signal terminal INIT1, a second initial signal terminal INIT2, and a third initial signal terminal INIT3. A second control sub-circuit is configured to provide the signal of the third initial signal terminal INIT3 to a second node N2, to one of the third node N3 and the fifth node N5, and to provide the signal of the second initial signal terminal INIT2 to a fourth node N4.

[0181] In an exemplary embodiment, Figure 5 is an equivalent circuit diagram of the second control sub-circuit. As shown in Figure 5, when the second control sub-circuit is electrically connected to the fifth node N5, the second control sub-circuit includes: a first transistor T1, a seventh transistor T7, and a ninth transistor T9. Specifically, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal INIT1, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the third reset signal terminal Reset3, the first electrode of the ninth transistor T9 is electrically connected to the third initial signal terminal INIT3, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2.

[0182] In an exemplary embodiment, Figure 6 is an equivalent circuit diagram of the second control sub-circuit. As shown in Figure 6, when the second control sub-circuit is electrically connected to the third node N3, the second control sub-circuit includes: a first transistor T1, a seventh transistor T7, and a ninth transistor T9. Specifically, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the third reset signal terminal Reset3, the first electrode of the ninth transistor T9 is electrically connected to the third initial signal terminal INIT3, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2.

[0183] In an exemplary embodiment, the voltage value of the signal at at least one of the first initial signal terminal INIT1, the second initial signal terminal INIT2, the third initial signal terminal INIT3, and the reference signal terminal REF is constant, and it is a DC signal. In an exemplary embodiment, the DC signal may be one in which neither the magnitude nor the direction of the signal changes with time.

[0184] In an exemplary embodiment, Figure 7 is an equivalent circuit diagram of the fourth control sub-circuit. As shown in Figure 7, when the second control sub-circuit is electrically connected to the fifth node N5, the fourth control sub-circuit includes a second capacitor C2, which includes a first plate and a second plate. Specifically, the first plate C21 of the second capacitor C2 is electrically connected to the first node N1, and the second plate C22 of the second capacitor C2 is electrically connected to the first power supply terminal VDD.

[0185] In an exemplary embodiment, Figure 8 is an equivalent circuit diagram of the fourth control sub-circuit. As shown in Figure 8, when the second control sub-circuit is electrically connected to the third node N3, the fourth control sub-circuit includes a second capacitor C2, which includes a first plate and a second plate. The first plate C21 of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate C22 of the second capacitor C2 is electrically connected to the second power supply terminal VSS.

[0186] In an exemplary embodiment, FIG9 is an equivalent circuit diagram of the driving sub-circuit and the third control sub-circuit. As shown in FIG9, the driving sub-circuit includes a third transistor T3, and the third control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. FIG9 is illustrated using the second control sub-circuit and the fifth node N5 as an example.

[0187] As shown in Figure 9, the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the light-emitting signal terminal EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the light-emitting signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0188] The third transistor, T3, can be called the driving transistor. The fifth transistor, T5, and the sixth transistor, T6, can be called light-emitting transistors.

[0189] The pixel driving circuit in this disclosure is disposed in a display substrate. The display substrate may include a display area and a non-display area. The pixel driving circuit is located in the display area. The non-display area is provided with at least one driving circuit, which is configured to provide signals to a first reset signal terminal Reset1, a second reset signal terminal Reset2, a third reset signal terminal Reset3, a fourth reset signal terminal Reset4, a first scan signal terminal Gate1, a second scan signal terminal Gate2, and a light emission signal terminal EM connected to the pixel driving circuit.

[0190] In an exemplary embodiment, FIG10 is an equivalent circuit diagram of a pixel driving circuit. As shown in FIG10, when the second control sub-circuit is electrically connected to the fifth node N5, the driving sub-circuit in the pixel driving circuit includes: a third transistor T3; the isolation sub-circuit includes: a second transistor T2 and a first capacitor C1; the first control sub-circuit includes: a fourth transistor T4 and an eighth transistor T8; the second control sub-circuit includes: a first transistor T1, a seventh transistor T7 and a ninth transistor T9; the third control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6; the fourth control sub-circuit includes: a second capacitor C2; the first capacitor C1 and the second capacitor C2 include: a first electrode and a second electrode.

[0191] As shown in Figure 10, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first terminal of the first transistor T1 is electrically connected to the first initial signal terminal INIT1, and the second terminal of the first transistor T1 is electrically connected to the fifth node N5; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first terminal of the second transistor T2 is electrically connected to the fifth node N5, and the second terminal of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first terminal of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of the fourth transistor T4 is electrically connected to the first node N1; the control electrode of the fifth transistor T5 is electrically connected to the light emission signal terminal EM, the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the light emission signal terminal... The EM terminal is electrically connected; the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4; the control terminal of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, and the first terminal of the seventh transistor T7 is electrically connected to the second initial signal terminal INIT2; the second terminal of the seventh transistor T7 is electrically connected to the fourth node N4; the control terminal of the eighth transistor T8 is electrically connected to the fourth reset signal terminal Reset4, and the first terminal of the eighth transistor T8 is electrically connected to the data signal terminal Data. The first terminal of the ninth transistor T9 is electrically connected to the first node N1; the control terminal of the ninth transistor T9 is electrically connected to the third reset signal terminal Reset3; the first terminal of the ninth transistor T9 is electrically connected to the third initial signal terminal INIT3; the second terminal of the ninth transistor T9 is electrically connected to the second node N2; the first plate C11 of the first capacitor C1 is electrically connected to the first node N1; the second plate C12 of the first capacitor C1 is electrically connected to the fifth node N5; the first plate C21 of the second capacitor C2 is electrically connected to the first node N1; the second plate C22 of the second capacitor C2 is electrically connected to the first power supply terminal VDD.

[0192] Figure 11 is a timing diagram of the pixel driving circuit provided in Figure 10. As shown in Figure 11, for the pixel driving circuit provided in Figure 10, the signal received by the first initial signal terminal INIT1 is the same as the signal received by the second power supply terminal VSS, and the signal received by the second reset signal terminal Reset2 is the same as the signal received by the fourth reset signal terminal Reset4. Figure 10 is illustrated using the example where the first initial signal terminal INIT1 and the second power supply terminal VSS are the same signal terminal.

[0193] As shown in Figure 11, in at least one display frame, the duration of the time period in which the second reset signal terminal Reset2 receives a valid level signal is the same as the duration of the time period in which the third reset signal terminal Reset3 receives a valid level signal. In this disclosure, the driving circuit that provides the signal to the second reset signal terminal Reset2 and the driving circuit that provides the signal to the third reset signal terminal Reset3 can be the same driving circuit.

[0194] As shown in Figure 11, the duration of the time period during which the first reset signal terminal Reset1 receives a valid level signal is the same as the duration of the time period during which the first scan signal terminal Gate1 receives a valid level signal. In this disclosure, the driving circuit that provides the signal to the first reset signal terminal Reset1 and the driving circuit that provides the signal to the first scan signal terminal Gate1 can be the same driving circuit.

[0195] As shown in Figure 11, in an exemplary embodiment, the duration of the time period in which at least one of the second reset signal terminal Reset2 and the third reset signal terminal Reset3 receives an effective level signal is longer than the duration of the time period in which at least one of the first reset signal terminal Reset1 and the first scan signal terminal Gate1 receives an effective level signal.

[0196] As shown in Figure 11, in an exemplary embodiment, for the same pixel driving circuit, the time period in which the signals of at least one of the first reset signal terminal Reset1, the second reset signal terminal Reset2, the third reset signal terminal Reset3, the fourth reset signal terminal Reset4, and the first scan signal terminal Gate1 are at an effective level is located within the time period in which the signal of the second scan signal terminal Gate2 is at an effective level.

[0197] As shown in Figure 11, the start time of the time period in which the signal of the second reset signal terminal Reset2 is at an effective level is earlier than the start time of the time period in which the signal of the third reset signal terminal Reset3 is at an effective level, and the end time of the time period in which the signal of the second reset signal terminal Reset2 is at an effective level is within the time period in which the signal of the third reset signal terminal Reset3 is at an effective level.

[0198] As shown in Figure 11, the start time of the time period in which the signal of the first reset signal terminal Reset1 is at an effective level is later than the start time of the time period in which the signal of the second reset signal terminal Reset2 is at an effective level, and earlier than the start time of the time period in which the signal of the third reset signal terminal Reset3 is at an effective level.

[0199] As shown in Figure 11, the time period in which the signal at the first scan signal terminal Gate1 is at an effective level is after the time period in which the signal at the third reset signal terminal Reset3 is at an effective level.

[0200] The display substrate including the pixel driving circuit shown in FIG10 may include: a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit. The first driving circuit is configured to provide signals to the light-emitting signal terminal of at least one pixel driving circuit; the second driving circuit is configured to provide signals to the second scan signal terminal of at least one pixel driving circuit; the third driving circuit is configured to provide signals to the second, third, and fourth reset signal terminals of at least one pixel driving circuit; and the fourth driving circuit is configured to provide signals to the first reset signal terminal and the first scan signal terminal of at least one pixel driving circuit.

[0201] In an exemplary embodiment, FIG12 is an equivalent circuit diagram of another pixel driving circuit. As shown in FIG12, when the second control sub-circuit is electrically connected to the third node N3, the driving sub-circuit in the pixel driving circuit includes: a third transistor T3; the isolation sub-circuit includes: a second transistor T2 and a first capacitor C1; the first control sub-circuit includes: a fourth transistor T4 and an eighth transistor T8; the second control sub-circuit includes: a first transistor T1, a seventh transistor T7 and a ninth transistor T9; the third control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6; the fourth control sub-circuit includes: a second capacitor C2; and the first capacitor C1 and the second capacitor C2 include: a first electrode and a second electrode.

[0202] As shown in Figure 12, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first terminal of the first transistor T1 is electrically connected to the first initial signal terminal INIT1, and the second terminal of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first terminal of the second transistor T2 is electrically connected to the fifth node N5, and the second terminal of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first terminal of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of the fourth transistor T4 is electrically connected to the first node N1; the control electrode of the fifth transistor T5 is electrically connected to the light emission signal terminal EM, the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the light emission signal terminal EM; ... second terminal of the sixth transistor T6 is electrically connected to The EM terminal is electrically connected; the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4; the control terminal of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, and the first terminal of the seventh transistor T7 is electrically connected to the second initial signal terminal INIT2; the second terminal of the seventh transistor T7 is electrically connected to the fourth node N4; the control terminal of the eighth transistor T8 is electrically connected to the fourth reset signal terminal Reset4, and the first terminal of the eighth transistor T8 is electrically connected to the data signal terminal Data. The first terminal of the ninth transistor T9 is electrically connected to the first node N1; the control terminal of the ninth transistor T9 is electrically connected to the third reset signal terminal Reset3; the first terminal of the ninth transistor T9 is electrically connected to the third initial signal terminal INIT3; the second terminal of the ninth transistor T9 is electrically connected to the second node N2; the first plate C11 of the first capacitor C1 is electrically connected to the first node N1; the second plate C12 of the first capacitor C1 is electrically connected to the fifth node N5; the first plate C21 of the second capacitor C2 is electrically connected to the fifth node N5; the second plate C22 of the second capacitor C2 is electrically connected to the second power supply terminal VSS.

[0203] In an exemplary embodiment, FIG13 is a driving timing diagram of the pixel driving circuit provided in FIG12. As shown in FIG13, for the same pixel driving circuit, the signal received by the first reset signal terminal Reset1 and the signal received by the second reset signal terminal Reset2 are the same.

[0204] In an exemplary embodiment, as shown in FIG13, for the same pixel driving circuit, the time period in which the signal of at least one of the first reset signal terminal Reset1, the second reset signal terminal Reset2, the third reset signal terminal Reset3, the fourth reset signal terminal Reset4 and the first scan signal terminal Gate1 is at an effective level is located within the time period in which the signal of the second scan signal terminal Gate2 is at an effective level.

[0205] As shown in Figure 13, the time period in which the signal of at least one of the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the third reset signal terminal Reset3 is at an effective level is within the time period in which the signal of the fourth scan signal terminal is at an effective level, and the end time of the time period in which the signal of the first reset signal terminal Reset1 is at an effective level is earlier than the start time of the time period in which the signal of the third reset signal terminal Reset3 is at an effective level.

[0206] As shown in Figure 13, the time period in which the signal at the first scan signal terminal Gate1 is at an effective level is after the time period in which the signal at the fourth scan signal terminal is at an effective level.

[0207] The display substrate including the pixel driving circuit shown in FIG12 may include: a first driving circuit, a second driving circuit, a third driving circuit, a fourth driving circuit, a fifth driving circuit, and a sixth driving circuit. The first driving circuit is configured to provide a signal to the light-emitting signal terminal of at least one pixel driving circuit; the second driving circuit is configured to provide a signal to the second scan signal terminal of at least one pixel driving circuit; the third driving circuit is configured to provide signals to the first reset signal terminal and the second reset signal terminal of at least one pixel driving circuit; the fourth driving circuit is configured to provide a signal to the third reset signal terminal of at least one pixel driving circuit; the fifth driving circuit is configured to provide a signal to the fourth reset signal terminal of at least one pixel driving circuit; and the sixth driving circuit is configured to provide a signal to the first scan signal terminal of at least one pixel driving circuit.

[0208] In an exemplary embodiment, as shown in Figures 11 and 13, for the pixel driving circuits provided in Figures 10 and 12, the end time of the valid level signal at the second scanning signal terminal Gate2 is within the time period in which the valid level signal at the light-emitting signal terminal EM is located; or, the end time of the valid level signal at the second scanning signal terminal Gate2 is earlier than the start time of the time period in which the valid level signal at the light-emitting signal terminal EM is located. The phase in which the valid level signal at the light-emitting signal terminal EM is located can be referred to as the light-emitting phase.

[0209] When the signal at the second scan signal terminal Gate2 is at an active level, the second transistor T2 is turned on, and the third node N3 and the fifth node N5 are connected. When the signal at the second scan signal terminal Gate2 is at an inactive level, the second transistor T2 is turned off, and the third node N3 and the fifth node N5 are disconnected.

[0210] In this disclosure, the end time of the valid signal level of the second scanning signal terminal Gate2 is within the time period when the valid signal level of the light-emitting signal terminal EM is located. That is, during the light-emitting stage, the third node N3 and the fifth node N5 are disconnected, which can reduce the influence of the fifth node N5 on the first node N1 (the control electrode of the third transistor T3) through the third node N3. Alternatively, the end time of the valid signal level of the second scanning signal terminal Gate2 in this disclosure is earlier than the start time of the time period when the valid signal level of the light-emitting signal terminal EM is located. That is, before the light-emitting stage, the third node N3 and the fifth node N5 are disconnected, which can avoid the influence of the fifth node N5 on the first node N1 (the control electrode of the third transistor T3) through the third node N3 during the light-emitting stage, thereby improving the reliability of the pixel driving circuit.

[0211] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0212] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor, the active layer of which is made of oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current.

[0213] In an exemplary embodiment, the P-type transistor can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon, which has advantages such as high mobility and fast charging.

[0214] In an exemplary embodiment, at least one of the first transistor T1 to the ninth transistor T9 is an oxide transistor. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0215] The following describes an exemplary embodiment of this disclosure using the pixel driving circuit illustrated in FIG10. The pixel driving circuit in FIG10 includes nine transistors (first transistor T1 to ninth transistor T9) and two capacitors (first capacitor C1 and second capacitor C2). The first transistor T1 to the ninth transistor T9 are N-type transistors.

[0216] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0217] In the first stage, P11, known as the initialization stage, the signals at the second reset signal terminal Reset2, the fourth reset signal terminal Reset4, and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third reset signal terminal Reset3, and the light emission signal terminal EM are low-level signals. The first reset signal terminal Reset1 is high-level for a portion of the time. The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned off.

[0218] The first transistor T1 is turned on, and the signal at the first initial signal terminal INIT1 is written to the fifth node N5, initializing (resetting) the fifth node N5 and clearing its internal pre-stored voltage, thus completing the initialization. The second transistor T2 is turned on, and the third node N3 and the fifth node N5 are turned on. The signal at the fifth node N5 is written to the third node N3, initializing (resetting) the third node N3 and clearing its internal pre-stored voltage, thus completing the initialization. The seventh transistor T7 is turned on, and the signal at the second initial signal terminal INIT2 is written to the fourth node N4 (which is also the anode of the light-emitting device L), initializing (resetting) the fourth node N4 (which is also the anode of the light-emitting device L) and clearing its internal pre-stored voltage, thus completing the initialization. The eighth transistor T8 is turned on, and the signal at the reference signal terminal REF is written to the first node N1, initializing (resetting) the first node N1 and clearing its internal pre-stored voltage, thus completing the initialization.

[0219] In this phase, the voltage value V of the signal at the first node N1 N1 =Vref, the voltage value V of the signal at the third node N3. N3 =Vinit1, the voltage value V of the signal at the fourth node N4. N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 =Vinit1, where Vref is the voltage value of the signal at the reference signal terminal REF, Vinit1 is the voltage value of the signal at the first initial signal terminal INIT1, and Vinit2 is the voltage value of the signal at the second initial signal terminal INIT2.

[0220] In the second stage, P12, also known as the first threshold compensation stage, the signals at the second reset signal terminal Reset2, the third reset signal terminal Reset3, the fourth reset signal terminal Reset4, and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the first reset signal terminal Reset1, and the light emission signal terminal EM are low-level signals. The second transistor T2, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, while the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0221] When the seventh transistor T7 is turned on, the signal from the second initial signal terminal INIT2 is written to the fourth node N4 (which is also the anode of the light-emitting device L), initializing (resetting) the fourth node N4 (which is also the anode of the light-emitting device L), clearing its internal pre-stored voltage, and completing the initialization. When the eighth transistor T8 is turned on, the signal from the reference signal terminal REF is written to the first node N1, initializing (resetting) the first node N1, clearing its internal pre-stored voltage, and completing the initialization. When the ninth transistor T9 is turned on, the signal from the third initial signal terminal INIT3 charges the third node N3 through the turned-on third transistor T3. When the second transistor T2 is turned on, the third node N3 and the fifth node N5 are turned on, and the signal from the fifth node N5 is written to the third node N3.

[0222] In this phase, the voltage value V of the signal at the first node N1 N1 =Vref, the voltage value V of the signal at the second node N2. N2 =Vinit3, the voltage value V of the signal at the fourth node N4. N4 =Vinit2,Vinit3 is the voltage value of the signal at the third initial signal terminal INIT3.

[0223] The second phase P12 in this disclosure lasts for a short period of time and can be executed multiple times; this disclosure does not impose any limitations on this.

[0224] In the third stage, P13, also known as the second threshold compensation stage, the signals at the third reset signal terminal Reset3 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the first reset signal terminal Reset1, the second reset signal terminal Reset2, the fourth reset signal terminal Reset4, and the light emission signal terminal EM are low-level signals. The second transistor T2 and the ninth transistor T9 are turned on, while the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0225] The ninth transistor T9 remains on, and the signal at the third initial signal terminal INIT3 continuously charges the third node N3 through the on-state third transistor T3 until the voltage value of the signal at the third node N3 is Vref - Vth, where Vth is the threshold voltage of the third transistor. At this point, the voltage difference stored in the first capacitor C1 is Vth. The second transistor T2 turns on, and the third node N3 and the fifth node N5 turn on. The signal at the fifth node N5 is written into the third node N3.

[0226] In this phase, the voltage value V of the signal at the first node N1 N1 =Vref, the voltage value V of the signal at the second node N2. N2 =Vinit3, the voltage value V of the signal at the third node N3. N3 =Vref - Vth, the voltage value V of the signal at the fourth node N4. N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 =Vref-Vth.

[0227] The fourth stage, P14, is called the data writing stage. The signal at the second scan signal terminal (Gate2) is high, while the signals at the first reset signal terminal (Reset1), the second reset signal terminal (Reset2), the third reset signal terminal (Reset3), the fourth reset signal terminal (Reset4), and the light emission signal terminal (EM) are low. The signal at the first scan signal terminal (Gate1) is high for a portion of the time. The second transistor (T2) and the fourth transistor (T4) are turned on, while the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), the eighth transistor (T8), and the ninth transistor (T9) are turned off.

[0228] When the fourth transistor T4 is turned on, the data signal on the data signal line Data is written to the first node N1, that is, the signal of the first node N1 changes. Under the action of the first capacitor C1, the signal of the fifth node N5 also changes, and the voltage value of the signal of the fifth node N5 after the change is Vref-Vth+[C1 / (C1+C2)](Vdata-Vref), where Vdata is the voltage value of the data signal at the data signal terminal Data, C1 is the capacitance value of the first capacitor C1, C2 is the voltage value of the second capacitor C2, the second transistor T2 is turned on, and the third node N3 and the fifth node N5 are connected.

[0229] In this phase, the voltage value V of the signal at the first node N1 N1 =Vdata, the voltage value V of the signal at the third node N3. N3 =Vref-Vth+[C1 / (C1+C2)](Vdata-Vref), where V is the voltage value of the signal at the fourth node N4. N4 =Vinit2, the voltage value V of the signal at the fifth node N5.N5 =Vref-Vth+[C1 / (C1+C2)](Vdata-Vref).

[0230] In the fifth stage, P15, known as the isolation stage, the signal at the EM terminal is high, while the signals at the first scan signal terminal (Gate1), the first reset signal terminal (Reset1), the second reset signal terminal (Reset2), the third reset signal terminal (Reset3), and the fourth reset signal terminal (Reset4) are low. The signal at the second scan signal terminal (Gate2) changes from high to low. The second transistor T2 changes from being on to being off, the fifth transistor T5 and the sixth transistor T6 are on, and the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are off.

[0231] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power signal output from the first power supply terminal VDD provides a driving voltage to the fourth node N4 (which is also the first terminal of the light-emitting device L) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, driving the light-emitting device L to emit light. When the second transistor T2 changes from turned on to turned off, that is, the third node N3 and the fifth node N5 change from connected to disconnected. When the third node N3 and the fifth node N5 are disconnected, the signal of the fifth node N5 remains unchanged and is not affected by the third node N3. If the signal of the third node N3 remains unchanged, the signal of the first node N1 also remains unchanged under the action of the first capacitor C1.

[0232] In this phase, the voltage value V of the signal at the first node N1 N1 =Vdata, the voltage value V of the signal at the third node N3. N3 =Vref-Vth+[C1 / (C1+C2)](Vdata-Vref), where V is the voltage value of the signal at the fifth node N5. N5 =Vref-Vth+[C1 / (C1+C2)](Vdata-Vref).

[0233] During a certain period of this phase, the second transistor T2 is turned on, connecting the third node N3 and the fifth node N5. This causes a signal transition in both the third and fifth nodes. Under the influence of the first capacitor C1, the first node N1 also transitions. At this time, the signal voltage value of the first node N1 is Vdata + V N3 -[Vref-Vth+[C1 / (C1+C2)](Vdata-Vref)], therefore the drive current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*(V N1 -V N3-Vth) 2 =K*[Vdata-Vref+Vth+[C1 / (C1+C2)](Vdata-Vref)-Vth] 2 =K*[[C2 / (C1+C2)](Vdata-Vref)] 2

[0234] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3.

[0235] In the sixth stage (P16), the light-emitting stage, the signal at the light-emitting signal terminal EM is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first reset signal terminal Reset1, the second reset signal terminal Reset2, the third reset signal terminal Reset3, and the fourth reset signal terminal Reset4 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0236] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power signal output from the first power supply terminal VDD provides a driving voltage to the fourth node N4 (which is also the first terminal of the light-emitting device L) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, driving the light-emitting device L to emit light. When the second transistor T2 is turned off, that is, the third node N3 and the fifth node N5 are disconnected. When the third node N3 and the fifth node N5 are disconnected, the signal of the fifth node N5 remains unchanged and is not affected by the third node N3. If the signal of the fifth node N5 remains unchanged, the signal of the first node N1 also remains unchanged under the action of the first capacitor C1.

[0237] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode.

[0238] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0239] In the pixel driving circuit shown in Figure 10, the threshold compensation stage is independent of the data writing stage, and the threshold compensation stage is the time period during which the signal at the third reset signal terminal is at an effective level. Therefore, this disclosure can control the threshold compensation time of the pixel driving circuit by adjusting the overlap time between the time period during which the signal at the third reset signal terminal is at an effective level and the time period during which the signal at the second scan signal terminal is at an effective level. This disclosure can increase the threshold compensation time of the pixel driving circuit, effectively solving the problem of insufficient threshold compensation time in high-frequency displays.

[0240] The following describes an exemplary embodiment of this disclosure through the operation of a pixel driving circuit illustrated in FIG12. The pixel driving circuit in FIG12 includes nine transistors (first transistor T1 to ninth transistor T9) and two capacitors (first capacitor C1 and second capacitor C2). The first transistor T1 to the ninth transistor T9 are N-type transistors.

[0241] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0242] In the first stage, P21, known as the initialization stage, the signals at the fourth reset signal terminal Reset4 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third reset signal terminal Reset3, and the light emission signal terminal EM are low-level signals. The signals at the first reset signal terminal Reset1 and the second reset signal terminal Reset2 are high-level signals for a portion of the time. The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned off.

[0243] The first transistor T1 is turned on, and the signal at the first initial signal terminal INIT1 is written to the third node N3, initializing (resetting) the third node N3 and clearing its internal pre-stored voltage, thus completing the initialization. The second transistor T2 is turned on, and the third node N3 and the fifth node N5 are turned on. The signal at the third node N3 is written to the fifth node N5, initializing (resetting) the third node N3 and clearing its internal pre-stored voltage, thus completing the initialization. The seventh transistor T7 is turned on, and the signal at the second initial signal terminal INIT2 is written to the fourth node N4 (which is also the anode of the light-emitting device L), initializing (resetting) the fourth node N4 (which is also the anode of the light-emitting device L) and clearing its internal pre-stored voltage, thus completing the initialization. The eighth transistor T8 is turned on, and the signal at the reference signal terminal REF is written to the first node N1, initializing (resetting) the first node N1 and clearing its internal pre-stored voltage, thus completing the initialization.

[0244] In this phase, the voltage value V of the signal at the first node N1 N1=Vref, the voltage value V of the signal at the third node N3. N3 =Vinit1, the voltage value V of the signal at the fourth node N4. N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 =Vinit1, where Vref is the voltage value of the signal at the reference signal terminal REF, Vinit1 is the voltage value of the signal at the first initial signal terminal INIT1, and Vinit2 is the voltage value of the signal at the second initial signal terminal INIT2.

[0245] In the second stage, P22, known as the threshold compensation stage, the signals at the third reset signal terminal Reset3, the fourth reset signal terminal Reset4, and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the light emission signal terminal EM are low-level signals. The second transistor T2, the eighth transistor T8, and the ninth transistor T9 are turned on, while the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0246] The eighth transistor T8 is turned on, and the signal at the reference signal terminal REF is written to the first node N1, initializing (resetting) the first node N1, clearing its internal pre-stored voltage, and completing the initialization. The ninth transistor T9 is turned on, and the signal at the third initial signal terminal INIT3 charges the third node N3 through the turned-on third transistor T3 until the voltage value of the signal at the third node N3 is Vref-Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage difference stored in the first capacitor C1 is Vth. The second transistor T2 is turned on, and the third node N3 and the fifth node N5 are turned on. The signal at the fifth node N5 is written to the third node N3.

[0247] In this phase, the voltage value V of the signal at the first node N1 N1 =Vref, the voltage value V of the signal at the second node N2. N2 =Vinit3, the voltage value V of the signal at the third node N3. N3 =Vref - Vth, the voltage value V of the signal at the fifth node N5. N5 =Vref-Vth, where Vinit3 is the voltage value of the signal at the third initial signal terminal INIT3.

[0248] The third stage, P23, is called the data writing stage. The signal at the second scan signal terminal (Gate2) is high, while the signals at the first reset signal terminal (Reset1), the second reset signal terminal (Reset2), the third reset signal terminal (Reset3), the fourth reset signal terminal (Reset4), and the light emission signal terminal (EM) are low. The signal at the first scan signal terminal (Gate1) is high for a portion of the time. The second transistor (T2) and the fourth transistor (T4) are turned on, while the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), the eighth transistor (T8), and the ninth transistor (T9) are turned off.

[0249] When the fourth transistor T4 is turned on, the data signal on the data signal line Data is written to the first node N1, that is, the signal of the first node N1 changes. Under the action of the first capacitor C1, the signal of the fifth node N5 also changes, and the voltage value of the signal of the fifth node N5 after the change is Vref-Vth+[C1 / (C1+C2)](Vdata-Vref), where Vdata is the voltage value of the data signal at the data signal terminal Data, C1 is the capacitance value of the first capacitor C1, C2 is the voltage value of the second capacitor C2, the second transistor T2 is turned on, and the third node N3 and the fifth node N5 are connected.

[0250] In this phase, the voltage value V of the signal at the first node N1 N1 =Vdata, the voltage value V of the signal at the third node N3. N3 =Vref-Vth+[C1 / (C1+C2)](Vdata-Vref), where V is the voltage value of the signal at the fourth node N4. N4 =Vinit2, the voltage value V of the signal at the fifth node N5. N5 =Vref-Vth+[C1 / (C1+C2)](Vdata-Vref).

[0251] In the fourth stage, P24, known as the isolation stage, the signal at the EM terminal is high, while the signals at the first scan signal terminal (Gate1), the first reset signal terminal (Reset1), the second reset signal terminal (Reset2), the third reset signal terminal (Reset3), and the fourth reset signal terminal (Reset4) are low. The signal at the second scan signal terminal (Gate2) changes from high to low. The second transistor T2 changes from on to off, the fifth transistor T5 and the sixth transistor T6 turn on, and the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 turn off.

[0252] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power signal output from the first power supply terminal VDD provides a driving voltage to the fourth node N4 (which is also the first terminal of the light-emitting device L) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, driving the light-emitting device L to emit light. When the second transistor T2 changes from turned on to turned off, that is, the third node N3 and the fifth node N5 change from connected to disconnected. When the third node N3 and the fifth node N5 are disconnected, the signal of the fifth node N5 remains unchanged and is not affected by the third node N3. If the signal of the third node N3 remains unchanged, the signal of the first node N1 also remains unchanged under the action of the first capacitor C1.

[0253] In this stage, the voltage value of the signal at the first node N1 is VN1 = Vdata, and the voltage value of the signal at the third node N3 is V... N3 =Vref-Vth+[C1 / (C1+C2)](Vdata-Vref), where V is the voltage value of the signal at the fifth node N5. N5 =Vref-Vth+[C1 / (C1+C2)](Vdata-Vref).

[0254] During a certain period of this phase, the second transistor T2 is turned on, connecting the third node N3 and the fifth node N5. This causes a signal transition in both the third and fifth nodes. Under the influence of the first capacitor C1, the first node N1 also transitions. At this time, the signal voltage value of the first node N1 is Vdata + V N3 -[Vref-Vth+[C1 / (C1+C2)](Vdata-Vref)], therefore the drive current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*(V N1 -V N3 -Vth) 2 =K*[Vdata-Vref+Vth+[C1 / (C1+C2)](Vdata-Vref)-Vth] 2 =K*[[C2 / (C1+C2)](Vdata-Vref)] 2

[0255] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3.

[0256] In the fifth stage (P25), the light-emitting stage, the signal at the light-emitting signal terminal EM is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first reset signal terminal Reset1, the second reset signal terminal Reset2, the third reset signal terminal Reset3, and the fourth reset signal terminal Reset4 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0257] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power signal output from the first power supply terminal VDD provides a driving voltage to the fourth node N4 (which is also the first terminal of the light-emitting device L) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, driving the light-emitting device L to emit light. When the second transistor T2 is turned off, that is, the third node N3 and the fifth node N5 are disconnected. When the third node N3 and the fifth node N5 are disconnected, the signal of the fifth node N5 remains unchanged and is not affected by the third node N3. If the signal of the fifth node N5 remains unchanged, the signal of the first node N1 also remains unchanged under the action of the first capacitor C1.

[0258] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode.

[0259] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0260] As can be seen from the operation of the pixel driving circuit provided in Figures 10 and 12, the isolation sub-circuit in this disclosure can effectively avoid the influence of the signal change of the third node on the signal of the first node during the light emission stage, which can ensure the stability of the signal of the first node and thus improve the reliability of the pixel driving circuit.

[0261] This disclosure also provides a method for driving a pixel driving circuit, configured to drive the pixel driving circuit provided in any of the foregoing embodiments. The method for driving the pixel driving circuit may include the following steps:

[0262] Step S100: The driving sub-circuit provides a driving signal to the third node under the control of the signals from the first and second nodes.

[0263] In step S200, the isolation sub-circuit, under the control of the signal at the second scanning signal terminal, connects or disconnects the third node and the fifth node, and stores the voltage difference between the signals of the first node and the fifth node.

[0264] Step S300: Under the control of the signal at the first scanning signal terminal, the first control sub-circuit provides the signal at the data signal terminal to the first node.

[0265] In step S400, the second control sub-circuit, under the control of at least one reset signal terminal, provides at least one initial signal terminal signal to one of the second node, the fourth node, the third node, and the fifth node.

[0266] In step S500, under the control of the signal at the light-emitting signal terminal, the third control sub-circuit provides the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node.

[0267] This disclosure also provides a display substrate, including: a substrate and a plurality of pixel driving circuits and a plurality of light-emitting devices arranged in an array on the substrate, wherein at least one of the plurality of light-emitting devices includes: an anode and a cathode. The at least one pixel driving circuit is electrically connected to the anode of the at least one light-emitting device.

[0268] In an exemplary embodiment, the cathodes of multiple light-emitting devices can be the same electrode.

[0269] In an exemplary embodiment, FIG14 is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure. As shown in FIG14, the display substrate further includes: multiple first initial signal lines INITL1, multiple second initial signal lines INITL2, multiple third initial signal lines INITL3, multiple first scan signal lines GL1, multiple second scan signal lines GL2, multiple light emission signal lines EL, multiple first reset signal lines RL1, multiple second reset signal lines RL2, multiple third reset signal lines RL3, multiple fourth reset signal lines RL4, multiple data signal lines DL, multiple first power supply lines VDDL, and multiple reference signal lines REFL. For ease of explanation, FIG14 only shows the signal lines connected to the (n+1)th column pixel driving circuit and does not show the signal lines connected to the nth column pixel driving circuit.

[0270] As shown in Figure 14, the pixel driving circuit includes: multiple transistors, a first capacitor, and a second capacitor. The first capacitor and the second capacitor each include: a first electrode and a second electrode. The multiple transistors include: first transistor T1 to ninth transistor T9.

[0271] Figure 15 is a schematic diagram of the connection of the first initial signal lines. As shown in Figures 14 and 15, in an exemplary embodiment, the display substrate further includes a plurality of first initial signal lines INITL1. At least one of the plurality of first initial signal lines INITL1 is electrically connected to a first initial signal terminal in at least one pixel driving circuit, and extends at least partially along the second direction D2.

[0272] As shown in Figure 15, when the second control sub-circuit in the pixel driving circuit is electrically connected to the fifth node, at least one of the multiple first initial signal lines INITL1 is electrically connected to the cathode 302 of at least one light-emitting device.

[0273] In an exemplary embodiment, as shown in FIG14, one of the multiple first initial signal lines INITL1 includes: multiple initial signal traces 201 and multiple initial connection portions 202, which are alternately arranged and interconnected.

[0274] In an exemplary embodiment, as shown in FIG14, at least one of the plurality of initial signal traces 201 extends at least partially along the second direction D2, and at least one of the plurality of initial connection portions 202 extends at least partially along the second direction D2.

[0275] In an exemplary embodiment, as shown in Figures 14 and 15, the display substrate further includes: a plurality of initial vias H, at least one of the plurality of initial vias H exposing at least one initial connection portion 202 of a plurality of initial connection portions 202, and the cathode 302 of at least one light-emitting device is connected to one of the plurality of first initial signal lines INITL1 through at least one initial via H.

[0276] In an exemplary embodiment, the initial via H can be formed by laser processing or etching process, and this disclosure does not limit it in any way.

[0277] In an exemplary embodiment, as shown in Figures 14 and 15, the line width of at least one of the plurality of initial connection portions 202 along the first direction D1 is greater than the line width of at least one of the plurality of initial signal traces 201 along the first direction D1, and the first direction D1 intersects with the second direction D2.

[0278] The initial connection portion 202 in this disclosure has a line width greater than that of the initial signal trace 201 in the first direction D1, which can increase the contact area between the cathode of the subsequently formed light-emitting device and the first initial signal trace, thereby ensuring the stability of the cathode of the light-emitting device and the first initial signal trace.

[0279] In an exemplary embodiment, as shown in FIG15, the display substrate may further include: a plurality of initial connection lines VCL.

[0280] In an exemplary embodiment, as shown in FIG15, at least one of the multiple initial connection lines VCL is electrically connected to multiple first initial signal lines INITL1, and extends at least partially along the first direction D1. The multiple initial connection lines VCL and the multiple first initial signal lines INITL1 are interwoven to form a mesh structure, which can ensure the uniformity of the signals transmitted by the first initial signal lines in the display substrate and improve the reliability of the display substrate.

[0281] In an exemplary embodiment, as shown in FIG14, at least one of the plurality of first power lines VDDL is electrically connected to a first power supply terminal in at least one pixel driving circuit, and extends at least partially along the second direction D2.

[0282] In an exemplary embodiment, as shown in FIG14, at least one of the plurality of first power lines VDDL includes: a power body line 101 and a plurality of power protrusions 102; the power body line 101 is connected to the plurality of power protrusions 102, and the plurality of power protrusions 102 are spaced apart.

[0283] In an exemplary embodiment, as shown in FIG14, the orthographic projection of at least one of the power protrusions 102 on the substrate at least partially overlaps with the orthographic projection of at least one of the first capacitors C1 and the second capacitor C2 in at least one pixel driving circuit on the substrate.

[0284] In an exemplary embodiment, as shown in FIG14, the orthographic projection of the first capacitor C1 on the substrate and the orthographic projection of the second capacitor C2 on the substrate at least partially overlap, and at least one electrode of the first capacitor and at least one electrode of the second capacitor are the same electrode. FIG14 is illustrated using the example that the first electrode C11 of the first capacitor and the first electrode C21 of the second capacitor are the same electrode.

[0285] In an exemplary embodiment, as shown in FIG14, at least one of the plurality of data signal lines DL is electrically connected to the data signal terminal in at least one pixel driving circuit, and extends at least partially along the second direction D2.

[0286] In an exemplary embodiment, as shown in FIG14, at least one of the plurality of reference signal lines REFL is electrically connected to a reference signal terminal in at least one pixel driving circuit, and extends at least partially along the second direction D2.

[0287] In an exemplary embodiment, as shown in FIG14, at least one pixel driving circuit is connected to a data signal line DL, a first power supply line VDDL, a reference signal line REFL, and a first initial signal line INITL1 arranged sequentially along a first direction D1.

[0288] In an exemplary embodiment, as shown in FIG14, at least one of the plurality of first scan signal lines GL1, plurality of second scan signal lines GL2, plurality of light emission signal lines EL, plurality of first reset signal lines RL1, plurality of second reset signal lines RL2, plurality of third reset signal lines RL3 and plurality of fourth reset signal lines RL4 extends at least partially along the first direction D1.

[0289] In an exemplary embodiment, at least one of the plurality of first scan signal lines GL1 is electrically connected to the first scan signal terminal of at least one pixel driving circuit; at least one of the plurality of second scan signal lines GL2 is electrically connected to the second scan signal terminal of at least one pixel driving circuit; at least one of the plurality of light emission signal lines is electrically connected to the light emission signal terminal of at least one pixel driving circuit; at least one of the plurality of first reset signal lines RL1 is electrically connected to the first reset signal terminal of at least one pixel driving circuit; at least one of the plurality of second reset signal lines RL2 is electrically connected to the second reset signal terminal of at least one pixel driving circuit; at least one of the plurality of third reset signal lines RL3 is electrically connected to the third reset signal terminal of at least one pixel driving circuit; and at least one of the plurality of fourth reset signal lines RL4 is electrically connected to the fourth reset signal terminal of at least one pixel driving circuit.

[0290] In an exemplary embodiment, as shown in FIG14, the second reset signal line RL2(m) connected to the m-th row pixel driving circuit and the fourth reset signal line RL4(m) connected to the (m-1)-th row pixel driving circuit are the same signal line.

[0291] In an exemplary embodiment, as shown in FIG14, the second reset signal line RL2, the light emission signal line, the third reset signal line RL3, the second scan signal line GL2, the first scan signal line GL1, the first reset signal line RL1, and the fourth reset signal line RL4 connected to at least one pixel driving circuit are arranged sequentially along the second direction D2.

[0292] In an exemplary embodiment, as shown in FIG14, at least one of the plurality of second initial signal lines INITL2 is electrically connected to the second initial signal terminal of at least one pixel driving circuit, and extends at least partially along the first direction D1. The orthographic projection of the second initial signal line INITL2 connected to the at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line RL2 on the substrate. The at least partial overlap of the orthographic projection of the second initial signal line INITL2 connected to the at least one pixel driving circuit on the substrate with the orthographic projection of the second reset signal line RL2 on the substrate in this disclosure can reduce the area occupied by the pixel driving circuit and achieve a high PPI of the display substrate.

[0293] In an exemplary embodiment, as shown in FIG14, at least one of the plurality of third initial signal lines INITL3 is electrically connected to the third initial signal terminal of at least one pixel driving circuit, and extends at least partially along the first direction D1. The orthographic projection of the third initial signal line INITL3 connected to the at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line on the substrate. The at least partial overlap of the orthographic projection of the third initial signal line INITL3 connected to the at least one pixel driving circuit on the substrate with the orthographic projection of the light-emitting signal line on the substrate in this disclosure can reduce the area occupied by the pixel driving circuit and achieve a high PPI of the display substrate.

[0294] In an exemplary embodiment, as shown in FIG14, the display substrate further includes a circuit structure layer disposed on the substrate, the circuit structure layer including a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate.

[0295] In an exemplary embodiment, the first conductive layer includes at least the second electrode C12 of the first capacitor.

[0296] In an exemplary embodiment, the semiconductor layer includes at least: an active pattern of at least one transistor among a plurality of transistors in at least one pixel driving circuit.

[0297] In an exemplary embodiment, the second conductive layer includes at least: multiple first scan signal lines GL1, multiple second scan signal lines GL2, multiple light emission signal lines, multiple first reset signal lines RL1, multiple second reset signal lines RL2, multiple third reset signal lines RL3, multiple fourth reset signal lines RL4, a control electrode of at least one transistor of at least one pixel driving circuit, a first electrode C11 of a first capacitor, and a first electrode C21 of a second capacitor.

[0298] In an exemplary embodiment, the third conductive layer includes at least: a plurality of second initial signal lines INITL2, a plurality of third initial signal lines INITL3, and the first and second poles of at least one transistor of at least one pixel driving circuit, as well as the second plate C22 of the second capacitor.

[0299] In an exemplary embodiment, the fourth conductive layer includes at least: multiple data signal lines DL, multiple reference signal lines REFL, multiple first power lines VDDL, and multiple first initial signal lines INITL1.

[0300] In an exemplary embodiment, the initial connection line may be located in at least one of the first conductive layer, the second conductive layer, and the third conductive layer.

[0301] In an exemplary embodiment, the circuit structure layer further includes: a first insulating layer, a second insulating layer, a third insulating layer, a first planarization layer, and a second planarization layer. The first insulating layer is located between the first conductive layer and the semiconductor layer, the second insulating layer is located between the semiconductor layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third insulating layer, the first planarization layer is located between the third conductive layer and the fourth conductive layer, and the second planarization layer is located on the side of the fourth conductive layer away from the substrate.

[0302] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer disposed on the side of the circuit structure layer away from the substrate. The light-emitting structure layer includes a fifth conductive layer, a pixel definition layer, an organic structure layer, and a sixth conductive layer.

[0303] The fifth conductive layer includes at least: the anode of at least one light-emitting device.

[0304] The organic structural layer includes at least one organic light-emitting layer for a light-emitting device.

[0305] The sixth conductive layer includes at least one cathode of a light-emitting device.

[0306] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0307] Figures 16 to 30 are schematic diagrams illustrating the fabrication process of a display substrate according to an exemplary embodiment. Figures 16 to 30 are illustrated with the example of a display substrate including the pixel driving circuit provided in Figure 10, and the signal received by the first initial signal terminal and the signal received by the second power supply terminal being the same signal.

[0308] The fabrication process of the display substrate provided in this disclosure may include, as shown in Figures 16 to 30:

[0309] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first conductive thin film on a substrate, and patterning the first conductive thin film by a patterning process to form a first conductive layer pattern, as shown in FIG16, FIG16 being a schematic diagram of the first conductive layer pattern.

[0310] In an exemplary embodiment, as shown in FIG16, the first conductive layer pattern may include at least: a second plate C12 of a first capacitor located in at least one pixel driving circuit. In the figure, C12(m) refers to the second plate of the first capacitor of a pixel driving circuit in the m-th row.

[0311] In an exemplary embodiment, the main body of the second plate C12 of the first capacitor may be rectangular in shape and at least partially extend along the first direction D1.

[0312] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film on a substrate on which the aforementioned pattern is formed, and patterning the semiconductor film by a patterning process to form a first insulating layer and a semiconductor layer pattern formed on the first insulating layer, as shown in Figures 17 and 18. Figure 17 is a schematic diagram of the semiconductor layer pattern, and Figure 18 is a schematic diagram after the semiconductor layer pattern is formed.

[0313] In an exemplary embodiment, as shown in Figures 17 and 18, the semiconductor layer pattern may include at least the active pattern of at least one transistor located in at least one pixel driving circuit. The active pattern of at least one transistor may include: an active pattern 11 of a first transistor, an active pattern 21 of a second transistor, an active pattern 31 of a third transistor, an active pattern 41 of a fourth transistor, an active pattern 51 of a fifth transistor, an active pattern 61 of a sixth transistor, an active pattern 71 of a seventh transistor, an active pattern 81 of an eighth transistor, and an active pattern 91 of a ninth transistor. 11(m) refers to the active pattern of the first transistor of a pixel driving circuit in the m-th row, 21(m) refers to the active pattern of the second transistor of a pixel driving circuit in the m-th row, and 31(m) refers to the active pattern of the first transistor of a pixel driving circuit in the m-th row. The active pattern of the third transistor of the pixel driving circuit, 41(m) refers to the active pattern of the fourth transistor of the pixel driving circuit in the m-th row, 51(m) refers to the active pattern of the fifth transistor of the pixel driving circuit in the m-th row, 61(m) refers to the active pattern of the sixth transistor of the pixel driving circuit in the m-th row, 71(m) refers to the active pattern of the seventh transistor of the pixel driving circuit in the m-th row, 81(m) refers to the active pattern of the eighth transistor of the pixel driving circuit in the m-th row, and 91(m) refers to the active pattern of the ninth transistor of the pixel driving circuit in the m-th row.

[0314] In an exemplary embodiment, for the same pixel driving circuit, in the second direction D2, the active pattern 21 of the second transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 71 of the seventh transistor, and the active pattern 91 of the ninth transistor are located on the side of the active pattern 31 of the third transistor near the previous row of pixel driving circuits. The active patterns 51 of the fifth transistor and 61 of the sixth transistor are arranged along the first direction D1, and the active pattern 61 of the sixth transistor is located on the side of the active pattern 51 of the fifth transistor near the next column of pixel driving circuits. The active pattern 71 of the seventh transistor is located on the side of the active patterns 51 of the fifth transistor and 61 of the sixth transistor near the previous row of pixel driving circuits. The straight line extending along the second direction D2 through the active pattern 71 of the seventh transistor is located between the straight line extending along the second direction D2 through the active pattern 51 of the fifth transistor and the straight line extending along the second direction D2 through the active pattern 61 of the sixth transistor. The active pattern 21 of the second transistor and the active pattern 71 of the ninth transistor are located on the side of the active pattern 51 of the fifth transistor and the active pattern 61 of the sixth transistor close to the next row of pixel driving circuits. The straight line extending along the second direction D2 through the active pattern 91 of the ninth transistor is located between the straight line extending along the second direction D2 through the active pattern 51 of the fifth transistor and the straight line extending along the second direction D2 through the active pattern 61 of the sixth transistor. The straight line extending along the second direction D2 through the active pattern 21 of the second transistor is located on the side away from the straight line extending along the second direction D2 through the active pattern 61 of the sixth transistor.

[0315] In an exemplary embodiment, for the same pixel driving circuit, in the second direction D2, the active pattern 11 of the first transistor, the active pattern 41 of the fourth transistor, and the active pattern 81 of the eighth transistor are located on the side of the active pattern 31 of the third transistor closer to the next row of pixel driving circuits. The active pattern 41 of the fourth transistor and the active pattern 51 of the fifth transistor are arranged along the second direction D2, the active pattern 11 of the first transistor and the active pattern 21 of the second transistor are arranged along the second direction D2, and the active pattern 61 of the sixth transistor and the active pattern 81 of the eighth transistor are arranged along the second direction D2.

[0316] In an exemplary embodiment, the active pattern 71(m) of the seventh transistor of a pixel driving circuit in the m-th row and the active pattern 81(m-1) of the eighth transistor of a pixel driving circuit in the (m-1)-th row are arranged along the first direction D1.

[0317] In an exemplary embodiment, at least one of the active patterns of the first transistor 11, the second transistor 21, the fourth transistor 41, the fifth transistor 51, the sixth transistor 61, the seventh transistor 71, the eighth transistor 81, and the ninth transistor 91 is strip-shaped and extends at least partially along the second direction D2, and the active pattern 31 of the third transistor is strip-shaped and extends at least partially along the first direction D1.

[0318] In an exemplary embodiment, the orthographic projection of the second plate of the first capacitor in at least one pixel driving circuit onto the substrate lies between the orthographic projection of the active pattern of the third transistor onto the substrate and the orthographic projection of the active pattern of the first transistor onto the substrate.

[0319] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, for at least one pixel driving circuit, the first region 11-1 and the second region 11-2 of the active pattern 11 of the first transistor, the first region 21-1 and the second region 21-2 of the active pattern 21 of the second transistor, the first region 31-1 and the second region 31-2 of the active pattern 31 of the third transistor, the first region 41-1 and the second region 41-2 of the active pattern 41 of the fourth transistor, the first region 51-1 and the second region 51-2 of the active pattern 51 of the fifth transistor, the first region 61-1 and the second region 61-2 of the active pattern 61 of the sixth transistor, the first region 71-1 and the second region 71-2 of the active pattern 71 of the seventh transistor, the first region 81-1 and the second region 81-2 of the active pattern 81 of the eighth transistor, and the first region 91-1 and the second region 91-2 of the active pattern 91 of the ninth transistor are individually configured.

[0320] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second insulating film and a second conductive film sequentially on a substrate on which the aforementioned pattern is formed, and patterning the second conductive film by a patterning process to form a second insulating layer and a second conductive layer pattern located on the second insulating layer, as shown in Figures 19 and 20, wherein Figure 19 is a schematic diagram of the second conductive layer pattern and Figure 20 is a schematic diagram after the second conductive layer pattern is formed.

[0321] In an exemplary embodiment, as shown in Figures 19 and 20, the second conductive layer pattern may include: multiple first scan signal lines GL1, multiple second scan signal lines GL2, multiple light emission signal lines EL, multiple first reset signal lines RL1, multiple second reset signal lines RL2, multiple third reset signal lines RL3, multiple fourth reset signal lines RL4, and control electrodes of at least one transistor located in at least one pixel driving circuit, a first electrode C11 of a first capacitor, and a first electrode C21 of a second capacitor. The control electrodes of the at least one transistor include, for example, control electrodes 12 of a first transistor, 22 of a second transistor, 32 of a third transistor, 42 of a fourth transistor, 52 of a fifth transistor, 62 of a sixth transistor, 72 of a seventh transistor, 82 of an eighth transistor, and 92 of a ninth transistor. In the diagram, GL1(m) is the first scan signal line connected to the first scan signal terminal of the m-th row pixel driving circuit; GL2(m) is the second scan signal line connected to the first scan signal terminal of the m-th row pixel driving circuit; EL(m) is the light emission signal line connected to the light emission signal terminal of the m-th row pixel driving circuit; RL1(m) is the first reset signal line connected to the first reset signal terminal of the m-th row pixel driving circuit; RL2(m) is the second reset signal line connected to the second reset signal terminal of the m-th row pixel driving circuit; RL3(m) is the third reset signal line connected to the third reset signal terminal of the m-th row pixel driving circuit; RL4(m) is the fourth reset signal line connected to the third reset signal terminal of the m-th row pixel driving circuit; 12(m) refers to the control electrode of the first transistor of a pixel driving circuit in the m-th row; and 22(m) refers to the control electrode of a pixel driving circuit in the m-th row. The control electrode of the second transistor in the m-th row, 32(m) refers to the control electrode of the third transistor in the m-th row pixel driving circuit, 42(m) refers to the control electrode of the fourth transistor in the m-th row pixel driving circuit, 52(m) refers to the control electrode of the fifth transistor in the m-th row pixel driving circuit, 62(m) refers to the control electrode of the sixth transistor in the m-th row pixel driving circuit, 72(m) refers to the control electrode of the seventh transistor in the m-th row pixel driving circuit, 82(m) refers to the control electrode of the eighth transistor in the m-th row pixel driving circuit, 92(m) refers to the control electrode of the ninth transistor in the m-th row pixel driving circuit, C11(m) refers to the first plate of the first capacitor in the m-th row pixel driving circuit, and C21(m) refers to the first plate of the second capacitor in the m-th row pixel driving circuit.

[0322] In an exemplary embodiment, for at least one pixel driving circuit, the first plate C11 of the first capacitor, the first plate C21 of the second capacitor, and the control electrode 32 of the third transistor are integrated into a single structure, and the shape of the integrated structure of the first plate of the first capacitor, the first plate of the second capacitor, and the control electrode 32 of the third transistor is cross-shaped.

[0323] In an exemplary embodiment, for at least one pixel driving circuit, the orthographic projection of the first plate C11 of the first capacitor onto the substrate at least partially overlaps with the orthographic projection of the second plate of the first capacitor onto the substrate.

[0324] In an exemplary embodiment, the second reset signal line connected to the m-th row pixel driving circuit and the fourth reset signal line connected to the (m-1)-th row pixel driving circuit are the same signal line, and the fourth reset signal line connected to the m-th row pixel driving circuit and the second reset signal line connected to the (m+1)-th row pixel driving circuit are the same signal line.

[0325] In an exemplary embodiment, at least one row of pixel driving circuits is connected to a second reset signal line RL2, an emission signal line EL, a third reset signal line RL3, a second scan signal line GL2, a first scan signal line GL1, a first reset signal line RL1, and a fourth reset signal line RL4, which are arranged sequentially along the second direction D2.

[0326] In an exemplary embodiment, the orthographic projection of at least one of the second reset signal line, light emission signal line, third reset signal line, and second scan signal line connected to at least one pixel driving circuit onto the substrate is located on the side of the first plate of the first capacitor (the first plate of the second capacitor and the control electrode of the third transistor) of at least one pixel driving circuit closer to the previous row of pixel driving circuits. The orthographic projection of at least one of the first scan signal line, first reset signal line, and fourth reset signal line connected to at least one pixel driving circuit onto the substrate is located on the side of the first plate of the first capacitor (the first plate of the second capacitor and the control electrode of the third transistor) of at least one pixel driving circuit closer to the next row of pixel driving circuits.

[0327] In an exemplary embodiment, the shape of the second reset signal line RL2 can be a line shape in which the main body extends along the first direction D1. The area where the second reset signal line RL2 connected to at least one pixel driving circuit overlaps with the active pattern of the seventh transistor can be the control electrode 72 of the seventh transistor. Exemplarily, the area where the second reset signal line RL2(m) connected to the m-th row pixel driving circuit overlaps with the active pattern of the seventh transistor of at least one pixel driving circuit in the m-th row can be the control electrode 72(m) of the seventh transistor.

[0328] In an exemplary embodiment, the shape of the light-emitting signal line EL can be a line shape extending along the first direction D1 of the main body portion. The area where the light-emitting signal line EL connected to at least one pixel driving circuit overlaps with the active pattern of the fifth transistor can be the control electrode 52 of the fifth transistor, and the area where the light-emitting signal line EL connected to at least one pixel driving circuit overlaps with the active pattern of the sixth transistor can be the control electrode 62 of the sixth transistor. Exemplarily, the area where the light-emitting signal line EL(m) connected to the m-th row pixel driving circuit overlaps with the active pattern of the fifth transistor of at least one pixel driving circuit in the m-th row can be the control electrode 52(m) of the fifth transistor, and the area where the light-emitting signal line EL(m) connected to the m-th row pixel driving circuit overlaps with the active pattern of the sixth transistor of at least one pixel driving circuit in the m-th row can be the control electrode 62(m) of the sixth transistor.

[0329] In an exemplary embodiment, the shape of the third reset signal line RL3 can be a line shape in which the main body extends along the first direction D1. The area where the third reset signal line RL3 connected to at least one pixel driving circuit overlaps with the active pattern of the ninth transistor can be the control electrode 92 of the ninth transistor. Exemplarily, the area where the third reset signal line RL3(m) connected to the m-th row pixel driving circuit overlaps with the active pattern of the ninth transistor of at least one pixel driving circuit in the m-th row can be the control electrode 92(m) of the ninth transistor.

[0330] In an exemplary embodiment, the shape of the second scan signal line GL2 can be a line shape in which the main body extends along the first direction D1. The area where the second scan signal line GL2 connected to at least one pixel driving circuit intersects with the active pattern of the second transistor can be the control electrode 22 of the second transistor. Exemplarily, the area where the second scan signal line GL2(m) connected to the m-th row pixel driving circuit intersects with the active pattern of the second transistor of at least one pixel driving circuit in the m-th row can be the control electrode 22(m) of the second transistor.

[0331] In an exemplary embodiment, the shape of the first scan signal line GL1 can be a line shape in which the main body extends along the first direction D1. The area where the first scan signal line GL1 connected to at least one pixel driving circuit overlaps with the active pattern of the fourth transistor can be the control electrode 42 of the fourth transistor. The area where the first scan signal line GL1(m) connected to the m-th row pixel driving circuit overlaps with the active pattern of the fourth transistor of at least one pixel driving circuit in the m-th row can be the control electrode 42(m) of the fourth transistor.

[0332] In an exemplary embodiment, the shape of the first reset signal line RL1 can be a line shape in which the main body extends along the first direction D1. The area where the first reset signal line RL1 connected to at least one pixel driving circuit intersects with the active pattern of the first transistor can be the control electrode 12 of the first transistor. The area where the first reset signal line RL1(m) connected to the m-th row pixel driving circuit intersects with the active pattern of the first transistor of at least one pixel driving circuit in the m-th row can be the control electrode 12(m) of the first transistor.

[0333] In an exemplary embodiment, the shape of the fourth reset signal line RL4 can be a line shape in which the main body extends along the first direction D1. The area where the fourth reset signal line RL4 connected to at least one pixel driving circuit overlaps with the active pattern of the eighth transistor can be the control electrode 82 of the eighth transistor. The area where the fourth reset signal line RL4(m) connected to the m-th row pixel driving circuit overlaps with the active pattern of the eighth transistor of at least one pixel driving circuit in the m-th row can be the control electrode 82(m) of the eighth transistor.

[0334] In an exemplary embodiment, the first scan signal line GL1, the second scan signal line GL2, the light emission signal line EL, the first reset signal line RL1, the second reset signal line RL2, the third reset signal line RL3, and the fourth reset signal line RL4 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0335] In an exemplary embodiment, after the second conductive layer pattern is formed, the second conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the second conductive layer forms the channel region of the first transistor to the ninth transistor, and the semiconductor layer in the region not shielded by the second conductive layer is conducted.

[0336] In an exemplary embodiment, the control electrode of the first transistor is disposed across the active pattern of the first transistor, the control electrode of the second transistor is disposed across the active pattern of the second transistor, the control electrode of the third transistor is disposed across the active pattern of the third transistor, the control electrode of the fourth transistor is disposed across the active pattern of the fourth transistor, the control electrode of the fifth transistor is disposed across the active pattern of the fifth transistor, the control electrode of the sixth transistor is disposed across the active pattern of the sixth transistor, the control electrode of the seventh transistor is disposed across the active pattern of the seventh transistor, the control electrode of the eighth transistor is disposed across the active pattern of the eighth transistor, and the control electrode of the ninth transistor is disposed across the active pattern of the ninth transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0337] (4) Forming a third insulating layer pattern includes: depositing a third insulating film on a substrate on which the aforementioned pattern has been formed, and patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned pattern. The third insulating layer has multiple via patterns, as shown in Figure 21. Figure 21 is a schematic diagram after the third insulating layer pattern has been formed.

[0338] In an exemplary embodiment, as shown in FIG21, the plurality of vias in the third insulating layer pattern include at least: a first via V1 to a twentieth via V20 located in at least one pixel driving circuit.

[0339] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the second electrode of the first capacitor onto the substrate. The second insulating layer and the first insulating layer within the first via V1 are etched away, exposing the surface of the second electrode of the first capacitor. The first via V1 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor) to be connected to the second electrode of the first capacitor through the via.

[0340] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the orthographic projection range of the first region of the active pattern of the first transistor onto the substrate. The second insulating layer within the second via V2 is etched away, exposing the surface of the first region of the active layer of the first transistor. The second via V2 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active layer of the first transistor through the via.

[0341] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the orthographic projection of the second region of the active pattern of the first transistor onto the substrate. The second insulating layer within the third via V3 is etched away, exposing the surface of the second region of the active pattern of the first transistor. The third via V3 is configured to allow the second terminal (which is also the first terminal of the second transistor) of the subsequently formed first transistor to be connected to the second region of the active pattern of the first transistor through the via.

[0342] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the second transistor onto the substrate. The second insulating layer within the fourth via V4 is etched away, exposing the surface of the first region of the active layer of the second transistor. The fourth via V4 is configured to allow the second electrode (which is also the first electrode of the second transistor) of the subsequently formed first transistor to be connected to the first region of the active layer of the second transistor through the via.

[0343] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the orthographic projection of the second region of the active pattern of the second transistor onto the substrate. The second insulating layer within the fifth via V5 is etched away, exposing the surface of the second region of the active pattern of the second transistor. The fifth via V5 is configured to allow the second terminal of the subsequently formed second transistor (which is also the second terminal of the third transistor and the first terminal of the sixth transistor) to be connected to the second region of the active pattern of the second transistor through the via.

[0344] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the orthographic projection of the first region of the active pattern of the third transistor onto the substrate. The second insulating layer within the sixth via V6 is etched away, exposing the surface of the first region of the active layer of the third transistor. The sixth via V6 is configured to allow the first electrode of the subsequently formed third transistor (which is also the second electrode of the fifth transistor and the second electrode of the ninth transistor) to be connected to the first region of the active layer of the third transistor through the via.

[0345] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the third transistor onto the substrate. The second insulating layer within the seventh via V7 is etched away, exposing the surface of the second region of the active pattern of the third transistor. The seventh via V7 is configured to allow the second terminal of the subsequently formed second transistor (which is also the second terminal of the third transistor and the first terminal of the sixth transistor) to be connected to the second region of the active pattern of the third transistor through the via.

[0346] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the orthographic projection of the first region of the active pattern of the fourth transistor onto the substrate. The second insulating layer within the eighth via V8 is etched away, exposing the surface of the first region of the active layer of the fourth transistor. The eighth via V8 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active layer of the fourth transistor through the via.

[0347] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the fourth transistor onto the substrate. The second insulating layer within the ninth via V9 is etched away, exposing the surface of the second region of the active pattern of the fourth transistor. The ninth via V9 is configured to allow the second electrode of the subsequently formed fourth transistor to be connected to the second region of the active pattern of the fourth transistor through the via.

[0348] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the fifth transistor onto the substrate. The second insulating layer within the tenth via V10 is etched away, exposing the surface of the first region of the active layer of the fifth transistor. The tenth via V10 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active layer of the fifth transistor through the via.

[0349] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the fifth transistor onto the substrate. The second insulating layer within the eleventh via V11 is etched away, exposing the surface of the second region of the active pattern of the fifth transistor. The eleventh via V11 is configured to allow the second terminal of the subsequently formed fifth transistor (which is also the first terminal of the third transistor and the second terminal of the ninth transistor) to be connected to the second region of the active pattern of the fifth transistor through the via.

[0350] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the orthographic projection of the first region of the active pattern of the sixth transistor onto the substrate. The second insulating layer within the twelfth via V12 is etched away, exposing the surface of the first region of the active layer of the sixth transistor. The twelfth via V12 is configured to allow the first electrode of the subsequently formed sixth transistor (which is also the second electrode of the second transistor and the second electrode of the third transistor) to be connected to the first region of the active layer of the sixth transistor through the via.

[0351] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the sixth transistor onto the substrate. The second insulating layer within the thirteenth via V13 is etched away, exposing the surface of the second region of the active pattern of the sixth transistor. The thirteenth via V13 is configured to allow the second electrode of the subsequently formed sixth transistor (which is also the second electrode of the seventh transistor) to be connected to the second region of the active pattern of the sixth transistor through the via.

[0352] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate is within the orthographic projection of the first region of the active pattern of the seventh transistor onto the substrate. The second insulating layer within the fourteenth via V14 is etched away, exposing the surface of the first region of the active layer of the seventh transistor. The fourteenth via V14 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the first region of the active layer of the seventh transistor through the via.

[0353] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the orthographic projection of the second region of the active pattern of the seventh transistor onto the substrate. The second insulating layer within the fifteenth via V15 is etched away, exposing the surface of the second region of the active pattern of the seventh transistor. The fifteenth via V15 is configured to allow the second terminal of the subsequently formed sixth transistor (which is also the second terminal of the seventh transistor) to be connected to the second region of the active pattern of the seventh transistor through the via.

[0354] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate is within the orthographic projection of the first region of the active pattern of the eighth transistor onto the substrate. The second insulating layer within the sixteenth via V16 is etched away, exposing the surface of the first region of the active layer of the eighth transistor. The sixteenth via V16 is configured to allow the first electrode of the subsequently formed eighth transistor to be connected to the first region of the active layer of the eighth transistor through the via.

[0355] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the orthographic projection of the second region of the active pattern of the eighth transistor onto the substrate. The second insulating layer within the seventeenth via V17 is etched away, exposing the surface of the second region of the active pattern of the eighth transistor. The seventeenth via V17 is configured to allow the second electrode of the subsequently formed eighth transistor to be connected to the second region of the active pattern of the eighth transistor through the via.

[0356] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 onto the substrate is within the orthographic projection range of the first region of the active pattern of the ninth transistor onto the substrate. The second insulating layer within the eighteenth via V18 is etched away, exposing the surface of the first region of the active layer of the ninth transistor. The eighteenth via V18 is configured to allow the first electrode of the subsequently formed ninth transistor to be connected to the first region of the active layer of the ninth transistor through the via.

[0357] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 onto the substrate is within the range of the orthographic projection of the second region of the active pattern of the ninth transistor onto the substrate. The second insulating layer within the nineteenth via V19 is etched away, exposing the surface of the second region of the active pattern of the ninth transistor. The nineteenth via V19 is configured to allow the second terminal of the subsequently formed ninth transistor (which is also the first terminal of the third transistor and the second terminal of the fifth transistor) to be connected to the second region of the active pattern of the ninth transistor through the via.

[0358] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate is located within the range of the orthographic projection of the first plate of the first capacitor (which is also the first plate of the second capacitor and the control electrode of the third transistor) onto the substrate. The twentieth via V20 exposes the surface of the first plate of the first capacitor (which is also the first plate of the second capacitor and the control electrode of the third transistor). The twentieth via V20 is configured to allow the second electrodes of the subsequently formed fourth transistor and eighth transistor to be connected to the first plate of the first capacitor (which is also the first plate of the second capacitor and the control electrode of the third transistor) through the via.

[0359] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive thin film using a patterning process to form a third conductive layer pattern, as shown in Figures 22 and 23. Figure 22 is a schematic diagram of the third conductive layer pattern, and Figure 23 is a schematic diagram after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0360] In an exemplary embodiment, as shown in Figures 22 and 23, the third conductive layer pattern may include: a second initial signal line INITL2, a third initial signal line INITL3, and the first and second poles of at least one transistor in at least one pixel driving circuit, and the second plate C22 of a second capacitor. The first and second terminals of at least one transistor located in at least one pixel driving circuit include: a first terminal 13 and a second terminal 14 of a first transistor, a first terminal 21 and a second terminal 22 of a second transistor, a first terminal 31 and a second terminal 32 of a third transistor, a first terminal 41 and a second terminal 42 of a fourth transistor, a first terminal 51 and a second terminal 52 of a fifth transistor, a first terminal 61 and a second terminal 62 of a sixth transistor, a first terminal 71 and a second terminal 72 of a seventh transistor, a first terminal 81 and a second terminal 82 of an eighth transistor, and a first terminal 91 and a second terminal 92 of a ninth transistor. 13(m) refers to the first terminal of the first transistor of a pixel driving circuit in the m-th row, 14(m) refers to the second terminal of the first transistor of a pixel driving circuit in the m-th row, 23(m) refers to the first terminal of the second transistor of a pixel driving circuit in the m-th row, 24(m) refers to the second terminal of the second transistor of a pixel driving circuit in the m-th row, 33(m) refers to the first terminal of the third transistor of a pixel driving circuit in the m-th row, and 34(m) refers to the first terminal of the third transistor of a pixel driving circuit in the m-th row. The second pole, 43(m) refers to the first pole of the fourth transistor of the pixel driving circuit in the m-th row, 44(m) refers to the second pole of the fourth transistor of the pixel driving circuit in the m-th row, 53(m) refers to the first pole of the fifth transistor of the pixel driving circuit in the m-th row, 54(m) refers to the second pole of the fifth transistor of the pixel driving circuit in the m-th row, 63(m) refers to the first pole of the sixth transistor of the pixel driving circuit in the m-th row, 64(m) refers to the second pole of the sixth transistor of the pixel driving circuit in the m-th row, 73(m) refers to the first pole of the seventh transistor of the pixel driving circuit in the m-th row, 74(m) refers to the second pole of the seventh transistor of the pixel driving circuit in the m-th row, 83(m) refers to the first pole of the eighth transistor of the pixel driving circuit in the m-th row, 84(m) refers to the second pole of the eighth transistor of the pixel driving circuit in the m-th row, 93(m) refers to the first pole of the ninth transistor of the pixel driving circuit in the m-th row, 94(m) refers to the second pole of the ninth transistor of the pixel driving circuit in the m-th row.

[0361] In an exemplary embodiment, the orthographic projection of the second initial signal line INITL2 connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line connected to at least one pixel driving circuit on the substrate. Exemplarily, the orthographic projection of the second initial signal line INITL2 connected to at least one pixel driving circuit on the substrate lies within the orthographic projection of the second reset signal line connected to at least one pixel driving circuit on the substrate.

[0362] In an exemplary embodiment, the orthographic projection of the third initial signal line INITL3 connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line connected to at least one pixel driving circuit on the substrate. Exemplarily, the orthographic projection of the third initial signal line INITL3 connected to at least one pixel driving circuit on the substrate lies within the orthographic projection of the light-emitting signal line connected to at least one pixel driving circuit on the substrate.

[0363] In an exemplary embodiment, the shape of the second initial signal line INIT2 can be a line shape in which the main body extends along the first direction D1. The second initial signal line INIT2, to which at least one pixel driving circuit is connected, is integrally structured with the first electrode 73 of the seventh transistor.

[0364] In an exemplary embodiment, the shape of the third initial signal line INIT3 can be a line shape in which the main body extends along the first direction D1. The third initial signal line INIT3, to which at least one pixel driving circuit is connected, is integrally structured with the first electrode 93 of the ninth transistor.

[0365] In an exemplary embodiment, the first electrode 13 of the first transistor is separately disposed and is strip-shaped extending along the first direction D1. The first electrode of the first transistor of at least one pixel driving circuit is connected to the first region of the active layer of the first transistor through a second via.

[0366] In an exemplary embodiment, the second electrode 14 of the first transistor and the first electrode 23 of the second transistor are integrally formed. The integral structure of the second electrode 14 of the first transistor and the first electrode 23 of the second transistor is strip-shaped, extending along the second direction D2. The second electrode (which is also the first electrode of the second transistor) of at least one pixel driving circuit is connected to the second plate of the first capacitor through a first via, to the second region of the active pattern of the first transistor through a third via, and to the first region of the active layer of the second transistor through a fourth via.

[0367] In an exemplary embodiment, the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 63 of the sixth transistor are integrally formed. The shape of this integral structure can be a "T" shape rotated 90 degrees to the left. The second electrode of the second transistor (which is also the second electrode of the third transistor and the first electrode of the sixth transistor) of at least one pixel driving circuit is connected to the second region of the active pattern of the second transistor through a fifth via, to the second region of the active pattern of the third transistor through a seventh via, and to the first region of the active layer of the sixth transistor through a twelfth via.

[0368] In an exemplary embodiment, the first electrode 33 of the third transistor, the second electrode 54 of the fifth transistor, and the second electrode 94 of the ninth transistor are a single, integrated structure. The shape of this integrated structure can be a "T" shape rotated 90 degrees to the left. The first electrode of the third transistor (which is also the second electrode of the fifth and ninth transistors) of at least one pixel driving circuit is connected to the first region of the active layer of the third transistor via a sixth via, to the second region of the active layer of the fifth transistor via an eleventh via, and to the second region of the active pattern of the ninth transistor via a nineteenth via.

[0369] In an exemplary embodiment, the first electrode 43 of the fourth transistor is provided separately. The shape of the first electrode 43 of the fourth transistor can be a strip extending along the first direction D1. The first electrode of the fourth transistor of at least one pixel driving circuit is connected to the first region of the active layer of the fourth transistor through an eighth via.

[0370] In an exemplary embodiment, the second electrode 44 of the fourth transistor is provided separately. The shape of the second electrode 44 of the fourth transistor can be a strip extending along the second direction D2. The second electrode of the fourth transistor of at least one pixel driving circuit is connected to the second region of the active layer of the fourth transistor through a ninth via, and is connected to the first plate of the first capacitor (which is also the first plate of the second capacitor and the control electrode of the third transistor) through a twentieth via.

[0371] In an exemplary embodiment, the first electrode 53 of the fifth transistor is provided separately. The shape of the first electrode 53 of the fifth transistor can be a strip extending along the first direction D1. The first electrode of the fifth transistor of at least one pixel driving circuit is connected to the first region of the active layer of the fifth transistor through a tenth via.

[0372] In an exemplary embodiment, the second electrode 64 of the sixth transistor and the second electrode 74 of the seventh transistor are an integral structure. The shape of the integral structure of the second electrode 64 of the sixth transistor and the second electrode 74 of the seventh transistor can be "L" shaped. The second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) of at least one pixel driving circuit is connected to the second region of the active pattern of the sixth transistor through a thirteenth via, and connected to the second region of the active pattern of the seventh transistor through a fifteenth via.

[0373] In an exemplary embodiment, the first electrode 73 of the seventh transistor is shaped as a strip extending along the second direction D2. The first electrode of the seventh transistor of at least one pixel driving circuit is connected to the first region of the active layer of the seventh transistor through a fourteenth via.

[0374] In an exemplary embodiment, the first electrode 83 of the eighth transistor is shaped as a strip extending along the first direction D1. The first electrode of the eighth transistor of at least one pixel driving circuit is connected to the first region of the active layer of the eighth transistor through a sixteenth via.

[0375] In an exemplary embodiment, the second electrode 84 of the eighth transistor is shaped as a strip extending along the second direction D2. The second electrode of the eighth transistor of at least one pixel driving circuit is connected to the second region of the active layer of the eighth transistor through a seventeenth via, and is connected to the first plate of the first capacitor (which is also the first plate of the second capacitor and the control electrode of the third transistor) through a twentyth via.

[0376] In an exemplary embodiment, the first electrode 93 of the ninth transistor is shaped as a strip extending along the second direction D2. The first electrode of the ninth transistor of at least one pixel driving circuit is connected to the first region of the active layer of the ninth transistor through an eighteenth via.

[0377] In an exemplary embodiment, the main outline of the second plate C22 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second plate C22 of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the main body of the first plate of the first capacitor (which is also the first plate of the second capacitor and the control electrode of the third transistor) on the substrate.

[0378] In an exemplary embodiment, the second initial signal line INITL2 and the third initial signal line INITL3 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0379] (6) Forming a first planarization layer pattern includes: coating a first planarization film on a substrate on which the aforementioned pattern is formed, and patterning the first planarization film through a patterning process to form a first planarization layer pattern covering the aforementioned pattern. The first planarization layer has multiple via patterns, as shown in Figure 24. Figure 24 is a schematic diagram after the formation of the first planarization layer pattern.

[0380] In an exemplary embodiment, as shown in FIG24, the plurality of vias in the first planarization layer pattern include at least: a twenty-first via V21 to a twenty-sixth via V26 located in at least one pixel driving circuit.

[0381] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the second plate of the second capacitor on the substrate. The 21st via V21 exposes the surface of the second plate of the second capacitor. The 21st via V21 is configured to allow a subsequently formed first power line to be connected to the second plate of the second capacitor through the via.

[0382] In an exemplary embodiment, the orthographic projection of the 22nd via V22 on the substrate is within the range of the orthographic projection of the first electrode of the first transistor on the substrate. The 22nd via V22 exposes the surface of the first electrode of the first transistor. The 22nd via V22 is configured to allow a subsequently formed first initial signal line to be connected to the first electrode of the first transistor through the via.

[0383] In an exemplary embodiment, the orthogonal projection of the 23rd via V23 onto the substrate is within the range of the orthogonal projection of the first electrode of the fourth transistor onto the substrate. The 23rd via V23 exposes the surface of the first electrode of the fourth transistor. The 23rd via V23 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor.

[0384] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate is within the range of the orthographic projection of the first electrode of the fifth transistor onto the substrate. The 24th via V24 exposes the surface of the first electrode of the fifth transistor. The 24th via V24 is configured to allow a subsequently formed first power line to be connected to the first electrode of the fifth transistor through the via.

[0385] In an exemplary embodiment, the orthogonal projection of the 25th via V25 onto the substrate lies within the range of the orthogonal projection of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) onto the substrate. The 25th via V25 exposes the surface of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor). The 25th via V25 is configured to allow a subsequently formed anode connection electrode to be connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the via.

[0386] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate is within the range of the orthographic projection of the first electrode of the eighth transistor onto the substrate. The 26th via V26 exposes the surface of the first electrode of the eighth transistor. The 26th via V26 is configured to allow a subsequently formed reference signal line to be connected to the first electrode of the eighth transistor through the via.

[0387] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern, as shown in Figures 25 and 26. Figure 25 is a schematic diagram of the fourth conductive layer pattern, and Figure 26 is a schematic diagram after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0388] In an exemplary embodiment, as shown in Figures 25 and 26, the fourth conductive layer pattern may include: a data signal line DL, a reference signal line REFL, a first power supply line VDDL, a first initial signal line INITL1, and an anode connection electrode AL located in at least one pixel driving circuit.

[0389] In an exemplary embodiment, at least one pixel driving circuit is connected to a data signal line DL, a first power supply line VDDL, a reference signal line REFL, and a first initial signal line INITL1, which are arranged sequentially along a first direction D1.

[0390] In an exemplary embodiment, the data signal line DL can be a line shape extending along the second direction D2 from the main body portion. The data signal line DL, to which at least one pixel driving circuit is connected, is connected to the first terminal of the fourth transistor via a twenty-third via.

[0391] In an exemplary embodiment, the reference signal line REFL can be a line shape extending along the second direction D2 from the main body portion. The reference signal line REFL, to which at least one pixel driving circuit is connected, is connected to the first terminal of the eighth transistor via a twenty-sixth via.

[0392] In an exemplary embodiment, the first power line VDDL includes a power body line 101 and a plurality of power protrusions 102. The plurality of power protrusions 102 are spaced apart and located on the side of the power body line 101 near the reference signal line. The power body line 101 is a line extending along a second direction D2. At least one of the plurality of power protrusions 102 may be rectangular in shape.

[0393] In an exemplary embodiment, the orthographic projection of at least one of the power protrusions 102 on the substrate at least partially overlaps with the orthographic projection of at least one of the first and second capacitors in at least one pixel driving circuit on the substrate.

[0394] In an exemplary embodiment, the power main line 101 of the first power line VDDL to which at least one pixel driving circuit is connected is connected to the first electrode of the fifth transistor through a twenty-fourth via. At least one of the plurality of power protrusions 102 of the first power line VDDL to which at least one pixel driving circuit is connected is connected to the second electrode of the second capacitor through a twenty-first via.

[0395] In an exemplary embodiment, the first power line VDDL includes a power body line 101 and a plurality of power protrusions 102. The power body line 101 is connected to the plurality of power protrusions 102. The plurality of power protrusions 102 are spaced apart and located on the side of the power body line 101 closer to the reference signal line. The power body line 101 is a line extending along a second direction D2. At least one of the plurality of power protrusions 102 may be rectangular in shape.

[0396] In an exemplary embodiment, the orthographic projection of at least one of the power protrusions 102 on the substrate at least partially overlaps with the orthographic projection of at least one of the first and second capacitors in at least one pixel driving circuit on the substrate.

[0397] In an exemplary embodiment, the power main line 101 of the first power line VDDL to which at least one pixel driving circuit is connected is connected to the first electrode of the fifth transistor through a twenty-fourth via. At least one of the plurality of power protrusions 102 of the first power line VDDL to which at least one pixel driving circuit is connected is connected to the second electrode of the second capacitor through a twenty-first via.

[0398] In an exemplary embodiment, the first initial signal line INITL1 includes a plurality of initial signal traces 201 and a plurality of initial connection portions 202, which are alternately arranged. At least one of the plurality of initial signal traces 201 has a line shape extending along a second direction D2. At least one of the plurality of initial connection portions 202 may have a rectangular shape.

[0399] In an exemplary embodiment, the linewidth of at least one of the plurality of initial connection portions 202 along the first direction D1 is greater than the linewidth of at least one of the plurality of initial signal traces 201 along the first direction D1.

[0400] In an exemplary embodiment, at least a portion of at least one of the initial connection portions 202 of the plurality of initial connection portions 202 is projected onto the substrate between the orthogonal projection of the first scan signal line connected to at least one pixel driving circuit onto the substrate and the orthogonal projection of the fourth reset signal line onto the substrate.

[0401] In an exemplary embodiment, at least one of the plurality of initial connection portions 202 of the first initial signal line INITL1 to which at least one pixel driving circuit is connected is connected to the first pole of the first transistor through a twenty-second via.

[0402] In an exemplary embodiment, the anode connection electrode AL is provided separately and can be strip-shaped extending along the second direction D2. The anode connection electrode AL is connected to the second terminal of the sixth transistor (which is also the second terminal of the seventh transistor) through a twenty-fifth via.

[0403] In an exemplary embodiment, the line width of at least one of the power supply body line of the first power line and at least one of the initial signal traces of the first initial signal line is greater than the line width of at least one of the data signal line and the reference signal line.

[0404] (8) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern includes: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film by a patterning process to form a second planarization layer pattern covering the aforementioned pattern. The second planarization layer has a plurality of via patterns, as shown in FIG27, FIG27 being a schematic diagram after the formation of the second planarization layer pattern.

[0405] In an exemplary embodiment, as shown in FIG27, the plurality of vias in the second planarization layer pattern include at least a twenty-seventh via V27 located in at least one pixel driving circuit.

[0406] In an exemplary embodiment, the orthographic projection of the 27th via V27 on the substrate is within the range of the orthographic projection of the anode connection electrode on the substrate. The 27th via V27 exposes the surface of the anode connection electrode. The 27th via V27 is configured to allow the anode of a subsequently formed light-emitting device to be connected to the anode connection electrode through the via.

[0407] At this point, the circuit structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the circuit structure layer may include multiple pixel driving circuits and multiple signal lines connected to the pixel driving circuits. In a plane perpendicular to the display substrate, the circuit structure layer may be disposed on the substrate. The pixel driving circuit for at least one sub-pixel includes at least one transistor and at least one capacitor, the capacitor including a first electrode and a second electrode.

[0408] The pixel driving circuit layer may include a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer, which are sequentially disposed on the substrate.

[0409] In an exemplary embodiment, the semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0410] In an exemplary embodiment, at least one of the first to fourth conductive layers may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the first conductive layer may include molybdenum.

[0411] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0412] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of organic materials.

[0413] In an exemplary embodiment, after the circuit structure layer is fabricated, a light-emitting structure layer is fabricated on the circuit structure layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0414] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern includes: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer pattern. As shown in Figures 28 and 29, Figure 28 is a schematic diagram of the fifth conductive layer pattern, and Figure 29 is a schematic diagram after the fifth conductive layer pattern is formed.

[0415] In an exemplary embodiment, as shown in Figures 28 and 29, the plurality of vias in the fifth conductive layer pattern include at least: an anode 301 of at least one light-emitting device.

[0416] In an exemplary embodiment, the anode 301 of at least one light-emitting device may be polygonal in shape. The anode 301 of at least one light-emitting device is connected to the anode connection electrode of at least one pixel driving circuit through a twenty-seventh via.

[0417] (10) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern includes: depositing a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer pattern. As shown in FIG30, FIG30 is a schematic diagram after forming the pixel definition layer pattern.

[0418] In an exemplary embodiment, as shown in FIG30, the plurality of vias in the pixel definition layer pattern include at least: a twenty-eighth via V28 and a twenty-ninth via V29 located in at least one pixel driving circuit.

[0419] In an exemplary embodiment, the orthographic projection of the 28th via V28 onto the substrate is located within the orthographic projection range of one of the initial connection portions of the plurality of initial connection portions of the first initial signal line onto the substrate. The second planarization layer within the 28th via V28 is etched away, exposing the surface of one of the initial connection portions of the plurality of initial connection portions of the first initial signal line. The 28th via V28 is configured to allow the cathode of at least one light-emitting device subsequently formed to be connected to one of the initial connection portions of the plurality of initial connection portions of the first initial signal line through the via.

[0420] In an exemplary embodiment, the orthographic projection of the 29th via V29 onto the substrate is within the range of the orthographic projection of the anode of at least one light-emitting device onto the substrate, the 29th via V29 exposes the surface of the anode of at least one light-emitting device, and the 27th via V27 is configured to allow the organic light-emitting layer of at least one light-emitting device subsequently formed to be connected to the anode of at least one light-emitting device through the via.

[0421] (11) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming a sixth conductive layer pattern includes: coating an organic light-emitting material on a substrate on which the aforementioned pattern is formed, patterning the organic light-emitting material using a patterning process to form an organic structure layer pattern, depositing a cathode conductive film on the substrate on which the organic material layer pattern is formed, and patterning the cathode conductive film using a patterning process to form a cathode conductive layer.

[0422] In an exemplary embodiment, the organic structure layer includes: an organic light-emitting layer of at least one light-emitting device.

[0423] The organic light-emitting layer of at least one light-emitting device is connected to the anode of at least one light-emitting device through a twenty-ninth via.

[0424] In an exemplary embodiment, the sixth conductive layer may include at least the cathodes of a plurality of light-emitting devices.

[0425] The cathode of at least one light-emitting device is connected to one of the initial connection portions of the first initial signal line through a twenty-eighth via.

[0426] At this point, the luminescent structure layer has been successfully fabricated on the substrate.

[0427] In an exemplary embodiment, the fifth conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0428] In an exemplary embodiment, the sixth conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0429] In an exemplary embodiment, the subsequent fabrication process may include: forming an encapsulation structure layer on the sixth conductive layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0430] The display substrate described in this embodiment can be used in display products of any resolution.

[0431] This disclosure also provides a display device, including: a display substrate provided in any of the foregoing embodiments.

[0432] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0433] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0434] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0435] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel driving circuit configured to drive a light-emitting device to emit light, comprising: The driving sub-circuit, the isolation sub-circuit, the first control sub-circuit, the second control sub-circuit, and the third control sub-circuit; The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node. The isolation sub-circuit is electrically connected to the second scan signal terminal, the first node, the third node, and the fifth node, respectively. It is configured to connect or disconnect the third node and the fifth node under the control of the signal at the second scan signal terminal, and to store the voltage difference between the signals of the first node and the fifth node. The first control sub-circuit is electrically connected to the first scan signal terminal, the data signal terminal and the first node respectively, and is configured to provide the data signal terminal to the first node under the control of the signal of the first scan signal terminal; The second control sub-circuit is electrically connected to at least one reset signal terminal, at least one initial signal terminal, a second node, a fourth node, and one of the third and fifth nodes, respectively, and is configured to provide a signal from at least one initial signal terminal to one of the second node, the fourth node, and one of the third and fifth nodes, respectively, under the control of the signal from at least one reset signal terminal. The third control sub-circuit is electrically connected to the light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively, and is configured to provide the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node under the control of the signal from the light-emitting signal terminal. The light-emitting device is electrically connected to the fourth node and the second power supply terminal, respectively.

2. The pixel driving circuit according to claim 1 further includes: Fourth control sub-circuit; When the second control sub-circuit is electrically connected to the fifth node, the fourth control sub-circuit is electrically connected to the first node and the first power supply terminal respectively, and is configured to store the voltage difference between the signals of the first node and the first power supply terminal. When the second control sub-circuit is electrically connected to the third node, the fourth control sub-circuit is electrically connected to the fifth node and the second power supply terminal respectively, and is configured to store the voltage difference between the signals of the fifth node and the second power supply terminal.

3. The pixel driving circuit according to claim 1, wherein, The isolation sub-circuit includes: a second transistor and a first capacitor, the first capacitor including: a first plate and a second plate; The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the fifth node.

4. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit is also electrically connected to the fourth reset signal terminal and the reference signal terminal respectively, and is configured to provide the reference signal terminal to the first node under the control of the signal of the fourth reset signal terminal; The first control sub-circuit includes: a fourth transistor and an eighth transistor; The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node. The control terminal of the eighth transistor is electrically connected to the fourth reset signal terminal, the first terminal of the eighth transistor is electrically connected to the reference signal terminal, and the second terminal of the eighth transistor is electrically connected to the first node.

5. The pixel driving circuit according to claim 1, wherein, The at least one reset signal terminal includes: a first reset signal terminal, a second reset signal terminal, and a third reset signal terminal; the at least one initial signal terminal includes: a first initial signal terminal, a second initial signal terminal, and a third initial signal terminal. The second control sub-circuit is configured to provide a signal from a third initial signal terminal to a second node, a signal from a first initial signal terminal to one of the third and fifth nodes, and a signal from a second initial signal terminal to a fourth node; When the second control sub-circuit is electrically connected to the fifth node, the second control sub-circuit includes: a first transistor, a seventh transistor, and a ninth transistor; The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the fifth node. The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node. The control terminal of the ninth transistor is electrically connected to the third reset signal terminal, the first terminal of the ninth transistor is electrically connected to the third initial signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node.

6. The pixel driving circuit according to claim 1, wherein, The at least one reset signal terminal includes: a first reset signal terminal, a second reset signal terminal, and a third reset signal terminal; the at least one initial signal terminal includes: a first initial signal terminal, a second initial signal terminal, and a third initial signal terminal. The second control sub-circuit is configured to provide a signal from a third initial signal terminal to a second node, a signal from a first initial signal terminal to one of the third and fifth nodes, and a signal from a second initial signal terminal to a fourth node; When the second control sub-circuit is electrically connected to the third node, the second control sub-circuit includes: a first transistor, a seventh transistor, and a ninth transistor; The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node. The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node. The control terminal of the ninth transistor is electrically connected to the third reset signal terminal, the first terminal of the ninth transistor is electrically connected to the third initial signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node.

7. The pixel driving circuit according to claim 2, wherein, The fourth control sub-circuit includes: a second capacitor, which includes: a first plate and a second plate; When the second control sub-circuit is electrically connected to the fifth node, the first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first power supply terminal. When the second control sub-circuit is electrically connected to the third node, the first plate of the second capacitor is electrically connected to the fifth node, and the second plate of the second capacitor is electrically connected to the second power supply terminal.

8. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit is also electrically connected to a fourth reset signal terminal and a reference signal terminal, respectively. The at least one reset signal terminal includes a first reset signal terminal, a second reset signal terminal, and a third reset signal terminal. The at least one initial signal terminal includes a first initial signal terminal, a second initial signal terminal, and a third initial signal terminal. When the second control sub-circuit is electrically connected to the fifth node, the pixel driving circuit further includes a fourth control sub-circuit, wherein the driving sub-circuit includes a third transistor, the isolation sub-circuit includes a second transistor and a first capacitor, the first control sub-circuit includes a fourth transistor and an eighth transistor, the second control sub-circuit includes a first transistor, a seventh transistor, and a ninth transistor, and the third control sub-circuit includes a fifth transistor and a sixth transistor. The fourth control sub-circuit includes a second capacitor, and the first and second capacitors include a first electrode and a second electrode. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the fifth node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node. The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node. The control terminal of the eighth transistor is electrically connected to the fourth reset signal terminal, the first terminal of the eighth transistor is electrically connected to the data signal terminal, and the second terminal of the eighth transistor is electrically connected to the first node. The control terminal of the ninth transistor is electrically connected to the third reset signal terminal, the first terminal of the ninth transistor is electrically connected to the third initial signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the fifth node. The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first power supply terminal.

9. The pixel driving circuit according to claim 8, wherein, For the same pixel driving circuit, the signal received by the first initial signal terminal is the same as the signal received by the second power supply terminal, and the signal received by the second reset signal terminal is the same as the signal received by the fourth reset signal terminal. In at least one display frame, the duration of the time period in which the second reset signal terminal receives the valid level signal is the same as the duration of the time period in which the third reset signal terminal receives the valid level signal, and the duration of the time period in which the first reset signal terminal receives the valid level signal is the same as the duration of the time period in which the first scan signal terminal receives the valid level signal.

10. The pixel driving circuit of claim 9, wherein, For the same pixel driving circuit, the time period in which the signal of at least one of the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the fourth reset signal terminal, and the first scan signal terminal is an effective level signal is located within the time period in which the signal of the second scan signal terminal is an effective level signal. The start time of the period in which the signal at the second reset signal terminal is at an effective level is earlier than the start time of the period in which the signal at the third reset signal terminal is at an effective level, and the end time of the period in which the signal at the second reset signal terminal is at an effective level is within the period in which the signal at the third reset signal terminal is at an effective level. The start time of the period in which the signal at the first reset signal terminal is at an effective level is later than the start time of the period in which the signal at the second reset signal terminal is at an effective level, and earlier than the start time of the period in which the signal at the third reset signal terminal is at an effective level. The time period during which the signal at the first scan signal terminal is at an effective level is after the time period during which the signal at the third reset signal terminal is at an effective level.

11. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit is also electrically connected to a fourth reset signal terminal and a reference signal terminal, respectively. The at least one reset signal terminal includes a first reset signal terminal, a second reset signal terminal, and a third reset signal terminal. The at least one initial signal terminal includes a first initial signal terminal, a second initial signal terminal, and a third initial signal terminal. When the second control sub-circuit is electrically connected to the third node, the pixel driving circuit further includes a fourth control sub-circuit, wherein the driving sub-circuit includes a third transistor, the isolation sub-circuit includes a second transistor and a first capacitor, the first control sub-circuit includes a fourth transistor and an eighth transistor, the second control sub-circuit includes a first transistor, a seventh transistor, and a ninth transistor, and the third control sub-circuit includes a fifth transistor and a sixth transistor. The fourth control sub-circuit includes a second capacitor, and the first and second capacitors include a first electrode and a second electrode. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the third node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node. The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node. The control terminal of the eighth transistor is electrically connected to the fourth reset signal terminal, the first terminal of the eighth transistor is electrically connected to the data signal terminal, and the second terminal of the eighth transistor is electrically connected to the first node. The control terminal of the ninth transistor is electrically connected to the third reset signal terminal, the first terminal of the ninth transistor is electrically connected to the third initial signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the fifth node. The first plate of the second capacitor is electrically connected to the fifth node, and the second plate of the second capacitor is electrically connected to the second power supply terminal.

12. The pixel driving circuit according to claim 11, wherein, For the same pixel driving circuit, the signal received by the first reset signal terminal and the signal received by the second reset signal terminal are the same.

13. The pixel driving circuit according to claim 11, wherein, For the same pixel driving circuit, the time period in which the signal of at least one of the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the fourth reset signal terminal, and the first scan signal terminal is an effective level signal is located within the time period in which the signal of the second scan signal terminal is an effective level signal. The time period in which the signal of at least one of the first reset signal terminal, the second reset signal terminal, and the third reset signal terminal is at an effective level is within the time period in which the signal of the fourth scan signal terminal is at an effective level, and the end time of the time period in which the signal of the first reset signal terminal is at an effective level is earlier than the start time of the time period in which the signal of the third reset signal terminal is at an effective level. The time period during which the signal at the first scan signal terminal is at an effective level is after the time period during which the signal at the fourth scan signal terminal is at an effective level.

14. The pixel driving circuit of claim 1, wherein, For the same pixel driving circuit, the end time of the effective level signal at the second scanning signal terminal is within the time period of the effective level signal at the light emission signal terminal, or the end time of the effective level signal at the second scanning signal terminal is earlier than the start time of the time period of the effective level signal at the light emission signal terminal.

15. The pixel driving circuit according to claim 8 or 11, wherein, At least one of the first to ninth transistors is an oxide transistor.

16. A display substrate, comprising: A substrate and a plurality of pixel driving circuits and a plurality of light-emitting devices arranged in an array on the substrate as described in any one of claims 1 to 15, wherein at least one of the plurality of light-emitting devices comprises: an anode and a cathode, and at least one pixel driving circuit is electrically connected to the anode of at least one light-emitting device. When the second control sub-circuit in the pixel driving circuit is electrically connected to the fifth node, the display substrate further includes: multiple first initial signal lines; At least one of the plurality of first initial signal lines is electrically connected to a first initial signal terminal in at least one pixel driving circuit, and extends at least partially along the second direction; At least one of the multiple first initial signal lines is electrically connected to the cathode of at least one light-emitting device.

17. The display substrate according to claim 16, wherein, One of the multiple first initial signal lines includes: multiple initial signal traces and multiple initial connection parts, which are alternately arranged and interconnected. At least one of the plurality of initial signal traces extends at least partially along the second direction, and at least one of the plurality of initial connection portions extends at least partially along the second direction; The display substrate further includes: a plurality of initial vias, at least one of the plurality of initial vias exposing at least one initial connection portion of a plurality of initial connection portions, and the cathode of at least one light-emitting device is connected to one of a plurality of first initial signal lines through at least one initial via; At least one of the multiple initial connection portions has a linewidth along a first direction that is greater than the linewidth of at least one of the multiple initial signal traces along the first direction, and the first direction intersects with the second direction.

18. The display substrate according to claim 17, further comprising: Multiple initial connection lines; At least one of the plurality of initial connection lines is electrically connected to the plurality of first initial signal lines and extends at least partially along the first direction.

19. The display substrate of claim 16, further comprising: Multiple first power lines, the pixel driving circuit includes: a first capacitor and a second capacitor; At least one of the plurality of first power lines is electrically connected to a first power terminal in at least one pixel driving circuit, and extends at least partially along the second direction; At least one of the multiple first power lines includes: a power main line and multiple power protrusions; the power main line is connected to the multiple power protrusions, and the multiple power protrusions are spaced apart; The orthographic projection of at least one of the plurality of power supply protrusions on the substrate at least partially overlaps with the orthographic projection of at least one of the first and second capacitors in at least one pixel driving circuit on the substrate. 20.The display substrate of claim 16, wherein, The pixel driving circuit includes: a first capacitor and a second capacitor, and the first capacitor and the second capacitor include: a first electrode plate and a second electrode plate. The orthographic projection of the first capacitor on the substrate and the orthographic projection of the second capacitor on the substrate at least partially overlap, and at least one plate of the first capacitor and at least one plate of the second capacitor are the same plate.

21. The display substrate according to claim 16, further comprising: Multiple first scan signal lines, multiple second scan signal lines, multiple light emission signal lines, multiple first reset signal lines, multiple second reset signal lines, multiple third reset signal lines, and multiple fourth reset signal lines; At least one of the following signals—a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of light emission signal lines, a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of third reset signal lines, and a plurality of fourth reset signal lines—extends at least partially along a first direction; At least one of the plurality of first scan signal lines is electrically connected to the first scan signal terminal of at least one pixel driving circuit; at least one of the plurality of second scan signal lines is electrically connected to the second scan signal terminal of at least one pixel driving circuit; at least one of the plurality of light emission signal lines is electrically connected to the light emission signal terminal of at least one pixel driving circuit; at least one of the plurality of first reset signal lines is electrically connected to the first reset signal terminal of at least one pixel driving circuit; at least one of the plurality of second reset signal lines is electrically connected to the second reset signal terminal of at least one pixel driving circuit; at least one of the plurality of third reset signal lines is electrically connected to the third reset signal terminal of at least one pixel driving circuit; and at least one of the plurality of fourth reset signal lines is electrically connected to the fourth reset signal terminal of at least one pixel driving circuit. The second reset signal line connected to the pixel driving circuit in row m is the same signal line as the fourth reset signal line connected to the pixel driving circuit in row (m-1). The second reset signal line, the light emission signal line, the third reset signal line, the second scan signal line, the first scan signal line, the first reset signal line, and the fourth reset signal line connected to at least one pixel driving circuit are arranged sequentially along the second direction.

22. The display substrate according to claim 21, further comprising: Multiple second initial signal lines and multiple third initial signal lines; At least one of the plurality of second initial signal lines is electrically connected to the second initial signal terminal of at least one pixel driving circuit, and extends at least partially along the first direction; At least one of the plurality of third initial signal lines is electrically connected to the third initial signal terminal of at least one pixel driving circuit, and extends at least partially along the first direction; The orthographic projection of the second initial signal line connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line on the substrate, and the orthographic projection of the third initial signal line connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the light emission signal line on the substrate.

23. The display substrate according to claim 16, further comprising: The pixel driving circuit includes multiple first initial signal lines, multiple second initial signal lines, multiple third initial signal lines, multiple first scan signal lines, multiple second scan signal lines, multiple light emission signal lines, multiple first reset signal lines, multiple second reset signal lines, multiple third reset signal lines, multiple fourth reset signal lines, multiple data signal lines, multiple first power supply lines, and multiple reference signal lines. The pixel driving circuit also includes multiple transistors, a first capacitor, and a second capacitor. The first and second capacitors each include a first electrode plate and a second electrode plate. The display substrate further includes: a circuit structure layer disposed on the substrate, the circuit structure layer including: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate; The first conductive layer includes at least: the second electrode of the first capacitor; The semiconductor layer includes at least: an active pattern of at least one transistor among a plurality of transistors in at least one pixel driving circuit; The second conductive layer includes at least: multiple first scan signal lines, multiple second scan signal lines, multiple light emission signal lines, multiple first reset signal lines, multiple second reset signal lines, multiple third reset signal lines, multiple fourth reset signal lines, the control electrode of at least one transistor of at least one pixel driving circuit, the first electrode of a first capacitor, and the first electrode of a second capacitor. The third conductive layer includes at least: multiple second initial signal lines, multiple third initial signal lines, and the first and second terminals of at least one transistor of at least one pixel driving circuit, as well as the second plate of the second capacitor; The fourth conductive layer includes at least: multiple data signal lines, multiple reference signal lines, multiple first power lines, and multiple first initial signal lines.

24. The display substrate according to claim 23, further comprising: Multiple initial connection lines; Multiple initial connection lines are located in at least one of the first conductive layer, the second conductive layer, and the third conductive layer.

25. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as described in any one of claims 1 to 15, the method comprising: The driving sub-circuit provides a driving signal to the third node under the control of the signals from the first and second nodes; The isolation sub-circuit, under the control of the signal at the second scanning signal terminal, connects or disconnects the third and fifth nodes, and stores the voltage difference between the signals of the first and fifth nodes; The first control sub-circuit provides the data signal terminal signal to the first node under the control of the signal at the first scan signal terminal; Under the control of at least one reset signal terminal, the second control sub-circuit provides at least one initial signal terminal signal to one of the second node, the fourth node, the third node, and the fifth node, respectively. Under the control of the signal at the light-emitting signal terminal, the third control sub-circuit provides the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node.

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