Method for warm boot of processor

Abstract

The present application provides a method for warm boot of a processor. In the method, a first warm boot vector of a master core and a second warm boot vector of slave cores are set in a power-off retention region of an internal memory, and in a cold boot phase, a master core image, a slave core image, a master core dynamic library and a service dynamic library are pre-stored in the power-off retention region. By setting the boot vectors of the master core and the slave cores in the power-off retention region, rapid boot of the master core and the slave cores can be realized. By storing the master core image, the slave core image, the master core dynamic library, and the service dynamic library required for running a first service in the power-off retention region of the internal memory, the steps of acquiring the master core image, the slave core image, the master core dynamic library, and the service dynamic library from an external memory can be removed, thereby shortening the warm boot duration of a computing device, reducing the energy consumption of the computing device, and improving a user experience.

Description

A processor hot boot method

[0001] This application claims priority to Chinese patent application No. 202411749181.8, filed on November 29, 2024, entitled "A Method for Hot-Starting a Processor", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of information and communication, and in particular to a method for hot-starting a processor. Background Technology

[0003] To reduce the energy consumption of computing devices, it is typically necessary to shut down unnecessary hardware resources when there is no business activity or low load, and then promptly wake up these hardware resources when business needs arise. Therefore, the rapid wake-up of hardware resources has become a key performance indicator for computing devices.

[0004] A recent hot-start solution has been proposed to accelerate the wake-up time of hardware resources. This solution employs Suspend To RAM (STR) technology. While the computing device is running, the current runtime state data of the operating system's business processes is saved to Double Data Rate SDRAM (DDR), and the processor and other hardware devices are shut down, entering a system hibernation state. Then, after hibernation ends, the aforementioned runtime state data is restored from DDR, the processor is restored to its running state, and the business processes continue to execute.

[0005] However, STR technology can only restore some hardware devices to their runtime state. Using STR technology requires accurate restoration of runtime state data, which is difficult to execute. It also requires a long period of stability during the operation of the computing device and may lead to network problems, such as service interruption and communication quality degradation.

[0006] We hope there will be an improvement plan that can better shorten the warm-up time of computing devices. Summary of the Invention

[0007] This specification describes a processor hot-start scheme through one or more embodiments. By storing the main core image, slave core image, main core dynamic library, and service dynamic library required to run the first service in the power-down retention area of ​​the internal memory, the steps of obtaining the main core image, slave core image, main core dynamic library, and service dynamic library from external memory can be omitted, thereby shortening the hot-start time of the computing device, reducing the power consumption of the computing device, and improving the user experience.

[0008] In a first aspect, this application provides a hot-start method for a processor, the processor including a main core and multiple slave cores, the method being applied to the main core, comprising: loading a main core image through a first hot-start vector in a first memory space to start the main core, the first memory space being a power-down retention area set in the internal memory, the first memory space including the main core image, slave core images, a main core dynamic library, and a service dynamic library required for running a first service, pre-stored during a cold start phase; activating a first slave core so that the first slave core loads the slave core image through a second hot-start vector in the first memory space to start the first slave core, the first slave core being one of the multiple slave cores; loading the main core image and the main core dynamic library in the first memory space into a second memory space, and using the first slave core to load the slave core image and the service dynamic library in the first memory space into a third memory space, the second memory space being the execution space corresponding to the main core in the internal memory, and the third memory space being the execution space corresponding to the first slave core in the internal memory.

[0009] In this application, a first hot-start vector for the master core and a second hot-start vector for the slave core are set in the power-down retention region of internal memory. During the cold start phase, the master core image, slave core image, master core dynamic library, and business dynamic library are pre-stored in the aforementioned power-down retention region. By setting the boot vectors of the master and slave cores in the power-down retention region, parallel booting of the master and slave cores can be achieved, eliminating the step of retrieving the aforementioned master core image, slave core image, master core dynamic library, and business dynamic library from external memory. This shortens the processor's hot-start time, reduces the power consumption of the computing device, and improves the user experience.

[0010] In some possible implementations, the main core image includes a first main core image corresponding to the first hot start vector, the first memory space includes a running area, and before loading the main core image through the first hot start vector in the first memory space, the method includes: during the cold start phase, loading the first main core image into the running area according to the first hot start vector.

[0011] In this application, during the cold start phase of the processor, the main core pre-stores the first main core image in the running area, so that the processor can maintain the image in memory when hibernating, so that the main core can quickly start according to the first hot start vector when the processor exits hibernation mode, thus shortening the hot start time of the processor.

[0012] In some possible implementations, the first memory space includes an external region, and the method includes: during the cold start phase, storing the main kernel image and the main kernel dynamic library to the external region.

[0013] In this application, during the cold start phase of the processor, the main core pre-stores data that will not be updated during runtime, such as the main core image and the main core dynamic library, in the external area. This allows the processor to maintain the main core image and the main core dynamic library in memory while hibernating, so that when the processor exits hibernation mode, the main core can quickly load the main core image and the main core dynamic library into the execution area of ​​the main core, shortening the processor's hot start time and enabling timely restoration of user services.

[0014] In some possible implementations, the first memory space includes a backup area, and the method further includes: during the cold start phase, storing a first loading attribute corresponding to the main core in the backup area; the first loading attribute includes the address information of the main core image and the address information of the main core dynamic library.

[0015] In this application, during the processor's cold start phase, the main core pre-stores runtime-updated data, such as the main core's loading attributes, in a backup area. This allows the processor to retain the main core's loading attributes in memory while hibernating, so that when the processor exits hibernation mode, the main core can quickly restore its runtime state data and promptly restore the user's services.

[0016] In some possible implementations, the first master kernel image includes pre-configured first recovery code. Loading the master kernel image and master kernel dynamic library from the first memory space into the second memory space includes: executing the first recovery code to obtain the first loading attribute from the backup area; obtaining the master kernel image from the external area and loading the master kernel image into the second memory space according to the address information of the master kernel image; obtaining the master kernel dynamic library from the external area and loading the master kernel dynamic library into the second memory space according to the address information of the master kernel dynamic library.

[0017] In this application, the first recovery code of the main core is pre-set in the first main core image. When the main core executes the above recovery code, it can restore its own image and dynamic library from the power-down retention area according to the first loading attribute. This omits the step of obtaining the main core image and main core dynamic library from external memory, and restores the main core to the state before power-down. This shortens the processor's hot boot time and enables timely restoration of user services.

[0018] In some possible implementations, the slave kernel image includes a first slave kernel image corresponding to the second hot boot vector, and before loading the master kernel image through the first hot boot vector in the first memory space, the method includes: during the cold boot phase, loading the first slave kernel image into the runtime area according to the second hot boot vector.

[0019] In this application, during the cold start phase of the processor, the main core pre-stores the image of the first slave core in the running area, so that the processor can maintain the image in memory when hibernating. This allows the first slave core to quickly start according to the second hot start vector when the processor exits hibernation mode, thus shortening the processor's hot start time.

[0020] In some possible implementations, the method further includes: during the cold start phase, storing the kernel image and the business dynamic library to the external area.

[0021] In this application, during the cold start phase of the processor, the main core pre-stores data that the first slave core will not update during runtime, such as the slave core image and business dynamic library, in an external area. This allows the processor to maintain the slave core image and business dynamic library in memory during hibernation, so that when the processor exits hibernation mode, the first slave core can quickly load the slave core image and business dynamic library into the execution area corresponding to the slave core, shortening the processor's hot start time and enabling timely restoration of user services.

[0022] In some possible implementations, the method further includes: during the cold start phase, storing the second loading attribute corresponding to the first slave core in the backup area, wherein the second loading attribute includes the address information of the slave core image and the address information of the business dynamic library.

[0023] In this application, during the cold start phase of the processor, the main core pre-stores the data updated by the first slave core during runtime, such as the loading attributes of the first slave core, in the backup area. This allows the processor to maintain the loading attributes of the first slave core in memory during hibernation, so that when the processor exits hibernation mode, the first slave core can quickly restore the runtime state data of the first slave core and promptly restore the user's business.

[0024] In some possible implementations, the first slave kernel image includes pre-set second recovery code. The step of loading the slave kernel image and the service dynamic library from the first memory space into a third memory space using the first slave kernel includes: executing the second recovery code using the first slave kernel to obtain the second loading attribute from the backup area; obtaining the slave kernel image from the external area using the first slave kernel and loading the slave kernel image into the third memory space according to the address information of the slave kernel image; and obtaining the service dynamic library from the external area using the first slave kernel and loading the service dynamic library into the third memory space according to the address information of the service dynamic library.

[0025] In this application, the second recovery code of the first slave core is pre-set in the first slave core image. The first slave core can execute the above recovery code from the power-down retention area according to the first loading attribute, and perform the recovery of its own image and the recovery of the business dynamic library in parallel. This omits the step of obtaining the slave core image and the business dynamic library from the external memory, shortens the processor's hot boot time, and enables timely recovery of the user's business.

[0026] In some possible implementations, after loading the slave core image and the service dynamic library into a third memory space, the method includes: activating the service dynamic library using the master core so that the first slave core runs the first service.

[0027] Secondly, this application proposes a hot-start method for a processor, the processor including a main core, the method being applied to the main core, including: loading a main core image through a first hot-start vector in a first memory space to start the main core, the first memory space being a power-down retention area set in the internal memory, the first memory space including the main core image and main core dynamic library pre-stored during the cold start phase; loading the main core image and main core dynamic library in the first memory space into a second memory space; the second memory space being the execution space corresponding to the main core in the internal memory.

[0028] In this application, a first hot-start vector for the main core is set in the power-down retention region of the processor's internal memory, and during the cold start phase, the main core image and main core dynamic library are pre-stored in the aforementioned power-down retention region. For single-core processors or multi-core processors with a symmetric architecture, at least one main core can achieve its own hot start through the hot-start vector in the power-down retention region, eliminating the step of obtaining the main core image and main core dynamic library from external memory, shortening the processor's hot start time, reducing the power consumption of the computing device, and improving the user experience.

[0029] In some possible implementations, the main core image includes a first main core image corresponding to the first hot start vector, the first memory space includes a running area, and before loading the main core image through the first hot start vector in the first memory space, the method includes: during the cold start phase, loading the first main core image into the running area according to the first hot start vector.

[0030] In some possible implementations, the first memory space includes an external region, and the method includes: during the cold start phase, storing the main kernel image and the main kernel dynamic library to the external region.

[0031] In some possible implementations, the first memory space includes a backup area, and the method further includes: during the cold start phase, storing a first loading attribute corresponding to the main core in the backup area; the first loading attribute includes the address information of the main core image and the address information of the main core dynamic library.

[0032] In some possible implementations, the first master kernel image includes pre-configured first recovery code. Loading the master kernel image and master kernel dynamic library from the first memory space into the second memory space includes: executing the first recovery code to obtain the first loading attribute from the backup area; obtaining the master kernel image from the external area and loading the master kernel image into the second memory space according to the address information of the master kernel image; obtaining the master kernel dynamic library from the external area and loading the master kernel dynamic library into the second memory space according to the address information of the master kernel dynamic library.

[0033] Thirdly, this application proposes a computer-readable storage medium including computer program instructions, which, when executed by a memory, enable the memory to perform the aforementioned processor hot-start method.

[0034] Fourthly, this application proposes a computer program product containing instructions that, when executed by a memory, cause the memory to perform the aforementioned processor hot-start method.

[0035] It should be understood that the beneficial effects achieved by the technical solutions of the third and fourth aspects of the embodiments of this application and the corresponding possible implementation methods can be referred to the above-described technical effects of the first aspect, and will not be repeated here. Attached Figure Description

[0036] Figure 1 is a schematic diagram of the startup principle and process of an asymmetric architecture processor.

[0037] Figure 2 is a schematic diagram of a cold start scenario for the main core in an asymmetric architecture processor;

[0038] Figure 3 is a schematic diagram of the first cold boot scenario from the core in an asymmetric architecture processor;

[0039] Figure 4 is a schematic diagram of the second cold boot scenario in an asymmetric architecture processor;

[0040] Figure 5 is a schematic diagram of the scenario after the asymmetric architecture processor performs a hibernation operation;

[0041] Figure 6 is a schematic diagram of a scenario during a warm boot of an asymmetric architecture processor.

[0042] Figure 7 is a flowchart illustrating a processor warm-start method;

[0043] Figure 8 is a flowchart illustrating a processor cold start method;

[0044] Figure 9 is a schematic diagram of a scenario during a hot boot of a symmetric architecture processor.

[0045] Figure 10 is a flowchart illustrating another processor warm-boot method. Detailed Implementation

[0046] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0047] To facilitate understanding of the technical solution of this application, the relevant terms used in this document are explained below.

[0048] Asymmetric Multi-Processing (AMP) is a multi-core processor architecture where each core can independently run different business logic, or even different operating systems or bare-metal programs. In an AMP architecture, there is typically a master core (also called the application processor) responsible for controlling the overall system operation, and one or more slave cores (also called coprocessors). The master core is usually responsible for managing the overall operation of the operating system, while the slave cores are responsible for executing specific tasks.

[0049] An image (also known as a base binary file) is a binary file containing an operating system and basic business functions. Both the master kernel and slave kernels have their own corresponding image files. To illustrate, after the master kernel loads its own image file, it can run the operating system, completing the master kernel boot process. Then, the master kernel loads the corresponding slave kernel images for one or more slave kernels, allowing these slave kernels to run their respective operating systems or basic business functions, thus completing the slave kernel boot process.

[0050] A dynamic link library (DL) contains concrete business logic code, such as functions, variables, structures, and classes. The main core has its own main core DL, and one or more slave cores have their own business logic DLs. After the main and slave cores start up, they can load the corresponding DLs based on the user-assigned business logic type to run the user-specified business logic. For example, a slave core loads the corresponding business logic DL into its execution space, matches and updates the symbol addresses in the DL with the symbol addresses in the program, so that the program can correctly call the functions or variables in the DL to run the user-specified business logic.

[0051] Hierarchical memory is a hardware memory architecture model that refers to one or more memory locations containing multiple blocks of memory with different access speeds and accessible by address. Developers can place code and data in different memory hierarchies based on factors such as functionality and performance, without needing to concern themselves with the specific storage location of the data.

[0052] Boot vector: The boot vector is a pre-defined address in internal memory used to store the boot image, and it is usually fixed. During startup, the processor jumps to the boot vector and begins executing the boot code.

[0053] With the ever-increasing demand for computing power and communication, the scale of various infrastructures, such as data centers and base stations, is also growing rapidly. Therefore, finding energy-efficient computing equipment solutions has become a crucial objective for suppliers. To reduce the energy consumption of computing equipment, the operating system of these devices needs to shut down unnecessary hardware resources when there is no business activity or low load, and then promptly wake up these hardware resources when business needs arise. Thus, the rapid wake-up of hardware resources has become a key performance indicator for these computing devices. For example, the faster the hardware resource wake-up speed, the more granular the idle intervals the system can utilize to enter power-saving mode, resulting in more energy-saving opportunities. Conversely, a slow wake-up time may lead to untimely service responses, impacting user experience.

[0054] A recent hot-start solution has been proposed to accelerate the wake-up time of hardware resources. This solution employs STR (Sleep-Start) technology, which, while the computing device is running, saves the current running state data of the operating system to DDR (Memory Transfer Record), and shuts down hardware devices such as the processor, RAM, and peripherals, entering a system hibernation state. The aforementioned running state data includes processor context data, current values ​​of peripheral registers, and data in RAM.

[0055] Then, after the hibernation ends, the above-mentioned running state data is restored from DDR, the processor is restored to the running state, and the peripheral registers are used to restore or reset the peripherals to continue executing the above-mentioned services.

[0056] However, STR technology can only restore some hardware devices to their runtime state. Using STR technology requires accurate restoration of runtime state data. Restoring the above hardware devices to different runtime states may cause business execution errors. Therefore, it is necessary to save complex power-on and power-off operation procedures during runtime, which is difficult to execute. It also requires a long period of stability during the operation of computing devices and may pose network risks during runtime.

[0057] Meanwhile, for multi-service scenarios of asymmetric processors, a parallel loading technology has recently been proposed to accelerate the warm boot process by loading the key data required by the main core and multiple slave cores in parallel when the operating system of the computing device starts.

[0058] This is illustrative of the case where, when a computing device enters energy-saving mode, no protective measures are taken, and the processing is directly powered off.

[0059] When the computing device exits power-saving mode, it first boots the main core from an external source. After the main core boots, it loads the slave core images required for running multiple slave cores in parallel to start the aforementioned multiple slave cores.

[0060] Then, after the multiple slave cores start up, the master core controls the multiple slave cores to load the dynamic libraries required by each slave core to run the corresponding business in parallel. Although parallel loading technology can speed up the warm start time of computing devices, the warm start time mentioned above is still difficult to meet user needs.

[0061] To shorten the warm-start time of computing devices, this application proposes a processor warm-start method. This method sets a first warm-start vector for the master core and a second warm-start vector for the slave core in the power-down retention region of internal memory. During the cold start phase, the master core image, slave core image, master core dynamic library, and service dynamic library are pre-stored in the aforementioned power-down retention region. By setting the boot vectors of the master and slave cores in the power-down retention region, rapid startup of the master and slave cores can be achieved. By storing the master core image, slave core image, master core dynamic library, and service dynamic library required for running the first service in the power-down retention region of internal memory, the step of retrieving the master core image, slave core image, master core dynamic library, and service dynamic library from external memory can be omitted, thus shortening the processor's warm-start time, reducing the power consumption of the computing device, and improving the user experience.

[0062] Figure 1 is a schematic diagram of the startup principle and process of an asymmetric architecture processor, taking computing device 10 as an example. As shown in the figure, computing device 10 includes a processor 100, internal memory 200, and external memory 300.

[0063] The processor 100 is a processor with an asymmetric processor architecture, including multiple processor cores, such as a master core 110 and slave core 1 (the first slave core is labeled 120) and slave core 2 (the second slave core is labeled 130). The master core 110, slave core 120 and slave core 130 can communicate with each other through shared memory or message passing.

[0064] Different services, and even different operating systems or bare-metal programs, can run on the main core 110, slave core 120, and slave core 130.

[0065] The main core 110 is the control core of the processor 100, used to control the overall operation of the slave cores 120 and 130, as well as the entire operating system.

[0066] Slave cores 120 and 130 are used to run specific services, such as data acquisition, signal processing, or input / output operations. This application does not limit the specific services implemented by the slave cores.

[0067] The main core 110, slave core 120, and slave core 130 can be one or more of the following cores: application processor (AP), modem, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU). In actual implementation, the main core 110, slave core 120, and slave core 130 can adopt x86 architecture, ARM architecture, or a hybrid architecture of the two. In other words, this application does not limit the type and implementation method of the main core and slave core.

[0068] The internal memory 200 is used to provide the memory space required for the processor 100 to run. In actual implementation, independent memory spaces can be allocated in the internal memory 200 for the multiple processor cores. For example, memory space 210 corresponds to the main core 110, memory space 220 corresponds to the slave core 120, and memory space 230 corresponds to the slave core 130.

[0069] Internal memory 200 may include one or more internal memories with different transfer levels (referred to as RAM). For example, the aforementioned memory may be one or more of RAM, static random-access memory (SRAM), read-only memory (ROM), and DDR. This application does not limit this.

[0070] The aforementioned memory space is used to load the main core image, the slave core image, the main core dynamic library, and the business dynamic library required to run the first business. The business code in the main core dynamic library includes business requests from the slave cores. For example, if the business request indicates that business 1 is run by slave core 120 and business 2 is run by slave core 120, then memory space 210 may include the main core image and main core dynamic library of the main core; memory space 220 may include the slave core image of slave core 120 and the business 1 dynamic library required to run business 1; and memory space 230 may include the slave core image of slave core 130 and the business 2 dynamic library required to run business 2.

[0071] External storage 300 may include, but is not limited to, flash memory such as NOR Flash and NAND Flash, hard disk drives (HDDs), solid state drives (SSDs), USB flash drives, and embedded multi-media cards (EMMCs). It may also include external storage implemented through network-attached storage (NAS), storage area networks (SANs), cloud storage, etc. This application does not limit this.

[0072] In this application, the external memory 300 is used to store the main core image, the main core dynamic library, the slave core image, the service 1 dynamic library, and the service 2 dynamic library. In actual implementation, the slave core image can be divided into the slave core 1 image required for the operation of slave core 120, and the slave core 2 image required for the operation of slave core 130.

[0073] It is worth noting that the internal memory 200 has a faster access speed than the external memory 300.

[0074] When the processor 100 starts up, firstly, the main core image can be obtained from the external memory 300 through an external chip or the Basic Input Output System (BIOS), and the main core image is loaded into the main core memory space 210 to complete the startup of the main core 110, corresponding to step ① in Figure 1. The external chip may include the southbridge chip, network chip, and baseboard management controller of the computing device 10, which is not limited in this application.

[0075] Secondly, the main core 110 can obtain the main core dynamic library from the external memory 300 and load the main core dynamic library into the main core memory space 210, corresponding to step ② in 1.

[0076] Then, the main core 110 can obtain the slave core 1 image from the slave core image in the external storage 300 according to the service request in the main core dynamic library, load the slave core 1 image into the memory space 220 of the slave core 120, and send a service request to the slave core 120 to request the slave core 120 to run service 1, thus completing the startup of the slave core 120, corresponding to step ③ in Figure 1.

[0077] Then, based on the service request, core 120 obtains the service 1 dynamic library required by core 120 to run service 1 from external memory 300, loads the service 1 dynamic library into the running space 220 of core 120, and starts service 1, corresponding to step ④ in Figure 1.

[0078] It is understandable that if the above service request specifies that service 2 be run by slave core 130, master core 110 can also load the slave core 2 image in the same way, corresponding to step ⑤ in Figure 1. Slave core 130 can load the service 2 dynamic library required to run service 2 in the same way, and running service 2 corresponds to step ⑥ in Figure 1.

[0079] In actual implementation, this application can load the images and dynamic libraries of each core into the corresponding hierarchical memory region as needed, based on the frequency of memory resource access, availability, performance, and purpose of hot boot, using multiple processor cores of the processor.

[0080] In order to shorten the hot start time of the processor 100, this application divides the internal memory 200 into a power-down loss region and a power-down retention region.

[0081] During the cold boot phase of processor 100, the main core 110 can store the critical data required for a hot boot in the power-down retention area. When processor 100 performs a hot boot, multiple processor cores of the processor then restore the critical data required for the hot boot of these multiple processor cores in the power-down retention area in parallel. This critical data includes the main core image, the slave core image, the main core dynamic library, and the business dynamic library required to run the specified business, as well as the loading attributes corresponding to the main core and slave cores.

[0082] Figure 2 is a schematic diagram of a main core cold start scenario. As shown in the figure, the internal memory 200 of the computing device 10 includes three levels of hierarchical memory consisting of SRAM and DDR.

[0083] Level 1 memory consists of SRAM, Level 2 memory consists of DDR power-saving areas, and Level 3 memory consists of DDR holding areas (first memory space). Understandably, based on the characteristics of SRAM and DDR, Level 1 memory has the fastest access speed and can be used to load frequently accessed images and dynamic libraries. Level 2 and Level 3 memory have slower access speeds than Level 1 memory and can be used to load less frequently accessed images and dynamic libraries.

[0084] The primary and secondary memory are power-down loss areas. When the operating system enters power-saving mode, the images and dynamic libraries loaded in the power-down loss areas will be lost. The tertiary memory is the power-down retention area. When the operating system enters power-saving mode, the images and dynamic libraries stored in the power-down retention area will be retained.

[0085] It is worth noting that the hierarchical memory in the internal memory 200 is only for the purpose of understanding the technical solution of this application. In actual implementation, other hierarchical memory levels can also be used. In other words, this application does not limit the memory level used in the internal memory.

[0086] For example, the power-down loss region includes an execution space 210 (second memory space). The execution space 210 is the memory area where the main core image and main core dynamic library run after the main core 110 loads the main core image and main core dynamic library. The execution space 210 includes a memory space 211 in the first-level memory and a memory space 212 in the second-level memory.

[0087] In some possible implementations, the power-down loss region also includes an execution space 220 (third memory space), which is the memory region where the kernel image and business dynamic library run after the kernel 120 loads the kernel image and business dynamic library. The execution space 220 includes a memory space 221 in primary memory and a memory space 222 in secondary memory.

[0088] Understandably, the master core 110 can use the same method to request execution space 230 for the slave core 130. For example, memory space 231 in the first-level memory and memory space 232 in the second-level memory corresponding to the slave core 130.

[0089] Level 3 memory 240, also known as DDR holding area (first memory space) 240, is a memory space shared by the main core 110 and the slave core 120. The first memory space 240 includes the running area 241, the external area 242, and the backup area 243.

[0090] The running area 241 includes a hot start vector (first hot start vector) for the main core image. The first hot start vector is the pre-set starting address of the main core image 3 (first main core image). When the main core 110 is hot-started, the main core image 3 can be loaded from the above starting address.

[0091] In some possible implementations, the run area 241 also includes a hot-start vector (second hot-start vector) from the kernel image, wherein the first hot-start vector is a pre-set starting address of the kernel image 3 (first kernel image), and the kernel image 3 can be loaded from the starting address during a hot start of the kernel 120 and / or the kernel 130.

[0092] External area 242 is used to store the key data required for the operation of slave core 110, slave core 120 and slave core 130. As mentioned above, the key data includes the master core image, slave core image, master core dynamic library and the business dynamic library required for each slave core to run the specified business.

[0093] In actual implementation, external region 242 includes an image version region and a dynamic library version region. The image version region is a memory area within external region 242 used to store the main core image and slave core images. The dynamic library version region is a memory area within external region 242 used to store the main core dynamic library and business dynamic libraries.

[0094] The aforementioned key data may also include the dynamic library symbol tables of each dynamic library. For example, the main kernel dynamic library symbol table corresponding to the main kernel dynamic library includes the names of data types such as functions, variables, structures, and classes defined in the main kernel dynamic library, as well as their corresponding address information.

[0095] Backup area 243 is used to store the loading attributes of the main core 110, slave core 120, and slave core 130. The loading attributes include the page tables of the memory management unit (MMU) corresponding to the main core 110, slave core 120, and slave core 130, as well as the dynamic library address information and image address information of multiple dynamic libraries corresponding to the main core and slave core.

[0096] In some possible implementations, the backup area 243 includes an area for storing the master core image and a dynamic library pre-linking area shared by the master and slave cores for performing dynamic library relocation; the aforementioned loading attributes may also include the running status data of the master core 110, slave core 120 and slave core 130 when performing related services.

[0097] The following content will introduce the address information of the MMU page table and dynamic libraries.

[0098] The MMU page table is a key component of the operating system's memory management, responsible for translating virtual addresses into physical addresses and providing functions such as access control and cache management. In this application, the processor 100 can manage the execution space (second memory space) corresponding to the main core 110, the execution space (third memory space) 220 corresponding to the slave core 120, and the memory space of the slave core 130 through the MMU page tables of the main core 110, slave core 120, and slave core 130, respectively.

[0099] The dynamic library address information is used to indicate the loading areas of the main core dynamic library and the business dynamic library in the second memory space and the third memory space, respectively. For example, the loading area corresponding to the main core dynamic library 1 in memory space 211 and the loading area corresponding to the main core dynamic library 2 in memory space 212, as well as the loading area of ​​the business dynamic library 1 in memory space 221 and the loading area of ​​the business dynamic library 2 in memory space 222.

[0100] The address information of the images is used to represent the corresponding load regions in the master core image, slave core image, second memory space, and third memory space. For example, the load region corresponding to master core image 1 in memory space 211 and the load region corresponding to master core image 2 in memory space 212, and the load region of slave core image 1 in memory space 221 and the load region of slave core image 2 in memory space 222.

[0101] Indicatively, this application divides the main core image into main core image 1 (second main core image) with high access frequency and main core image 2 (third main core image) with low access frequency.

[0102] During a cold boot of the main core 110, the computing device 10 can load the main core image 1 into the memory space 211 via an external chip or BIOS to wake up the main core. The memory space 211 includes a cold boot vector (first cold boot vector) corresponding to the main core image 1. This first cold boot vector is a pre-set starting address of the main core image 1, from which the main core image 1 can be loaded during a cold boot of the main core 110.

[0103] After the main core 110 is woken up, it can load the main core image 1 through the first cold boot vector, run the operating system corresponding to the main core image 1 and perform DDR self-test. After the DDR completes the self-test, the computing device 10 can load the main core image 2 into the memory space 212 through an external chip or BIOS to complete the boot of the main core 110.

[0104] After the main core 110 completes its boot process, the main core 110 can store the main core image in the main core image version area of ​​external partition 242 through the operating system. The main core image in external partition 242 includes the first cold boot vector. The main core image includes all image files of the main core 110.

[0105] The main core 110 can also perform symbol relocation of the main core dynamic library in the dynamic library pre-linking area to obtain the relocated main core dynamic library and the corresponding main core dynamic library symbol table, and store the relocated main core dynamic library and the corresponding main core dynamic library symbol table in the main core dynamic library version area of ​​the external area 242.

[0106] As one possible implementation, the main core 110 can load the main core image 3 corresponding to the first hot boot vector into the runtime area 241 according to the first hot boot vector. The main core image 3 includes the image file required for the hot boot of the main core 110.

[0107] The main core 110 can load a portion of the main core dynamic libraries with high access frequency (main core dynamic library 1 shown in Figure 1) into memory space 211 and a portion of the main core dynamic libraries with low access frequency (main core dynamic library 2 shown in Figure 1) into memory space 212 according to business requests.

[0108] In some possible implementations, to improve the hot boot speed of the main core 110, after loading the main core dynamic library, the main core 110 can also back up its loading attributes (first loading attributes) to the backup area 243 through the operating system. The loading attributes of the main core 110 include the MMU page table of the main core 110, the address information of the main core image and the main core dynamic library, and runtime status data.

[0109] After the main core 110 starts up, this application can trigger the cold start process of the slave cores 120 and 130 through the main core 110. As mentioned above, the key data of the slave core 120 includes the slave core 1 image and the business dynamic library required for the slave core 1 to run business 1 (hereinafter referred to as the business 1 dynamic library); the key data of the slave core 130 includes the slave core 2 image and the business dynamic library required for the slave core 130 to run business 2 (hereinafter referred to as the business 2 dynamic library).

[0110] Figure 3 is a schematic diagram of the first slave core cold boot scenario. As shown in the figure, the master core 110 can store the slave core image to the slave core image version area of ​​the external area 242 through the operating system, and load the service 1 dynamic library to the service dynamic library version area of ​​the external area 242. The slave core image includes the cold boot vectors of slave cores 120 and 130. The slave core image includes all image files of slave cores 120 and 130.

[0111] Indicatively, the kernel 1 image includes kernel 1 image 1 (second kernel image), which is accessed frequently during kernel 1 runtime, and kernel 1 image 2 (third kernel image), which is accessed less frequently.

[0112] The master core 110 can load slave core 1 image 1 (the second slave core image) into memory space 221, load slave core 1 image 2 into memory space 222, wake up slave core 120, and send service requests to slave core 120. Memory space 221 includes the cold start vector (the second cold start vector) of slave core 120. This second cold start vector is a pre-set starting address of slave core 1 image 1, from which master core image 1 can be loaded during a cold start of slave core 120.

[0113] After being woken up from core 120, the corresponding operating system or business function can be run through the second cold start vector, and the symbol relocation of the business 1 dynamic library can be performed to obtain the relocated business 1 dynamic library and the business 1 dynamic library symbol table. The relocated business 1 dynamic library and the business 1 dynamic library symbol table are then stored in the business dynamic library version area of ​​external area 242.

[0114] Core 120 can also load a portion of the frequently accessed Business 1 dynamic libraries (Business 1 dynamic library 1 shown in Figure 1) into memory space 211 and a portion of the frequently accessed Business 1 dynamic libraries (Business 1 dynamic library 2 shown in Figure 1) into memory space 212 according to business requests.

[0115] As one possible implementation, the main core 110 can load the slave core image 3 corresponding to the second hot boot vector into the run area 241 according to the second hot boot vector, wherein the slave core image 3 includes the image files required for hot boot of slave core 120 and slave core 130.

[0116] In some possible implementations, to improve the hot boot speed of slave core 120, master core 110 can, after slave core 120 has loaded the dynamic library of service 1, store the loading attributes (second loading attributes) of slave core 120 to backup area 243 through the operating system. The loading attributes of slave core 120 include the MMU page table of slave core 120, the address information of slave core 1 image and service 1 dynamic library, and runtime status data.

[0117] It is understandable that, as shown in Figure 4, which illustrates the cold start of the second slave core, the master core 110 can use the same method to store the dynamic library of service 2 to the service dynamic library version area of ​​the external area 242.

[0118] The main core 110 can load the slave core 2 image 1 required for the operation of slave core 2 into memory space 231, and load the memory space 232 of slave core 2 image 2, in order to wake up slave core 130, depending on the access frequency.

[0119] After core 130 is woken up, the dynamic library 1 of service 2 required for running service 2 can be loaded into memory space 231, and the dynamic library 2 of service 2 can be loaded into memory space 232.

[0120] As mentioned earlier, the master core 110 can load the slave core image 3 into the runtime area 241 and store the load attributes (third load attributes) of the slave core 130 into the backup area 243. Among them, the load attributes of the slave core 130 include the MMU page table of the slave core 130, the address information of the slave core 2 image and the service 2 dynamic library, and the runtime status data.

[0121] It is worth noting that the cold start process of slave core 120 and slave core 130 described above is only for the purpose of understanding this application. In actual implementation, slave core 120 and slave core 130 can be woken up by master core 110 at the same time to perform cold start. In other words, this application does not limit the startup timing or startup method (e.g., serial startup or parallel startup) for cold start of multiple slave cores.

[0122] As mentioned above, in order to save energy, the operating system of computing device 10 needs to shut down unnecessary hardware resources in the main core 110, slave core 120 and slave core 130 when there is no business or low load, so as to save energy. When there is a business request, the main core 110, slave core 120 and slave core 130 are woken up by warm boot.

[0123] Figure 5 is a schematic diagram of the scenario after the processor performs a hibernation operation. As shown in the figure, all critical data of the master core 110, slave core 120, and slave core 130 are lost in the power-down loss area. The power-down retention area still retains the critical data required for the warm-up of the master core 110, slave core 120, and slave core 130.

[0124] Schematic, the running area 241 includes the master kernel image 3 and slave kernel image 3 saved during the cold boot phase.

[0125] The main core image 3 includes the self-recovery code (first self-recovery code) of the main core 110. When the first self-recovery code is executed by the main core 110, it enables the main core 110 to obtain the first load attributes from the backup area. Based on the first load attributes, the main core 110 can obtain the main core image from the image version area of ​​the external area 242, obtain the main core dynamic library from the dynamic library version area of ​​the external area 242, and load the main core image and the main core dynamic library into the second memory space.

[0126] The slave kernel image 3 includes the self-recovery code (second self-recovery code) of the slave kernel 120. When the second self-recovery code is executed by the slave kernel 120, it enables the slave kernel 120 to obtain the second load attribute from the backup area. Based on the second load attribute, the slave kernel 120 can obtain the slave kernel image from the image version area of ​​the external area 242, obtain the business dynamic library from the dynamic library version area of ​​the external area 242, and load the slave kernel image and the business dynamic library into the third memory space.

[0127] In some possible implementations, kernel image 3 also includes self-recovery code from kernel 130. The function of the self-recovery code from kernel 130 will not be elaborated here.

[0128] External region 242 includes the master kernel image and slave kernel image saved during the cold start phase, the master kernel relocation dynamic library and the master kernel dynamic library symbol table, the service 1 relocation dynamic library and the service 1 dynamic library symbol table, the service 2 relocation dynamic library and the service 2 dynamic library symbol table.

[0129] The aforementioned main core image includes all the image files required for the main core 110 to run, such as main core image 1 required for cold boot, main core image 2 required for runtime, and main core image 3 required for warm boot.

[0130] It is worth noting that the aforementioned slave kernel images include all the image files required for slave kernel 120 and slave kernel 130 to run. For example, slave kernel 1 image 1 and slave kernel 2 image 2 for slave kernel 120, slave kernel 2 image 1 and slave kernel 2 image 2 for slave kernel 130, and slave kernel image 3 required for warm boot of slave kernel 120 and slave kernel 130.

[0131] Backup area 243 includes the load attributes of the master core 110, slave core 120, and slave core 130. For example, the first load attribute corresponding to the master core 110 and the second load attribute corresponding to the slave core 120.

[0132] When the aforementioned hardware resources need to be woken up, the master core 110, slave core 120, and slave core 130 can each execute their respective hot start procedures based on the key data in the power-down retention area shown in Figure 5.

[0133] Figure 6 is a schematic diagram of a processor hot boot scenario. As mentioned earlier, the running area 241 includes the master core image 3 (first master core image) corresponding to the first hot boot vector and the slave core image 3 (first slave core image) corresponding to the second hot boot vector. As mentioned earlier, the master core image 3 includes the self-recovery code (first self-recovery code) of the master core 110, and the slave core image 3 includes the self-recovery code of the slave core 120 and the slave core 130.

[0134] First, the main core 110 loads the main core image 3 through the first hot boot vector and executes the self-recovery code in the main core image 3 to complete its own hot boot, corresponding to step 1 in Figure 6.

[0135] Secondly, the master core 110 activates the slave core 120, which executes the self-recovery code corresponding to the slave core 120 to complete its own hot boot, corresponding to step 2 in Figure 6.

[0136] Then, the main core 110 obtains the first loading attribute from the backup area 243, obtains the main core image 1 and the main core image 2 from the external area 242, and loads the main core image 1 into the memory space 211 and the main core image 2 into the memory space 212 according to the first loading attribute, corresponding to step 3 in Figure 6.

[0137] Then, the main core 110 retrieves the main core dynamic library 1 and main core dynamic library 2 from the external area 242 according to the first loading attribute, and loads the main core dynamic library 1 into the memory space 211 and the main core dynamic library 2 into the memory space 212, corresponding to step 4 in Figure 6.

[0138] In some possible implementations, after the core 120 completes its own hot boot, it can obtain the second loading attribute from the backup area 243, and obtain the core 1 image 1 and the core 2 image 2 from the external area 242 according to the second loading attribute. The core 1 image 1 is loaded into the memory space 221, and the core 2 image 2 is loaded into the memory space 222, corresponding to step 5 in Figure 6.

[0139] Then, according to the second loading attribute, the kernel 120 retrieves the Service 1 relocation dynamic library 1 and Service 1 dynamic library 2 from the external area 242, loads the Service 1 dynamic library into memory space 221, and loads the Service 1 dynamic library 2 into memory space 222, corresponding to step 6 in Figure 6.

[0140] It is worth noting that in this application, steps 3 and 4 in the hot start of the master core 110 and steps 5 and 6 in the hot start of the slave core 120 can be executed concurrently.

[0141] It is understandable that the main core 110 can also use the same method to trigger the hot boot process of the slave core 130 to load the image and dynamic library required by the slave core 130 to execute business 1 into the corresponding memory space to run business 2. This will not be elaborated here.

[0142] Next, based on the above description, a startup method for an asymmetric processor provided in this application embodiment will be introduced. It is understood that this method is based on the above description, and some or all of its content can be found in the above description.

[0143] Figure 7 is a flowchart of the processor hot start method. As shown in Figure 7, the main core 110 of the processor 100 can achieve hot start of the asymmetric processor through S710 to S740.

[0144] S710: The main core is started by loading the main core image through the first hot boot vector.

[0145] As previously described, the computing device 10 includes an asymmetric processor 100 and internal memory 200. The asymmetric processor 100 includes a master core 110, a slave core 120 (first slave core), and a slave core 130, as shown in FIG1. ​​The master core 110, slave core 120, and slave core 130 are communicatively connected to the internal memory 200. Among them, slave core 120 can execute service 1 (first service), and slave core 130 can execute service 2 (second service).

[0146] When computing device 10 is warm-started, the main core 110 can be loaded with the main core image through the first warm-start vector of the first memory space 240 and the main core 110 can be started.

[0147] The internal memory 200 includes a first memory space 240 with power-down retention capability. This first memory space 240 is a shared memory space for the master core 110 and the slave core 120, and includes a running area 241, an external area 242, and a backup area 243.

[0148] During the cold start phase of computing device 10, the main core 110 can load the main core image of the main core 110 into the running area 241 according to the first hot start vector, and load the slave core image of the slave core 120 into the running area 241 according to the second hot start vector.

[0149] As one possible implementation, the main core 110 may also store the main core image, the slave core image, the main core dynamic library, and the service 1 dynamic library required to run the first service in the external area 242.

[0150] For illustration purposes, based on the frequency of access, the main core image can be divided into main core image 1 and main core image 2, and the main core dynamic library can be divided into main core dynamic library 1 and main core dynamic library 2; the slave core image of slave core 1 can be divided into slave core 1 image 1 and slave core 1 image 2, and the business 1 dynamic library can be divided into business 1 dynamic library 1 and business 1 dynamic library 2.

[0151] In some possible implementations, the master core 110 may also store the first load attributes of the master core 110 and the second load attributes of the slave core 120 in the backup area 243.

[0152] As mentioned above, the internal memory 200 also includes an execution space 210 (second memory space) corresponding to the main core 110 and an execution space 220 (third memory space) corresponding to the slave core 120.

[0153] When the computing device 10 exits hibernation mode and enters the hot start phase, the first memory space includes the main core 110, slave core 120 and slave core 130 pre-stored during the cold start phase to run service 1 and the key data required for the service, the main core image and main core dynamic library in the second memory space, and the slave core image and service dynamic library in the third memory space, which are lost when the processor 100 is powered off.

[0154] Schematic, the running area 241 of the first memory space 240 includes a first hot start vector and a second hot start vector. The first hot start vector corresponds to the master core image 3 shown in Figure 5, and the second hot start vector corresponds to the slave core image 3 shown in Figure 5.

[0155] The external storage area 242 of the first memory space 240 includes the aforementioned main core image, slave core image, main core dynamic library, and the business 1 dynamic library required to run the first business.

[0156] The backup area 243 of the first memory space 240 includes the first load attributes of the main core 110 and the second load attributes of the slave core 120.

[0157] When the computing device 10 is warm-started, the main core 110 can load the main core image 3 according to the first warm-start vector of the running area 241 to start the main core 110.

[0158] It is understandable that the main core 110 can also use the same method during the cold start phase to store the slave image of the slave core 130, the dynamic library of the business required to run the second business, and the third loading attribute of the slave core 130 into the memory area corresponding to the first memory space, which will not be elaborated here.

[0159] S720: Activate the first slave core. The first slave core loads the slave core image and starts the first slave core through the second hot boot vector.

[0160] Taking slave core 120 as an example, after master core 110 loads the master core image, it can run the operating system corresponding to master core image 1 and activate slave core 120 in the operating system.

[0161] As mentioned earlier, the runtime area 241 of the first memory space 120 also includes a second hot boot vector, which corresponds to a slave kernel image. The slave kernel image includes a slave kernel 1 image of slave kernel 120.

[0162] Once kernel 120 is activated, it can load the aforementioned kernel 1 image according to the second hot boot vector of run zone 241 to complete its own boot process.

[0163] Understandably, the master core 110 can also activate the slave core 130 in the same way, so that the slave core 130 can load the slave core 2 image according to the second hot boot vector and complete its own boot.

[0164] S730: Loads the master core image and master core dynamic library from the first memory space to the second memory space, and uses the first slave core to load the slave core image and business dynamic library from the first memory space to the third memory space.

[0165] After the main core 110 and the slave core 120 have finished booting, the main core 110 can load the main core image and main core dynamic library from the first memory space 240 into the second memory space 210.

[0166] Meanwhile, the slave kernel image and business dynamic library in the first memory space 240 can also be loaded into the third memory space 220 from the slave kernel 120.

[0167] As previously described, the master kernel image includes pre-configured self-recovery code (first recovery code) for the master kernel 110, and the slave kernel image includes self-recovery code (second recovery code) for the slave kernel 120. The backup area 243 includes the first load attributes of the master kernel 110 and the second load attributes of the slave kernel 120.

[0168] The main core 110 executes the first recovery code in the main core image and can obtain the first loading attributes from the backup area 243.

[0169] The main core 110 can obtain the main core image pre-stored during the cold start phase from the external area 242 of the first memory space 240, and load the main core image into the second memory space 210 according to the first loading attribute.

[0170] As mentioned above, the second memory space 210 includes memory space 211 in the first-level memory and 212 in the second-level memory; the main core image can be divided into main core image 1 and main core image 2 according to the different access frequencies.

[0171] To illustrate, firstly, the main core 110 obtains the corresponding memory addresses of memory spaces 211 and 212 based on the MMU page table in the first load attribute.

[0172] Then, the main core 110 can obtain the main core image 1 and the main core image 2 from the external area 242, and load the main core image 1 into the memory space 211 and the main core image 2 into the memory space 212 according to the address information of the image in the first loading attribute.

[0173] The main core 110 can also obtain the main core dynamic library pre-stored during the cold start phase from the external area 242 of the first memory space 240, and load the main core dynamic library into the second memory space 220 according to the first loading attribute.

[0174] As mentioned earlier, based on the frequency of access, the main kernel dynamic library can be divided into main kernel dynamic library 1 and main kernel dynamic library 2.

[0175] Indicatively, the main core 110 can obtain the main core dynamic library 1 and the main core dynamic library 2 from the external area 242, and load the main core dynamic library 1 into memory space 211 and the main core dynamic library 2 into memory space 212 according to the address information of the dynamic library in the first loading attribute.

[0176] It is worth noting that while the main core loads the main core image and main core dynamic library of the first memory space 240 into the second memory space 210, the slave core 120 can also load the slave core image and business dynamic library of the first memory space 210 into the third memory space 220 in parallel.

[0177] As an illustration, executing the second recovery code from the kernel image from kernel 120 can retrieve the second load attributes from backup area 243.

[0178] Slave kernel 120 can obtain the slave kernel image pre-stored during the cold boot phase from the external area 242 of the first memory space 240, and load the slave kernel image into the third memory space 220 according to the second loading attribute.

[0179] As mentioned earlier, the third memory space 220 includes memory space 221 in the primary memory and 222 in the secondary memory. Based on the frequency of access, the slave kernel 1 image in the slave kernel image can be divided into slave kernel 1 image 1 and slave kernel 1 image 2.

[0180] To illustrate, firstly, core 120 can obtain the corresponding memory addresses of memory spaces 221 and 222 from the MMU page table in the second load attribute.

[0181] Then, from core 120, it can obtain core 1 image 1 and core 1 image 2 from the external region, and load core 1 image 1 into memory space 221 and core 1 image 2 into memory space 222 according to the address information of the image in the first load attribute.

[0182] The main core 110 can also obtain the business dynamic library pre-stored during the cold start phase from the external area 242 of the first memory space 240, and load the above business dynamic library into the third memory space 220 according to the first loading attribute.

[0183] As mentioned earlier, based on the frequency of access, the Business 1 dynamic library can be divided into Business 1 dynamic library 1 and Business 1 dynamic library 2.

[0184] Indicatively, core 120 can obtain service 1 dynamic library 1 and service 1 dynamic library 2 from external region 242, and load service 1 dynamic library 1 into memory space 221 and service 1 dynamic library 2 into memory space 222 according to the address information of the dynamic library in the first loading attribute.

[0185] As mentioned earlier, the dynamic libraries in external region 242 are relocated dynamic libraries obtained after performing relocation operations during the cold start process. Each relocated dynamic library also includes a corresponding dynamic library symbol table.

[0186] Taking the main core dynamic library as an example, the external area 242 includes the main core relocation dynamic library and the main core dynamic library symbol table.

[0187] In actual implementation, the main core 110 can load main core dynamic library 1 and main core dynamic library 2 according to the main core dynamic library symbol table during the warm boot process, so as to ensure that the operating system can correctly link the functions, variables, structures and classes in the main core dynamic library 1 and main core dynamic library 2.

[0188] By pre-storing the relocation dynamic library and the corresponding dynamic library symbol table in the external area 242, the correct loading of the dynamic library can be ensured, the hot boot steps of each core of the processor can be simplified, and the hot boot time of the computing device can be shortened.

[0189] It is understandable that while the main core 110 and the slave core 120 are loading the corresponding images and dynamic libraries, the slave core 130 can also use the same method to load its own image and dynamic libraries into memory space 230, which will not be elaborated here.

[0190] S740: Activate the service dynamic library of the first slave core using the master core so that the first slave core can execute the first service to complete the processor's hot boot.

[0191] After both the master core 110 and the slave core 120 have completed loading the image and dynamic library, the master core 110 can activate the business dynamic library of the slave core 120 so that the slave core 120 can execute the first business.

[0192] Understandably, the master core 110 can also activate the slave core 130 in the same way so that the slave core 130 can perform a second service.

[0193] As described in step S710, during the cold start process of the computing device, the main core 110 can pre-store the key data required for the main core 110 and the slave core 120 to run service 1 in the first memory space 210. Next, the cold start method for asymmetric processors will be introduced below. It should be understood that this method is based on the content described above, and some or all of the content of this method can be found in the description above.

[0194] Figure 8 is a flowchart of the processor cold start method. As shown in Figure 8, the cold start of an asymmetric processor can be achieved through S711 to S717.

[0195] S711: Based on the first cold start vector, load the main core image 1 in the external memory into the memory space 211 and wake up the main core.

[0196] As mentioned above, the internal memory 200 includes three levels of hierarchical memory consisting of SRAM and DDR. The computing device 10 can load the frequently accessed main core image 1 into the memory space 211 and wake up the main core 110 through an external chip or BIOS according to the first cold start vector.

[0197] S712: Loads main core image 1, performs DDR self-test, and returns a successful DDR self-test result to the external network after the DDR self-test is completed.

[0198] After the main core 110 is woken up, it can load main core image 1 according to the first cold boot vector to run the operating system corresponding to main core image 1 and perform DDR self-test. After the DDR self-test is completed, the main core 110 can return the result of successful DDR self-test to the external chip or BIOS.

[0199] S713: Load the main core image 2 from external storage into memory space 212.

[0200] After receiving a successful DDR self-test result from the main core 110, the computing device 10 can use an external chip or BIOS to load the main core image 2, which has a low access frequency, into the memory space 212.

[0201] S714: Load the main core dynamic library 1 and main core dynamic library 2 from the external memory into the corresponding memory space, and allocate a third memory space 220 for the slave core 120.

[0202] After loading of main core image 1 and main core image 2 is complete, the main core 110 can first store the main core image in the external area 242. The main core image includes the first cold start vector.

[0203] Secondly, the main core 110 can perform symbol relocation of the main core dynamic library in the dynamic library pre-linking area to obtain the relocated main core dynamic library and the main core dynamic library symbol table corresponding to the main core dynamic library, and store the relocated main core dynamic library and the main core dynamic library symbol table in the external area 242.

[0204] Then, the main core 120 can load the main core dynamic library 1, which is accessed more frequently, into memory space 211, and load the main core dynamic library 2 into memory space 212, according to the different access frequencies.

[0205] Then, the processor runs the main core dynamic library 1 and the main core dynamic library 2, and allocates the corresponding third memory space 220 to the slave core 120 according to the business requests in the above dynamic libraries. The third memory space 220 includes the memory space 221 in the primary memory and the memory space 222 in the secondary memory.

[0206] Finally, the main core 110 can store its own MMU page table, main core image and main core dynamic library address information, as well as runtime status data (first load attribute) to the backup area 243.

[0207] S715: Based on the second cold start vector, load core 1 image 1 into memory space 221 and load core 1 image 2 into memory space 222.

[0208] The main core 110 can load the slave core image and the dynamic library of service 1 into the external region 242. The slave core image includes the second cold start vector.

[0209] The master core 110 can load the slave core 1 image 1 into memory space 221 and the slave core 1 image 2 into memory space 222 according to the second cold start vector, so as to wake up the slave core 120 and send a service request to the slave core 120 to run service 1. The memory space 211 includes the second cold start vector.

[0210] S716: Load image 1 from core 1 and image 2 from core 2, load dynamic library 1 of service 1 into memory space 221, load dynamic library 2 of service 1 into memory space 222, and return a result indicating successful loading.

[0211] First, after the kernel 120 is woken up, it can load the kernel 1 image 1 and kernel 2 image 2 according to the second cold start vector to run the corresponding operating system or business function, and perform symbol relocation on the business 1 dynamic library to obtain the relocated business 1 dynamic library and the business 1 dynamic library symbol table, and store the relocated business 1 dynamic library and the business 1 dynamic library symbol table in the external area 242.

[0212] Then, based on the above business requests, core 120 loads the frequently accessed business 1 dynamic library 1 into memory space 221, loads the infrequently accessed business 1 dynamic library 2 into memory space 222, and returns the result of successful dynamic library loading to main core 110.

[0213] S717: Activate Service 1 dynamic library 1 and Service 1 dynamic library 2 to complete the processor's cold start.

[0214] After receiving the result of successful loading of the aforementioned dynamic library from the slave core 120, the main core 110 can activate the service 1 dynamic library 1 and service 1 dynamic library 2 loaded by the slave core 120 so that the slave core can run service 1 and complete the cold start of the processor 100.

[0215] The main core 110 can also store the MMU page table of the slave core 120, the address information of the slave core image and the service 1 dynamic library, as well as the running status data (second loading attribute) to the backup area 243.

[0216] It is understandable that the main core 110 can also use the same method to achieve a cold boot of the slave core 130, which will not be elaborated here.

[0217] This application proposes a processor hot-start method. This method sets a first hot-start vector for the master core and a second hot-start vector for the slave core in the power-down retention region of internal memory. During the cold start phase, the master core image, slave core image, master core dynamic library, and service dynamic library are pre-stored in the aforementioned power-down retention region. By setting the boot vectors for the master and slave cores in the power-down retention region, rapid startup of the master and slave cores can be achieved. By storing the master core image, slave core image, master core dynamic library, and service dynamic library required for running the first service in the power-down retention region of internal memory, the steps of retrieving the master core image, slave core image, master core dynamic library, and service dynamic library from external memory can be omitted, shortening the hot-start time of the computing device, reducing the power consumption of the computing device, and improving the user experience.

[0218] Secondly, this application proposes a hot-start method. It is applicable to single-core processors or multi-core processors employing a symmetric architecture, wherein the processor includes at least one main core.

[0219] Figure 9 illustrates a scenario during a hot boot of a symmetric architecture processor. As shown, compared to the processor 100 shown in Figure 2, processor 100' includes main core 1 (corresponding to label 110) and main core 2 (corresponding to label 150). The power-down loss region of internal memory 200 includes the execution space 250 of main core 150. The execution space 250 of main core 150 is the memory region where the main core image and main core dynamic library run after the main core 150 is loaded. The aforementioned execution space 250 includes memory space 251 in primary memory and memory space 252 in secondary memory.

[0220] During the cold boot phase, processor 100' can utilize either main core 110 or main core 150 to back up critical data required for a hot boot to the first memory space 210. This critical data includes the main core 1 image, main core 1 dynamic library, and main core 1 loading attributes corresponding to main core 110. Similarly, the critical data also includes the main core 2 image 3, main core 2 image, main core 2 dynamic library, and main core 2 loading attributes corresponding to main core 150.

[0221] As mentioned earlier, the main core 1 image includes all the image files required for the main core 110 to run, such as main core 1 image 1 required for a cold boot, main core 1 image 2 required for runtime, and main core 1 image 3 required for a warm boot. It can be understood that the main core 2 image includes main core 2 image 1 required for a cold boot, main core 2 image 2 required for runtime, and main core 2 image 3 required for a warm boot.

[0222] For example, taking the main core 110 as an example, during the cold start phase, firstly, the main core 110 can load the main core 1 image 3 into the running area 241 according to the first hot start vector, and load the main core 2 image 3 into the running area 241 according to the hot start vector of the main core 150.

[0223] Then, the main core 110 can store the main core 1 image and main core 1 dynamic library corresponding to the main core 110, and the main core 2 image and main core 2 dynamic library corresponding to the main core 150 to the external area 242. This is an illustration of the main core 1 relocated dynamic library and the main core 1 dynamic library symbol table after relocation.

[0224] Finally, the main core 110 can store the first load attribute corresponding to the main core 110 and the load attribute corresponding to the main core 150 in the backup area 243. Indicatively, the first load attribute includes the address information of the main core 1 image and the address information of the main core 1 dynamic library.

[0225] As mentioned earlier, the main core 1 image 3 includes the self-recovery code (first self-recovery code) of main core 110. It can be understood that the main core 2 image 3 includes the self-recovery code of main core 150.

[0226] During the warm boot phase after the processor is powered off, firstly, the main core 110 loads the main core 1 image 3 through the first warm boot vector and executes the self-recovery code in the main core 1 image 3 to complete its own warm boot, corresponding to step 1 in Figure 9.

[0227] Then, the main core 110 obtains the main core 1 loading attributes (first loading attributes) from the backup area 243, obtains the main core 1 image 1 and main core 1 image 2 from the external area 242, and loads the main core 1 image 1 into the memory space 211 and the main core 1 image 2 into the memory space 212 according to the first loading attributes, corresponding to step 2 in Figure 9.

[0228] Finally, the main core 110 retrieves the main core 1 dynamic library 1 and main core 1 dynamic library 2 from the external area 242 according to the first loading attribute, and loads the main core 1 dynamic library 1 into memory space 211 and the main core 1 dynamic library 2 into memory space 212, corresponding to step 3 in Figure 6.

[0229] Using the same method, the main core 150 can also load the main core 2 image 3 through the corresponding hot boot vector to complete its own hot boot and execute the self-recovery code in the main core 2 image 3. This corresponds to step 4 in Figure 9.

[0230] Main core 150 can obtain the corresponding main core 2 loading attributes, and load main core 2 image 1 into memory space 251 and main core 2 image 2 into memory space 252 according to the main core 2 loading attributes, corresponding to step 5 in Figure 9.

[0231] Main core 150 can load main core 2 dynamic library 1 into memory space 251 and main core 2 dynamic library 2 into memory space 252 according to the main core 2 loading attributes, corresponding to step 6 in Figure 9.

[0232] It is worth noting that in this application, steps 1 to 3 in the hot boot of the main core 110 and steps 4 to 6 in the hot boot of the main core 150 can be executed concurrently.

[0233] For example, Figure 10 is a flowchart illustrating another processor hot-start method. As shown in the figure, this method can utilize the main core of a single-core processor or any main core of a symmetric processor to achieve processor hot-start through steps S10 to S30. It is understood that this method is proposed based on the scenario diagram described in Figure 9, and some or all of the content of this method can be found in the description above.

[0234] S10: During the cold start phase, back up the critical data required for a warm start to the first memory space.

[0235] During the cold start phase, the main core 110 can back up the critical data required for a warm start to the first memory space 240.

[0236] As mentioned earlier, the key data required for a hot boot of the processor 100 includes the main core 1 image corresponding to the main core 110, the main core 1 dynamic library, and the loading attributes of the main core 1. The main core 1 image includes all the image files required for the main core 110 to run, such as main core 1 image 1 required for a cold boot, main core 1 image 2 required for runtime, and main core 1 image 3 (the first main core image) required for a hot boot.

[0237] As previously mentioned, the internal memory includes a power-down retention area (first memory space) 240, wherein the first memory space 240 includes a running area 241, an external area 242, and a backup area 243.

[0238] In some possible implementations, the main core 110 may load the first main core image into the run area 241 according to the first hot start vector.

[0239] As one possible implementation, the main core 110 can store the main core image and the main core dynamic library in the external area 242.

[0240] In some possible implementations, the main core 110 may store the first loading attributes corresponding to the main core in the backup area 242; wherein, the first loading attributes include the address information of the main core 1 image and the address information of the main core 1 dynamic library.

[0241] S20: Load the first main core image through the first hot boot vector to complete the main core hot boot.

[0242] During the warm boot phase after the processor 100 is powered down, the main core 110 can load the main core 1 image 3 through the first warm boot vector in the first memory space 240 and start the main core. The first main core image includes pre-configured first recovery code.

[0243] S30: Load the main kernel image and main kernel dynamic library from the first memory space into the second memory space.

[0244] As mentioned above, the internal memory also includes a power-down loss region, which includes the execution space 210 (second memory space) corresponding to the main core 110.

[0245] The main core 110 can load the main core image and main core dynamic library from the first memory space 240 into the second memory space 210.

[0246] In some possible implementations, firstly, the main core 110 executes the first recovery code in the main core 1 image 3 and obtains the first loading attributes from the backup area 242;

[0247] Then, the main core 110 can obtain the main core 1 image from the external area and load the main core image into the second memory space 210 according to the address information of the main core 1 image in the first loading attribute.

[0248] Finally, the main core 110 can obtain the main core 1 dynamic library from the external area 242, and load the main core 1 dynamic library into the second memory space according to the address information of the main core dynamic library in the first loading attribute.

[0249] Once the main core 110 has finished loading the main core 1 image and main core 1 dynamic library, it can run the operating system or basic business functions corresponding to the main core 1 image, thus completing a hot boot of the main core 110.

[0250] It is understandable that if processor 100' is a symmetric multi-core processor, other processors besides the main core 110 can also achieve their own hot boot in the same way as the main core 110, which will not be elaborated here.

[0251] In addition to the methods, apparatus, and electronic devices described above, embodiments of this application may also provide a computer program product, comprising computer program instructions. When executed by a processor, the computer program instructions cause the processor to perform the steps of the processor startup methods of the various embodiments of this application described in the "Methods" section of this specification. The computer program product can be written in any combination of one or more programming languages ​​to execute computer program code for performing the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The computer program code can be in source code form, object code form, executable file, or some intermediate form. The computer program code can be executed entirely on a user's computing device, partially on a user's device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0252] Furthermore, embodiments of this application may also provide a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps of the processor startup method according to various embodiments of this disclosure as described in the "Method" section above. The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. It should be noted that the content contained in the computer-readable medium may be appropriately added to or subtracted according to the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, a computer-readable medium may not include electrical carrier signals and telecommunication signals.

[0253] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0254] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0255] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of the various embodiments of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the specific details described above.

[0256] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0257] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0258] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

[0259] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The specific embodiments described above have further detailed the purpose, technical solutions, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

[0260] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for hot-starting a processor, characterized in that, The processor includes a main core and multiple slave cores, and the method is applied to the main core, including: The main core image is loaded by the first hot start vector in the first memory space, and the main core is started. The first memory space is the power-down retention area set by the internal memory. The first memory space includes the main core image, the slave core image, the main core dynamic library and the business dynamic library required to run the first service, which are pre-stored in the cold start phase. Activate the first slave core so that the first slave core loads the slave core image through the second hot boot vector in the first memory space and starts the first slave core, wherein the first slave core is one of the plurality of slave cores; The master core image and the master core dynamic library in the first memory space are loaded into the second memory space. The slave core image and the business dynamic library in the first memory space are loaded into the third memory space using the first slave core. The second memory space is the execution space corresponding to the master core in the internal memory, and the third memory space is the execution space corresponding to the first slave core in the internal memory.

2. The method according to claim 1, characterized in that, The main core image includes the first main core image corresponding to the first hot boot vector, the first memory space includes a runtime area, and the method includes the following steps before loading the main core image through the first hot boot vector in the first memory space: During the cold start phase, the first master core image is loaded into the running area according to the first hot start vector.

3. The method according to claim 2, characterized in that, The first memory space includes an external region, and the method includes: During the cold start phase, the main kernel image and the main kernel dynamic library are stored in the external area.

4. The method according to claim 3, characterized in that, The first memory space includes a backup area, and the method further includes: During the cold start phase, the first loading attribute corresponding to the main core is stored in the backup area; the first loading attribute includes the address information of the main core image and the address information of the main core dynamic library.

5. The method according to claim 4, characterized in that, The first master kernel image includes pre-configured first recovery code. Loading the master kernel image and master kernel dynamic library from the first memory space into the second memory space includes: Execute the first recovery code to obtain the first loaded attribute from the backup area; The main core image is obtained from the external region, and the main core image is loaded into the second memory space according to the address information of the main core image; The main core dynamic library is obtained from the external area, and the main core dynamic library is loaded into the second memory space according to the address information of the main core dynamic library.

6. The method according to claim 2, characterized in that, The slave core image includes the first slave core image corresponding to the second hot boot vector. Before loading the master core image through the first hot boot vector in the first memory space, the method includes: During the cold start phase, the first slave kernel image is loaded into the runtime region according to the second warm start vector.

7. The method according to any one of claims 3-6, characterized in that, The method further includes: During the cold start phase, the kernel image and the business dynamic library are stored in the external area.

8. The method according to any one of claims 7, characterized in that, The method further includes: During the cold start phase, the second loading attribute corresponding to the first slave core is stored in the backup area. The second loading attribute includes the address information of the slave core image and the address information of the business dynamic library.

9. The method according to claim 8, characterized in that, The first slave kernel image includes pre-configured second recovery code. The step of loading the slave kernel image and the business dynamic library from the first memory space into the third memory space using the first slave kernel includes: The second recovery code is executed using the first slave core, and the second loading attribute is obtained from the backup area; The slave core image is obtained from the external region using the first slave core, and the slave core image is loaded into the third memory space according to the address information of the slave core image; The first slave core retrieves the service dynamic library from the external region, and loads the service dynamic library into the third memory space according to the address information of the service dynamic library.

10. The method according to claim 1, characterized in that, After loading the kernel image and the business dynamic library into the third memory space, the method includes: Activate the business dynamic library so that the first slave core can run the first business.

11. A method for hot-starting a processor, characterized in that, The processor includes a main core, and the method is applied to the main core, including: The main core is started by loading the main core image through the first hot boot vector in the first memory space. The first memory space is the power-down retention area set by the internal memory. The first memory space includes the main core image and main core dynamic library pre-stored during the cold boot phase. The main kernel image and the main kernel dynamic library in the first memory space are loaded into the second memory space; the second memory space is the execution space corresponding to the main kernel in the internal memory.

12. The method according to claim 11, characterized in that, The main core image includes the first main core image corresponding to the first hot boot vector, the first memory space includes a runtime area, and the method includes the following steps before loading the main core image through the first hot boot vector in the first memory space: During the cold start phase, the first master core image is loaded into the running area according to the first hot start vector.

13. The method according to claim 12, characterized in that, The first memory space includes an external region, and the method includes: During the cold start phase, the main kernel image and the main kernel dynamic library are stored in the external area.

14. The method according to claim 13, characterized in that, The first memory space includes a backup area, and the method further includes: During the cold start phase, the first loading attribute corresponding to the main core is stored in the backup area; the first loading attribute includes the address information of the main core image and the address information of the main core dynamic library.

15. The method according to claim 14, characterized in that, The first master kernel image includes pre-configured first recovery code. Loading the master kernel image and master kernel dynamic library from the first memory space into the second memory space includes: Execute the first recovery code to obtain the first loaded attribute from the backup area; The main core image is obtained from the external region, and the main core image is loaded into the second memory space according to the address information of the main core image; The main core dynamic library is obtained from the external area, and the main core dynamic library is loaded into the second memory space according to the address information of the main core dynamic library.

16. A computer-readable storage medium, characterized in that, It includes computer program instructions, which, when executed by a processor, enable the processor to perform the data processing method as described in any one of claims 1-10.

17. A computer program product containing instructions, characterized in that, When the instruction is executed by the processor, the processor performs the data processing method as described in any one of claims 1-10.

Images