Hybrid integrated circuits and systems and methods for manufacturing same

Abstract

A partially completed wafer contains complementary metal–oxide–semiconductor (CMOS) active devices formed with a CMOS fabrication line. Thin-film active devices are formed over the CMOS active devices with a thin-film fabrication line. Wiring between the CMOS active devices and the thin-film active devices may be formed with either or both fabrication lines. Wiring above the thin-film active devices may be formed with the thin-film fabrication line. The thin-film active devices and related wiring provide enhanced functionality to functionality provided by the CMOS active devices.

Description

P13861PC00Hybrid Integrated Circuits and Systems and Methods for Manufacturing SameCross-Reference to Related Applications

[0001] This application claims priority to and the benefit of CA 3274172, filed May 16, 2025, which is incorporated in its entirety herein by reference.Field

[0002] The present invention relates to integrated circuits and systems and methods of manufacturing integrated circuits.Background

[0003] Semiconductor chip fabrication is highly complex. Demand for chips with ever- increasing density of active devices, such as transistors, drives this complexity and the associated high costs. For example, extreme ultraviolet (EUV) lithography, which is an essential component in making state-of-the-art chips, is one of the most complex technologies ever devised. A single EUV lithography system can cost upwards of $300 million. At the same time, planar density is approaching its limit and Moore’s Law, which states that the number of transistors on a chip doubles every two years, may soon no longer hold true.Summary

[0004] The present invention provides techniques for semiconductor fabrication that can improve density while reducing or at least maintaining current levels of manufacturing complexity. Moreover, the present invention can help diversify the global semiconductor supply chain to reduce or eliminate the world’s reliance on a handful of critical fabrication facilities. Further, according to the present invention, enhanced functionality can be added to conventional complementary metal-oxide-semiconductor (CMOS) chips without the use of chiplets, and suchP13861PC00 enhanced functionality can improve the utility, security, and other features of conventional CMOS integrated circuit designs.

[0005] According to various aspects of the present invention, a partially completed wafer contains CMOS active devices formed with a CMOS fabrication line. Thin-film active devices are formed over the CMOS active devices with a thin-film fabrication line. Wiring between the CMOS active devices and the thin-film active devices may be formed with either or both fabrication lines. Wiring above the thin-film active devices may be formed with the thin-film fabrication line. The thin-film active devices and related wiring provide enhanced functionality to functionality provided by the CMOS active devices.

[0006] These and other aspects of the present invention will be described in detail in the following.Brief Description of the Figures

[0007] FIG. 1 is a diagram of an example method of manufacturing hybrid semiconductor chips according to the present invention.

[0008] FIGS. 2A - 2D are cross-sectional diagrams of example hybrid semiconductor chips according to the present invention.

[0009] FIG. 3 is a cross-sectional diagram of an example semiconductor chip showing wire and via interconnections according to the prior art.

[0010] FIG. 4 is a cross-sectional diagram of an example hybrid semiconductor chip showing wire and via interconnections according to the present invention.

[0011] FIG. 5 is a cross-sectional diagram of an example hybrid semiconductor chip showing wire and via design considerations according to the present invention.

[0012] FIG. 6 is a cross-sectional diagram of an example thin-film transistor according to the present invention.P13861PC00Detailed Description

[0013] The present invention concerns fabricating thin-film active devices, such as transistors, over complementary metal-oxide-semiconductor (CMOS) active devices. This increases density in the third dimension over a conventional planar die, allowing greater overall density in state-of- the-art chips than provided by CMOS alone or improved density in older generation chip designs. Moreover, irrespective of any increase in density, existing CMOS designs can be augmented with valued-added enhanced functionality provided by thin-film logic and wiring.

[0014] FIG. 1 shows an example method 100 of manufacturing a plurality of hybrid integrated circuits (ICs) or chips 180. The method 100 begins with conventional CMOS fabrication techniques before transitioning to thin-film or thin-film transistor (TFT) fabrication techniques (Note that the term “TFT” is used herein for convenience and devices other than transistors may be formed). The method 100 is intended to be performed with two corresponding fabrication lines, namely a CMOS fabrication line 102 and a TFT fabrication line 104. The fabrication lines 102, 104 may be located geographically distant from each other, such as being located in different countries. The method 100 also describes a system, in that each block of the method corresponds to a station, machine, or tool in a system.

[0015] The CMOS fabrication line 102 may be a state-of-the-art line with current- generation processes, such as EUV lithography. Accordingly, the TFT fabrication line 104 may improve active device density beyond what is currently possible with the CMOS line 102 alone. Alternatively, the CMOS line 102 may be an older-generation line, in which case the TFT fabrication line 104 may improve active device density beyond what is possible with older equipment. In both cases, no fundamental changes are required to be made to the CMOS line 102 and it can still produce fully functional chips without the TFT line 104.

[0016] The CMOS line 102 may be configured to manufacture chips with intended functionality, such as microprocessors, central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), memory, or similar. According to the present invention, the manufacture of chips on the CMOS line 102 is stopped at a selected point, so that the intended functionality may be enhanced by completing manufacture on the TFT fabrication line 104. As such, the CMOS line 102 may be operated in two ways: 1) completing chips, orP13861PC00 wafers containing such chips, with the intended functionality and 2) partially completing wafers for subsequent enhancement with the TFT fabrication line 104. In the latter case, the intended functionality of the chips may be fully or partially realized at the CMOS line 102, and the enhanced functionality added to the chips at the TFT line 104 may be designed to alter, supplement, or even redefine the intended functionality.

[0017] It is important to note that the design fabricated by the CMOS 102 line is not changed to accommodate the TFT line 104. The same design is made by the CMOS line 102 whether to completion of a CMOS chip or for transfer of partially completed wafers to the TFT line 104 for functional enhancement. For a wafer that is to be completed on the TFT line 104, the operator of the CMOS line 102 need only halt processing of the wafer and perform transfer treatment on the wafer in preparation for completion on the TFT line 104. Impact on the CMOS line 102 is thus minimal.

[0018] Blocks 110 - 120 are performed with conventional CMOS fabrication techniques on the CMOS fabrication line 102.

[0019] At block 110, a silicon wafer is prepared. Various conventional CMOS fabrication techniques may be used, such as forming a layer of silicon dioxide or similar material on a silicon wafer.

[0020] At block 112, photolithography is performed on the wafer to apply a pattern to the wafer using photoresist, as is well known.

[0021] At block 114, etching is performed on the wafer to etch the pattern formed at block 112.

[0022] Then, at block 116, ion implantation is performed on the wafer to dope regions of the wafer according to the etched pattern.

[0023] Blocks 112 - 116 are typically repeated for a sequence of patterns to form an arrangement of active semiconductor devices, such as transistors, in regions of the wafer under manufacture. In addition, alignment marks are typically formed on the wafer at the same time to facilitate proper alignment for photolithography and other processes.P13861PC00

[0024] Then, at block 118, after the CMOS devices are formed, electrical contacts, such as tungsten plugs, are formed to electrically connect the devices to subsequent wiring.

[0025] Blocks 110 - 118 are typically performed at temperatures that peak at around 1000 °C in what is commonly referred to as the front-end of line (FEOL). Numerous additional and / or alternative FEOL techniques and variations of blocks 110 - 118 may be performed. Any suitable conventional CMOS fabrication technique may be used. Blocks 110 - 118 are merely one illustrative example.

[0026] In a conventional CMOS line, wiring is performed next at block 120 in order to interconnect the semiconductor devices formed at blocks 112 - 118 to create logic circuits that implement the intended functionality of the chips under manufacture. Logics circuits vary in complexity and range from low-level logic gates (e.g., AND, OR, NAND, etc.) to functional units (e.g., adder, multiplexer, arithmetic logic unit or ALU, etc.) and further to complex devices, such as processing cores / units and memory cell arrays. In a conventional CMOS line, the wiring at block 120 includes forming layers of metal wires and vias to create these interconnections.The wiring at block 120 is considered part of the back-end of line (BEOL) and / or middle-of-line (MOL) and is typically performed at temperatures that peak at around 400 °C.

[0027] In the conventional CMOS line, once wiring is completed at block 120, further processes, such as passivation, dicing, and packaging, are performed at block 122 to create a plurality of completed chips. Completion steps at block 122 may be performed on another line. The CMOS line 102 may be operated in this manner to create chips with the intended functionality, as is well known. However, according to the present invention, for at least some of the wafers processed by the CMOS line 102, the completion steps at block 122 are omitted (these steps will be done later) and the amount of wiring formed at block 120 becomes a controllable variable, so that some, all, or none of the wiring is formed at the CMOS line 102. These wafers are diverted to the TFT fabrication line 104 for completion with enhanced functionality.

[0028] According to the present invention, the amount of wiring that is formed with the CMOS line 102 varies, and this is designated as portion of wiring 120A. There are three cases: 1) No wiring is formed with the CMOS line (block 120 and portion 120A are ignored), some wiring isP13861PC00 formed with the CMOS line as indicated by portion 120A, or all wiring is formed with the CMOS line (portion 120 A corresponds to all the wiring normally performed at block 120).

[0029] In the first case, wiring at the CMOS line 102 is omitted completely, so that the electrical contact points (e.g., plugs) of the fabricated CMOS devices, such as transistors, remain unconnected and may be used at the TFT line 104 to directly interface with individual CMOS devices. In such case, the realized portion of the intended functionality of the CMOS chip amounts to an arrangement of devices.

[0030] In the second case, some wiring is formed at the CMOS line 102, so that some interconnections among CMOS devices are made to realize a corresponding degree of the intended functionality of the CMOS chip. For example, several metal and via layers may be formed at block 120A to interconnect CMOS transistors to form logic gates, functional units, etc. The last metal / via layer formed at the CMOS line 102, which is not the final layer of the CMOS design, allows direct interfacing with such logic gates, functional units, etc.

[0031] In the third case, all wiring to implement the intended functionality of the CMOS design is done with the CMOS line at block 120A. The final metal / via layer formed at the CMOS line 102 allows interfacing with the designed microprocessor, FPGA, etc. as a whole.

[0032] After wiring, if any, is formed at block 120A with the CMOS line 102, the wafer under manufacture is treated at block 124 to facilitate transfer of the now partially completed wafer 130 to the TFT line 104. Treatment may include applying a protective coating to the partially completed wafer 130, such as photoresist, polymer, silicon dioxide (e.g., a SiO2 layer of at least 10 nm thick), or similar. The protective coating is applied to the entire surface of the partially completed wafer 130 to protect the CMOS devices and / or any wiring from damage or degradation while the partially completed wafer 130 is transported to the TFT line 104 and during intermediate storage before the partially completed wafer 130 is processed by the TFT line 104.

[0033] The protective coating is preferably applied by a tool that is already present at the CMOS line 102. A relatively small change in the conventional workflow is required to apply the coating, but it is contemplated that no new tooling is needed.P13861PC00

[0034] Partially completed wafers 130 may be kept in storage at block 140 to ensure that the TFT fabrication line 104 has sufficient reserve stock. A stockpile of partially completed wafers 130 may be selected to last a desired duration, such as one week, one month, several months, one year, two years, or longer, depending on various logistic and economic factors. The protective treatment applied at block 124 should be selected to be effective for the planned storage duration, so that partially completed wafers 130 do not degrade while in storage. Storage of partially completed wafers 130 may be located at or proximate the TFT fabrication line 104.

[0035] Subsequently, partially completed wafers 130 are processed at the TFT fabrication line 104. Blocks 142 - 152 include thin-film fabrication techniques that are performed to form thin- film structures that provide enhanced functionality to the chip dies of the partially completed wafers 130. Blocks 142 - 152 may be considered BEOL and / or MOL processes and may be limited to temperatures substantially lower than the FEOL processes, such as 400 °C (vs. 1000 °C for FEOL).

[0036] At block 142, a partially completed wafer 130 is prepared. Preparation includes removing any protective coating that was applied at block 124 at the end of CMOS fabrication. A silicon dioxide coating, for instance, may be removed by polishing. Photoresist or polymer coating may be removed with piranha solution, a suitable solvent, or similar treatment. Block 142 may include polishing, such as chemical-mechanical polishing or CMP, to prepare the surface of the partially completed wafer 130 for thin-film formation.

[0037] Preparation may additionally include testing chip dies of the partially completed wafers 130. Testing may be designed to verify that the expected functionality of a chip die meets requirements. Testing may be designed to check for unexpected, unauthorized, or hidden functionality that may be malicious or at least undesired. For sake of efficiency, a sample of wafers 130 may be tested using a statistical methodology. Wafer samples may be selected from a batch or order from a particular CMOS line 102. Additionally or alternatively, again for sake of efficiency, a sample of chip dies of a wafer 130 or of a sample of wafers 130 may be tested using a statistical methodology. Testing may include connecting probes to contacts of a chip die and applying signals, such as a test vectors, which may be predetermined or random. Output of theP13861PC00 chip die generated by such signals may be analyzed and compared to expected or acceptable output.

[0038] A chip die that fails a test may be marked, rendered inoperable, or otherwise noted, so that subsequent processing is not performed on that chip die or, alternatively, so that the finished chip 108 may be discarded or at least identified as failing the test. A chip die that fails a test may still be useable in certain circumstances, such as the end user accepting the failure or by the functionality subsequently added with the TFT line 104 being designed to ameliorate, rectify, contain, or otherwise overcome the failure. For example, if a test determines that a chip die contains an unexpected functionality (e.g., a remote connection function that may be used for unauthorized access to data managed by the chip 80), it may then be determined whether the enhanced functionality to be implemented with the TFT line 104 sufficiently addresses such function (e.g., by blocking certain types of commands or signals). If the unexpected functionality is satisfactorily addressed, the chip die may be retained. If not, the chip die may be marked for subsequent disposal (i.e., after dicing 170).

[0039] The alignment marks applied to the wafer at the CMOS line 102 are used to align the wafer to the tooling used in the TFT line 104, so that the structures formed at the TFT line 104 are properly aligned with the contacts (block 118) or wiring (block 120A), as the case may be, formed at the CMOS line 102. For example, if manufacture of the partially completed wafer 130 is stopped at a layer of vias, the wafer is aligned to the TFT line 104 so that conductive material (e.g., source / drain contacts, wiring, etc.) may be formed in electrical contact with such vias. This ensures that the CMOS devices and wiring, if any, formed at the CMOS line 102 are electrically connected to the thin-film semiconductor devices and wiring formed at the TFT line 104.

[0040] At block 144, thin-film deposition is used to form a layer of material on the partially completed wafer 130. Various techniques, such as atomic layer deposition (ALD), sputtering, etc., may be used.

[0041] At block 146, photolithography is performed to apply a pattern to the thin film deposited at block 144.P13861PC00

[0042] At block 148, etching is performed to etch the pattern formed at block 146 to shape the deposited film to the pattern.

[0043] Several cycles of blocks 144 - 148 with various materials are required to form complete active devices and interconnecting wiring.

[0044] At block 150, wiring is formed to interconnect devices formed at blocks 144 - 148. Wiring includes forming metal wires and vias to create interconnections. Hence, block 150 may include forming insulative layers, such as interlayer dielectric or ILD, at which metal wires and / or vias are formed.

[0045] Blocks 144 - 150 represent additional techniques that may be used to form thin-film devices. For example, oxidation, annealing, and other treatments may be performed as part of the fabrication of thin-film devices and related wiring. In other examples, blocks 144 - 150 include additional and / or alternative thin-film forming steps. Blocks 144 - 150 are merely one illustrative example.

[0046] In addition to thin-film active devices, blocks 144 - 150 may also be used to form thin- film passive devices, such as resistors, capacitors, and inductors.

[0047] Blocks 144 - 150 may be repeated to form tiers of semiconductor devices, such as TFTs, and related wiring on the wafer under manufacture. This in combination with the previously formed CMOS devices creates a three-dimensional (3D) arrangement of semiconductor devices. Blocks 144 - 150 may be used to form any suitable number of tiers of thin-film semiconductor devices and related wiring. Multiple tiers of thin-film devices and related wiring may be stacked to grow the 3D arrangement of semiconductor devices.

[0048] Once all desired thin-film semiconductor devices and related wiring are formed, passivation is performed at block 152 to protect the underlying stack.

[0049] A completed wafer 160 results. The wafer 160 may then undergo dicing 170 and packaging 172 to obtain a plurality of chips 180. Dicing and packaging 170, 172 may be performed at the TFT line 104 or at another line, which may be at a different geographic location.P13861PC00

[0050] Each of the chips 180 includes a 3D stack of a number of tiers of thin-film semiconductor devices over a single tier of CMOS devices. Thin-film semiconductor devices may be used in this way to enhance the intended functionality of the CMOS devices in a number of different ways. The CMOS line 102 may continue to produce its CMOS chips with the original intended functionality, while diverting a portion of partially completed wafers to the TFT line 104 for enhancement.

[0051] FIGS. 2A - 2D show several example stacks or 3D arrangements of thin-film semiconductor devices over CMOS devices. Each example includes a base of CMOS devices 200 and one or more tiers of thin-film (“TF”) semiconductor devices 202 with one or more tiers of related wiring 204. CMOS devices 200 includes source / drain / gate electrical contacts, such as plugs. A tier of wiring 204 may include vias without wires or may include vias and wires on different layers, in what is sometimes referred to as a routing layer pair.

[0052] With reference back to FIG. 1 , the CMOS devices 200 are formed on the CMOS fabrication line 102 and the thin-film semiconductor devices 202 are formed on the TFT fabrication line 104. Wiring 204 between the CMOS devices 200 and the thin-film semiconductor devices 202 may be formed on either or both lines 102, 104, depending on the specific enhanced functionality to be provided with the thin-film semiconductor devices 202. Wiring 204 above the thin-film semiconductor devices 202 is formed on the TFT line 104 using thin-film processes, which may be considered BEOE or MOE processes.

[0053] Wiring 204, in general, interconnects devices, whether CMOS devices, thin-film devices, or a combination of such, to create circuits. A greater number of tiers of wiring 204 allows for more complicated circuits to be created.

[0054] FIG. 2A shows a stack 210 with a single tier of thin-film semiconductor devices 202 formed over a base tier of CMOS devices 200. The electrical contacts of the thin-film semiconductor devices 202 are formed in contact with the plugs of the CMOS devices 200. A tier of wiring 204 is formed over the thin-film semiconductor devices 202 to provide interconnections and off-chip connections. In this example, the CMOS devices 200 lack dedicated wiring and may thus provide only an arrangement of active devices, such as transistors. The tier of thin-film semiconductor devices 202 is directly connected to the CMOSP13861PC00 devices 200. The placement and configuration of the thin-film semiconductor devices 202 and their connection to the CMOS devices 200 may be configured to create simple circuits. Wiring 204 over the thin-film semiconductor devices 202 may assist in interconnecting such circuits to increase their complexity, in addition to providing off-chip connections.

[0055] FIG. 2B shows a stack 220 with a single tier of thin-film semiconductor devices 202 formed over a tier of wiring 204A, which is formed over a base of CMOS devices 200. This sandwiched tier of wiring 204A provides electrical interconnections between the thin-film semiconductor devices 202 and CMOS devices 200 and allows for the creation of circuits with greater complexity than the stack 210 of FIG. 2A. Because it is positioned between the CMOS devices 200 and thin-film devices 202, wiring 204A may be formed with the CMOS line 102, the TFT line 104 (FIG. 1), or both (z.e., respective portions of wiring formed by each line 102, 104). Another tier of wiring 204B is formed over the thin-film semiconductor devices 202 to provide additional interconnections and off-chip connections.

[0056] FIG. 2C shows a stack 230 with a single tier of thin-film semiconductor devices 202 formed over multiple tiers of wiring 204C, 204D, which are formed over a base of CMOS devices 200. The intermediate tiers of wiring 204C, 204D provide electrical interconnections between the thin-film semiconductor devices 202 and CMOS devices 200 and allow for the creation of circuits of greater complexity compared to the stack 220 of FIG. 2B. Another tier of wiring 204E is formed over the thin-film semiconductor devices 202 to provide additional interconnections as well as off-chip connections.

[0057] FIG. 2D shows a stack 240 including multiple tiers of thin-film semiconductor devices 202 and intermediate wiring 204. Circuit complexity may be increased relative to the stack 230 of FIG. 2C and is limited by the stack height able to be manufactured on the TFT line 104. By increasing the number of tiers of wiring 204 and / or the number of tiers of thin-film semiconductor devices 202 enhanced functionality of increasing complexity may be realized.

[0058] The stacks 210 - 240 of FIGS. 2 A - 2D are examples that illustrate the principles of the present invention. Numerous other stacks within the scope of the present invention will be apparent to the person of ordinary skill in the art given the benefit of this disclosure.P13861PC00

[0059] FIG. 3 shows an example stack of a traditional CMOS integrated circuit (chip) 300. This kind of chip may be formed with the CMOS fabrication line 102 (FIG. 1) with the wiring and completion blocks 120, 122.

[0060] The CMOS chip 300 includes a silicon substrate 302 that is provided with an arrangement of CMOS transistors 304 (and / or other active devices), as is well known. A contact layer 306 formed over the CMOS transistors 304 includes plugs 308 (e.g., tungsten plugs) situated within an insulating material 310 (e.g., borophosphosilicate glass or BPSG, silicon dioxide, etc.). The plugs 308 provide electrical interconnections between the CMOS transistors 304 and the wiring above.

[0061] Formed above the contact layer 306 are wiring layers of conductive wires 330 and vias 332 formed within insulating material 334, such as silicon dioxide or similar, which may be ILD. Wires 330 provide lateral connections and vias 332 provide vertical (z-direction) connections. Wiring layers with wires 330 may be referred to as metal layers or metallization layers and may be designated Ml, M2, M3, etc. Wiring layers with vias 332 may be designated V 1 , V2, etc.

[0062] Formed over the top metal layer, which in this example is metal layer M3, is a layer of passivation material 340, such as silicon dioxide or aluminum oxide. External contacts, such as solder bumps 350, may be formed over and through the passivation material 340 to provide off- chip electrical connections to the top wiring layer M3.

[0063] FIG. 4 shows an example stack of a hybrid CMOS -TFT integrated circuit (chip) 400. This kind of chip may be formed with the CMOS fabrication line 102 (FIG. 1), up to wiring block 120A and transfer treatment block 124, followed by the TFT fabrication line 104.

[0064] In this example, wiring formed at block 120 A of the CMOS line 102 stops after forming via layer VI, at which may be termed a transition plane 402. As a result, the structures of chips 300 and 400 of FIGS. 3 and 4 below the transition plane 402 are identical. The transfer treatment of block 124 of the CMOS line 102 may include applying a protective coating at this plane 402, and the preparation of block 142 of the TFT line 104 may remove this protective coating.

[0065] An arrangement of TFTs 404 is formed with the TFT line 104 at the transition plane 402 over the top layer of vias VI formed with the CMOS line 102. With the example TFT designP13861PC00 shown, source and drain contacts, indicated by example contact 406, may be formed over and in contact with vias 332 of layer VI to form circuits with the underlying metal layer Ml and CMOS transistors 304.

[0066] Wiring is formed over the arrangement of TFTs 404, as shown by via layer 408 and wire layer 410. Via layer 408 includes vias 412 formed within a layer of insulating material 414, such as ILD. Given that vias 412 are made on the TFT line 104 while vias 332 are made on the CMOS line 102, the vias 332, 412 may be made with different materials and / or processes that are suitable for the respective line 102, 104. Similarly, the material and / or process to form insulating material 414 with the TFT line 104 may be different to the material and / or process used to form the comparable insulating material 334 formed with the CMOS line 102.

[0067] Wire layer 410 includes wires 416 formed at a layer of insulating material 414. Similar to the vias, wires 416 may be made with the TFT line 104 with different materials and / or processes compared to wires 330 made with the CMOS line 102.

[0068] A layer of passivation material 420, such as silicon dioxide or aluminum oxide, is formed over the top wiring layer 410. External contacts, such as solder bumps 450, may be formed over and through the passivation material 420 to provide electrical connections to the top layer of wiring 410. Because the layers formed by the TFT line 104 may contain different materials from those formed by the CMOS line 102, the passivation material 420 may be made with different materials and / or processes compared to the passivation material 340 of the CMOS-only stack 300.

[0069] The example chip 400 of FIG. 4 corresponds to the general principles described above for stack 220 of FIG. 2B. Following those principles, in other examples, wiring layer Ml and / or via layer VI of the stack 400 may be made with the TFT line 104 instead of the CMOS line 102.

[0070] Note that in FIGS. 3 and 4, relatively few layers are shown for sake of explanation. State- of-the-art CMOS ICs often have quite a few more metal / via layers. The number of wiring and active layers for the CMOS -TFT IC 400 of the present invention is not particularly limited, other than by manufacturing practices and yield concerns, and may be as high as 10, 20, 30, 50 or more.P13861PC00

[0071] FIG. 5 shows a generalized stack 500 that summarizes the principles of the present invention discussed above with regard to IC design and applications. The stack 500 is originally intended to embody a CMOS IC design that is designated by 502 and 508 together.

[0072] A partially completed CMOS design 502 includes CMOS active devices 504 (e.g., transistors) and a number of metal and via layers Ml, VI, M2, V2, M3, V3, etc. that collectively provide CMOS functionality that is desired to be enhanced. Fabrication on a CMOS line 102 (FIG. 1) is stopped at a plane 506 after the desired CMOS functionality is formed. An omitted portion of the CMOS design 508 is part of the original design of the CMOS chip and is not manufactured. If the original CMOS design has m metal layers and n via layers, fabrication on the CMOS line 102 is stopped after forming a chosen metal layer 1, 2 ... m ~ 1, or m or a chosen via layer 1, 2 ... n - 1, or n. Stopping CMOS fabrication after via layer V3, as illustrated, is one example.

[0073] A TFT design 510 is manufactured by a TFT fabrication line 104 (FIG. 1) over the partially completed CMOS design 502 to enhance the CMOS functionality. The TFT design 510 includes any number of layers of TFTs 512 (or other active devices, hence denoted as “TF”) and related wiring 514, which may be arranged in an alternating fashion. Optional transition wiring 516 may be provided to interface the TFT design 510 with the partially completed CMOS design 502 Transition wiring 516 may be useful if the none of the metal and via layers Ml, VI, M2, V2, M3, V3 ... Mm, Vn of the partially completed CMOS design 502 provides suitable electrical contacts to expose at a stop or transition plane 506. Transition wiring 516 may act as a shim layer that converts wiring exposed at the transition plane 506 to be compatible with the layer of TFTs 512. Any suitable number of TFT layers 512 and wiring layers 514 may be used, with the numbers shown being one example.

[0074] Selecting the plane 506 at which to stop CMOS fabrication and arrive at the partially completed CMOS design 502 depends on the desired CMOS functionality to be retained and how such functionality is to be enhanced by the TFT design 510.

[0075] As mentioned above, a complete CMOS design may implement functionality, such as a microprocessor, CPU, GPU, FPGA, memory, or similar. A selected degree of this functionality is retained with the partially completed CMOS design 502, and the TFT design 410 is added toP13861PC00 provide enhanced functionality to the partially completed CMOS design 502 to arrive at a hybrid CMOS-TFT design.

[0076] The choice of where to position the transition plane 506 determines the degree of original CMOS design that is retained in the partially completed CMOS design 502. In various CMOS designs that are commercially available today, stopping after metal M 1 or via V 1 exposes source / drain / gate contacts for connection to the TFT design. This may be useful when CMOS active devices are desired for their high operating frequency or other characteristics. The TFT design 510 may provide enhanced functionality such as connective logic and / or thin-film active devices that control or configure the CMOS active devices.

[0077] Stopping after the metal M2, M3, or M4 (or the corresponding via layer) may retain CMOS wiring sufficient for individual memory cells (e.g., static random-access memory or SRAM cells, or compact array thereof). This may be useful when CMOS SRAM cells are desired for their well-known characteristics. The TFT design 510 may provide enhanced functionality such as memory access control, power distribution, authentication, encryption, and so on.

[0078] Stopping after the metal M3, M4, M5, or M6 (or the corresponding via layer) may retain CMOS wiring sufficient for logic gates (e.g., AND, OR, NAND, NOR, etc.). This may be useful when CMOS logic gates are required for their operational characteristics. The TFT design 510 may provide enhanced functionality in the form of configuring CMOS logic gates into higher- level functionality, such as multiplexers, adders, ALUs, latches, registers, etc.

[0079] Stopping after the metal M3, M4, or M5 (or the corresponding via layer) may retain CMOS wiring sufficient for banks of memory cells, such as small arrays of SRAM cells. This may be useful when such memory banks are desired. The TFT design 510 may provide enhanced functionality such as memory bank access control, power distribution, authentication, encryption, and so on.

[0080] The above examples are merely illustrative. A chip designer or other person of ordinary skill in the art, given the benefit of this disclosure, can select a CMOS design that is useful for a particular application, determine the enhanced functionality to add to the CMOS design, andP13861PC00 further determine where to stop CMOS fabrication and begin TFT fabrication (z.e., the location of the transition plane 506).

[0081] In addition, an IC design program may be configured with data describing the partial CMOS design 502 as an immutable constraint during automated or semi-automated generation of layouts for elements of the TFT design 510, such as transition wiring 516, TFTs 512, and / or wiring 514. Such a constraint may include a layout of wiring (z.e., vias or wires) at the transition plane or a layout of electrical contact points (e.g., plugs), if wiring is not fabricated with the CMOS line, as well as the functionality provided by the partial CMOS design 502. For example, a topmost wiring layer (z.e., at the transition plane 506) of the partial CMOS design 502 exposes electrical connection points to the functionality provided by the CMOS active devices. The position and purpose of each connection point may be included in a set of immutable constraints provided to an IC design program. The IC design program may then be utilized, in a fully or semi-automated manner, to generate layouts for each layer of the TFT design 510 that is to be formed over the partial CMOS design 502. Examples of such IC design programs include various tools provided by Cadence™, Synopsys™, and others, as well as libraries such as GDSFactory. Such programs are generally capable of automated design of wiring layouts. A modification, such as an extension, plugin, or library may be created to incorporate the teachings of the present invention to support layouts that include active devices of a TFT design 510. Alternatively, a new IC design program can be created for layout of wiring and thin-film active devices over CMOS.

[0082] The present invention enables numerous applications, several of which are described below.

[0083] Military, security, and related applications may benefit from enhanced functionality such as tamper-proof security features, data encryption and decryption, nonvolatile storage of proprietary software, and nonvolatile product configuration. Product configuration may include (1) on-chip storage of security keys, checksums, passwords, password images, or challenge questions; (2) on-chip logging of a login and session activity; (3) the creation of different versions of the same underlying semiconductor system, where the different versions might have different feature sets, authorization levels, or price points; (4) the permanent storage of a tamper-P13861PC00 proof configuration into an FPGA fabric; and (5) the pre-emptive destruction of sensitive data or the disabling of normal chip operation if tampering or intrusion attempts are detected.

[0084] Another example of enhanced functionality is read-only memory (ROM), where the contents of the ROM can be added relatively late in a fully custom IC design or retrofitted to an existing IC design. Promising applications that would be enabled by the addition of ROM to an IC design include relatively inexpensive storage of encryption keys, which may be obfuscated. Such keys may be used to track different IC versions as well as providing key-controlled product differentiation through the selective unlocking of system-on-chip (SoC) features. Keys may also be used to implement hardware-enforced, tamper-proof restrictions on access to certain SoC functions depending on a user’s authorization or security clearance level. Obfuscation of the key storage ROM circuit may be used to provide a barrier against attempts to reverse engineer the key storage subsystem to recover the keys.

[0085] In another example, added ROM may be used to store tamper-proof factory versions of diagnostic and boot software for on-chip processors. Providing tamper-proof storage of such software may be useful for speeding up system recovery following software corruption or malware attacks by an adversary. Late-arriving final or revised versions of the software can be accommodated in an IC design by relatively inexpensive changes to the transistor connections that are formed in the final version of the added ROM.

[0086] In another example, software that enables forward compatibility, implemented with relatively inexpensive future mask updates, may extend the marketable life and profitability of an SoC. This software may be used to emulate, for example, new CPU or GPU instructions so that an older SoC can remain competitive with more recent designs by executing the emulation software on an existing on-chip CPU. The forward compatibility provided by such emulation software may also help extend the service life of older equipment.

[0087] In still another example, ROM may be useful for built-in self-test (BIST) software and test vectors, which can be finalized at a relatively late design stage. While pseudorandom, hardware-generated test vectors that require minimal memory capacity are widely used in industry, it is also common to enhance those generated test vectors with precomputed and stored test vectors that target specific erroneous behaviors that would otherwise be missed. In addition,P13861PC00BIST software is often required for controlling test vector sequencers that execute one or more diagnostic routines for error detection. Added ROM would allow updated, more effective BIST software to be loaded from on-chip storage and then executed by the BIST sequencers.

[0088] Security applications include on-chip authentication, cryptographic logic, and similar.

[0089] On-chip authentication is used to restrict access to stored data and software, thus protecting against unauthorized attempts to retrieve or change critical data, or blocking attempts to install new hardware designs that have been compromised with hidden spyware or malware. For example, authentication can be used to restrict attempts to access and possibly change stored encryption and decryption keys, boot software, diagnostic software, or FPGA configurations. Authentication can also be used to enforce different degrees of access to system functions, depending on a user’s security level.

[0090] Data encryption is used to protect information against unauthorized interception by third parties while the information is being exchanged between two trusted systems. For example, data encryption is available in some FPGAs to encrypt configuration bitstreams against spying and tampering while they are being transmitted to an FPGA to reconfigure it in the field with a revised design. In some commercially available FPGAs, hardware implementations of standard decryption algorithms, such as the Advanced Encryption Standard (AES), are already available to decrypt configuration bitstreams that were encrypted by a trusted source. However, the use of standard algorithms, such as AES, allows third parties to exploit and benefit from known standard attack strategies.

[0091] Enhanced functionality may be used to modify standard authentication and encryption algorithms, to make them less vulnerable to standard attack. For example, proposed extensions to the AES cryptosystem may include extending the key length to more than the standard maximum of 256 bits, providing additional data remapping functions beyond the Rijndael S boxes that are already used, and combining AES with a second cryptosystem that increases the strength of the encryption.

[0092] AES is a symmetric -key (also called a single-key) cryptosystem, where the same key is used by both the encryption and decryption algorithms. A well-known vulnerability ofP13861PC00 symmetric-key cryptosystems is the requirement to provide a secure system to distribute keys to all trusted parties. A related vulnerability is that each trusted device must contain a copy of the one common key, making theft of any device containing the common key a system-level vulnerability.

[0093] Alternatives to symmetric key cryptosystems include public-key cryptosystems, which use two numeric keys: one private key and one public key, which can be freely distributed. A well-known public key cryptosystem is the Rivest-Shamir- Aiderman (RSA) cryptosystem. The two keys are generated in such a way that knowledge of the public key does not reveal the private key. The centrally held private key can be used to encrypt information, such as a new FPGA configuration, that is to be distributed. The second, public key, is known to all of the other devices (such as FPGAs) and is used to decrypt the information that was encrypted centrally using the private key. Effectively, encryption using the private key is equivalent to providing a tamper-proof signature for the encrypted information. Digital systems, such as FPGA, may be designed so that they do not permit the installation of a new configuration bitstream if the decryption step using the public key did not validate the signature, that is, when the new configuration bitstream cannot be correctly decrypted using the public key. This prevents the installation of potentially dangerous updates, such as new FPGA configurations that have hidden spyware or malware, or modified configurations that circumvent security features.

[0094] Public-key cryptosystems are not commonly implemented in commercially available chips, such as FPGAs, but with the present invention existing designs can be retrofitted with public-key cryptosystem hardware that is implemented using thin-film active devices. The operational speed of such hardware can be relaxed by using less complicated, known alternatives to the RSA algorithm, which would still be sufficient to provide secure distribution of conventional keys, such as AES keys. In this way, the security of existing high speed cryptosystem hardware, such as the AES implementations in some available FPGAs, can be enhanced significantly.

[0095] Another application is backside power.

[0096] One of the current challenges facing the semiconductor industry, and especially the Al hardware sector, is the ability to provide and distribute sufficient power to the many systems ofP13861PC00 large-scale integrated circuits. The current leading technological candidate to address this issue is the idea of placing power regulation and distribution circuitry on the backside (i.e. - the side opposite the CMOS logic) of the IC which avoids space constraints which occur when such circuitry competes with logic circuitry for space on the front side of the ICs and allows for larger and better-isolated power distribution conductors. A further challenge exists with such power systems in that the actual semiconductor manufacturing processes are typically optimized for the needs of the CMOS logic (speed, etc.) and are not optimal for the analog power distribution systems, resulting in reduced power efficiency with resultant increased cooling needs.

[0097] Power distribution and regulation circuitry implemented with Zinite technology can easily be manufactured on the backside of semi-finished wafers forwarded from conventional Fabs, and the Zinite process technology can be optimized for analog power circuit requirements.

[0098] Still other enhanced functionality includes kill switches, enhanced imaging systems (e.g., light detection and ranging or LiDAR), and radiofrequency (RF) components.

[0099] FIG. 6 shows an example TFT 600 according to the present invention. The TFT 600 may be used as TFTs 404 (FIG. 4) or any other TFT formed by the TFT fabrication line 104 (FIG. 1). The TFT 600 includes a source 612, drain 614, and gate 616.

[0100] The TFT 600 is formed on a planar substrate 620, which, with reference to FIG. 4, may be a layer of ILD or other insulative material 334, 414 that contains vias and / or wires.

[0101] An adhesion layer 622 may be formed over the substrate 620 to promote adhesion of subsequently formed material to the substrate 620. The adhesion layer 622 may be formed of titanium nitride, hafnium nitride, or similar material.

[0102] The source 612 is formed of a body of source material 630 disposed over (with respect to the depicted orientation) the substrate 620. In this example, the body of source material 630 is formed by sputtering to a thickness of about 15 nm. In other examples, other source thicknesses may be used, such as about 30 nm, 25 nm, 20 nm, 10 nm, etc.

[0103] Examples of source materials include various metals and other conductors, such as nickel, ruthenium, tungsten, cobalt, molybdenum, chromium, copper, titanium nitride, etc.P13861PC00Further examples of source materials include heavily doped n-type materials, degenerate n-type silicon, and III-V compound semiconductors with high conductivity with predominately n-type or electron transport, etc. Suitable combinations of such materials may be used. In this example, the source material is ruthenium.

[0104] In this example, the drain 614 is formed of a body of drain material 632 and has the same or similar material and / or structure as the source 612. Accordingly, such material and / or structure may be referred to as “source / drain” or similar terminology. In other examples, the drain 614 has a material and / or structure different to the source 612.

[0105] The adhesion layer 622, if used, promotes the adhesion of the bodies of source and drain material 630, 632 to the substrate 620. In other examples, the adhesion layer 622 may be omitted if the source / drain material has suitable adhesion without it.

[0106] The source 612 may include a source carrier reservoir 646 that is formed of reservoir material, which is an oxide semiconductor and preferably a metal-oxide semiconductor, such as tin oxide, zinc oxide, etc. The source carrier reservoir 646 may have a naturally high concentration of n-type carriers. The source carrier reservoir 646 may be doped to further increase its n-type concentration. Other examples of materials that may be used for the source carrier reservoir 646 include titanium nitride, indium gallium zinc oxide (IGZO), tungsten oxide, and indium tin oxide (ITO).

[0107] The source carrier reservoir 646 may be formed over and in contact with the body of source material 630. The source carrier reservoir 646 may be formed to a thickness of from about 5 nm to about 20 nm or from about 10 nm to about 15 nm. More specifically, in various examples, the thickness of the source carrier reservoir 646 is about 12.5 nm.

[0108] The drain 614 may include a drain reservoir 648. The drain reservoir 648 may have the same or similar structure and / or material as the source carrier reservoir 646. In this example, the drain reservoir 648 is formed of the same reservoir material disposed over and in contact with the body of drain material 632.P13861PC00

[0109] The body of source material 630 may be subject to inline treatment, such as plasma treatment, anneal treatment, chemical or electro-chemical treatment, or similar. Different types of treatment may be combined. A treatment may be repeated two or more times.

[0110] The treatment may form a p-type (in this example) or n-type (in other examples) sourcechannel interface 640 at the body of source material 630 at least between the body of source material 630 and semiconductor channel material 650. The source-channel interface 640 may tune the threshold voltage at which the TFT 600 turns on, making the transistor operate in enhancement or depletion mode, to reduce leakage current through TFT 600 in the off state. The source-channel interface 640 may create a repository of complimentary excess positive or negative charge that functions to deplete the channel in at least the region of the body of channel material 650 adjacent to the body of source material 630. In this manner, the source-channel interface 640 serves as a voltage-controlled electron transport barrier, resulting in substantially less current flow through body of channel material 650 when the TFT 600 is in an off state. Further, the source-channel interface 640 may also serve to reduce stress induced leakage currents (“SILC”) in TFT 600 by inhibiting the formation of interlayer stress-induced flaws between the body of channel material 650 and the body of source material 630. A drain-channel interface 642 may be similarly formed and may have similar characteristics, but it is contemplated that the source-channel interface 640 provides significant benefit without the drain-channel interface 642 and may provide most or all of the benefit.

[0111] In this example, the bodies of source and drain material 630, 632 are treated with oxygen plasma to form a layer of oxidized material that are the source and drain channel interfaces 640, 642. In the example of ruthenium as source / drain material, the source and drain channel interfaces 640, 642 are consequently formed of ruthenium oxide, which is contemplated to be primarily or exclusively of the +4 oxidation state, i.e., RuC .

[0112] The body of semiconductor channel material 650 disposed between the source 612 and drain 614 and over the substrate 620 between the source 612 and drain 614. The body of channel material 650 is a metal oxide. In this example, the body of channel material 650 is a layer of tin oxide, which is primarily or entirely tin (IV) oxide (SnCh), with a thickness of about 5 nm to about 10 nm. In this example, the layer of tin oxide is about 7 nm thick.P13861PC00

[0113] The tin oxide forming the body of channel material 650 is generally polycrystalline with a preferred crystallite orientation of Miller index < 110>, as determined using grazing-incidence x-ray diffraction (GI-XRD) with co = 0.5° on 20 nm and / or 40 nm thick samples. Polycrystalline tin oxide with this preferred crystal orientation provides good carrier mobility and good stability, which improves the performance and useful life of the TFT 600.

[0114] For sake of clarity, tin oxide with an orientation of <110> means that one of the directions in the family of directions <110>, such as direction

[0110] , is substantially normal to the plane of the substrate 620. In other words, a plane of the family { 110}, such as the plane (110), is substantially parallel to the plane of the substrate 620.

[0115] The crystallinity of the thin film of tin oxide is preferably at least about 80%, more preferably at least about 85%, more preferably at least about 90%, and still more preferably at least about 95%. Regions outside the 20 angular range of 20 - 60° may be ignored when computing crystallinity.

[0116] Source carrier reservoir 646 acts as a carrier source adjacent source material 630 and channel material 650 to provide a reservoir of negative charge carriers to mitigate carrier starvation. If used, drain reservoir 648 may serve a similar purpose for the drain 614.

[0117] The TFT 600 further includes a body of dielectric material 652 disposed over the body of channel material 650. In this example, the body of gate dielectric material 652 is a layer of hafnium oxide that is primarily or entirely hafnium (IV) oxide (Hf’Ch) and that may be polycrystalline or amorphous. The body of gate dielectric material 652 has a suitable thickness, such as about 10 - 15 nm thick, or more particularly, about 12.5 nm.

[0118] The TFT 600 further includes a body of gate material 654 (also termed “gate metal”) disposed over the gate dielectric material 652. The gate material is a conductor. Examples of gate materials include tungsten, titanium, titanium nitride, molybdenum, gold, platinum, aluminum, nickel, copper, chromium, hafnium, indium, manganese, iron, vanadium, zinc, tantalum, or alloys / combinations thereof. In this example, the body of gate material 654 is a layer of tungsten.P13861PC00

[0119] The bodies of channel material 650, dielectric material 652, and gate material 654 may be formed as complete layers over the bodies of reservoir material 646, 648 and the substrate 620 before being polished down (e.g., using CMP) to the form the structures depicted.

[0120] In operation, when a voltage is applied across the source 612 and drain 614, and when a suitable voltage is applied to the gate 616, a carrier channel forms in the body of semiconductor channel material 650, which causes flow of current between source 612 and drain 614. When the voltage is removed, the flow of current is reduced to a very low amount, assisted by the sourcechannel interface 640 and, optionally, the drain-channel interface 642. An on-to-off current ratio of about 1010has been measured in various tests.

[0121] Additional TFT designs and features may be used with the present invention, such as those described in US patent nos. 11,949,019 and 12,148,838, which are incorporated herein by reference in their entirety.

[0122] It should be apparent from the above that semiconductor supply chains can be improved by the present invention. Further, a thin-film fabrication line, which can be built at a fraction of the cost of a state-of-the-art CMOS line, can take advantage of the functionality of both CMOS and thin-film technologies. Moreover, wafers made by an untrusted CMOS line can be enhanced with a trusted thin-film design to provide security and control over chip fabrication by the operator of the thin-film line. Numerous other advantages and improvements should also be readily apparent to one of ordinary skill in the art.

[0123] The manufacture of materials, layers, and / or features of thin-film active devices is referred to herein as “forming.” Unless otherwise mentioned, “forming” is intended to include all semiconductor manufacturing techniques suitable and applicable therefor including, without limitation, deposition (e.g., chemical vapor deposition or CVD, atomic layer deposition or ALD, physical vapor deposition or PVD, etc.), plasma-enhanced / assisted atomic layer deposition (PEALD / PAALD), thermal ALD (T-ALD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, lithography / photolithography, etching, implantation, annealing, oxidation, and similar processes. When examples of specific types of forming are given herein, it should be understood that comparable methods of forming may be alternatively or additionally used, unless otherwise mentioned, without departing from the present invention.P13861PC00

[0124] Auxiliary verbs “can” and “may” are used interchangeably herein to denote components, features, and / or aspects of the present invention that are capable, configurable, selectable, modifiable, or optional, as would be apparent to one of ordinary skill in the art given the benefit of this disclosure. These terms should not be taken as limiting the present invention, unless otherwise specified.

[0125] Spatial prepositions, such as “over”, “under”, “above”, “below”, “up”, “down”, “beside”, etc., are provided for sake of explanation and should not be taken as limiting the present invention to an absolute spatial orientation or arrangement, unless otherwise specified. For example, one of ordinary skill in the art would understand that a first element is above or below a second element depending on the perspective of the observer.

[0126] The articles “a”, “an”, “the”, “said”, etc. indicate singular and plural, unless otherwise specified.

[0127] The conjunction “or” is used inclusively and should be understood to mean “and / or”, unless otherwise specified.

[0128] Sets of elements A, B, C described as A, B, or C; A, B, and C; A, B, and / or C; or A, B, C should be considered open sets from which one or more elements or a combination of one or more elements may be selected, unless otherwise specified. Sets of elements are open, unless specified to be closed, for example, by use of the term “consist”, “consisting”, or similar closed language.

[0129] The above clarifications apply to both the specification and claims.

[0130] The figures are not to scale, unless otherwise specified.

[0131] The above-described embodiments of the invention are intended to be examples of the present invention and alterations and modifications may be effected thereto, by those of ordinary skill in the art, without departing from the scope of the invention which is defined solely by the claims appended hereto.

Claims

P13861PC00Claims1. A method of manufacturing an integrated circuit, the method comprising: receiving a partially completed wafer containing complementary metal-oxide- semiconductor (CMOS) active devices formed with a CMOS fabrication line; and forming thin-film active devices over the CMOS active devices with a thin-film fabrication line, wherein the thin-film active devices provide enhanced functionality to functionality provided by the CMOS active devices.

2. The method of claim 1 , wherein the partially completed wafer includes a protective coating, the method further comprising removing the protective coating before forming the thin-film active devices.

3. The method of claim 1, wherein the partially completed wafer comprises wiring formed over the CMOS active devices, the method further comprising forming the thin-film active devices in electrical connection with the wiring.

4. The method of claim 1 , further comprising forming wiring over the CMOS active devices with the thin-film fabrication line.

5. The method of claim 1, further comprising forming wiring over the thin-film active devices with the thin-film fabrication line.

6. The method of claim 1 , further comprising selecting a transition plane at which to stop manufacture of the partially completed wafer with the CMOS fabrication line.

7. The method of claim 6, wherein the transition plane is immediately above a layer of vias formed over the CMOS active devices by the CMOS fabrication line.

8. The method of claim 6, wherein the transition plane is immediately above a layer of wires formed over the CMOS active devices by the CMOS fabrication line.

9. The method of claim 6, wherein the transition plane is immediately above electrical contacts of the CMOS active devices.P13861PC0010. The method of claim 6, wherein selecting the transition plane includes an integrated circuit design program referencing, as an immutable constraint, a layout of wiring formed on the partially completed wafer or a layout the CMOS active devices.

11. The method of claim 1 , wherein the partially completed wafer comprises a partially completed CMOS design.

12. The method of claim 1, wherein the partially completed wafer comprises a completed CMOS design.

13. The method of claim 1, further comprising, after forming the thin-film active devices, dicing and packaging the wafer to form a plurality of chips.

14. The method of claim 1, wherein the enhanced functionality includes read-only memory.

15. The method of claim 1, wherein the enhanced functionality includes encryption.

16. The method of claim 1, wherein the enhanced functionality includes tamper resistance.

17. An integrated circuit manufactured by the method of any one of claims 1 to 16.

18. A semiconductor chip comprising: complementary metal-oxide-semiconductor (CMOS) active devices formed with a CMOS fabrication line; and thin-film active devices formed over the CMOS active devices with a thin-film fabrication line; wherein the thin-film active devices provide enhanced functionality to functionality provided by the CMOS active devices.

19. The semiconductor chip of claim 18, further comprising wiring formed over the CMOS active devices with the CMOS fabrication line, wherein the CMOS active devices and the thin- film active devices are in electrical connection through the wiring.P13861PC0020. The semiconductor chip of claim 18, further comprising wiring formed over the CMOS active devices with the thin-film fabrication line, wherein the CMOS active devices and the thin- film active devices are in electrical connection through the wiring.

21. The semiconductor chip of claim 18, further comprising wiring formed over the thin-film active devices with the thin-film fabrication line, wherein the thin-film active devices are in electrical connection with the wiring.

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