Semiconductor drive device and electric power conversion device

Abstract

This semiconductor drive device (10) comprises a gate drive unit (11) that drives a semiconductor switching element (50), and an overcurrent protection unit (12). The overcurrent protection unit (12) has: an overcurrent determination unit (13) that receives input of a detection signal and determines an overcurrent; a gate voltage reduction unit (14) that reduces a voltage applied to a gate when the overcurrent is determined; and an off-gate current adjustment unit (18) that reduces an off-gate current when the overcurrent is determined. When an overcurrent is detected in the semiconductor switching element (50), the gate voltage is reduced, and the off-gate current during an operation to turn off the semiconductor switching element is reduced, resulting in a soft shutdown.

Description

Semiconductor Drive Device and Power Conversion Device

[0001] The present disclosure relates to a semiconductor drive device and a power conversion device.

[0002] Semiconductor switching elements are applied to various power conversion devices. A semiconductor drive device that controls the on / off of the semiconductor switching element is equipped with an overcurrent protection circuit that instantaneously detects an overcurrent in the semiconductor switching element due to an arm short circuit or the like generated by a malfunction or a failure and protects the semiconductor switching element.

[0003] As an example of a semiconductor drive device equipped with an overcurrent protection circuit, when an overcurrent detection unit detects an overcurrent, the gate voltage is clamped to a predetermined value to suppress the short-circuit current. Further, the off-gate resistance at the time of short-circuit interruption is greatly switched to perform soft interruption, thereby reducing the surge voltage and preventing the destruction of the semiconductor switching element due to overvoltage (see, for example, Patent Document 1). However, in a configuration in which a drive device that requires a power supply and a switching element are mounted separately, since a gate wiring having a large parasitic inductance is interposed, noise superimposed on the wiring becomes a factor, and it may not be possible to achieve high-speed and high-precision overcurrent detection and protection operation. The overcurrent detection unit and the part that clamps the gate voltage in this Patent Document 1 also require a power supply.

[0004] On the other hand, the applicant has provided an overcurrent detection unit and a gate voltage reduction unit that do not require a power supply in the immediate vicinity of the semiconductor switching element, suppress malfunction due to noise caused by long wiring, and realize high-speed and high-precision overcurrent detection and prevention of overvoltage breakdown by suppressing the short-circuit current (see Patent Document 2).

[0005] Japanese Patent Application Laid-Open No. 2014-82904 International Publication No. 2023 / 032024

[0006] According to Patent Document 2, by providing an overcurrent detection unit and a gate voltage reduction unit that do not require a power supply in the immediate vicinity of the semiconductor switching element, high-speed and high-precision overcurrent detection and prevention of overvoltage breakdown of the semiconductor switching element can be achieved.

[0007] On the other hand, when a smoothing capacitor and a snubber capacitor are applied to the main circuit of a power converter equipped with a semiconductor drive device that has a circuit to reduce the gate voltage when overcurrent is detected, reducing the gate voltage when overcurrent is detected causes voltage resonance between the smoothing capacitor and the snubber capacitor, and the problem of overvoltage breakdown of the semiconductor switching element becomes apparent when the current is cut off. In particular, this voltage resonance tends to be larger when the parasitic inductance of the gate wiring is large.

[0008] Therefore, even in a power conversion device equipped with a semiconductor drive device according to Patent Document 2, if a long gate wiring is present and a smoothing capacitor and a snubber capacitor are applied, this problem needs to be solved.

[0009] This disclosure provides a technology to solve the above-mentioned problems, and aims to provide a highly reliable semiconductor drive that can protect a semiconductor switching element from overcurrent even when the semiconductor switching element and the gate drive unit of the semiconductor drive are spaced apart, and can protect the semiconductor switching element from overvoltage even when the power conversion device equipped with the semiconductor switching element driven by this semiconductor drive has a smoothing capacitor and a snubber capacitor.

[0010] The semiconductor drive device according to this disclosure includes: a gate drive unit that drives a semiconductor switching element on and off by applying a voltage to the control terminal of the semiconductor switching element; a first overcurrent determination unit that receives a detection signal based on the voltage and current between the main terminals of the semiconductor switching element and determines an overcurrent flowing through the semiconductor switching element; a gate voltage reduction unit that reduces the voltage applied to the control terminal when an overcurrent is determined; and an off-gate current adjustment unit that adjusts the off-gate current flowing between the gate drive unit and the control terminal when the semiconductor switching element is turned off by the gate drive unit; and an overcurrent protection unit that protects the semiconductor switching element, wherein the first overcurrent determination unit includes a clamp diode that clamps the potential of a signal input unit, which is the input unit of the detection signal, to the potential of the control terminal; a first transistor to which the signal input unit is connected; and a low-pass filter provided at the signal input unit, wherein when the potential of the signal input unit reaches a set value, the first transistor turns on and determines an overcurrent in the semiconductor switching element. The off-gate current adjustment unit reduces the off-gate current when an overcurrent is detected by the first overcurrent detection unit, or when the voltage applied to the control terminal is reduced by the gate voltage reduction unit.

[0011] According to this disclosure, it is possible to protect semiconductor switching elements from overcurrent and also from overvoltage during shutdown, thereby providing a semiconductor drive device that can drive semiconductor switching elements with high reliability.

[0012] This is a diagram showing the schematic configuration of the semiconductor drive device according to Embodiment 1. This is a diagram showing the circuit configuration of the overcurrent protection unit according to Embodiment 1. This is a waveform diagram of each part showing the operation of the semiconductor drive device according to Embodiment 1. This is a diagram showing another circuit configuration of the overcurrent protection unit according to Embodiment 1. This is a waveform diagram of each part showing the operation of the semiconductor drive device according to Embodiment 1. This is a diagram showing the circuit configuration of the overcurrent protection unit according to Embodiment 2. This is a diagram showing the circuit configuration of the overcurrent protection unit according to Embodiment 3. This is a diagram showing the schematic configuration of the semiconductor drive device according to Embodiment 4. This is a waveform diagram of each part showing the operation of the semiconductor drive device according to Embodiment 4. This is a diagram showing the schematic configuration of the semiconductor drive device according to Embodiment 5. This is a waveform diagram of each part showing the operation of the semiconductor drive device according to Embodiment 5. This is a diagram showing the schematic configuration of the semiconductor drive device according to Embodiment 6. This is a waveform diagram of each part showing the operation of the semiconductor drive device according to Embodiment 6. This is a diagram showing the schematic configuration of the semiconductor drive device according to Embodiment 7. This is a diagram showing the circuit configuration of the overcurrent protection unit according to Embodiment 7. This is a waveform diagram of each part showing the operation of the semiconductor drive device according to Embodiment 7. This is a diagram showing the schematic configuration of the semiconductor drive device according to Embodiment 8. This is a diagram showing the circuit configuration of the overcurrent protection unit according to Embodiment 8. This is a waveform diagram of each part showing the operation of the semiconductor drive device according to Embodiment 8. This is a block diagram showing the schematic configuration of a power converter according to Embodiment 9. This is a diagram showing the schematic configuration of a power converter according to Embodiment 9. This is a diagram showing the circuit configuration of the overcurrent protection unit according to Embodiment 9. This is a waveform diagram of each part showing the operation of the power converter according to Embodiment 9. This is a diagram showing the schematic configuration of a power converter according to Embodiment 10. This is a waveform diagram of each part showing the operation of the power converter according to Embodiment 10. This is a diagram showing the schematic configuration of a power converter according to Embodiment 11. This is a waveform diagram of each part showing the operation of the power converter according to Embodiment 11. This is a diagram showing the schematic configuration of a power converter according to Embodiment 12. This is a waveform diagram of each part showing the operation of the power converter according to Embodiment 12. This is a diagram showing the schematic configuration of a power converter according to Embodiment 13. This is a waveform diagram of each part showing the operation of the power converter according to Embodiment 13. This is a diagram showing the schematic configuration of a power converter according to Embodiment 14. This is a waveform diagram of each part showing the operation of the power converter according to Embodiment 14.This is a block diagram showing the schematic configuration of a power converter according to Embodiment 15. This is a diagram showing the schematic configuration of a power converter according to Embodiment 15. This is a waveform diagram showing the operation of each part of the power converter according to Embodiment 15. This is a diagram showing the configuration of a power converter according to Embodiment 16. This is a diagram showing another configuration of the power converter according to Embodiment 16. This is a diagram showing yet another configuration of the power converter according to Embodiment 16. This is a diagram showing the schematic configuration of a power converter using a different semiconductor switching element. This is a diagram showing the schematic configuration of a power converter using a different semiconductor switching element. This is a diagram showing the hardware configuration of the control unit according to Embodiments 1 to 16.

[0013] The following description of this embodiment will be made with reference to the figures. In each figure, the same reference numerals indicate the same or corresponding parts.

[0014] Embodiment 1. Figure 1 is a diagram showing a schematic configuration of a semiconductor drive device according to Embodiment 1. The semiconductor drive device 10 controls the conduction / non-conduction state between the collector C and emitter E, which are the main terminals of the semiconductor switching element 50, by a gate voltage Vge applied between the control terminal (hereinafter referred to as the gate terminal) G and the reference terminal (hereinafter referred to as the emitter control terminal) ES. In this case, an IGBT (Insulated Gate Bipolar Transistor) is shown as an example of the semiconductor switching element 50, but it can also be applied to other semiconductor switching elements such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) which has a control terminal.

[0015] As shown in Figure 1, the semiconductor drive unit 10 comprises a gate drive unit 11 and an overcurrent protection unit 12. The overcurrent protection unit 12 is positioned immediately adjacent to or above the semiconductor switching element 50, and the gate drive unit 11 and the overcurrent protection unit 12 are connected by a two-wire connection cable 15. The gate drive unit 11 comprises an output stage circuit consisting of a positive power supply PG1 and a negative power supply PG2, a P-type MOSFET MG1 and an N-type MOSFET MG2, and gate resistors RG1 and RG2, a control unit 16 that controls this output stage circuit, and a protection operation detection unit 19. The emitter control terminal ES of the semiconductor switching element 50 is connected to a reference potential VG0 at the connection point between the positive power supply PG1 and the negative power supply PG2.

[0016] The control unit 16 receives a command signal SIN transmitted from a higher-level control unit (not shown) and controls the output stage circuit based on the signal GSD from the protection operation detection unit 19. In addition to the signal GSD, the control unit 16 may also control the output stage circuit by logically synthesizing various abnormality detection signals such as over-temperature or power supply failure. The operation of the protection operation detection unit 19 will be described later.

[0017] Furthermore, although this example shows the output stage circuit outputting a positive power supply potential VG1 or a negative power supply potential VG2, a configuration without a negative power supply potential PG2 is also possible, i.e., a configuration where the negative power supply potential VG2 is equal to the reference potential VG0. Also, in this example, a constant voltage drive is shown in which a P-type MOSFET MG1 and an N-type MOSFET MG2 are used as the output stage buffer of the gate drive unit 11, and the switching speed is adjusted by gate resistors RG1 and RG2, but this is not the only option.

[0018] The overcurrent protection unit 12 includes a first overcurrent determination unit 13 that determines the overcurrent flowing through the semiconductor switching element 50, a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined, and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50. The first overcurrent determination unit 13 includes a first transistor Q1, a clamp diode D1, and a low-pass filter (R, C1) consisting of a resistor R and a capacitor C1. A detection signal SOC, which is the collector voltage Vce that is the voltage between the main terminals of the semiconductor switching element 50, is input to the first transistor Q1 via the low-pass filter (R, C1), and an overcurrent determination signal OCD is output.

[0019] In this case, when the first transistor Q1 is turned on, the determination signal OCD changes, and an overcurrent in the semiconductor switching element 50 is determined. The gate voltage reduction unit 14 receives the overcurrent determination signal OCD as input and operates to reduce the gate voltage Vge applied to the gate terminal G to a level lower than the voltage of the positive power supply PG1 (VG1). At this time, the gate drive unit 11 detects that the gate voltage reduction unit 14 has reduced the gate voltage Vge using the protection operation detection unit 19, generates a signal GSD which is a protection operation detection signal, and transmits it to the control unit 16.

[0020] When the first overcurrent determination unit 13 determines that there is an overcurrent in the semiconductor switching element 50, the off-gate current adjustment unit 18 turns off the transistor Qg1, and when the gate drive unit 11 turns off the semiconductor switching element 50, the off-gate current flows through the resistor RG3, reducing the off-gate current and performing a soft shutdown of the semiconductor switching element 50.

[0021] When the control unit 16 receives the signal GSD, it keeps the semiconductor switching element 50 in the off state for a predetermined period, regardless of the state of the command signal SIN. The method by which the protection operation detection unit 19 detects the protection operation of the gate voltage reduction unit 14 can be implemented using known techniques, such as when the output potential or output current of the gate drive unit 11 (output stage circuit) drops below a set value for a preset period, so a detailed explanation is omitted.

[0022] In this case, the detection signal SOC input to the first overcurrent determination unit 13 is the voltage of the collector sense terminal CS (collector voltage Vce). The parasitic inductance Lc between the collector C and the collector sense terminal CS, and the parasitic inductance Le between the emitter E and the emitter control terminal ES are shown in the figure.

[0023] The emitter control terminal ES and collector sense terminal CS are typically formed close to the main element to minimize the parasitic inductance L interposed on the main element side. This eliminates the influence of the electromotive force (L・dI / dt) caused by the parasitic inductance L. Semiconductor switching elements 50 used in high-capacity power modules and the like are typically provided with an emitter control terminal ES to prevent a decrease in the gate voltage Vge due to the electromotive force (L・dI / dt). Furthermore, when detecting the collector voltage Vce, a collector sense terminal CS is provided to prevent the addition of extra voltage due to the electromotive force (L・dI / dt) and to detect the collector voltage Vce.

[0024] In this embodiment, the case in which an emitter control terminal ES and a collector sense terminal CS are provided is shown. However, it is also possible to use the emitter E and collector C, which are the main terminals used by the semiconductor switching element 50 for connecting with external elements, without providing the emitter control terminal ES and collector sense terminal CS. The collector voltage Vce in this embodiment is slightly different from the actual voltage between the main terminals (collector C, emitter E), but it is the voltage between the main terminals (Vce) used for control.

[0025] Figure 2 is a circuit diagram showing the details of the overcurrent protection unit 12 of the semiconductor drive device according to Embodiment 1. As shown in Figure 2, the overcurrent protection unit 12 includes a first overcurrent determination unit 13 that receives a detection signal SOC and outputs an overcurrent determination signal OCD, a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD, and an off-gate current adjustment unit 18 that reduces the off-gate current when an overcurrent of the semiconductor switching element 50 is detected. The gate voltage reduction unit 14 also includes a drive circuit 141 that reduces the gate voltage Vge and an amplification circuit 142 that amplifies the output signal from the first overcurrent determination unit 13 and drives the drive circuit 141.

[0026] The first overcurrent detection unit 13 comprises resistors R1, R2, R3, and R4 connected in series, a clamp diode D1, and a capacitor C1. Furthermore, it includes a series circuit in which a first transistor Q1, which is made of an NPN bipolar transistor, resistors R5 and R6, and a reverse current prevention diode D3 are connected in series. Capacitor C2 is connected in parallel with resistor R6, and a protection diode D2 is provided between the base and emitter of the first transistor Q1. In this case, the resistor R formed by the three resistors R1, R2, and R3 and capacitor C1 constitute a low-pass filter (R, C1). The connection point P1 between resistor R (R1, R2, R3) and resistor R4 becomes the input part of the detection signal SOC and is connected to the base of the first transistor Q1. The potential of the connection point P1, which is the base potential of the first transistor Q1 with reference to the emitter control terminal ES, is set as the input potential VA1.

[0027] The clamp diode D1 has its anode connected to capacitor C1 of the low-pass filter (R, C1), and its connection point is connected to connection point P1 and the base of the first transistor Q1. The detection signal SOC is voltage-divided by resistors R1 to R4 and input to the base of the first transistor Q1 via the low-pass filter (R, C1) composed of the voltage-dividing resistors R(R1, R2, R3) and capacitor C1. When the semiconductor switching element 50 is in the off state, the base of the first transistor Q1 is clamped to the negative power supply potential VG2 by the clamp diode D1. Although the example shown illustrates the clamp diode D1 being connected to the output side of the low-pass filter (R, C1), it may also be connected to the input side of the low-pass filter (R, C1).

[0028] In this case, when the semiconductor switching element 50 is turned off, the gate drive unit 11 negatively biases the gate voltage Vge, so the base potential and collector potential of the first transistor Q1 are also negatively biased. For this reason, a protection diode D2 and a reverse current prevention diode D3 are provided to protect the first transistor Q1. The protection diode D2 is an anti-parallel diode commonly used in bipolar transistors, and prevents the characteristics of the first transistor Q1 from degrading due to the application of a large negative voltage between the base and emitter.

[0029] The reverse current blocking diode D3 protects the first transistor Q1 by blocking current flowing in the direction of current flow. In this case, when the first transistor Q1 is in the off state, a negative voltage is applied to the gate terminal G, thereby preventing and protecting against reverse bias between the collector and emitter of the first transistor Q1. Furthermore, the reverse current blocking diode D3 is provided on the emitter side of the first transistor Q1, and the base potential (input potential VA1) of the first transistor Q1, referenced to the emitter control terminal ES, can be raised to the voltage level required for the first transistor Q1 to turn on. Therefore, immunity to voltage-derived noise can be improved. Note that the reverse current blocking diode D3 may also be provided on the collector side of the first transistor Q1.

[0030] Since the base-emitter junction of a bipolar transistor is a PN junction, similar to that of a diode, the base threshold voltage (the voltage between the base and emitter required for the bipolar transistor to turn on) and the forward voltage of the diode are both defined as Vf for simplicity. In this case, overcurrent is detected when the first transistor Q1 turns on. The base potential (input potential VA1) when the first transistor Q1 turns on is expressed by the following equation (1): VA1 = Vce × R4 / (R1 + R2 + R3 + R4) = 2Vf ... (1)

[0031] When the semiconductor switching element 50 is turned off, the base potential (input potential VA1) of the first transistor Q1 is immediately negatively biased by the action of the clamp diode D1. This prevents false detection of overcurrent due to an increase in the collector voltage Vce during the off operation of the semiconductor switching element 50. Furthermore, by negatively biasing the initial state of the capacitor C1 in the low-pass filter (R, C1), false detection of overcurrent during the on operation of the semiconductor switching element 50, while waiting for the collector voltage Vce to decrease, can also be prevented.

[0032] Next, the amplification circuit 142 within the gate voltage reduction unit 14 is a circuit that amplifies the judgment signal OCD from the first overcurrent determination unit 13, and includes a series circuit in which a second transistor Q2, which is made of a PNP bipolar transistor, and resistors R7 and R8 are connected in series. Capacitor C3 is connected in parallel with resistor R8, and a protection diode D4 is provided between the base and emitter of the second transistor Q2. The voltage of the judgment signal OCD is applied to the base of the second transistor Q2. The drive circuit 141 within the gate voltage reduction unit 14 is a circuit that amplifies the output signal from the first overcurrent determination unit 13, and includes a series circuit in which a third transistor Q3, which is made of an NPN bipolar transistor, resistor R10, and diode D6 are connected in series. Resistor R9 is provided between this series circuit and the base of the second transistor Q2, and a protection diode D5 is provided between the base and emitter of the third transistor Q3.

[0033] When the first transistor Q1 turns on and determines that the semiconductor switching element 50 is in an overcurrent state, the second transistor Q2 turns on, and then the third transistor Q3 turns on. Specifically, it operates as follows: When the semiconductor switching element 50 is in a normal ON state, the first transistor Q1 is OFF, so the potential of the determination signal OCD, that is, the base potential of the second transistor Q2, is the same as the gate potential of the semiconductor switching element 50 (positive power supply potential VG1). When the first transistor Q1 turns on due to the occurrence of an overcurrent, the potential of the determination signal OCD decreases, and when it drops to a potential (VG1-Vf) that is one threshold voltage Vf of the second transistor Q2 lower than the positive power supply potential VG1, the second transistor Q2 turns on.

[0034] The resistors R5 and R6 connected in series with the first transistor Q1 are pre-set to satisfy the following equation: (VG1 - Vf) × R6 / (R5 + R6) > Vf

[0035] When the second transistor Q2 is turned on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1. As a result, the base potential of the third transistor Q3 also rises, and a voltage greater than or equal to the threshold voltage Vf is applied to the base of the third transistor Q3, causing the third transistor Q3 to turn on.

[0036] The resistors R7 and R8 connected in series with the second transistor Q2 are pre-set to satisfy the following equation: VG1 × R8 / (R7 + R8) > Vf

[0037] In this way, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are turned on sequentially. Then, by discharging the gate charge accumulated in the capacitance between the gate and emitter of the semiconductor switching element 50, a gate discharge current IA flows through the third transistor Q3, reducing the gate voltage Vge. This makes it possible to suppress overcurrent of the semiconductor switching element 50.

[0038] In the semiconductor switching element 50, the gate input capacitance increases as the current capacity increases. Therefore, in order to reduce the gate voltage Vge of a semiconductor switching element 50 with a large current capacity and protect it from overcurrent, it is necessary to discharge a large amount of gate charge. For example, in the case of a semiconductor switching element 50 with a current capacity of several hundred amperes, it is necessary to flow a gate discharge current IA of several amperes.

[0039] The base current of the first transistor Q1 is determined by the constraint of minimizing the parasitic leakage current, i.e., heat generation, during the period when the semiconductor switching element 50 is off. Therefore, the magnitude of the collector current of the first transistor Q1 is also constrained. The base current of the first transistor Q1, which becomes the parasitic leakage current, is about 1 mA. Also, considering the temperature characteristics and frequency characteristics, the current amplification factor of the first transistor Q1 and the third transistor Q3 is, for example, about 30. If two-stage current amplification is performed without the amplification circuit 142, only a gate discharge current IA of about 1 A or less can be passed. In this case, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are turned on in order, and the base current is increased sequentially, enabling a discharge of a large amount of gate charge in a short time through three-stage current amplification. With three-stage current amplification, it is possible to handle a gate discharge current IA of, for example, several tens of A.

[0040] Furthermore, since the drive circuit 141 within the gate voltage reduction unit 14 can operate even without the amplification circuit 142, it can be omitted if necessary.

[0041] Generally, when the third transistor Q3 is turned on and the gate voltage Vge is reduced, this operation causes the overcurrent detection signal SOC to approach a non-overcurrent state, the operation to reduce the gate voltage Vge is canceled, and an overcurrent occurs again, which can cause oscillation. In this embodiment, a resistor R9 is provided to give deep hysteresis to the overcurrent determination operation and prevent the above oscillation operation. That is, when the third transistor Q3 is turned on, the base potential of the second transistor Q2 decreases due to the action of resistor R9, and the overcurrent determination operation is maintained for a predetermined time. As a result, the gate voltage reduction unit 14 continues the operation to reduce the gate voltage Vge for a predetermined time.

[0042] The value of the resistor R10 that defines the gate discharge current IA flowing during the overcurrent protection operation needs to be designed to prevent the surge voltage generated when the gate voltage Vge of the semiconductor switching element 50 rapidly decreases to a value below the gate threshold voltage Vth. For example, it is set to satisfy the following formula (2). (VG1 - VG0) × R10 / (RG1 + R10) > Vth... (2)

[0043] Note that since it is common for the semiconductor switching element 50 to have a built-in gate resistor, in practice, even if the above formula (2) is not satisfied, if the period during which the gate voltage Vge is reduced is short, the gate voltage inside the semiconductor switching element 50 will be maintained at a state higher than the gate threshold voltage Vth. Therefore, the surge voltage may not be a problem.

[0044] On the other hand, when the protection operation detection unit 19 detects the protection operation and the control unit 16 turns off the semiconductor switching element 50, if the gate voltage Vge after being reduced by the protection operation is too large, there is a concern that a sudden current interruption will occur and the semiconductor switching element 50 will be deteriorated by the surge voltage. For this reason, it is desirable to adjust the value of the resistor R10 so that the surge voltage Vsa generated in the collector voltage Vce during the protection operation and the surge voltage Vsb generated in the collector voltage Vce when the semiconductor switching element 50 is turned off thereafter are of the same level.

[0045] Next, the off-gate current adjustment unit 18 is connected to a connection wiring 15 in which a parallel circuit in which diode Dg4 and resistor RG3 are connected in parallel is connected to the gate terminal G of the semiconductor switching element 50. A series circuit in which transistor Qg1, which is made up of a PNP bipolar transistor, and reverse current prevention diode Dg2 are connected in series is connected in parallel to this parallel circuit. Furthermore, a series circuit in which resistors R11 and R12 are connected in series is connected in parallel to the series circuit of transistor Qg1 and reverse current prevention diode Dg2. The base of transistor Qg1 is connected to the midpoint of resistors R11 and R12, the reverse current prevention diode Dg1, and the collector of the second transistor Q2. In addition, a protection diode Dg3 is connected between the base and emitter of transistor Qg1.

[0046] When the semiconductor switching element 50 is in the normal ON state (P-type MOSFET MG1 of the gate drive unit 11 is ON, and N-type MOSFET MG2 is OFF), the on-gate current flows mainly through the diode Dg4 to the gate terminal G. When the semiconductor switching element 50 is in the normal ON state, as described above, the base potential of the second transistor Q2 is the same as the gate potential of the semiconductor switching element 50, so the second transistor Q2 is OFF. Therefore, the base potential of transistor Qg1 is at the emitter level, and no signal is input to the base of transistor Qg1 due to the reverse current prevention diode Dg1.

[0047] Furthermore, when the semiconductor switching element 50 is turned off (the P-type MOSFET MG1 of the gate drive unit 11 is off and the N-type MOSFET MG2 is on), the gate drive unit 11 negatively biases the gate voltage Vge, causing the wiring of the gate terminal G to drop from positive potential to negative potential. Consequently, the negative voltage is divided by resistors R11 and R12, and the divided voltage is applied to the base of transistor Qg1. This voltage is pre-designed to exceed the threshold voltage Vf of transistor Qg1, causing transistor Qg1 to turn on. As a result, the off-gate current flows from the gate terminal G of the semiconductor switching element 50 through diode Dg2 and transistor Qg1. Under normal conditions, it is sufficient for transistor Qg1 to be in the ON state when the off-gate voltage is high during switching off.

[0048] When an overcurrent in the semiconductor switching element 50 is detected, the first transistor Q1 and the second transistor Q2 turn on. When the second transistor Q2 turns on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, and the potential at the base of the transistor Qg1 drops to the potential (VG1 - Vf) which is decreased by the forward voltage of the diode Dg1 from the power supply potential VG1. On the other hand, the emitter of the transistor Qg1 becomes the potential decreased by the forward voltage of the diode Dg2, and the base of the transistor Qg1 is in a state where a reverse bias of Vf is applied, so the transistor Qg1 turns off.

[0049] That is, when an overcurrent in the semiconductor switching element 50 is detected, the transistor Qg1 turns off and the off-gate current flows through the resistor RG, in the parallel combination of the resistor RG3 and the transistor Qg1 in the off-gate current adjustment unit 18. Thereby, even when the power conversion device including the semiconductor switching element 50 driven by this semiconductor drive device 10 has a smoothing capacitor and a snubber capacitor, when an overcurrent in the semiconductor switching element 50 is detected and the semiconductor switching element 50 is turned off, the off-gate current is reduced, so that the voltage resonance between the smoothing capacitor and the snubber capacitor can be suppressed.

[0050] The switching to the resistor RG3 by this off-gate current adjustment unit 18 corresponds to a function of increasing the gate resistance when the control unit 16 turns off the semiconductor switching element 50 after the protection operation detection unit 19 detects a protection operation, to be larger than that in normal off state, that is, a so-called soft cut-off function. However, the off-gate current adjustment unit 18 in the present embodiment can increase the gate resistance promptly when an overcurrent in the semiconductor switching element 50 is detected, as compared with the conventional method.

[0051] Furthermore, when an overcurrent is detected in the semiconductor switching element 50, the gate voltage reduction unit 14 turns on the third transistor Q3 to perform a protective operation for the semiconductor switching element 50. At this time, the charge accumulated in the gate-emitter capacitance is discharged, and a gate discharge current IA flows from the gate terminal G to the gate voltage reduction unit 14. However, in the path from the gate terminal G to the gate voltage reduction unit 14, the off-gate current adjustment unit 18 has transistor Qg1 turned off, so the current flows through resistor RG3. The resistance value of resistor RG3 will be described later.

[0052] Furthermore, the reverse current prevention diode Dg1 connected to the base of transistor Qg1 is provided to prevent malfunction of transistor Qg1. The protection diode Dg3 connected between the base and emitter of transistor Qg1 is an anti-parallel diode commonly used in bipolar transistors, and prevents degradation of the characteristics of transistor Qg1 due to the application of a large positive voltage between the base and emitter.

[0053] The reverse current blocking diode Dg2 connected to the emitter side of transistor Qg1 protects transistor Qg1 by blocking current flowing in the reverse direction of the transistor's energization. Furthermore, by being located on the emitter side of transistor Qg1, the base potential of transistor Qg1, relative to the emitter, can be raised to the voltage level required for transistor Qg1 to turn on. In particular, the reverse current blocking diode Dg1 is connected to the base of transistor Qg1, preventing the on / off control of transistor Qg1 from being disrupted by the forward voltage of this reverse current blocking diode Dg1.

[0054] Figure 3 is a waveform diagram showing the operation of each part of the semiconductor drive device according to Embodiment 1. The details of the overcurrent protection operation by the semiconductor drive device 10 will be explained below based on Figures 2 and 3. Under normal conditions prior to time t1, the gate voltage Vge is output in accordance with the command signal SIN transmitted from the higher-level control device, and the collector current Ic of the semiconductor switching element 50 and the collector voltage Vce, which becomes the detection signal SOC, also have waveforms corresponding to the command signal SIN. The base potential (input potential) VA1 of the first transistor Q1 with reference to the emitter control terminal ES is clamped to a potential (VG2 + Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2 when the semiconductor switching element 50 is in the off state. When the semiconductor switching element 50 is in the on state, the collector voltage Vce drops to several volts, and the voltage VA1 divided by resistors R (R1, R2, R3) and resistor R4 becomes close to the reference potential VG0.

[0055] The potential of the determination signal OCD, that is, the base potential of the second transistor Q2, is the same as the gate potential (positive power supply potential VG1) when the semiconductor switching element 50 is ON, and is lowered to the negative power supply potential VG2 when it is OFF.

[0056] Under normal conditions, when the semiconductor switching element 50 is ON, the resistance of resistor RG3 is sufficiently large, so the on-gate current flows mainly through diode Dg4, and when the semiconductor switching element 50 is OFF, the off-gate current flows through transistor Qg1, so the resistance value R_OFFGI of the off-gate current adjustment unit 18 is small. Note that under normal conditions, transistor Qg1 of the off-gate current adjustment unit 18 is ON when the semiconductor switching element 50 is OFF, and ON or OFF when the semiconductor switching element 50 is ON, depending on the base potential of transistor Qg1. Therefore, in Figure 3, under normal conditions before time t1, when the semiconductor switching element 50 is ON, transistor Qg1 is shown as ON with a dotted line.

[0057] At time t1, if an overcurrent occurs after the semiconductor switching element 50 is turned on, due to an arm short circuit with other connected arms, the peak value Icp of the collector current Ic will saturate, and the collector voltage Vce, which normally decreases, will remain high. As a result, the base potential (input potential) VA1 of the first transistor Q1 will rise above the reference potential VG0.

[0058] At time t2, the base potential (input potential) VA1 of the first transistor Q1 rises to 2Vf, that is, when equation (1) above is satisfied, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50. When the first transistor Q1 turns on, the potential of the judgment signal OCD decreases, and when it drops to a potential (VG1-Vf) lower than the positive power supply potential VG1 by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 turns on. As a result, the base potential of the third transistor Q3 also rises, and a voltage of Vf or higher is applied to the base, turning on the third transistor Q3. Then, a gate discharge current IA flows and the gate voltage Vge is reduced. At that time, the collector current Ic decreases to a value Ica corresponding to the reduced gate voltage Vge, and a surge voltage Vsa is generated in the collector voltage Vce.

[0059] Furthermore, when the second transistor Q2 is turned on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, and the base potential of transistor Qg1 drops from the positive power supply potential VG1 to a potential (VG1 - Vf) which is the forward voltage of diode Dg1. On the other hand, the emitter of transistor Qg1 is at a potential which is the forward voltage of diode Dg2, and the base of transistor Qg1 is in a state where a reverse bias of Vf is applied, so transistor Qg1 is turned off. Consequently, the resistance value R_OFFGI of the off-gate current adjustment unit 18 increases (RG3).

[0060] At time t3, the protection operation detection unit 19 detects a decrease in the gate voltage Vge and generates the signal GSD. Between time t3 and time t4, the control unit 16 performs a current interruption operation on the semiconductor switching element 50 to turn it off. At this time, a surge voltage Vsb is generated in the collector voltage Vce. As mentioned above, it is desirable to set the resistor R10 to satisfy equation (2) above so that the surge voltage Vsb is approximately the same as the surge voltage Vsa that occurs beforehand. Also, when the control unit 16 turns off the semiconductor switching element 50, the off-gate current flows through the resistor RG3 of the off-gate current adjustment unit 18, so the off-gate current is reduced compared to normal operation and soft interruption is performed.

[0061] At time t5, after a delay time Tf has elapsed since the generation of signal GSD, the command signal SIN from the higher-level control device remains in the OFF state, and the abnormal signal FAIL is generated.

[0062] Next, the magnitude of the resistance value of the resistor RG3 in the off-gate current adjustment unit 18 will be explained. When an overcurrent is detected in the semiconductor switching element 50, the first transistor Q1 and the second transistor Q2 turn on, and the third transistor Q3 also turns on, thereby reducing the gate voltage by allowing the gate discharge current IA drawn from the gate terminal G to flow through the gate voltage reduction unit 14. This reduces the short-circuit current and performs a protective operation for the semiconductor switching element 50. Furthermore, the transistor Qg1 of the off-gate current adjustment unit 18 turns off, reducing the off-gate current when the semiconductor switching element 50 is off, thereby performing a soft shutdown and suppressing surge voltage.

[0063] To ensure these operations are performed reliably, the resistance value of resistor RG3 for soft shutdown must be greater than that of resistor R10, which allows the gate discharge current IA to flow through the gate voltage reduction unit 14. In other words, RG3 > R10 must be satisfied. By making the resistance value of resistor R10 smaller than that of resistor RG3, the gate voltage is sufficiently reduced to suppress the short-circuit current, and when turning off the semiconductor switching element 50, the off-gate current is suppressed by the high-resistance resistor RG3, thereby suppressing the surge voltage and ensuring reliable soft shutdown. When an overcurrent is detected, the route for the gate discharge current IA drawn from the gate terminal G to flow through the gate voltage reduction unit 14 also goes through resistor RG3, but because the resistance value of resistor R10 is smaller than that of resistor RG3, the gate voltage can be reduced by allowing sufficient gate discharge current IA to flow.

[0064] Furthermore, the resistance value of resistor R10 must be greater than the resistance value of the gate resistor RG1 of the gate drive unit 11. The gate resistor RG1 is an on-gate resistor that limits the on-gate current. When an overcurrent is detected in the semiconductor switching element 50, the P-type MOSFET MG1 of the gate drive unit 11 is on and the N-type MOSFET MG2 is off, so an on-gate current flows, but the gate discharge current IA flows and the gate voltage Vge is reduced. At that time, the collector current Ic decreases to a value Ica corresponding to the reduced gate voltage Vge, and a surge voltage Vsa is generated in the collector voltage Vce. However, if the resistance value of resistor R10 is sufficiently small at this time, the surge voltage Vsa will become large. Therefore, by satisfying equation (2) above and satisfying RG1 < R10, the surge voltage Vsa can be suppressed.

[0065] As described above, in this embodiment, the semiconductor drive device 10 includes an overcurrent protection unit 12 having a first overcurrent determination unit 13 that determines the overcurrent flowing through the semiconductor switching element 50, and a gate voltage reduction unit 14 that reduces the gate voltage Vge when an overcurrent is determined. The first overcurrent determination unit 13 includes a clamp diode D1 that clamps the potential (input potential) VA1 of the signal input unit (connection point P1) of the detection signal SOC to the gate potential, a first transistor Q1 to which the signal input unit is connected, and a low-pass filter (R, C1) provided at the signal input unit. When the input potential VA1 reaches a set value of 2Vf, the first transistor Q1 turns on and determines the overcurrent of the semiconductor switching element 50.

[0066] As a result, the overcurrent protection unit 12 can detect and protect the semiconductor switching element 50 from overcurrent by utilizing the threshold voltage of the first transistor Q1, without requiring its own power supply. Furthermore, the clamp diode D1 and the low-pass filter (R, C1) suppress malfunctions due to noise, enabling overcurrent protection. This allows the overcurrent protection unit 12, which does not require a power supply, to be placed close to the semiconductor switching element 50 even when the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are spaced apart, enabling highly reliable overcurrent protection.

[0067] Furthermore, the off-gate current adjustment unit 18 is provided, and when an overcurrent is detected, the resistance is adjusted to suppress the off-gate current when the semiconductor switching element 50 is off, thereby suppressing surge voltage and enabling soft shutdown. In particular, even when the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are spaced apart, it is possible to provide a highly reliable semiconductor drive device that can implement overcurrent protection for the semiconductor switching element 50. Moreover, even if the power conversion device equipped with the semiconductor switching element 50 driven by this semiconductor drive device 10 has a smoothing capacitor and a snubber capacitor, when an overcurrent is detected, the off-gate current when the semiconductor switching element 50 is off is suppressed, so soft shutdown is performed, which suppresses voltage resonance and makes it possible to provide a highly reliable power conversion device.

[0068] Furthermore, the functions of the clamp diode D1 and the low-pass filter (R, C1) will be explained below. When the collector voltage Vce is used as the detection signal SOC as in this embodiment, false detection of overcurrent may occur if the timing of the change in the collector voltage Vce due to switching exceeds the design range, or if the voltage amplitude of the collector voltage Vce exceeds the design range.

[0069] For example, in the former case, when the semiconductor switching element 50 is turned on, the drop in the collector voltage Vce is delayed due to the influence of noise, etc. In this case, the gate voltage Vge rises, causing the clamp diode D1 to not clamp the input potential VA1, and the delayed drop in the collector voltage Vce, i.e., the normal on operation, is misinterpreted as an overcurrent. On the other hand, an example of the latter case is when electric field-coupled or magnetically coupled noise is superimposed when the semiconductor switching element 50 is turned off or recovering. When the clamp diode D1 is clamping the input potential VA1, a change in voltage or current at the main terminal of the semiconductor switching element 50 may cause noise above a threshold voltage to be superimposed on the input potential VA1, i.e., the base of the first transistor Q1. In this case, the normal off operation or recovery of the semiconductor switching element 50 is misinterpreted as an overcurrent.

[0070] In this embodiment, a clamp diode D1 is provided to clamp the input potential VA1 to the gate potential, thereby preventing false detection due to overcurrent noise when the semiconductor switching element 50 is in the off state. Furthermore, by providing the clamp diode D1 and a low-pass filter (R, C1), the aforementioned false detection of overcurrent can also be suppressed.

[0071] For example, the problem of false detection during the ON operation of the semiconductor switching element 50 can be improved as follows: During the delay period from when the clamp diode D1 stops clamping the input potential VA1 until the collector voltage Vce actually drops, the low-pass filter (R, C1) can prevent false detection of overcurrent. Also, when the gate potential is negatively biased while the semiconductor switching element 50 is in the OFF state, the capacitor C1 for the low-pass filter (R, C1) is also negatively biased via the clamp diode D1. This expands both the voltage margin and the charge margin before false detection of overcurrent, improving the noise immunity of the electric field coupling or magnetic coupling during the OFF operation or recovery of the semiconductor switching element 50.

[0072] Furthermore, in this embodiment, a reverse current prevention diode D3 is provided to block current flowing in the reverse direction of the current flowing through the first transistor Q1, thereby protecting the first transistor Q1, and a large negative bias (VG2 + Vf) is applied to the capacitor C1 without being affected by the protection diode D2. This improves the noise immunity of the first transistor Q1 and suppresses false detection of overcurrent. In addition, since an NPN bipolar transistor is used for the first transistor Q1, and the signal with the input potential VA1 used for determination is input to a base that provides current amplification, the first transistor Q1 can be operated effectively with a small signal input.

[0073] Although the example described uses a PNP bipolar transistor as the transistor Qg1 in the off-gate current adjustment unit 18, an NPN bipolar transistor may also be used. Figure 4 is a different circuit diagram from Figure 2, showing the details of the overcurrent protection unit 12 of the semiconductor drive device according to Embodiment 1. The configuration of the off-gate current adjustment unit 18A differs from that of Figure 2, but the other configurations are the same, so the following description will focus on the differences from Figure 2.

[0074] Next, the off-gate current adjustment unit 18A is connected within a connection wiring 15 in which a parallel circuit consisting of diode Dg4 and resistor RG3 connected in parallel is connected to the gate terminal G of the semiconductor switching element 50. A series circuit consisting of transistor Qg1 (an NPN bipolar transistor), reverse current blocking diode Dg2, and reverse current blocking diode Dg5 connected in series is connected in parallel to this parallel circuit. Furthermore, a series circuit consisting of resistors R11 and R12 connected in series is connected in parallel to the series circuit of transistor Qg1 and reverse current blocking diode Dg2. Additionally, resistors R11 and R12 are connected to the midpoint, reverse current blocking diode Dg1, and resistor R9 to the base of transistor Qg1. Moreover, a protection diode Dg3 is connected between the base and emitter of transistor Qg1.

[0075] When the semiconductor switching element 50 is in the normal ON state, gate current flows mainly through the diode Dg4 to the gate terminal G. When the semiconductor switching element 50 is in the normal ON state, as described above, the base potential of the second transistor Q2 is the same as the gate potential of the semiconductor switching element 50, so the second transistor Q2 is off, and the third transistor Q3 is also off. Therefore, the base potential of transistor Qg1 is at the emitter level.

[0076] Furthermore, when the semiconductor switching element 50 is turned off, the gate drive unit 11 negatively biases the gate voltage Vge, causing the wiring of the gate terminal G to drop from positive potential to negative potential. Consequently, the negative voltage is divided by resistors R11 and R12, and the divided voltage is applied to the base of transistor Qg1. At this time, the emitter of transistor Qg1 is at a potential that is raised by the forward voltage of diodes Dg2 and Dg5. The base of transistor Qg1 is pre-designed to have a positive voltage of Vf applied to it, and transistor Qg1 turns on. As a result, the gate current flows from the gate terminal G of the semiconductor switching element 50 through transistor Qg1 and diode Dg2.

[0077] When an overcurrent is detected in the semiconductor switching element 50, the first transistor Q1 and the second transistor Q2 turn on. When the second transistor Q2 turns on, the base potential of the second transistor Q2 drops from the positive power supply potential VG1 to VG1-Vf, the third transistor Q3 turns on, and current flows from the connecting wiring 15 to the gate voltage reduction unit 14. As a result, the voltage is divided by resistors R11 and R12, and a potential increased by the forward voltage of diode Dg1 is applied to the base of transistor Qg1. On the other hand, the emitter has a potential increased by the forward voltage of diodes Dg2 and Dg5, so a negative voltage of Vf is applied to the base of transistor Qg1, causing it to turn off.

[0078] Furthermore, the reverse current prevention diode Dg1 connected to the base of transistor Qg1 is provided to prevent malfunction of transistor Qg1. The protection diode Dg3 connected between the base and emitter of transistor Qg1 is an anti-parallel diode commonly used in bipolar transistors, and prevents degradation of the characteristics of transistor Qg1 due to the application of a large negative voltage between the base and emitter.

[0079] The reverse current blocking diode Dg2 connected to the emitter side of transistor Qg1 protects transistor Qg1 by blocking current flowing in the reverse direction of the transistor's energization. Furthermore, by being located on the emitter side of transistor Qg1, the base potential of transistor Qg1, relative to the emitter, can be raised to the voltage level required for transistor Qg1 to turn on. In particular, the reverse current blocking diode Dg1 is connected to the base of transistor Qg1, preventing the on / off control of transistor Qg1 from being disrupted by the forward voltage of this reverse current blocking diode Dg1.

[0080] Figure 5 is a waveform diagram showing the operation of each part of the semiconductor drive device equipped with the overcurrent protection unit 12 shown in Figure 4. Similar to Figure 3, at time t1, if an overcurrent occurs due to an arm short circuit with other connected arms after the semiconductor switching element 50 is turned on, the peak value Icp of the collector current Ic saturates, and the collector voltage Vce, which normally decreases, remains high. As a result, the base potential (input potential) VA1 of the first transistor Q1 rises above the reference potential VG0.

[0081] At time t2, the base potential (input potential) VA1 of the first transistor Q1 rises to 2Vf, that is, when equation (1) above is satisfied, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50. When the first transistor Q1 turns on, the potential of the judgment signal OCD decreases, and when it drops to a potential (VG1-Vf) lower than the positive power supply potential VG1 by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 turns on. As a result, the base potential of the third transistor Q3 also rises, and a voltage of Vf or higher is applied to the base, turning on the third transistor Q3. Then, a gate discharge current IA flows and the gate voltage Vge is reduced. At that time, the collector current Ic decreases to a value Ica corresponding to the reduced gate voltage Vge, and a surge voltage Vsa is generated in the collector voltage Vce.

[0082] Furthermore, when the third transistor Q3 is turned on, current flows from the connection wiring 15 to the gate voltage reduction unit 14. As a result, the voltage is divided by resistors R11 and R12, and a potential increased by the forward voltage of diode Dg1 is applied to the base of transistor Qg1. On the other hand, the emitter has a potential increased by the forward voltage of diodes Dg2 and Dg5, so a negative voltage equal to Vf is applied to the base of transistor Qg1, and transistor Qg1 is turned off. The resistance value R_OFFGI of the off-gate current adjustment unit 18 increases (RG3). As a result, the off-gate current when the gate drive unit 11 turns off the semiconductor switching element 50 flows through the resistor RG3 of the off-gate current adjustment unit 18.

[0083] As described above, if the transistor Qg1 provided by the off-gate current adjustment unit 18 is a PNP bipolar transistor, it can be turned off using the collector voltage of the second transistor Q2, that is, using the determination result of the first overcurrent determination unit 13. Also, if the transistor Qg1 provided by the off-gate current adjustment unit 18 is an NPN bipolar transistor, it can be turned off by the signal of the gate voltage reduction unit 14.

[0084] Embodiment 2. In Embodiment 1, a first transistor Q1 consisting of an NPN bipolar transistor was used, but in Embodiment 2, the first transistor Q1 is made of a PNP bipolar transistor. The second transistor Q2 is made of an NPN bipolar transistor, and the third transistor Q3 is made of a PNP bipolar transistor. Figure 6 shows the overcurrent protection unit 12A in the circuit configuration of the semiconductor drive device according to Embodiment 2. The semiconductor drive device 10 includes a gate drive unit 11 and an overcurrent protection unit 12A, but the detailed circuit configuration of the overcurrent protection unit 12A differs from that of Embodiment 1, while the other parts are the same as those of Embodiment 1.

[0085] The overcurrent protection unit 12A includes a first overcurrent determination unit 13A that uses the same detection signal SOC as in the first embodiment and outputs an overcurrent determination signal OCD when the detection signal SOC is input; a gate voltage reduction unit 14A that reduces the gate voltage Vge based on the determination signal OCD; and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50 when an overcurrent is detected by the first overcurrent determination unit 13A. The gate voltage reduction unit 14A also includes a drive circuit 141A that reduces the gate voltage Vge and an amplification circuit 142A that amplifies the output signal from the overcurrent determination unit 13A and drives the drive circuit 141A.

[0086] The first overcurrent detection unit 13A comprises resistors R1, R2, R3, and R4 connected in series, a clamp diode D1, and a capacitor C1. Furthermore, it includes a series circuit in which a first transistor Q1, which is made of a PNP bipolar transistor, resistors R5 and R6, and a reverse current prevention diode D3 are connected in series. Capacitor C2 is connected in parallel with resistor R6, and a protection diode D2 is provided between the base and emitter of the first transistor Q1. Furthermore, it includes resistors R14 and R15 connected in series, and a capacitor C4 connected in parallel with resistor R15.

[0087] In this case as well, the resistor R formed by the three resistors R1, R2, and R3, and the capacitor C1 constitute a low-pass filter (R, C1). Furthermore, the connection point P2 between resistor R (R1, R2, R3) and resistor R4 becomes the input to the detection signal SOC and is connected to the emitter of the first transistor Q1. The potential of the connection point P2, which is the emitter potential of the first transistor Q1 with respect to the emitter control terminal ES, is defined as the input potential VA2.

[0088] The emitter potential (input potential VA2) of the first transistor Q1 is given by the following equation: VA2 = Vce × R4 / (R1 + R2 + R3 + R4) Also, the base potential VB of the first transistor Q1 is the potential at the connection point between resistors R14 and R15, and is given by the following equation: VB = Vge × R15 / (R14 + R15)

[0089] In this embodiment as well, overcurrent is detected when the first transistor Q1 is turned on. The emitter potential (input potential VA2) when the first transistor Q1 is turned on is expressed by the following equation (3): VA2 = VB + Vf ... (3)

[0090] When the semiconductor switching element 50 is turned off, the emitter potential (input potential VA2) of the first transistor Q1 is immediately negatively biased by the action of the clamp diode D1. This suppresses false detection of overcurrent when the semiconductor switching element 50 is turned off. Furthermore, by negatively biasing the initial state of the capacitor C1 in the low-pass filter (R, C1), false detection of overcurrent can also be suppressed when the semiconductor switching element 50 is turned on.

[0091] Next, the amplification circuit 142A within the gate voltage reduction unit 14A is a circuit that amplifies the judgment signal OCD from the first overcurrent determination unit 13A, and comprises a series circuit in which a second transistor Q2, made of an NPN bipolar transistor, resistors R7 and R8, and a reverse current prevention diode D7 are connected in series. In addition, a capacitor C3 is connected in parallel with resistor R8, and a protection diode D4 is provided between the base and emitter of the second transistor Q2. The base of the second transistor Q2 is at the same potential as the judgment signal OCD. The drive circuit 141A within the gate voltage reduction unit 14A is a circuit that amplifies the output signal from the overcurrent determination unit 13A, and comprises a series circuit in which a third transistor Q3, made of a PNP bipolar transistor, resistor R10, and diode D6 are connected in series. In addition, a resistor R9 is provided between this series circuit and the base of the second transistor Q2, and a protection diode D5 is provided between the base and emitter of the third transistor Q3.

[0092] In this embodiment as well, similar to Embodiment 1, when the first transistor Q1 turns on and the overcurrent state of the semiconductor switching element 50 is determined, the second transistor Q2 turns on, and then the third transistor Q3 turns on. In this case as well, by appropriately setting the resistors R5 and R6 connected in series with the first transistor Q1, the second transistor Q2 turns on after the first transistor Q1 turns on. Also, by appropriately setting the resistors R7 and R8 connected in series with the second transistor Q2, the third transistor Q3 turns on after the second transistor Q2 turns on.

[0093] Then, by discharging the gate charge accumulated in the capacitance between the gate and emitter of the semiconductor switching element 50, a gate discharge current IA flows through the third transistor Q3, reducing the gate voltage Vge. This makes it possible to suppress overcurrent of the semiconductor switching element 50.

[0094] The off-gate current adjustment unit 18 is connected within a connection wiring 15 to which a parallel circuit consisting of a diode Dg4 and a resistor RG3 connected in parallel is connected to the gate terminal G of the semiconductor switching element 50. A series circuit consisting of a transistor Qg1, which is a PNP bipolar transistor, and a reverse current prevention diode Dg2 connected in series is connected in parallel to this parallel circuit. Furthermore, a series circuit consisting of a resistor R11 and a resistor R12 connected in series is connected in parallel to the series circuit consisting of the transistor Qg1 and the reverse current prevention diode Dg2. The base of the transistor Qg1 is connected to the midpoint of resistors R11 and R12, the reverse current prevention diode Dg1, and the output of the judgment signal OCD. In addition, a protection diode Dg3 is connected between the base and emitter of the transistor Qg1. The base of the transistor Qg1 is at the same potential as the judgment signal OCD.

[0095] Under normal conditions, the emitter potential (input potential) VA2 of the first transistor Q1, with reference to the emitter control terminal ES, is clamped to a potential (VG2 + Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2 when the semiconductor switching element 50 is in the off state. When the semiconductor switching element 50 is in the on state, the collector voltage Vce drops to a few volts, and the voltage VA2 divided by resistors R (R1, R2, R3) and resistor R4 becomes close to the reference potential VG0. The potential of the judgment signal OCD, i.e., the base potential of the second transistor Q2, is maintained at the reference potential VG0 regardless of the on / off state of the semiconductor switching element 50.

[0096] Furthermore, when the semiconductor switching element 50 is turned off, the gate drive unit 11 negatively biases the gate voltage Vge, causing the wiring of the gate terminal G to drop from positive potential to negative potential. Consequently, the negative voltage is divided by resistors R11 and R12, and the divided voltage is applied to the base of transistor Qg1. This voltage is pre-designed to exceed the threshold voltage Vf of transistor Qg1, causing transistor Qg1 to turn on. As a result, gate current flows from the gate terminal G of the semiconductor switching element 50 through diode Dg2 and transistor Qg1. It is sufficient for transistor Qg1 to be in the ON state when the switching is off, when the off-gate voltage is high.

[0097] When the emitter potential (input potential) VA2 of the first transistor Q1 rises to (VB + Vf), that is, when equation (3) above is satisfied, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50. When the first transistor Q1 turns on, the potential of the judgment signal OCD rises, and when it reaches a potential (VG0 + Vf) that is higher than the reference potential VG0 by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 turns on. As a result, the base potential of the third transistor Q3 also decreases, and a voltage of Vf or higher is applied to the base, turning on the third transistor Q3. Then, a gate discharge current IA flows and the gate voltage Vge is reduced. At that time, the collector current Ic decreases to a value Ica corresponding to the reduced gate voltage Vge, and a surge voltage Vsa is generated in the collector voltage Vce.

[0098] When the first transistor Q1 turns on and an overcurrent is detected in the semiconductor switching element 50, the potential of the judgment signal OCD rises. The base of transistor Qg1 rises from this potential to a potential that is lowered by the forward voltage of diode Dg1. On the other hand, the emitter of transistor Qg1 is at a potential that is lowered by the forward voltage of diode Dg2, and the base of transistor Qg1 is subjected to a reverse bias of Vf, so transistor Qg1 turns off.

[0099] In this embodiment, as in the first embodiment described above, the overcurrent protection unit 12A can detect and protect the semiconductor switching element 50 from overcurrent by utilizing the threshold voltage of the first transistor Q1 without requiring its own power supply. Furthermore, the clamp diode D1 and the low-pass filter (R, C1) suppress malfunctions due to noise, enabling overcurrent protection. As a result, even when the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are spaced apart, the overcurrent protection unit 12, which does not require a power supply, can be placed close to the semiconductor switching element 50, enabling highly reliable overcurrent protection. Moreover, by detecting the overcurrent of the semiconductor switching element 50 and reducing the off-gate current when the semiconductor switching element is turned off by the off-gate current adjustment unit 18, soft shutdown can be achieved.

[0100] Furthermore, the inclusion of a reverse current prevention diode D3 protects the first transistor Q1 and improves its noise immunity, thereby suppressing false detection of overcurrent.

[0101] Furthermore, in this embodiment, since a PNP bipolar transistor is used for the first transistor Q1 in the first overcurrent determination unit 13A, the input potential VA2 used for determination can be set to a higher level, thereby improving voltage noise immunity.

[0102] Embodiment 3. In Embodiments 1 and 2 described above, overcurrent was determined based on input potentials VA1 and VA2 obtained by attenuating the collector voltage Vce (detection signal SOC) of the semiconductor switching element 50 with a voltage divider resistor. However, this embodiment uses a different method. Figure 7 shows the overcurrent protection unit 12B in the circuit configuration of the semiconductor driving device according to Embodiment 3. The semiconductor driving device 10 includes a gate driving unit 11 and an overcurrent protection unit 12B. As shown in Figure 7, the overcurrent protection unit 12B includes a first overcurrent determination unit 13B that outputs an overcurrent determination signal OCD based on the detection signal SOC, similar to Embodiments 1 and 2 described above, a gate voltage reduction unit 14A that reduces the gate voltage Vge based on the determination signal OCD, and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50 when an overcurrent is detected by the first overcurrent determination unit 13B.

[0103] In this embodiment, the configuration is the same as in Embodiment 2, except that the detection signal SOC is connected to the first overcurrent determination unit 13B. In this case, a desatt method is used in which a constant current is passed to the collector sense terminal CS side of the semiconductor switching element 50 via the high-voltage diode D8 to determine the collector voltage Vce (detection signal SOC). The differences from Embodiment 2 will be described below. In the first overcurrent determination unit 13B, the constant current diode CRD, resistor R1, and high-voltage diode D8 are connected in series to the collector sense terminal CS. The constant current diode CRD is connected to the power line connected to the gate terminal G, and the connection point between the constant current diode CRD and resistor R1 is connected to the emitter of the first transistor Q1.

[0104] In this case, the low-pass filter (R, C1) is formed by resistor R1 alone. Furthermore, the connection point P2, which connects the constant current diode CRD to the emitter of the first transistor Q1, is used as the input to the detection signal SOC, and the potential of the connection point P2, which is the emitter potential of the first transistor Q1, is used as the input potential VA2.

[0105] When the semiconductor switching element 50 is ON, the constant current diode CRD acts to supply a constant current of several mA from the positive power supply potential VG1. In the normal state where the semiconductor switching element 50 is not current saturated, the collector voltage Vce drops to several volts, so the current in the constant current diode CRD flows to the collector sense terminal CS. At this time, the emitter potential (input potential VA2) of the first transistor Q1 drops to several volts, so the first transistor Q1 does not turn ON.

[0106] When the semiconductor switching element 50 becomes saturated and the collector voltage Vce rises, the current from the constant current diode CRD cannot flow to the collector sense terminal CS and instead flows to the resistor R4. As a result, the emitter potential (input potential) VA2 of the first transistor Q1 rises to (VB + Vf), that is, when equation (3) above is satisfied, the first transistor Q1 turns on. This allows the overcurrent of the semiconductor switching element 50 to be detected. The product of the constant current value of the constant current diode CRD and the resistance value of the resistor R4 is designed in advance to be greater than VB + Vf.

[0107] When the first transistor Q1 is turned on, the second transistor Q2 turns on, and then the third transistor Q3 turns on. Then the gate discharge current IA flows and the gate voltage Vge is reduced. Also, when the first transistor Q1 is turned on and an overcurrent is detected, the transistor Qg1 of the off-gate current adjustment unit 18 turns off, and the off-gate current that the gate drive unit 11 uses to turn off the semiconductor switching element 50 flows through RG3, adjusting the off-gate current to be reduced.

[0108] Furthermore, this third embodiment provides the same effects as the second embodiment described above. In addition, this embodiment allows for the detection of the collector voltage Vce at a lower level compared to embodiments 1 and 2, which detect the collector voltage Vce by attenuating it with a voltage divider resistor.

[0109] Embodiment 4. In each of Embodiments 1 to 3 described above, the collector voltage Vce of the semiconductor switching element 50 was detected from the collector sense terminal CS and used as the detection signal SOC. However, in this embodiment, a different detection signal SOC is used. Figure 8 is a diagram showing the schematic configuration of the semiconductor drive device according to Embodiment 4. In this Embodiment 4, the semiconductor switching element 50A is equipped with a current detection element on the emitter side through which a current reduced to, for example, 1 / several thousandths flows, and the reduced emitter current Icc flowing from the current detection terminal EE is used as the detection signal SOC.

[0110] As shown in Figure 8, the semiconductor drive unit 10C includes a gate drive unit 11 and an overcurrent protection unit 12C. The overcurrent protection unit 12C includes a first overcurrent determination unit 13C that outputs an overcurrent determination signal OCD based on the emitter current Iee (detection signal SOC), a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD, and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50 when an overcurrent is detected by the first overcurrent determination unit 13C. The gate drive unit 11, gate voltage reduction unit 14, and off-gate current adjustment unit 18 are the same as in the first embodiment described above. The first overcurrent determination unit 13C also has the same circuit configuration as the overcurrent determination unit 13 in the first embodiment, although it handles a different detection signal SOC.

[0111] Figure 9 is a waveform diagram showing the operation of each part of the semiconductor drive device according to Embodiment 4. In this case, the emitter current Iee, which becomes the detection signal SOC, is connected to the base of the first transistor Q1 and is input to the base. When an overcurrent occurs while the semiconductor switching element 50A is ON, the emitter current Iee (detection signal SOC) rises, and when it exceeds the set threshold IX, the first transistor Q1 turns ON. This detects the overcurrent of the semiconductor switching element 50. Except for using the emitter current Iee as the detection signal SOC, the operation waveforms of each part are the same as those shown in Figure 3 of Embodiment 1 above.

[0112] In this embodiment as well, the same effects as in Embodiment 1 can be obtained. Furthermore, although it is applicable only to semiconductor switching elements 50A equipped with a current detection element, it can detect overcurrents with higher accuracy because it detects the current value itself to determine overcurrent without requiring contact with the high-voltage section.

[0113] Embodiment 5. In this embodiment, a different detection signal SOC is used. Figure 10 is a diagram showing the schematic configuration of the semiconductor drive device according to Embodiment 5. In this Embodiment 5, the emitter voltage VEe between the emitter E, which is the low-voltage side main terminal of the semiconductor switching element 50B, and the emitter control terminal ES is used as the detection signal SOC. This utilizes the electromotive force (Le・dIc / dt) generated in the parasitic inductance Le on the emitter side.

[0114] As shown in Figure 10, the semiconductor drive unit 10D includes a gate drive unit 11 and an overcurrent protection unit 12D. The overcurrent protection unit 12D includes a first overcurrent determination unit 13D that outputs an overcurrent determination signal OCD based on the emitter voltage VEe (detection signal SOC), a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD, and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50 when an overcurrent is detected by the first overcurrent determination unit 13D. The gate drive unit 11, the gate voltage reduction unit 14, and the off-gate current adjustment unit 18 are the same as in the first embodiment described above.

[0115] Furthermore, the first overcurrent determination unit 13D has the same circuit configuration as the first overcurrent determination unit 13 in Embodiment 1, although it handles a different detection signal SOC. However, in Embodiment 1, the entire overcurrent protection unit 12 was configured based on the potential of the emitter control terminal ES, but in this embodiment, only the first overcurrent determination unit 13D within the overcurrent protection unit 12D is configured based on the potential of the emitter E, while the others are configured based on the potential of the emitter control terminal ES. That is, the emitter control terminal ES is connected to the high-voltage side of resistor R1, and the emitter voltage VEe (detection signal SOC) from emitter E is connected to the low-voltage side of resistor R4.

[0116] Figure 11 is a waveform diagram showing the operation of each part of the semiconductor drive device according to Embodiment 5. In this case, the emitter voltage VEe, which is the detection signal SOC, has a waveform similar to the derivative of the collector current Ic (dIc / dt). When an overcurrent occurs while the semiconductor switching element 50B is ON, the emitter voltage VEe (detection signal SOC) decreases, and when it decreases below the set threshold VX, the first transistor Q1 turns ON. This detects the overcurrent of the semiconductor switching element 50B. Except for using the emitter voltage VEe as the detection signal SOC, the operation waveforms of each part are the same as those shown in Figure 3 of Embodiment 1 above.

[0117] In this embodiment as well, the same effects as in Embodiment 1 can be obtained. Furthermore, by utilizing the electromotive force generated in the parasitic inductance Le on the emitter side, current information can be acquired at high speed and with high accuracy without the need for a current detection element, and overcurrent can be detected.

[0118] In the above embodiment, the emitter voltage VEe was compared with a threshold voltage VX which serves as the determination voltage. However, the voltage amplitude (Le・dIc / dt) of the emitter voltage VEe may also be integrated using an integration circuit to obtain information similar to the collector current Ic, and overcurrent may be determined from there.

[0119] Embodiment 6. In this embodiment, the signal obtained by detecting the rate of change of the current between the main terminals and converting it into a voltage is used as the detection signal SOC. Figure 12 is a diagram showing the schematic configuration of the semiconductor drive device according to Embodiment 6. As shown in Figure 12, a current-voltage conversion element CT is provided outside the emitter E, which is one of the main terminals of the semiconductor switching element 50C. The current-voltage conversion element CT detects the rate of change of the collector current Ic, which is the current between the main terminals, and outputs voltage information Vct (detection signal SOC). As an example of the current-voltage conversion element CT, there is a Rogowski coil formed on a printed circuit board that constitutes the overcurrent protection unit 12E.

[0120] As shown in Figure 12, the semiconductor drive unit 10E includes a gate drive unit 11 and an overcurrent protection unit 12E. The overcurrent protection unit 12E includes a first overcurrent determination unit 13E that outputs an overcurrent determination signal OCD based on voltage information Vct (detection signal SOC), a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD, and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50 when an overcurrent is detected by the first overcurrent determination unit 13E. The gate drive unit 11, gate voltage reduction unit 14, and off-gate current adjustment unit 18 are the same as in the first embodiment described above.

[0121] Furthermore, although the detection signal SOC handled by the first overcurrent determination unit 13E is different, the circuit configuration is the same as that of the first overcurrent determination unit 13 in Embodiment 1. Figure 13 is a waveform diagram of each part showing the operation of the semiconductor drive device according to Embodiment 6. In this case, the voltage information Vct, which becomes the detection signal SOC, has a waveform similar to the derivative of the collector current Ic (dIc / dt). When an overcurrent occurs while the semiconductor switching element 50C is ON, the voltage information Vct (detection signal SOC) rises, and when it exceeds the set threshold VXa, the first transistor Q1 turns ON. This detects the overcurrent of the semiconductor switching element 50C. Except for using the voltage information Vct as the detection signal SOC, the operation waveforms of each part are the same as those shown in Figure 3 of Embodiment 1.

[0122] In this embodiment as well, the same effects as in Embodiment 1 can be obtained. Furthermore, by mounting the overcurrent protection unit 12E on a printed circuit board and utilizing a Rogowski coil (current-voltage conversion element CT) formed on the printed circuit board, non-contact, high-precision overcurrent detection can be achieved.

[0123] Embodiment 7. In Embodiment 1, a low-pass filter (R, C1) was provided at the input of the detection signal SOC. In this embodiment, a semiconductor drive device is shown that includes a first low-pass filter and a second low-pass filter as the low-pass filter. Figure 14 is a diagram showing the schematic configuration of the semiconductor drive device according to Embodiment 7. As shown in Figure 14, the semiconductor drive device 10F includes a gate drive unit 11 and an overcurrent protection unit 12F. The overcurrent protection unit 12F includes a first overcurrent determination unit 13F that determines the overcurrent flowing through the semiconductor switching element 50, a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined, and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50 when an overcurrent is detected by the first overcurrent determination unit 13F. The gate drive unit 11, the gate voltage reduction unit 14, and the off-gate current adjustment unit 18 are the same as in Embodiment 1.

[0124] The first overcurrent determination unit 13F comprises a first transistor Q1, a clamp diode D1, a reverse current prevention diode D3, a resistor R, capacitors C1a and C1b, and a diode DL. In this case, a first low-pass filter (R, C1a) is formed by the resistor R and capacitor C1a, and a second low-pass filter (R, C1b) is formed by the resistor R and capacitor C1b. The detection signal SOC, which is the collector voltage Vce that is the voltage between the main terminals of the semiconductor switching element 50, is input to the first transistor Q1 via the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b), and outputs an overcurrent determination signal OCD.

[0125] Figure 15 shows the overcurrent protection unit 12F of the semiconductor drive device according to Embodiment 7. As shown in Figure 15, in the first overcurrent determination unit 13F, the resistor R formed by three resistors R1, R2, and R3, and capacitors C1a and C1b constitute the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b). In addition, the connection point P1 between resistor R (R1, R2, R3) and resistor R4 becomes the input part of the detection signal SOC and is connected to the base of the first transistor Q1. The potential of the connection point P1, which is the base potential of the first transistor Q1 with reference to the emitter control terminal ES, is set as the input potential VA1.

[0126] A clamp diode D1, which clamps to the gate potential (Vge), has its anode connected to capacitor C1 of the first low-pass filter (R, C1a). This connection point is connected to connection point P1 and the base of the first transistor Q1, and is also connected to capacitor C1b of the second low-pass filter (R, C1b) via diode DL. The detection signal SOC is voltage-divided by resistors R1 to R4 and input to the base of the first transistor Q1 via the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b), which are composed of the voltage-dividing resistors R(R1, R2, R3) and the two capacitors C1a and C1b.

[0127] The base of the first transistor Q1 is clamped to the negative power supply potential VG2 by the clamp diode D1 when the semiconductor switching element 50 is in the off state. The first low-pass filter (R, C1a) is clamped to the gate potential (Vge) via the clamp diode D1. On the other hand, the second low-pass filter (R, C1b) is not clamped to the gate potential (Vge) due to the action of diode DL.

[0128] Diode DL is provided to prevent the second low-pass filter (R, C1b) from being clamped to the negative power supply potential VG2, but its forward voltage becomes the offset voltage of the second low-pass filter (R, C1b). This offset voltage reduces the noise immunity of the first transistor Q1. For this reason, a diode with a small forward voltage, such as a Schottky barrier diode, is used to suppress the offset voltage. Also, as shown in Figure 15, the above offset voltage can be eliminated by providing a reverse current blocking diode D3 on the emitter side of the first transistor Q1.

[0129] Furthermore, the capacitor C1a of the first low-pass filter (R, C1a) is configured to have a small capacitance, while the capacitor C1b of the second low-pass filter (R, C1b) is configured to have a large capacitance. When the semiconductor switching element 50 is in the off state, the capacitor C1a of the first low-pass filter (R, C1a) is negatively biased. When the semiconductor switching element 50 turns on and recovers from the negative bias state, if the capacitance of capacitor C1a is large, it will take time to recover. Here, by reducing the capacitance of capacitor C1a, capacitor C1a can recover quickly from the negative bias, and overcurrent detection can be achieved within a predetermined delay time. The first low-pass filter (R, C1a) functions similarly to the low-pass filter (R, C1) shown in Embodiment 1 above, suppressing false detection of overcurrent.

[0130] If the second low-pass filter (R, C1b) is absent, that is, in the same case as in Embodiment 1 above, when the semiconductor switching element 50 is in the ON state, the immunity to current noise will be reduced if only the first low-pass filter (R, C1a) with a small capacitance C1a is present. In this case, because a second low-pass filter (R, C1b) with a large capacitance C1b is provided, false detection of overcurrent due to current noise can be suppressed even when the semiconductor switching element 50 is in the ON state.

[0131] Figure 16 is a waveform diagram showing the operation of various parts of the semiconductor drive device according to Embodiment 7. The operating waveforms, other than the base potential (input potential) VA1 of the first transistor Q1 with reference to the emitter control terminal ES, are the same as those shown in Figure 3 of Embodiment 1. Note that the VA1 waveform in Embodiment 1 is shown as a dotted line.

[0132] Under normal conditions prior to time t1, the base potential (input potential) VA1 of the first transistor Q1 is clamped to a potential (VG2 + Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2 when the semiconductor switching element 50 is in the off state. When the semiconductor switching element 50 is in the on state, the collector voltage Vce drops to a few volts, and the voltage VA1 divided by resistors R (R1, R2, R3) and resistor R4 becomes close to the reference potential VG0. In this case, because a small capacitance capacitor C1a is used in the first low-pass filter (R, C1a) clamped by the clamp diode D1, the period during which the base potential (input potential) VA1 recovers from negative bias when the semiconductor switching element 50 transitions from the off state to the on state is shortened.

[0133] At time t1, if an overcurrent occurs after the semiconductor switching element 50 is turned on, such as due to an arm short circuit with other connected arms, the peak value Icp of the collector current Ic will saturate, and the collector voltage Vce, which normally decreases, will remain high. Here too, after the semiconductor switching element 50 is turned on, the base potential (input potential) VA1 quickly recovers from the negative bias and rises even higher than the reference potential VG0.

[0134] In this embodiment, as in the first embodiment described above, the overcurrent protection unit 12F can detect and protect the semiconductor switching element 50 from overcurrent by utilizing the threshold voltage of the first transistor Q1 without requiring its own power supply. Furthermore, the clamp diode D1 and the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b) work together to suppress malfunctions due to noise and provide overcurrent protection. As a result, even when the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are spaced apart, the overcurrent protection unit 12, which does not require a power supply, can be placed close to the semiconductor switching element 50, enabling highly reliable overcurrent protection. Moreover, by detecting the overcurrent of the semiconductor switching element 50 and reducing the off-gate current when the semiconductor switching element is turned off by the off-gate current adjustment unit 18, soft shutdown can be achieved.

[0135] Furthermore, the first low-pass filter (R, C1a) is configured to clamp to the gate potential (Vge), while the second low-pass filter (R, C1b) is configured not to clamp to the gate potential (Vge). This allows the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b) to be used individually in the off and on states of the semiconductor switching element 50, effectively eliminating the effects of noise. Additionally, the capacitor C1a of the first low-pass filter (R, C1a) is configured to be small in capacitance, while the capacitor C1b of the second low-pass filter (R, C1b) is configured to be large in capacitance. This shortens the period during which the base potential (input potential) VA1 of the first transistor Q1 recovers from negative bias, enabling rapid overcurrent detection and improving noise immunity.

[0136] In embodiments 1 to 7 described above, an example was shown in which the overcurrent protection unit is equipped with an off-gate current adjustment unit. When the overcurrent protection unit is mounted on a single substrate, the overcurrent protection unit does not have a power supply and can adjust the off-gate resistance and perform soft shutdown based on the signal from the first overcurrent determination unit. The substrate on which this overcurrent protection unit is mounted corresponds to a semiconductor switching element, and when there are multiple instances of semiconductor switching elements and overcurrent protection units mounted in parallel on a single substrate, that is, when configuring a power conversion device equipped with multiple semiconductor switching elements, the substrate can be used as a common substrate on which the overcurrent protection unit is mounted. Furthermore, multiple semiconductor switching elements and the overcurrent protection unit can be controlled with a single gate drive unit. Therefore, since the substrate can be standardized, costs can be reduced, there is no need to adjust the substrate constants for each substrate, and the performance of the semiconductor switching elements and, consequently, the power conversion device can be improved.

[0137] Embodiment 8. While Embodiments 1 to 7 described above showed an example in which the overcurrent protection unit is equipped with an off-gate current adjustment unit, this embodiment describes an example in which the gate drive unit is equipped with an off-gate current adjustment unit. Figure 17 is a diagram showing the schematic configuration of a semiconductor drive device according to Embodiment 8. As shown in Figure 17, the semiconductor drive device 10G includes a gate drive unit 11G and an overcurrent protection unit 12G. The overcurrent protection unit 12G includes a first overcurrent determination unit 13 that determines the overcurrent flowing through the semiconductor switching element 50, and a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined. The gate drive unit 11G, similar to Embodiments 1 to 7 described above, includes an output stage circuit, a control unit 16 that controls the output stage circuit, and a protection operation detection unit 19 that detects a decrease in the gate voltage Vge after overcurrent detection and generates a signal GSD to turn off the semiconductor switching element 50. An off-gate current adjustment unit 18G is provided in the output stage circuit of the gate drive unit 11G.

[0138] The off-gate current adjustment unit 18G includes an N-type MOSFET MG3 connected between the N-type MOSFET MG2 and the gate resistor RG2, and a resistor RG4 connected in parallel to the series circuit of the gate resistor RG2 and the N-type MOSFET MG3. The resistance value of resistor RG4 is set to be greater than the resistance value of the gate resistor RG2 (RG4 > RG2).

[0139] Under normal conditions, when the semiconductor switching element 50 is turned on, the control unit 16 turns on the P-type MOSFET MG1 based on the command signal SIN, and an on-gate current flows from the gate resistor RG1 towards the gate terminal G. Under normal conditions, when the semiconductor switching element 50 is turned off, the control unit 16 turns on the N-type MOSFET MG2 based on the command signal SIN, and an off-gate current flows from the gate terminal G through the gate resistor RG2 towards the gate terminal G. Under normal conditions, the N-type MOSFET MG3 is always on.

[0140] When the first transistor Q1 is turned on, the determination signal OCD changes, and an overcurrent in the semiconductor switching element 50 is determined. That is, an overcurrent is detected by the first overcurrent determination unit 13. The gate voltage reduction unit 14 receives the overcurrent determination signal OCD and operates to reduce the gate voltage Vge applied to the gate terminal G to a level lower than the voltage of the positive power supply PG1 (VG1). At this time, the gate drive unit 11G detects that the gate voltage reduction unit 14 has reduced the gate voltage Vge using the protection operation detection unit 19, and generates a signal GSD, which is a protection operation detection signal, and transmits it to the control unit 16. Here, the N-type MOSFET MG3 is pre-set so that its gate changes from high to low upon input of the signal GSD. Therefore, the N-type MOSFET MG3 is turned off upon input of the signal GSD.

[0141] When the control unit 16 receives the signal GSD, it keeps the semiconductor switching element 50 in the off state for a predetermined period, regardless of the state of the command signal SIN. At this time, the N-type MOSFET MG3 is off, so when the N-type MOSFET MG2 is turned on, an off-gate current flows from the gate terminal G towards the resistor RG4. As described above, the resistance value of resistor RG4 is greater than the resistance of gate resistor RG2 through which the off-gate current flows under normal conditions, so the off-gate current is reduced and soft shutdown is performed.

[0142] Next, the circuit configuration of the overcurrent protection unit 12G will be described. Figure 18 shows the circuit configuration of the overcurrent protection unit 12G. It differs from the overcurrent protection unit 12 shown in Figures 2 and 4 of Embodiment 1 only in that it does not have an off-gate current adjustment unit 18. The other configurations and operations are the same, so their explanation will be omitted.

[0143] Figure 19 is a waveform diagram showing the operation of each part of the semiconductor drive device according to Embodiment 1. The details of the overcurrent protection operation by the semiconductor drive device 10G will be explained below based on Figures 17 and 18. Under normal conditions prior to time t1, the gate voltage Vge is output in accordance with the command signal SIN transmitted from the higher-level control device, and the collector current Ic of the semiconductor switching element 50 and the collector voltage Vce, which becomes the detection signal SOC, also have waveforms corresponding to the command signal SIN. The base potential (input potential) VA1 of the first transistor Q1 with reference to the emitter control terminal ES is clamped to a potential (VG2 + Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2 when the semiconductor switching element 50 is in the off state. When the semiconductor switching element 50 is in the on state, the collector voltage Vce drops to several volts, and the voltage VA1 divided by resistors R (R1, R2, R3) and resistor R4 becomes close to the reference potential VG0.

[0144] The potential of the determination signal OCD, that is, the base potential of the second transistor Q2, is the same as the gate potential (positive power supply potential VG1) when the semiconductor switching element 50 is ON, and is lowered to the negative power supply potential VG2 when it is OFF.

[0145] At time t1, if an overcurrent occurs after the semiconductor switching element 50 is turned on, due to an arm short circuit with other connected arms, the peak value Icp of the collector current Ic will saturate, and the collector voltage Vce, which normally decreases, will remain high. As a result, the base potential (input potential) VA1 of the first transistor Q1 will rise above the reference potential VG0.

[0146] At time t2, the base potential (input potential) VA1 of the first transistor Q1 rises to 2Vf, that is, when equation (1) above is satisfied, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50. When the first transistor Q1 turns on, the potential of the judgment signal OCD decreases, and when it drops to a potential (VG1-Vf) lower than the positive power supply potential VG1 by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 turns on. As a result, the base potential of the third transistor Q3 also rises, and a voltage of Vf or higher is applied to the base, turning on the third transistor Q3. Then, a gate discharge current IA flows and the gate voltage Vge is reduced. At that time, the collector current Ic decreases to a value Ica corresponding to the reduced gate voltage Vge, and a surge voltage Vsa is generated in the collector voltage Vce.

[0147] At time t3, the protection operation detection unit 19 detects a decrease in the gate voltage Vge and generates the signal GSD. Between time t3 and time t4, the control unit 16 performs a current interruption operation on the semiconductor switching element 50, turning it off. The signal GSD from the protection operation detection unit 19 is input to the control unit 16 and also to the gate of the N-type MOSFET MG3, turning the N-type MOSFET MG3 off. The off-gate current flows from the gate terminal G towards the resistor RG4. When the control unit 16 performs the interruption operation on the semiconductor switching element 50, the off-gate current flows through the resistor RG4, which has a high resistance, so the off-gate current is reduced compared to normal operation, and soft interruption is performed.

[0148] During this current interruption operation, a surge voltage Vsb is generated in the collector voltage Vce. As mentioned above, it is desirable to set the resistor R10 to satisfy equation (2) above so that the surge voltage Vsb is approximately the same as the surge voltage Vsa that occurs beforehand. Furthermore, since the off-gate current is also reduced when the gate voltage is reduced, and soft interruption is performed, even if the power converter equipped with the semiconductor switching element 50 driven by this semiconductor drive device 10G has a smoothing capacitor and a snubber capacitor, resonance between capacitors is suppressed when the semiconductor switching element is interrupted, and a highly reliable semiconductor drive device that can implement overcurrent protection can be provided.

[0149] At time t5, after a delay time Tf has elapsed since the generation of signal GSD, the command signal SIN from the higher-level control device remains in the OFF state, and the abnormal signal FAIL is generated.

[0150] In this embodiment as well, similar to Embodiment 1, the overcurrent protection unit 12G can detect and protect the semiconductor switching element 50 from overcurrent by utilizing the threshold voltage of the first transistor Q1 without requiring its own power supply. Furthermore, the clamp diode D1 and the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b) work together to suppress malfunctions due to noise and provide overcurrent protection. As a result, even when the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are spaced apart, the overcurrent protection unit 12, which does not require a power supply, can be placed close to the semiconductor switching element 50, enabling highly reliable overcurrent protection.

[0151] Furthermore, by providing an off-gate current adjustment unit 18G in the gate drive unit 11G, and by reducing the off-gate current with the signal GSD generated when the protection operation detection unit 19 detects a decrease in the gate voltage Vge, the off-gate current is reduced when the gate voltage is reduced, enabling soft shutdown. Therefore, even if the power conversion device equipped with the semiconductor switching element 50 driven by this semiconductor drive device 10G has a smoothing capacitor and a snubber capacitor, resonance between the capacitors is suppressed when the semiconductor switching element is shut off, and a highly reliable semiconductor drive device 10G that can perform overcurrent protection can be provided. In addition, when using a common substrate in which the semiconductor switching element and the overcurrent protection unit are mounted on a single substrate, the size of the substrate is limited, and if the substrate area is small, the constraint of the substrate size can be met by providing the off-gate current adjustment unit 18G in the gate drive unit 11G, as in this embodiment.

[0152] In addition, the circuit configuration of the overcurrent protection unit 12G shown in Figure 18 differs from that of the overcurrent protection unit 12 shown in Figures 2 and 4 of Embodiment 1 only in that it does not include an off-gate current adjustment unit 18, but it is not limited to this. The overcurrent protection unit 12G according to this embodiment may be the overcurrent protection unit 12A shown in Figure 6 of Embodiment 2 with the off-gate current adjustment unit 18 removed, the overcurrent protection unit 12B shown in Figure 7 of Embodiment 3 with the off-gate current adjustment unit 18 removed, or the overcurrent protection unit 12F shown in Figures 14 and 15 of Embodiment 7, which includes a first overcurrent determination unit 13F and excludes the off-gate current adjustment unit 18.

[0153] Furthermore, the circuit configuration of the overcurrent protection unit 12G in this embodiment may be the same as the semiconductor switching element 50A shown in Figure 8 of Embodiment 4, with the off-gate current adjustment unit 18 removed from the overcurrent protection unit 12C in Figure 8; or the semiconductor switching element 50 may be the same as the semiconductor switching element 50B shown in Figure 10 of Embodiment 5, with the off-gate current adjustment unit 18 removed from the overcurrent protection unit 12D in Figure 10; or the semiconductor switching element 50 may be the same as the semiconductor switching element 50C shown in Figure 12 of Embodiment 6, with the off-gate current adjustment unit 18 removed from the overcurrent protection unit 12E in Figure 12.

[0154] Embodiment 9. Hereinafter, a power conversion device according to Embodiment 9 will be described with reference to the figures. Figure 20 is a block diagram showing the schematic configuration of a power conversion device 1 according to Embodiment 9. In Figure 20, the power conversion device 1 includes a power converter 20 equipped with semiconductor switching elements that converts power from a DC power supply (not shown) to supply power to a load 70, and a semiconductor drive device 10H that drives the semiconductor switching elements of the power converter 20. The semiconductor drive device 10H includes a gate drive unit 11H which includes a second overcurrent determination unit 17, a control unit 16 that receives a command signal SIN transmitted from a higher-level control device (not shown) and generates an on / off command signal for the semiconductor switching elements based on the signal from the second overcurrent determination unit 17, and an output stage circuit 110 that applies voltage to the semiconductor switching elements and drives them based on the on / off command signal input via an isolated communication unit ICV, and an overcurrent protection unit 12 that detects and protects against overcurrent of the semiconductor switching elements. Next, the detailed circuit configuration will be described using Figures 21 and 22.

[0155] Figure 21 shows the circuit configuration of the main part of the power converter according to Embodiment 9, and Figure 22 shows the circuit configuration of the overcurrent protection unit 12. The power converter 20 includes an arm section in which semiconductor switching elements 50a and 50b are connected in series. An on / off command signal GDOa output from the control unit 16 is input to the output stage circuit 110a via an isolated communication unit ICVa at the control terminal (hereinafter referred to as the gate terminal) Ga of the semiconductor switching element 50a of the upper arm, and a voltage based on this on / off command signal GDOa is applied. In addition, an overcurrent protection unit 12a is provided that detects the overcurrent flowing through the semiconductor switching element 50a and reduces the gate voltage if it is determined that an overcurrent is flowing.

[0156] Similarly, the on / off command signal GDOb output from the control unit 16 is input to the output stage circuit 110b via the isolated communication unit ICVb at the gate terminal Gb of the semiconductor switching element 50b of the lower arm, and a voltage based on this on / off command signal GDOb is applied. In addition, an overcurrent protection unit 12b is provided to detect overcurrent flowing through the semiconductor switching element 50b and reduce the gate voltage if it is determined that an overcurrent is flowing.

[0157] Thus, the functional units related to the control of the upper and lower arms and the semiconductor switching elements 50a and 50b are equivalent, and in the following description, they may be described with the designation a or b respectively, or the description of one of them may be omitted. Also, the functional units may be described collectively without designating them a or b. Furthermore, Figure 21 shows an example in which the leg circuit composed of the upper and lower arms is one, i.e., an example of a single-phase power converter 20, but for example, it may be a three-phase power converter 20 in which three leg circuits are connected in parallel. The power converter 20 is equipped with at least one leg circuit.

[0158] The semiconductor drive device 10H controls the conduction / non-conductivity state between the collector C and emitter E, which are the main terminals of the semiconductor switching element 50, by a gate voltage Vge applied between the gate terminal G and the reference terminal (hereinafter referred to as the emitter control terminal) ES. In this case, as described in Embodiment 1 above, an IGBT is shown as an example of the semiconductor switching element 50, but it can also be applied to other semiconductor switching elements such as MOSFETs that have control terminals.

[0159] The overcurrent protection unit 12 is positioned immediately adjacent to or above the semiconductor switching element 50, and the gate drive unit 11H and the overcurrent protection unit 12 are connected by a two-wire connection cable 15. As will be described in detail later, the overcurrent protection unit 12 includes a first overcurrent determination unit 13, a gate voltage reduction unit 14, and an off-gate current adjustment unit 18. The output stage circuit 110 includes an output stage circuit composed of a positive power supply PG1 and a negative power supply PG2, a P-type MOSFET MG1 and an N-type MOSFET MG2, and gate resistors RG1 and RG2, and is connected to a control unit 16 that controls this output stage circuit via an isolated communication unit ICV. The emitter control terminal ES of the semiconductor switching element 50 is connected to the reference potential VG0 at the connection point between the positive power supply PG1 and the negative power supply PG2.

[0160] As described above, the control unit 16 receives the command signal SIN transmitted from the higher-level control unit (not shown) and controls the output stage circuit 110 via the isolated communication unit ICV based on the determination signal OCD1 from the second overcurrent determination unit 17. In addition to the determination signal OCD1, the control unit 16 may also control the output stage circuit by logically synthesizing various abnormality detection signals such as overtemperature or power supply failure. The operation of the second overcurrent determination unit 17 will be described later.

[0161] The isolated communication unit ICV is configured to electrically isolate the input and output and transmit instruction signals from the input to the output. The on / off command signal GDO generated by the control unit 16 is input to it and output to the gates of the P-type MOSFET MG1 and N-type MOSFET MG2 of the output stage circuit 110. The isolated communication unit ICV is configured, for example, by a photocoupler, but it may be configured by means other than a photocoupler, as long as it can electrically isolate the input and output and transmit instruction signals from the input to the output.

[0162] Furthermore, although an example is shown in which the output stage circuit 110 outputs a positive power supply potential VG1 or a negative power supply potential VG2, a configuration without a negative power supply PG2 is also possible, i.e., a configuration in which the negative power supply potential VG2 is equal to the reference potential VG0. Also, in this case, a constant voltage drive is shown in which a P-type MOSFET MG1 and an N-type MOSFET MG2 are used as the output stage buffer of the output stage circuit 110, and the switching speed is adjusted by gate resistors RG1 and RG2, but it is not limited to this. The output stage circuit 110 is also the same as the configuration described in Embodiment 1 above.

[0163] The overcurrent protection unit 12 includes a first overcurrent determination unit 13 that determines the overcurrent flowing through the semiconductor switching element 50, a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined, and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50. Although Figure 21 shows a simplified view of the structure of the overcurrent protection unit 12b connected to the lower arm, as described above, the structure of the overcurrent protection unit 12a connected to the upper arm is the same as that of the overcurrent protection unit 12b. The first overcurrent determination unit 13b of the overcurrent protection unit 12b connected to the lower arm uses the determination signal OCD2b, and the first overcurrent determination unit 13a (not shown) of the overcurrent protection unit 12a connected to the upper arm uses the determination signal OCD2a.

[0164] Figure 22 is a circuit diagram showing the details of the overcurrent protection unit 12 according to Embodiment 9. As described above, if the overcurrent protection unit 12 is for the upper arm, the reference numeral 'a' is used for each part in Figure 22, and if it is for the lower arm, the reference numeral 'b' is used for each part. As shown in Figure 22, the overcurrent protection unit 12 includes a first overcurrent determination unit 13 that receives a detection signal SOC and outputs an overcurrent determination signal OCD2, and a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD2. The gate voltage reduction unit 14 also includes a drive circuit 141 that reduces the gate voltage Vge, and an amplification circuit 142 that amplifies the output signal from the first overcurrent determination unit 13 and drives the drive circuit 141. Note that the details of the circuit configuration and the basic operation of the overcurrent protection unit 12 differ only from those in Figure 3 of Embodiment 1 described above in that it does not include an off-gate current adjustment unit 18, so a detailed explanation is omitted here.

[0165] Next, the second overcurrent determination unit 17 will be explained using Figure 21. The second overcurrent determination unit 17 includes a first comparator VHD that determines whether the potential of the output terminal Ea of the power converter 20, which consists of upper and lower arms, is near the positive potential, and a second comparator VLD that determines whether the potential of the output terminal Ea is near the negative potential. Furthermore, it includes a logic synthesis unit 171 that detects overcurrents in the semiconductor switching elements 50a and 50b based on the outputs of the first comparator VHD and the second comparator VLD and on / off command signals GDOa and GDOb that control the on / off states of the semiconductor switching elements 50a and 50b, and outputs a determination signal OCD1 to the control unit 16. A detailed explanation follows below.

[0166] At the negative input terminal of the first comparator VHD, the potential of the connection point P0 is divided by resistors R173, R174, R175 and resistors R177, R178 and input as a reference voltage, while at the positive input terminal, the potential of the emitter control terminal ESa of the semiconductor switching element 50a is divided by resistors R170, R171, R172 and resistor R176 and input. At the positive input terminal of the second comparator VLD, the potential of the connection point P0 is divided by resistors R173, R174, R175, R178 and resistor R177 and input as a reference voltage, while at the negative input terminal, the potential of the emitter control terminal ESa of the semiconductor switching element 50a is divided by resistors R170, R171, R172 and resistor R176 and input.

[0167] Although the potential of the emitter control terminal ESa of the semiconductor switching element 50a is strictly different from the potential of the output terminal Ea of the power converter 20, they are equivalent in the steady state after the switching of the semiconductor switching element 50a is complete. Therefore, in this explanation, we will treat them as equivalent, assuming that state. During the period when the semiconductor switching element 50a of the upper arm is ON, the potential of the output terminal Ea is the positive electrode potential of the DC power supply (not shown), and during the period when the semiconductor switching element 50b of the lower arm is ON, the potential of the output terminal Ea is the negative electrode potential of the DC power supply (not shown). Therefore, the potential of the emitter control terminal ESa or the potential of the output terminal Ea of the power converter 20 corresponds to the output potential of the REG circuit.

[0168] Furthermore, the wiring to which connection point P0 is connected has one end connected to the positive terminal of a DC power supply (not shown) and the other end connected to the positive terminal of the upper arm. The potential of connection point P0 is the power supply potential and corresponds to the positive-negative voltage of the leg circuit consisting of the upper and lower arms. Therefore, by generating the reference voltages of the first comparator VHD and the second comparator VLD from the main circuit power supply voltage, the robustness of the voltage determination accuracy against fluctuations in the main circuit power supply voltage is improved.

[0169] Here, resistors R170, R171, R172 and capacitor C170 constitute the low-pass filter LF1. Bypass capacitors for stabilizing the reference voltage input to the negative input terminal of the first comparator VHD and the positive input terminal of the second comparator VLD are omitted.

[0170] The first comparator VHD and the second comparator VLD are composed of window comparators. The first comparator VHD compares the reference voltage with the divided potential of the emitter control terminal ESa, and outputs high (H) if it is within the set range. In other words, it is determined that the potential of the emitter control terminal ESa is near the positive potential. Similarly, the second comparator VLD compares the reference voltage with the divided potential of the emitter control terminal ESa, and outputs high (H) if it is within the set range. In other words, it is determined that the potential of the emitter control terminal ESa is near the negative potential. Note that the potential of the emitter control terminal ESa does not have to be the same as the power supply potential; if it is within a certain range, it may be considered to be the power supply potential. Here, since it can be considered to be that potential or near that potential if it is within a preset range relative to the power supply potential, the term "nearby" is used. The set value of the window comparator is set to a value that can be considered to be near that potential.

[0171] The outputs of the first comparator VHD and the second comparator VLD are input to the logic synthesis unit 171 and are logically processed with the input on / off command signals GDOa and GDOb. Note that the on / off command signal GDOa for the upper arm is output almost inverted from the on / off command signal GDOb. Under normal conditions, when the on / off command signal GDOa is output (high: H), the semiconductor switching element 50a of the upper arm is on, and the potential of the emitter control terminal ESa is near the positive potential of the DC power supply (not shown), so the output from the first comparator VHD is high. In this case, the logic synthesis unit 171 outputs a low (L) judgment signal OCD1.

[0172] Similarly, under normal conditions, when the on / off command signal GDOb is output (high: H), the semiconductor switching element 50b of the lower arm is on, and the potential of the emitter control terminal ESa is near the negative potential of the DC power supply (not shown), so the output from the second comparator VLD is high. In this case, the logic synthesis unit 171 outputs a low (L) judgment signal OCD1.

[0173] If any other condition persists for a period longer than the preset time, it is determined that an overcurrent has flowed through one of the arms, and the logic synthesis unit 171 outputs a determination signal OCD1 high (H) to the control unit 16. Note that during the dead time period and voltage transition period when the semiconductor switching elements 50a and 50b switch, the on / off command signals GDOa and GDOb, the output of the first comparator VHD, and the output of the second comparator VLD will be in a different state than the normal state described above. In order to avoid misdetecting this state as an overcurrent state, it is determined whether an overcurrent has flowed based on whether the condition persists for a preset time longer than the preset time.

[0174] When the control unit 16 receives a high (H) judgment signal OCD1, it does not output on / off command signals GDOa and GDOb and stops the operation of the power converter 20. At this time, that is, when it is determined that an overcurrent has flowed through the arm, the judgment signal OCD2 turns on the first transistor Q1 and the second transistor Q2, causing the collector potential of the second transistor Q2 to rise to the positive power supply potential VG1 and the transistor Qg1 to turn off, so the resistance value R_OFFGI of the off-gate current adjustment unit 18 increases (RG3). This is because the off-gate current when the control unit 16 turns off the semiconductor switching element 50b mainly flows through the resistor RG3 of the off-gate current adjustment unit 18. Therefore, the power converter 20 is soft-shut down.

[0175] Figure 23 is a waveform diagram showing the operation of each part of the power converter 1 according to Embodiment 9. The details of the overcurrent protection operation of the power converter 1 will be explained below based on Figures 21, 22, and 23. Here, we will explain using an example where a failure occurs in the upper arm, but the example where a failure occurs in the lower arm can be explained similarly and will be omitted. In the normal state before time t0, the lower arm outputs a gate voltage Vgeb in accordance with the on / off command signal GDOb generated by the command signal SIN transmitted from the higher control device, and the collector current Icb of the semiconductor switching element 50b and the collector voltage Vceb which becomes the detection signal SOCb also have waveforms corresponding to the on / off command signal GDOb. The base potential (input potential) VA1b of the first transistor Q1b with reference to the emitter control terminal ESb is clamped to a potential (VG2b + Vf) obtained by adding the forward voltage Vf of the clamp diode D1b to the negative power supply potential VG2b when the semiconductor switching element 50b is in the off state. Furthermore, when the semiconductor switching element 50b is ON, the collector voltage Vceb drops to a few volts, and the voltage VA1b, which is divided by resistors Rb (R1b, R2b, R3b) and resistor R4b, becomes close to the reference potential VG0b.

[0176] The potential of the determination signal OCD2b, i.e., the base potential of the second transistor Q2b, is the same as the gate potential (positive power supply potential VG1b) when the semiconductor switching element 50b is ON, and is lowered to the negative power supply potential VG2b when it is OFF. Furthermore, since the ON / OFF command signal GDOa for the upper arm is almost inverted from the ON / OFF command signal GDOb, the collector voltage Vcea, which becomes the detection signal SOCa for the semiconductor switching element 50a of the upper arm, also has a waveform that is almost inverted from the collector voltage Vceb of the lower arm.

[0177] Under normal conditions, when the semiconductor switching element 50b is ON, the resistance of resistor RG3 is sufficiently large, so current flows mainly through diode Dg4, and when the semiconductor switching element 50b is OFF, current flows through transistor Qg1, so the resistance value R_OFFGI of the off-gate current adjustment unit 18 is small. Under normal conditions, transistor Qg1 of the off-gate current adjustment unit 18 is ON when the semiconductor switching element 50b is OFF, and is ON or OFF depending on the base potential of transistor Qg1 when the semiconductor switching element 50b is ON. Therefore, in Figure 23, under normal conditions before time t0, transistor Qg1 is shown as ON when the semiconductor switching element 50b is ON, indicated by a dotted line.

[0178] The output waveform of the second comparator VLD corresponds to the on / off command signal GDOb for the lower arm, while the output waveform of the first comparator VHD is inverted from that of the on / off command signal GDOb for the lower arm. That is, when the on / off command signal GDOb for the lower arm is high, the output waveform of the second comparator VLD is high, and the output waveform of the first comparator VHD is low. When the on / off command signal GDOb for the lower arm is low, the output waveform of the second comparator VLD is low, and the output waveform of the first comparator VHD is high. Note that in Figure 23, because the on / off duty cycle of the semiconductor switching element is not 50%, the output waveforms of the first comparator VHD and the second comparator VLD are not perfectly inverted in phase.

[0179] Suppose a failure occurs in the upper arm at time t0. At this time, the on / off command signal GDOa (not shown) for the upper arm transitions from high to low, and the semiconductor switching element 50a is turned off. The collector voltage Vcea should be maintaining a high voltage, but due to the failure (abnormal voltage withstand capability) of the upper arm, the collector voltage Vcea starts to drop while it is rising. Therefore, the output waveform of the first comparator VHD also drops pulse-like in accordance with the collector voltage Vcea.

[0180] Subsequently, at time t11, since the upper arm remains conductive due to a malfunction, the on / off command signal GDOb for the lower arm goes high, and at the moment the semiconductor switching element 50b turns on, an overcurrent occurs due to a short circuit in the arm. Consequently, the peak value Icbp of the collector current Icb saturates, and the collector voltage Vceb, which normally decreases, remains high. As a result, the base potential (input potential) VA1b of the first transistor Q1b rises above the reference potential VG0b. At this time, under normal circumstances, the output of the first comparator VHD would switch to low, but due to the occurrence of the overcurrent, it remains in a high state.

[0181] At time t12, when the base potential (input potential) VA1b of the first transistor Q1b rises to 2Vf, that is, when equation (1) above is satisfied, the first transistor Q1b turns on. This detects an overcurrent in the semiconductor switching element 50b. When the first transistor Q1b turns on, the potential of the determination signal OCD2b decreases, and when it drops to a potential (VG1b - Vf) lower than the positive power supply potential VG1b by the threshold voltage Vf of the second transistor Q2b, the second transistor Q2b turns on. As a result, the base potential of the third transistor Q3b also rises, and a voltage greater than or equal to the threshold voltage Vf is applied to the base, and the third transistor Q3b turns on. Then the gate discharge current IAb flows and the gate voltage Vgeb decreases. At that time, the collector current Icb decreases from the peak value Icbp to a value Icba corresponding to the reduced gate voltage Vgeb, and a surge voltage Vsa is generated in the collector voltage Vceb.

[0182] Furthermore, when the second transistor Q2 is turned on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, and the base potential of transistor Qg1 drops from the positive power supply potential VG1 to a potential (VG1 - Vf) which is the forward voltage of diode Dg1. On the other hand, the emitter of transistor Qg1 is at a potential which is the forward voltage of diode Dg2, and the base of transistor Qg1 is in a state where a reverse bias of Vf is applied, so transistor Qg1 is turned off. Consequently, the resistance value R_OFFGI of the off-gate current adjustment unit 18 increases (RG3).

[0183] At time t13, the second overcurrent determination unit 17 detects an overcurrent in the power converter 20, and the determination signal OCD1 goes high. Between time t13 and time t14, the control unit 16 stops the operation of the power converter 20. Specifically, it stops the on / off command signals GDOa and GDOb and performs a current interruption operation on the semiconductor switching elements 50a and 50b to turn them off. At this time, a surge voltage Vsb is generated in the collector voltage Vceb. In order to stop the operation of the power converter 20, the control unit 16 applies an off-gate voltage to the gate terminals Ga and Gb of the semiconductor switching elements 50a and 50b. However, at time t12, the transistor Qg1 of the off-gate current adjustment unit 18 is in the off state, so the off-gate current flows through the resistor RG3 with a high resistance value, and soft interruption is performed.

[0184] When the control unit 16 turns off the semiconductor switching element 50, if the gate voltage Vgeb is too large even after being reduced, there is a concern that a sudden current interruption will occur and the semiconductor switching element 50 will deteriorate due to the surge voltage. For this reason, it is desirable to adjust the value of resistor R10 so that the surge voltage Vsa generated in the collector voltage Vcee during the protection operation and the surge voltage Vsb generated in the collector voltage Vceb when the semiconductor switching element 50 is turned off afterward are approximately the same.

[0185] Furthermore, the control unit 16 increases the gate resistance when turning off the semiconductor switching element 50 by the off-gate current adjustment unit 18 compared to the normal off state. This reduces the off-gate current and enables soft shutdown, thereby suppressing the surge voltage during protection operation. The resistance value of the resistor RG3 for executing soft shutdown should be greater than the resistance value of the resistor R10 in the gate voltage reduction unit 14, as described in Embodiment 1. It is desirable that the resistance value of resistor R10 be greater than the resistance value of the gate resistor RG1 in the output stage circuit 110.

[0186] Immediately after time t0 in Figure 23, the logic synthesis unit 171 of the second overcurrent determination unit 17 should output the determination signal OCD1 as high because the output waveform of the first comparator VHD became low, even though the on / off command signal GDOa switched to low. However, in this embodiment, the determination signal OCD1 occurs at time t13, which is later than time t0. At time t0, the second overcurrent determination unit 17 detects an overcurrent in the power converter 20 and the determination signal OCD1 becomes high, and the control unit 16 controls the semiconductor switching element 50 for stopping the power converter 20 to turn off, which causes the problem described above. That is, the off operation of the semiconductor switching element 50 and the gate voltage reduction operation by the overcurrent protection unit 12 to mitigate the overcurrent of the semiconductor switching element 50 occur simultaneously, and the turn-off operation of the semiconductor switching element 50 becomes faster than usual. This results in the generation of an excessive surge voltage. Furthermore, this excessive surge voltage may cause secondary damage to the semiconductor switching element 50.

[0187] In this embodiment, the determination signal OCD1 that can be generated at time t0 is controlled to be delayed until time t13. This suppresses the generation of excessive surge voltage and prevents secondary failure of the semiconductor switching element 50. In addition, since the off-gate current is reduced by the off-gate current adjustment unit 18, the speed of the turn-off operation is also suppressed.

[0188] Next, the timing of outputting the judgment signal OCD1 will be explained. (1) Method for delaying the output of the judgment signal OCD1 Since the first overcurrent determination unit 13 and the second overcurrent determination unit 17 of the overcurrent protection unit 12 are each equipped with low-pass filters, one method is to make the time constant of the low-pass filter LF1 of the second overcurrent determination unit 17 larger than the time constant of the low-pass filter of the first overcurrent determination unit 13. The low-pass filter (R, C1) of the first overcurrent determination unit 13, together with the clamp diode D1, has its time constant set to suppress malfunctions due to noise and perform overcurrent protection. Therefore, by making the time constant of the low-pass filter LF1 of the second overcurrent determination unit 17 larger than that, the generation of the judgment signal OCD1 can be delayed from time t0. The method for delaying the generation of the judgment signal OCD1 is not limited to adjusting the time constant. For example, the output of the judgment signal OCD1 can be delayed by providing a signal mask circuit in the logic synthesis unit 171 of the second overcurrent determination unit 17 that prohibits output for a certain period of time. A signal mask circuit is, for example, a timer.

[0189] (2) Timing for outputting the judgment signal OCD1 The timing for outputting the judgment signal OCD1, turning off the semiconductor switching element 50, and stopping the power converter 20 is the time from the operation to reduce the gate voltage Vge of the semiconductor switching element 50 until the allowable short-circuit withstand capability of the semiconductor switching element 50 (short-circuit allowable time). Specifically, as shown in Figure 23, this is the time after the collector current Icb is reduced from its peak value Icbp to the value Icba due to the gate voltage reduction operation, which reduces the gate voltage Vgeb. In other words, it is the time after the gate discharge current IAb has flowed. For example, if the time from the occurrence of overcurrent due to a fault (time t0) to the short-circuit withstand capability of the semiconductor switching element 50 is 10us, then the time for outputting the judgment signal OCD1 (t13) should preferably be around 7 or 8us. In this case, the secondary breakdown described above can be prevented by adjusting the timing at which the overcurrent protection unit 12 reduces the gate voltage of the semiconductor switching element 50 to about half of that, for example, around 3 or 4us.

[0190] Furthermore, as described above, after the first overcurrent determination unit 13 detects an overcurrent, the gate voltage reduction unit 14 maintains the operation of reducing the gate voltage Vge for a predetermined period of time. However, it is desirable that the duration of this maintenance exceeds the time at which the second overcurrent determination unit 17 determines the overcurrent. In other words, to prevent the state of reducing the gate voltage Vge from being released before the time at which the second overcurrent determination unit 17 determines the overcurrent, and to prevent the occurrence of another excessive short-circuit current, the predetermined period for which the state of reducing the gate voltage Vge is maintained should be set to be longer than the time difference between when the first overcurrent determination unit 13 determines the overcurrent and when the second overcurrent determination unit 17 determines the overcurrent.

[0191] Furthermore, as described in Embodiment 1, the functions of the clamp diode D1 and the low-pass filter (R, C1) are the same. That is, in this Embodiment 9 as well, since a clamp diode D1 is provided to clamp the input potential VA1 to the gate potential, false detection due to overcurrent noise can be prevented when the semiconductor switching element 50 is in the off state. In addition, by providing the clamp diode D1 and the low-pass filter (R, C1), the false detection of overcurrent mentioned above can also be suppressed.

[0192] Furthermore, in this embodiment 9, a reverse current prevention diode D3 is provided to block current flowing in the direction of energization of the first transistor Q1, thereby protecting the first transistor Q1, and a large negative bias (VG2 + Vf) is applied to the capacitor C1 without being affected by the protection diode D2. This improves the noise immunity of the first transistor Q1 and suppresses false detection of overcurrent. In addition, since an NPN bipolar transistor is used for the first transistor Q1, and the signal with the input potential VA1 used for determination is input to a base that provides current amplification, the first transistor Q1 can be operated effectively with a small signal input.

[0193] Furthermore, since the second overcurrent determination unit 17 uses the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20, the control unit 16 can confirm whether the output is being output according to the pulse width of the output on / off command signal GDOa. For example, this can be done by comparing the period when the on / off command signal GDOa is high with the period when the comparator VHD is high. Normally, the pulse width of the output voltage of the power converter 20 varies due to the characteristics of the semiconductor switching element and the circuit constants of the gate drive unit, but by comparing the period when the on / off command signal GDOa that it generates is high with the period when the output of the comparator VHD is high and feeding this back to the control unit 16, it becomes possible to generate an on / off command signal with the difference corrected. In other words, high-precision control can be achieved.

[0194] Furthermore, the control unit 16 can obtain the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20, by dividing the voltage via the second overcurrent determination unit 17, thereby enabling detection of abnormalities in the main breakdown voltage of the semiconductor switching element.

[0195] For example, the logic synthesis unit 171 can be configured to detect a main breakdown voltage abnormality based on the output of comparators VHD and VLD during the period when both the semiconductor switching elements 50a of the upper arm and 50b of the lower arm, which are connected in series, are off, and to transmit this to the control unit 16. In other words, during the power converter's shutdown period when there is no need to detect an overcurrent state and neither on / off command signals GDOa and GDOb are output, the logic synthesis unit 171 is configured to set the determination signal OCD1 to low when the output of comparators VHD and VLD is low, and to set OCD1 to high otherwise. As a result, when there is no main breakdown voltage abnormality, the potential of the output terminal Ea is set to near the midpoint according to the ratio of resistances provided in the semiconductor drive device 10, but when a main breakdown voltage abnormality occurs, the potential of the output terminal Ea becomes near the positive or negative side, so the output of comparator VHD or VLD becomes high, causing the determination signal OCD1 to become high, and this state can be identified as a state in which a main breakdown voltage abnormality has occurred. The specific determination method can be one of the publicly known methods proposed by the applicant (for example, International Publication No. 2024 / 004208).

[0196] As described above, the power converter of this embodiment 9 achieves the same effects as embodiments 1 to 7. Furthermore, the overcurrent determination in the first overcurrent determination unit precedes the overcurrent determination in the second overcurrent determination unit, and the control unit is configured to control at least the semiconductor switching element of the leg circuit that has been determined to have an overcurrent to be in the off state when an overcurrent is determined in the second overcurrent determination unit. Therefore, the off operation of the semiconductor switching element to stop the power converter and the gate voltage reduction operation to mitigate the overcurrent of the semiconductor switching element do not function simultaneously. If both were to function simultaneously, the turn-off operation of the semiconductor switching element would be faster than usual, generating an excessive surge voltage, which could lead to secondary damage to the semiconductor switching element. However, this problem is eliminated. Accordingly, this configuration protects the semiconductor switching element and the power converter from overcurrent and provides a highly reliable power converter.

[0197] Furthermore, since the first overcurrent detection unit and the second overcurrent detection unit each have a filter element that sets the time from the point in time when the input signal is in an overcurrent state until the first and second overcurrent detection units determine that it is an overcurrent, the overcurrent detection in the first overcurrent detection unit can be easily made to precede the overcurrent detection in the second overcurrent detection unit through circuit design.

[0198] Furthermore, even if this power converter has a smoothing capacitor and a snubber capacitor, when an overcurrent is detected, the off-gate current of the semiconductor switching element when it is off is reduced and soft shutdown is performed, thereby suppressing voltage resonance and making it possible to provide a highly reliable power converter.

[0199] At this time, the time constant of the first filter element in the second overcurrent determination unit is greater than the time constant of the second filter element in the first overcurrent determination unit. The time from when an overcurrent signal is input to the first overcurrent determination unit until an overcurrent determination is made is set to be shorter than the short-circuit tolerance time determined by the short-circuit withstand capability of the semiconductor switching element. This not only prevents the off operation of the semiconductor switching element to stop the power converter and the gate voltage reduction operation to mitigate the overcurrent of the semiconductor switching element from functioning simultaneously, but also makes it possible to stop (turn off) the semiconductor switching element within the short-circuit withstand capability of the semiconductor switching element, thereby providing a more reliable power converter.

[0200] Furthermore, when the first overcurrent detection unit determines that there is an overcurrent, the gate voltage reduction unit continues to reduce the voltage applied to the control terminal of the semiconductor switching element for a predetermined period of time. By setting this period to be longer than the time difference between when the first overcurrent detection unit determines that there is an overcurrent and when the second overcurrent detection unit determines that there is an overcurrent, it becomes possible to suppress the generation of surge voltages that occur even with rapid fluctuations in the gate voltage.

[0201] In the power converter of this embodiment 9, the second overcurrent determination unit uses the potential of the output terminal of the reg circuit to determine overcurrent in the semiconductor switching element. Based on this potential of the output terminal of the reg circuit, the control unit can generate an on / off command signal with an adjusted pulse width. Furthermore, the first overcurrent determination unit can determine an abnormality in the main breakdown voltage of the semiconductor switching element based on the potential of the output terminal of the reg circuit during periods when no on / off command signal is output. This makes it possible to provide a power converter capable of high-precision control.

[0202] Although the circuit configuration of the overcurrent protection unit 12 is shown in Figure 22, which is the same as that shown in Figure 2 of Embodiment 1, it may also be the same as the overcurrent protection unit 12 shown in Figure 4 of Embodiment 1, the overcurrent protection unit 12A shown in Figure 6 of Embodiment 2, and the overcurrent protection unit 12B shown in Figure 7 of Embodiment 3. The operation is the same for each, so the explanation will be omitted. Even with such a configuration, the same effects as in Embodiment 9 will be achieved.

[0203] Embodiment 10. The power conversion device according to Embodiment 10 will be described below with reference to the figures. Figure 24 is a diagram showing the configuration of the power conversion device 1 according to Embodiment 10. In Embodiment 10, a second overcurrent determination unit 17A with a different circuit configuration from the second overcurrent determination unit 17 of Embodiment 9 is used. Note that the overcurrent protection unit 12 is the same as in Embodiment 9, so its description will be omitted.

[0204] In the second overcurrent determination unit 17 of the above-described embodiment 9, the power supply voltage of the DC power supply, which is the potential of the connection part P0, was used as the reference voltage. However, in this embodiment, a reference voltage generation unit 172 is provided in the second overcurrent determination unit 17A, and a single comparator VHLD is configured to determine whether the potential of the output terminal Ea is near the positive potential or near the negative potential.

[0205] In Figure 24, the reference voltage generation unit 172 receives the on / off command signals GDOa and GDOb output from the control unit 16, and switches between outputting a reference voltage for determining the vicinity of the positive electrode potential and a reference voltage for determining the vicinity of the negative electrode potential depending on the state of the input on / off command signals GDOa and GDOb. Specifically, when the on / off command signal GDOa is high, the reference voltage for determining the vicinity of the positive electrode potential is output to the negative input terminal of the comparator VHLD, and when the on / off command signal GDOb is high, the reference voltage for determining the vicinity of the negative electrode potential is output to the negative input terminal of the comparator VHLD. The potential of the emitter control terminal ESa of the semiconductor switching element 50a is divided by resistors R170, R171, R172 and resistor R176 and input to the positive input terminal of the comparator VHLD. As described above, the potential of the emitter control terminal ESa corresponds to the potential of the output terminal Ea of the power converter 20.

[0206] The comparator VHLD is configured to switch the reference voltage using a reference voltage generation unit 172 instead of a window comparator, and compares this reference voltage with the voltage-divided potential of the emitter control terminal ESa. When a reference voltage for determining the vicinity of the positive electrode potential is input, and the potential of the emitter control terminal ESa is within the set range, it is determined that the potential of the emitter control terminal ESa is near the positive electrode potential, and a high (H) output is output. Similarly, when a reference voltage for determining the vicinity of the negative electrode potential is input, and it is within the set range, it is determined that the potential of the emitter control terminal ESa is near the negative electrode potential, and a low (L) output is output.

[0207] Specifically, the timing for detecting a short circuit in the upper arm is limited to when the upper arm is ON, i.e., when the ON / OFF command signal GDOa is high, and during that period there is no need to detect a short circuit in the lower arm. Therefore, during the period when the upper arm is ON, the setting value of the comparator VHLD is set to a high level value Vrefa close to the positive electrode potential. If the potential of the emitter control terminal ESa is within the range of the positive electrode potential and Vrefa, it is determined that the potential is near the positive electrode potential. If it does not reach Vrefa, the logic synthesis unit 171 determines that there is a short circuit. Conversely, during the period when the lower arm is ON, the setting value of the comparator VHLD is set to a low level value Vrefb close to the negative electrode potential. If the potential of the emitter control terminal ESa is within the range of the negative electrode potential and Vrefb, it is determined that the potential is near the negative electrode voltage. If it is outside that range, the logic synthesis unit 171 determines that there is a short circuit.

[0208] The output of the comparator VHLD is input to the logic synthesis unit 171 and is logically processed with the input on / off command signals GDOa and GDOb. Under normal conditions, when the on / off command signal GDOa is output (high: H), the output voltage of the power converter 20 is the output voltage from the upper arm, that is, the potential of the emitter control terminal ESa is near the positive voltage, so the output from the comparator VHLD is high. In this case, the logic synthesis unit 171 outputs the decision signal OCD1 as low (L). Similarly, when the on / off command signal GDOb is output (high: H), the output voltage of the power converter 20 is the output voltage from the lower arm, that is, the potential of the emitter control terminal ESa is near the negative voltage, so the output from the comparator VHLD is low. In this case, the logic synthesis unit 171 outputs the decision signal OCD1 as low (L). In any other case, it is determined that an overcurrent has flowed through one of the arms, and the logic synthesis unit 171 outputs a determination signal OCD1 of high (H) to the control unit 16.

[0209] When the determination signal OCD1 is set to high (H), the control unit 16 does not output the on / off command signals GDOa and GDOb, and stops the operation of the power converter 20.

[0210] In this second overcurrent determination unit 17A, a low-pass filter LF2 is configured with a resistor R179 and a capacitor C170. Here, similar to embodiment 9, the output of the determination signal OCD1 is delayed. That is, the time constant of the low-pass filter LF2 in the second overcurrent determination unit 17A is made larger than the time constant of the low-pass filter in the first overcurrent determination unit 13. Alternatively, a signal mask circuit is provided, such as a timer, in the logic synthesis unit 171. This makes it possible to reduce the gate voltage of the semiconductor switching element 50 after determination in the first overcurrent determination unit 13, and then stop the semiconductor switching element 50 with the second overcurrent determination unit 17A, thereby preventing the semiconductor switching element 50 from being destroyed by an excessive surge voltage.

[0211] Figure 25 is a waveform diagram showing the operation of each part of the power converter 1 according to Embodiment 10. The following explanation will focus on the differences from Figure 23 of Embodiment 9, and overlapping points will be omitted. Under normal conditions before time t0, the signal of comparator VHLD is inverted with the on / off command signal GDOb. That is, when the on / off command signal GDOb is high, comparator VHLD is low, and it is determined that the potential of the emitter control terminal ESa is near the negative voltage.

[0212] Suppose a failure occurs in the upper arm at time t0. At this time, the on / off command signal GDOa (not shown) for the upper arm transitions from high to low, and the semiconductor switching element 50a is turned off. The collector voltage Vcea should be maintaining a high voltage, but due to the failure (abnormal voltage withstand capability) of the upper arm, the collector voltage Vcea starts to drop while it is rising. Therefore, the output waveform of the comparator VHLD also drops pulse-like in accordance with the collector voltage Vcea.

[0213] Subsequently, at time t11, since the upper arm remains conductive due to a malfunction, the on / off command signal GDOb for the lower arm goes high, and at the moment the semiconductor switching element 50b turns on, an overcurrent occurs due to a short circuit in the arms. Consequently, the peak value Icbp of the collector current Icb saturates, and the collector voltage Vceb, which normally decreases, remains high. As a result, the emitter potential (input potential) VA2b of the first transistor Q1b rises to 2Vf, exceeding the reference potential VG0b. At this time, under normal circumstances, the output of the comparator VHLD would switch to low, but due to the occurrence of the overcurrent, it remains high.

[0214] Subsequently, at time t12, the first overcurrent determination unit 13 detects an overcurrent in the semiconductor switching element 50b, and the gate voltage Vgeb is reduced by the gate voltage reduction unit 14. At this time, the collector current Ic decreases from its peak value Icbp to a value Icba corresponding to the reduced gate voltage Vgeb, and a surge voltage Vsa is generated in the collector voltage Vceb as a result.

[0215] Furthermore, when the second transistor Q2 is turned on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, and the base potential of transistor Qg1 drops from the positive power supply potential VG1 to a potential (VG1 - Vf) which is the forward voltage of diode Dg1. On the other hand, the beemitter of transistor Qg1 is at a potential which is the forward voltage of diode Dg2, and the base of transistor Qg1 is in a state where a reverse bias of Vf is applied, so transistor Qg1 is turned off. Consequently, the resistance value R_OFFGI of the off-gate current adjustment unit 18 increases (RG3).

[0216] At time t13, the second overcurrent determination unit 17A detects an overcurrent in the power converter 20, and the determination signal OCD1 goes high. Between time t13 and time t14, the control unit 16 stops the operation of the power converter 20. Specifically, it stops the on / off command signals GDOa and GDOb, and performs a current interruption operation on the semiconductor switching elements 50a and 50b to turn them off. At this time, a surge voltage Vsb is generated in the collector voltage Vceb.

[0217] The control unit 16 applies an off-gate voltage to the gate terminals Ga and Gb of the semiconductor switching elements 50a and 50b in order to stop the operation of the power converter 20. However, at time t12, the transistor Qg1 of the off-gate current adjustment unit 18 is in the off state, so the off-gate current flows through the resistor RG3, which has a high resistance value, and soft shutdown is performed.

[0218] Furthermore, the control unit 16 increases the gate resistance when turning off the semiconductor switching element 50 using the off-gate current adjustment unit 18, which is greater than that during normal off-time. This reduces the off-gate current and enables soft shutdown, thereby suppressing surge voltage during protection operation. The resistance value of the resistor RG3 for performing soft shutdown should be greater than that of the resistor R10 in the gate voltage reduction unit 14, as described in Embodiment 1. It is desirable that the resistance value of resistor R10 be greater than that of the gate resistor RG1 in the output stage circuit 110.

[0219] Furthermore, similar to Embodiment 9, the second overcurrent determination unit 17A uses the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20. Therefore, the control unit 16 can confirm whether the output is in accordance with the pulse width of the output on / off command signal GDOa. For example, this can be done by comparing the period when the on / off command signal GDOa is high with the period when the comparator VHLD is high. Normally, the pulse width of the output voltage of the power converter 20 varies due to the characteristics of the semiconductor switching element and the circuit constants of the gate drive unit, but the control unit 16 can correct the difference by comparing the period when the on / off command signal GDOa it has generated is high with the period when the output of the comparator VHLD is high and feeding this back to the control unit 16.

[0220] Furthermore, similar to Embodiment 9, the control unit 16 can obtain the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20, by dividing the voltage via the second overcurrent determination unit 17A, thereby enabling detection of abnormalities in the main breakdown voltage of the semiconductor switching element.

[0221] For example, the logic synthesis unit 171 can be configured to detect a main breakdown voltage anomaly based on the output of the comparator VHLD during the period when both the semiconductor switching elements 50a and 50b of the upper and lower arms, which are connected in series, are off, and to transmit this to the control unit 16. In other words, during the power converter's shutdown period when there is no need to detect an overcurrent state and neither on / off command signals GDOa nor GDOb are output, the logic synthesis unit 171 is configured to set the determination signal OCD1 to low when the output of the comparator VHLD is low, and to set OCD1 to high when the output of the comparator VHLD is high. As a result, when there is no main breakdown voltage anomaly, the potential of the output terminal Ea is set to near the midpoint according to the ratio of resistances provided in the semiconductor drive device 10, but when a main breakdown voltage anomaly occurs, the potential of the output terminal Ea becomes near the positive or negative side, so the output of the comparator VHLD becomes high, causing the determination signal OCD1 to become high, and this state can be identified as a state in which a main breakdown voltage anomaly has occurred. The specific determination method can be one of the publicly known methods proposed by the applicant (for example, International Publication No. 2024 / 004208).

[0222] As described above, the same effects as in Embodiment 9 can be obtained in Embodiment 10. Specifically, the determination signal OCD1 that can be generated at time t0 is controlled to be delayed until time t13, and the gate resistance when the semiconductor switching element 50 is turned off by the control unit 16 is made larger than that when it is turned off by the off-gate current adjustment unit 18. As a result, the off-gate current is reduced and soft shutdown is performed, so the generation of excessive surge voltage is suppressed and secondary failure of the semiconductor switching element 50 can be prevented. Furthermore, even if this power conversion device has a smoothing capacitor and a snubber capacitor, when an overcurrent is detected, the off-gate current when the semiconductor switching element is turned off is reduced and soft shutdown is performed, which makes it possible to suppress voltage resonance and provide a highly reliable power conversion device.

[0223] In Embodiment 10, the overcurrent protection unit 12 is not limited to that of Embodiment 9, i.e., the same configuration as Figure 2 of Embodiment 1 shown in Figure 22. It may also be the same configuration as the overcurrent protection unit 12 shown in Figure 4 of Embodiment 1, the overcurrent protection unit 12A shown in Figure 6 of Embodiment 2, and the overcurrent protection unit 12B shown in Figure 7 of Embodiment 3. Applying these will also produce similar effects.

[0224] Embodiment 11. The power conversion device according to Embodiment 11 will be described below with reference to the figures. In Embodiments 9 and 10 above, the collector voltage Vce of the semiconductor switching element 50 was detected from the collector sense terminal CS and used as the detection signal SOC, but in this embodiment, a different detection signal SOC is used. Figure 26 is a diagram showing the schematic configuration of the power conversion device 1 according to Embodiment 11. In this Embodiment 11, the semiconductor switching element 50Ab is equipped with a current detection element on the emitter side through which a current reduced to, for example, 1 / 1000 flows, and the reduced emitter current Ieeb flowing from its current detection terminal EEb is used as the detection signal SOCb. The semiconductor switching element 50Aa on the upper arm is similarly equipped with a current detection element and a current detection terminal EEa, and redundant explanations will be omitted below.

[0225] As shown in Figure 26, the power converter 1 comprises a power converter 20A and a semiconductor drive unit 10J that drives the semiconductor switching elements of the power converter 20A. The semiconductor drive unit 10J comprises a control unit 16, isolated communication units ICVa and ICVb, output stage circuits 110a and 110b, overcurrent protection units 12Ca and 12Cb, and a second overcurrent determination unit 17. The overcurrent protection units 12Ca and 12Cb comprise a first overcurrent determination unit 13C that outputs an overcurrent determination signal OCD2 based on the emitter current Iee (detection signal SOC), and a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD2. The output stage circuits 110a and 110b and the gate voltage reduction unit 14 are the same as those in Embodiment 9 described above. The overcurrent protection units 12Ca and 12Cb are the same circuits as the overcurrent protection unit 12C shown in Figure 8 of Embodiment 4. Furthermore, the first overcurrent determination unit 13C has the same circuit configuration as the first overcurrent determination unit 13 in Embodiment 9, although it handles a different detection signal SOC. It also has the same circuit configuration as the first overcurrent determination unit 13C shown in Figure 8 of Embodiment 4, which handles the same detection signal SOC, and operates in the same manner.

[0226] Figure 27 is a waveform diagram showing the operation of each part of the power converter 1 according to Embodiment 11. In Figure 27, the device operates normally before time t0, and at time t0, a failure such as a voltage breakdown error occurs in the upper arm. In Figure 27, the emitter current Ieeb, which becomes the detection signal SOCb, is connected to the base of the first transistor Q1b and is input to the base. When an overcurrent occurs while the semiconductor switching element 50Ab is ON (time t11), the emitter current Ieeb (detection signal SOCb) rises, and when it exceeds the set threshold IX, the first transistor Q1b turns ON. This detects the overcurrent of the semiconductor switching element 50Ab. Except for using the emitter current Ieeb as the detection signal SOCb, the operation waveforms of each part are the same as those shown in Figure 23 of Embodiment 9 above.

[0227] In this embodiment 11, the same effects as in the embodiment 9 described above can be obtained. Furthermore, although it is applicable only to semiconductor switching elements 50 equipped with a current detection element, it can detect overcurrents with higher accuracy because it detects the current value itself to determine overcurrent without requiring contact with the high-voltage section.

[0228] Although Figure 26 describes an example in which the power converter 1 of Embodiment 11 is equipped with a second overcurrent determination unit 17, it goes without saying that the second overcurrent determination unit 17A described in Embodiment 10 can also be applied.

[0229] Embodiment 12. The power conversion device according to Embodiment 12 will be described below with reference to the figures. In Embodiment 12, a detection signal SOC different from the detection signal SOC used in Embodiments 9 and 10 and the detection signal SOC used in Embodiment 11 is used.

[0230] Figure 28 shows a schematic configuration of the power conversion device 1 according to Embodiment 12. In this Embodiment 12, the emitter voltage VEe between the emitter E, which is the low-voltage side main terminal of the semiconductor switching element 50B, and the emitter control terminal ES is used as the detection signal SOC. This utilizes the electromotive force (Le・dIc / dt) generated in the parasitic inductance Le on the emitter side.

[0231] As shown in Figure 28, the power converter 1 comprises a power converter 20B and a semiconductor drive device 10K that drives the semiconductor switching elements of the power converter 20B. The semiconductor drive device 10K comprises a control unit 16, isolated communication units ICVa and ICVb, output stage circuits 110a and 110b, overcurrent protection units 12a and 12b, and a second overcurrent determination unit 17. The overcurrent protection units 12a and 12b comprise a first overcurrent determination unit 13D that outputs an overcurrent determination signal OCD2 based on the emitter voltage VEe (detection signal SOC), and a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD2. The other configurations are the same as in the above embodiment 9. The overcurrent protection units 12Da and 12Db are circuits similar to the overcurrent protection unit 12D shown in Figure 10 of embodiment 5.

[0232] Furthermore, the first overcurrent determination unit 13D has a circuit configuration similar to the first overcurrent determination unit 13 in Embodiment 9, although it handles a different detection signal SOC. However, in Embodiment 9, the entire overcurrent protection unit 12 was configured based on the potential of the emitter control terminal ES, but in this embodiment, only the first overcurrent determination unit 13 within the overcurrent protection unit 12D is configured based on the potential of the emitter E, while the others are configured based on the potential of the emitter control terminal ES. That is, the emitter control terminal ES is connected to the high-voltage side of resistor R1, and the emitter voltage VEe (detection signal SOC) from emitter E is connected to the low-voltage side of resistor R4. In this respect, it is similar to the operation of the first overcurrent determination unit 13D shown in Figure 10 of Embodiment 5, which handles the same detection signal.

[0233] Figure 29 is a waveform diagram showing the operation of each part of the power converter 1 according to Embodiment 12. In Figure 29, the device operates normally before time t0, and at time t0, a failure such as a voltage breakdown error occurs in the upper arm. In Figure 29, the emitter voltage VEeb, which becomes the detection signal SOCb, has a waveform similar to the derivative of the collector current Ic (dIcb / dt). When an overcurrent occurs while the semiconductor switching element 50Bb is ON, the emitter voltage VEeb (detection signal SOCb) decreases, and when it decreases below the set threshold VX, the first transistor Q1b turns ON. This detects the overcurrent of the semiconductor switching element 50Bb. Except for using the emitter voltage VEeb as the detection signal SOCb, the operation waveforms of each part are the same as those shown in Figure 23 of Embodiment 9 above.

[0234] In this embodiment 12, the same effects as in embodiment 9 can be obtained. Furthermore, by utilizing the electromotive force generated in the parasitic inductance Le on the emitter side, current information can be acquired at high speed and with high accuracy without the need for a current detection element, and overcurrent can be detected.

[0235] In the above embodiment, the emitter voltage VEe was compared with a threshold voltage VX which serves as the determination voltage. However, the voltage amplitude (Le・dIc / dt) of the emitter voltage VEe may be integrated using an integration circuit to obtain information similar to the collector current Ic and determine whether an overcurrent has occurred.

[0236] Although Figure 28 describes an example in which the power converter 1 of Embodiment 12 is equipped with a second overcurrent determination unit 17, it goes without saying that the second overcurrent determination unit 17A described in Embodiment 10 can also be applied.

[0237] Embodiment 13. Hereinafter, a power conversion device according to Embodiment 13 will be described with reference to the figures. In this Embodiment 13, the signal obtained by detecting the rate of change of the current between the main terminals and converting it into a voltage is used as the detection signal SOC. Figure 30 is a diagram showing the schematic configuration of the power conversion device 1 according to Embodiment 13. As shown in Figure 30, a current-voltage conversion element CT is provided on the outside of the emitter E, which is one of the main terminals of the semiconductor switching element 50C. The current-voltage conversion element CT detects the rate of change of the collector current Ic, which is the current between the main terminals, and outputs voltage information Vct (detection signal SOC). As an example of the current-voltage conversion element CT, there is a Rogowski coil formed on a printed circuit board that constitutes the overcurrent protection unit 12E.

[0238] As shown in Figure 30, the power converter 1 comprises a power converter 20C and a semiconductor drive device 10L that drives the semiconductor switching elements of the power converter 20C. The semiconductor drive device 10 comprises a control unit 16, isolated communication units ICVa and ICVb, output stage circuits 110a and 110b, overcurrent protection units 12Ea and 12Eb, and a second overcurrent determination unit 17. The overcurrent protection units 12Ea and 12Eb comprise a first overcurrent determination unit 13E that outputs an overcurrent determination signal OCD2 based on voltage information Vct (detection signal SOC), and a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD2. The other configurations are the same as in the above embodiment 9. The overcurrent protection units 12Ea and 12Eb are the same circuits as the overcurrent protection unit 12E shown in Figure 12 of embodiment 6.

[0239] The first overcurrent determination unit 13E also has the same circuit configuration as the first overcurrent determination unit 13 in Embodiment 9, although it handles a different detection signal SOC. Furthermore, it has the same circuit configuration as the first overcurrent determination unit 13E shown in Figure 12 of Embodiment 6, which handles the same detection signal SOC, and operates in the same manner.

[0240] Figure 31 is a waveform diagram showing the operation of each part of the power converter 1 according to Embodiment 13. In Figure 31, the device operates normally before time t0, and at time t0, a failure such as a voltage breakdown error occurs in the upper arm. In Figure 31, the voltage information Vctb, which becomes the detection signal SOCb, has a waveform similar to the derivative of the collector current Icb (dIcb / dt). When an overcurrent occurs with the semiconductor switching element 50Cb in the ON state (time t11), the voltage information Vctb (detection signal SOCb) rises, and when it exceeds the set threshold VXa (time t2), the first transistor Q1b turns ON. This detects the overcurrent of the semiconductor switching element 50Cb. Except for using the voltage information Vctb as the detection signal SOCb, the operation waveforms of each part are the same as those shown in Figure 23 of Embodiment 9 above.

[0241] In this embodiment 13, the same effects as in embodiment 9 can be obtained. Furthermore, by mounting the overcurrent protection unit 12E on a printed circuit board and utilizing a Rogowski coil (current-voltage conversion element CT) formed on the printed circuit board, non-contact, high-precision overcurrent detection can be achieved.

[0242] Although Figure 30 describes an example in which the power converter 1 of Embodiment 13 is equipped with a second overcurrent determination unit 17, it goes without saying that the second overcurrent determination unit 17A described in Embodiment 10 can also be applied.

[0243] Embodiment 14. The power conversion device according to Embodiment 14 will be described below with reference to the figures. In Embodiment 9 described above, as shown in Figure 22, a low-pass filter (R, C1) is provided at the input of the detection signal SOC of the first overcurrent determination unit 13. In Embodiment 14, the low-pass filter of the first overcurrent determination unit 13F is provided as a first low-pass filter and a second low-pass filter.

[0244] Figure 32 is a diagram showing the schematic configuration of a power converter 1 according to Embodiment 14. As shown in Figure 32, the power converter 1 comprises a power converter 20 and a semiconductor drive device 10M that drives the semiconductor switching elements of the power converter 20. The semiconductor drive device 10M comprises a control unit 16, isolated communication units ICVa and ICVb, output stage circuits 110a and 110b, overcurrent protection units 12Fa and 12Fb, and a second overcurrent determination unit 17. The overcurrent protection units 12Fa and 12Fb comprise a first overcurrent determination unit 13F that determines the overcurrent flowing through the semiconductor switching element 50, and a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined. The control unit 16, isolated communication units ICVa and ICVb, output stage circuits 110a and 110b, and gate voltage reduction unit 14 are the same as those in Embodiment 9 described above.

[0245] The first overcurrent determination unit 13F according to Embodiment 14 includes a first transistor Q1, a clamp diode D1, a reverse current prevention diode D3, a resistor R, capacitors C1a and C1b, and a diode DL. In this case, a first low-pass filter (R, C1a) is formed by the resistor R and capacitor C1a, and a second low-pass filter (R, C1b) is formed by the resistor R and capacitor C1b. The detection signal SOC, which is the collector voltage Vce that is the voltage between the main terminals of the semiconductor switching element 50, is input to the first transistor Q1 via the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b), and outputs an overcurrent determination signal OCD2. The circuit configuration of the overcurrent protection unit 12F according to Embodiment 14 is the same as that of Embodiment 7, Figure 15, and the operation is the same, so a detailed explanation is omitted.

[0246] The capacitor C1a of the first low-pass filter (R, C1a) is configured to have a small capacitance, while the capacitor C1b of the second low-pass filter (R, C1b) is configured to have a large capacitance. When the semiconductor switching element 50 is in the off state, the capacitor C1a of the first low-pass filter (R, C1a) is negatively biased. When the semiconductor switching element 50 turns on and recovers from the negative bias state, if the capacitance of capacitor C1a is large, it will take time to recover. Here, by reducing the capacitance of capacitor C1a, capacitor C1a recovers quickly from the negative bias, and overcurrent detection can be achieved within a predetermined delay time. The first low-pass filter (R, C1a) functions similarly to the low-pass filter (R, C1) shown in embodiments 1 and 9 above, suppressing false detection of overcurrent.

[0247] If the second low-pass filter (R, C1b) is absent, that is, in the same case as in Embodiment 1 above, when the semiconductor switching element 50 is in the ON state, the immunity to current noise will be reduced if only the first low-pass filter (R, C1a) with a small capacitance C1a is present. In this case, because a second low-pass filter (R, C1b) with a large capacitance C1b is provided, false detection of overcurrent due to current noise can be suppressed even when the semiconductor switching element 50 is in the ON state.

[0248] Figure 33 is a waveform diagram showing the operation of each part of the power converter 1 according to Embodiment 14. In Figure 33, the device operates normally before time t0, and at time t0, a failure such as a voltage breakdown error occurs in the upper arm. In Figure 33, the operating waveforms other than the base potential (input potential) VA1b of the first transistor Q1b, with reference to the emitter control terminal ESb, are the same as those shown in Figure 23 of Embodiment 9. Note that the VA1b waveform in Embodiment 9 is shown as a dotted line.

[0249] Under normal conditions prior to time t0, the base potential (input potential) VA1b of the first transistor Q1b is clamped to a potential (VG2 + Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2b when the semiconductor switching element 50b is in the off state. When the semiconductor switching element 50b is in the on state, the collector voltage Vceb drops to a few volts, and the voltage VA1b, which is divided by resistors Rb (R1b, R2b, R3b) and resistor R4b, becomes close to the reference potential VG0b. In this case, because a small capacitance capacitor C1ab is used in the first low-pass filter (Rb, C1ab) clamped by the clamp diode D1b, the period during which the base potential (input potential) VA1b recovers from negative bias when the semiconductor switching element 50b transitions from the off state to the on state is shortened.

[0250] At time t0, a failure such as a voltage withstand error occurred in the upper arm. At time t11, since the upper arm remains conductive due to the failure, if an overcurrent occurs due to a short circuit in the arm at the moment the semiconductor switching element 50b turns on, the peak value Icbp of the collector current Icb will saturate, and the collector voltage Vceb, which normally decreases, will remain high. Here as well, after the semiconductor switching element 50b turns on, the base potential (input potential) VA1b quickly recovers from the negative bias and rises even higher than the reference potential VG0b.

[0251] At time t12, when the base potential (input potential) VA1b of the first transistor Q1b rises to 2Vf, that is, when equation (1) above is satisfied, the first transistor Q1b turns on. This allows the overcurrent of the semiconductor switching element 50b to be detected. When the first transistor Q1b turns on, the second transistor Q2b and the third transistor Q3b also turn on. Then the gate discharge current IAb flows and the gate voltage Vgeb decreases. At that time, the collector current Icb decreases from its peak value Icbp to a value Icba corresponding to the reduced gate voltage Vgeb, and a surge voltage Vsa is generated in the collector voltage Vceb as a result.

[0252] Furthermore, when the second transistor Q2 is turned on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, and the base potential of transistor Qg1 drops from the positive power supply potential VG1 to a potential (VG1 - Vf) which is the forward voltage of diode Dg1. On the other hand, the emitter of transistor Qg1 is at a potential which is the forward voltage of diode Dg2, and the base of transistor Qg1 is in a state where a reverse bias of Vf is applied, so transistor Qg1 is turned off. Consequently, the resistance value R_OFFGI of the off-gate current adjustment unit 18 increases (RG3).

[0253] In this embodiment as well, similar to embodiment 9 described above, at time t13, the second overcurrent determination unit 17 detects an overcurrent in the power converter 20 and the determination signal OCD1 becomes high. Between time t13 and time t14, the control unit 16 stops the operation of the power converter 20. Specifically, it stops the on / off command signals GDOa and GDOb and performs a current interruption operation on the semiconductor switching elements 50a and 50b to turn them off. At this time, a surge voltage Vsb is generated in the collector voltage Vceb.

[0254] In this embodiment, the time constant of the low-pass filter LF1 provided by the second overcurrent determination unit 17 is set to be greater than that of either the first low-pass filter (R, C1a) or the second low-pass filter (R, C1b) of the overcurrent protection unit 12F. As a result, after the gate voltage is reduced by the overcurrent protection unit 12F, the determination signal OCD1 from the second overcurrent determination unit 17 causes the semiconductor switching element 50 to perform a current interruption operation. The control unit 16 applies an off-gate voltage to the gate terminals Ga and Gb of the semiconductor switching elements 50a and 50b in order to stop the operation of the power converter 20. However, at time t12, the transistor Qg1 of the off-gate current adjustment unit 18 is in the off state, so the off-gate current flows through the resistor RG3 with a high resistance value, and a soft interruption is performed.

[0255] In this embodiment as well, similar to embodiment 9 described above, the overcurrent protection unit 12F can detect and protect the semiconductor switching element 50 from overcurrent by utilizing the threshold voltage of the first transistor Q1 without requiring its own power supply. Furthermore, the clamp diode D1 and the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b) work together to suppress malfunctions due to noise and provide overcurrent protection. As a result, even when the semiconductor switching element 50 and the output stage circuits 110a, 110b of the semiconductor drive device 10M or the gate drive unit 11 are spaced apart, the overcurrent protection unit 12F, which does not require a power supply, can be placed close to the semiconductor switching element 50, enabling highly reliable overcurrent protection.

[0256] Although Figure 32 describes an example in which the power converter 1 of Embodiment 14 is equipped with a second overcurrent determination unit 17, it goes without saying that the second overcurrent determination unit 17A described in Embodiment 10 can also be applied. In this case as well, the time constant of the low-pass filter LF2 equipped with the second overcurrent determination unit 17A is set to be greater than that of either the first low-pass filter (R, C1a) or the second low-pass filter (R, C1b) of the overcurrent protection unit 12F.

[0257] In embodiments 9 to 14 described above, an example was shown in which the overcurrent protection unit includes an off-gate current adjustment unit. When the overcurrent protection unit is mounted on a single substrate, the overcurrent protection unit does not have a power supply and can adjust the off-gate resistance and perform soft shutdown based on the signal from the first overcurrent determination unit. The substrate on which this overcurrent protection unit is mounted corresponds to each arm of the power converter and can be used as a common substrate for mounting the overcurrent protection unit. Furthermore, multiple semiconductor switching elements and the overcurrent protection unit can be controlled by a single gate drive unit. Therefore, since the substrate can be standardized, costs can be reduced, there is no need to adjust the substrate constants for each substrate, and the performance of the power converter can be improved.

[0258] Embodiment 15. While embodiments 9 to 14 described above showed examples in which the overcurrent protection unit includes an off-gate current adjustment unit, this embodiment will describe an example in which the gate drive unit includes an off-gate current adjustment unit. Figure 34 is a block diagram showing the schematic configuration of the power converter 1 according to embodiment 15. As shown in Figure 34, the power converter 1 includes a power converter 20 that supplies power to a load 70, and a semiconductor drive unit 10N that drives the semiconductor switching elements of the power converter 20. The semiconductor drive unit 10N includes a gate drive unit 11N which includes a second overcurrent determination unit 17, a control unit 16 that receives a command signal SIN transmitted from a higher-level control unit (not shown) and generates an on / off command signal for the semiconductor switching element based on the signal from the second overcurrent determination unit 17, and an output stage circuit 110A that applies voltage to the semiconductor switching element and drives it based on the on / off command signal input via an isolated communication unit ICV, and an overcurrent protection unit 12G that detects and protects against overcurrent of the semiconductor switching element. Next, the detailed circuit configuration will be described using Figure 35.

[0259] Figure 35 is a diagram showing the circuit configuration of the main part of the power converter according to Embodiment 15. In Figure 35, the output stage circuit 110A includes an off-gate current adjustment unit 18G and a protection operation detection unit 19. Although both output stage circuits 110Aa and 110Ab include an off-gate current adjustment unit 18G and a protection operation detection unit 19, the circuit configuration and operation of the output stage circuits 110Aa and 110Ab are the same, so here only the circuit configuration of output stage circuit 110Ab will be shown and explained in detail. The off-gate current adjustment unit 18G includes an N-type MOSFET MG 3b connected between an N-type MOSFET MG 2b and a gate resistor RG 2b, and a resistor RG 4b connected in parallel to the series circuit of the gate resistor RG 2b and the N-type MOSFET MG 3b. The resistance value of resistor RG 4b is set to be greater than the resistance value of the gate resistor RG 2b (RG 4b > RG 2b).

[0260] Under normal conditions, when the semiconductor switching element 50b is turned on, the control unit 16 turns on the P-type MOSFET MG1b based on the on / off command signal GDOb, and the on-gate current flows from the gate resistor RG1b towards the gate terminal Gb. Under normal conditions, when the semiconductor switching element 50b is turned off, the control unit 16 turns on the N-type MOSFET MG2b based on the on / off command signal GDOb, and the off-gate current flows mainly from the gate terminal Gb towards the gate resistor RG2b. Under normal conditions, the N-type MOSFET MG3b is always on.

[0261] When an overcurrent is detected in any arm of the power converter 20, the overcurrent protection unit 12G reduces the gate voltage Vgeb. Upon detection of this, the protection operation detection unit 19b inputs the signal GSDb to the gate of the N-type MOSFETMG 3b. Here, the N-type MOSFETMG 3b is pre-set so that its gate changes from high to low upon input of the signal GSDb. Therefore, the N-type MOSFETMG 3b is turned off upon input of the signal GSDb.

[0262] Furthermore, if it is determined that an overcurrent has flowed through any of the arms, the logic synthesis unit 171 outputs a determination signal OCD1 of high (H) to the control unit 16. When the control unit 16 receives a high (H) determination signal OCD1, it does not output the on / off command signals GDOa and GDOb, and stops the operation of the power converter 20.

[0263] At this time, that is, when it is determined that an overcurrent has flowed through the arm, the N-type MOSFET MG3b is turned off by the input of the signal GSDb. Therefore, when the N-type MOSFET MG2b is turned on, the off-gate current flows from the gate terminal Gb towards the resistor RG4b. As described above, the resistance value of resistor RG4b is greater than the resistance of gate resistor RG2b through which the off-gate current flows under normal conditions, so the off-gate current is reduced and soft shutdown is performed. In other words, when it is determined that an overcurrent has flowed through the arm, the resistance value R_OFFGI of the off-gate current adjustment unit 18G becomes greater than under normal conditions (RG2b) (RG4b).

[0264] The operation of the off-gate current adjustment unit 18G of the output stage circuit 110A is the same as the operation of the off-gate current adjustment unit 18G in the gate drive unit 11G shown in Figure 17 of Embodiment 8. Furthermore, the circuit configuration of the overcurrent protection unit 12G is the same as that shown in Figure 18 of Embodiment 8, and its operation is the same, so a description is omitted.

[0265] Figure 36 is a waveform diagram showing the operation of each part of the power converter 1 according to Embodiment 15. The details of the overcurrent protection operation by the power converter 1 will be explained below based on Figures 35 and 36. Here, we will explain using an example where a failure occurs in the upper arm, but the example where a failure occurs in the lower arm can be explained similarly and will be omitted. In normal operation before time t0, the lower arm outputs a gate voltage Vgeb in accordance with the on / off command signal GDOb generated by the command signal SIN transmitted from the higher control device, and the collector current Icb of the semiconductor switching element 50b and the collector voltage Vceb which becomes the detection signal SOCb also have waveforms corresponding to the on / off command signal GDOb. The base potential (input potential) VA1b of the first transistor Q1b with reference to the emitter control terminal ESb is clamped to a potential (VG2b + Vf) obtained by adding the forward voltage Vf of the clamp diode D1b to the negative power supply potential VG2b when the semiconductor switching element 50b is in the off state. Furthermore, when the semiconductor switching element 50b is ON, the collector voltage Vceb drops to a few volts, and the voltage VA1b, which is divided by resistors Rb (R1b, R2b, R3b) and resistor R4b, becomes close to the reference potential VG0b.

[0266] The potential of the determination signal OCD2b, i.e., the base potential of the second transistor Q2b, is the same as the gate potential (positive power supply potential VG1b) when the semiconductor switching element 50b is ON, and is lowered to the negative power supply potential VG2b when it is OFF. Furthermore, since the ON / OFF command signal GDOa for the upper arm is almost inverted from the ON / OFF command signal GDOb, the collector voltage Vcea, which becomes the detection signal SOCa for the semiconductor switching element 50a of the upper arm, also has a waveform that is almost inverted from the collector voltage Vceb of the lower arm.

[0267] The output waveform of the second comparator VLD corresponds to the on / off command signal GDOb for the lower arm, while the output waveform of the first comparator VHD is the inverted waveform of the on / off command signal GDOb for the lower arm. That is, when the on / off command signal GDOb for the lower arm is high, the output waveform of the second comparator VLD is high, and the output waveform of the first comparator VHD is low. When the on / off command signal GDOb for the lower arm is low, the output waveform of the second comparator VLD is low, and the output waveform of the first comparator VHD is high.

[0268] Suppose a failure occurs in the upper arm at time t0. At this time, the on / off command signal GDOa (not shown) for the upper arm transitions from high to low, and the semiconductor switching element 50a is turned off. The collector voltage Vcea should be maintaining a high voltage, but due to the failure (abnormal voltage withstand capability) of the upper arm, the collector voltage Vcea starts to drop while it is rising. Therefore, the output waveform of the first comparator VHD also drops pulse-like in accordance with the collector voltage Vcea.

[0269] Subsequently, at time t11, since the upper arm remains conductive due to a malfunction, the on / off command signal GDOb for the lower arm goes high, and at the moment the semiconductor switching element 50b turns on, an overcurrent occurs due to a short circuit in the arm. Consequently, the peak value Icbp of the collector current Icb saturates, and the collector voltage Vceb, which normally decreases, remains high. As a result, the base potential (input potential) VA1b of the first transistor Q1b rises above the reference potential VG0b. At this time, under normal circumstances, the output of the first comparator VHD would switch to low, but due to the occurrence of the overcurrent, it remains in a high state.

[0270] At time t12, when the base potential (input potential) VA1b of the first transistor Q1b rises to 2Vf, that is, when equation (1) above is satisfied, the first transistor Q1b turns on. This detects an overcurrent in the semiconductor switching element 50b. When the first transistor Q1b turns on, the potential of the determination signal OCD2b decreases, and when it drops to a potential (VG1b - Vf) lower than the positive power supply potential VG1b by the threshold voltage Vf of the second transistor Q2b, the second transistor Q2b turns on. As a result, the base potential of the third transistor Q3b also rises, and a voltage greater than or equal to the threshold voltage Vf is applied to the base, and the third transistor Q3b turns on. Then the gate discharge current IAb flows and the gate voltage Vgeb decreases. At that time, the collector current Icb decreases from the peak value Icbp to a value Icba corresponding to the reduced gate voltage Vgeb, and a surge voltage Vsa is generated in the collector voltage Vceb.

[0271] At time t13, the protection operation detection unit 19b detects a decrease in the gate voltage Vgeb and generates the signal GSDb. Also, the second overcurrent determination unit 17 detects an overcurrent in the power converter 20 and the determination signal OCD1 becomes high. Between time t13 and time t14, the control unit 16 stops the operation of the power converter 20. Specifically, it stops the on / off command signals GDOa and GDOb and performs a current interruption operation on the semiconductor switching elements 50a and 50b to turn them off.

[0272] The control unit 16 applies off-gate voltages to the gate terminals Ga and Gb of the semiconductor switching elements 50a and 50b to stop the operation of the power converter 20. At this time, the signal GSDb from the protection operation detection unit 19b is input to the gate of the N-type MOSFET MG3b, and the N-type MOSFET MG3b turns off. An off-gate current flows from the gate terminal Gb towards the resistor RG4b. When the control unit 16 shuts off the semiconductor switching element 50, the off-gate current flows through the resistor RG4b, which has a high resistance, so the off-gate current is reduced compared to normal operation, and soft shutdown is performed.

[0273] During this current interruption operation, a surge voltage Vsb is generated in the collector voltage Vceb. As mentioned above, it is desirable to set the resistor R10 to satisfy equation (2) above so that the surge voltage Vsb is approximately the same as the surge voltage Vsa that occurs beforehand. Furthermore, since the off-gate current is also reduced when the gate voltage is reduced, and soft interruption is performed, even if this power converter 1 has a smoothing capacitor and a snubber capacitor, resonance between capacitors is suppressed when the semiconductor switching element is interrupted, and a semiconductor drive device with highly reliable overcurrent protection can be provided. Moreover, when a common board is used in which the arm and the overcurrent protection unit are mounted on a single board, the size of the board is limited, and if the board area is small, the constraint of the board size can be satisfied by providing the off-gate current adjustment unit 18G on the gate drive unit 11N, as in this embodiment.

[0274] Furthermore, the circuit configuration of the overcurrent protection unit 12G in this embodiment is the same as that shown in Figure 18 of Embodiment 8, and operates similarly, but is not limited to this. The configuration of the off-gate current adjustment unit 18A may be omitted from the overcurrent protection unit 12 shown in Figure 4 of Embodiment 1, or the off-gate current adjustment unit 18 may be omitted from the overcurrent protection unit 12A shown in Figure 6 of Embodiment 2, or the off-gate current adjustment unit 18 may be omitted from the overcurrent protection unit 12B shown in Figure 7 of Embodiment 3, or the overcurrent protection unit 12F shown in Figure 15 of Embodiment 7 may be provided with a first overcurrent determination unit 13F and the off-gate current adjustment unit 18 may be omitted.

[0275] Furthermore, the circuit configuration of the overcurrent protection unit 12G in this embodiment may be such that the power converter 20 is the same as the power converter 20A shown in Figure 26 of Embodiment 11, and the overcurrent protection unit is the same as the overcurrent protection unit 12C in Figure 26 with the off-gate current adjustment unit 18 removed; or the power converter 20 is the same as the power converter 20B shown in Figure 28 of Embodiment 12, and the overcurrent protection unit is the same as the overcurrent protection unit 12D in Figure 28 with the off-gate current adjustment unit 18 removed; or the power converter 20 is the same as the power converter 20C shown in Figure 30 of Embodiment 13, and the overcurrent protection unit is the same as the overcurrent protection unit 12E in Figure 30 with the off-gate current adjustment unit 18 removed.

[0276] Furthermore, in this embodiment, the second overcurrent determination unit 17 provided in the semiconductor drive device 10N may be the second overcurrent determination unit 17A shown in Figure 24 of Embodiment 10.

[0277] Embodiment 16. Figure 37 shows the configuration of the power conversion device according to Embodiment 16. As shown in Figure 37, the power conversion device 1 comprises a power converter 20X having a plurality of semiconductor switching elements 50, and a semiconductor drive device 10X that drives each semiconductor switching element 50 in the power converter 20X. In this case, the power conversion device 1 is an inverter that converts DC power from a DC power supply 60 into AC power and supplies it to a load 70 (AC motor). The semiconductor drive devices 10, 10C, 10D, 10E, 10F, and 10G according to Embodiments 1 to 8 are provided for each semiconductor switching element 50, and the collection of these individual semiconductor drive devices 10 is referred to as the semiconductor drive device 10X of this embodiment. Furthermore, the semiconductor drive devices 10H, 10I, 10J, 10K, 10L, 10M, and 10N according to Embodiments 9 to 15 are provided for each upper and lower arm, i.e., each leg circuit, and the collection of these semiconductor drive devices 10 is referred to as the semiconductor drive device 10X of this embodiment.

[0278] The power converter 20X is a three-phase (U, V, W) inverter circuit equipped with a smoothing capacitor 40, a snubber capacitor 45, and a leg circuit 23 for each phase between the DC buses. The leg circuit 23 for each phase is composed of an upper arm 21A and a lower arm 22A, each having a semiconductor switching element 50, connected in series.

[0279] In this embodiment 16, the semiconductor switching elements 50 in the power converter 20X are driven by a semiconductor drive device 10X to which the semiconductor drive device according to embodiments 1 to 15 is applied. As a result, overcurrent protection for the semiconductor switching elements 50 can be implemented with high reliability without requiring an additional power supply. Therefore, even when the semiconductor switching elements 50 and the gate drive unit of the semiconductor drive device 10X are spaced apart, overcurrent protection for the semiconductor switching elements 50 can be implemented with high reliability, resulting in an inexpensive and highly reliable power converter 1.

[0280] Although the power converter 20X is shown outputting two levels of AC voltage, positive and negative, it may also be an inverter capable of multi-level voltage output by connecting any number of semiconductor switching elements 50 in series and parallel. In that case as well, the power converter 20X will have a configuration that includes a leg circuit 23 formed by connecting an upper arm 21A and a lower arm 22A, each having a semiconductor switching element 50, in series.

[0281] Figure 38 shows the configuration of a power converter according to another example of Embodiment 16. As shown in Figure 38, the power converter 1 comprises a power converter 20Y having a plurality of semiconductor switching elements 50, and a semiconductor drive device 10Y that drives each semiconductor switching element 50 in the power converter 20Y. In this case, the power converter 1 operates as a boost converter that boosts the DC voltage of the DC power supply 60 and supplies it to a DC load 70A. As described above, the semiconductor drive device 10Y may be a collection of individual semiconductor drive devices 10 that drive each semiconductor switching element 50, or it may be a semiconductor drive device 10 that drives the REG circuit 23A.

[0282] The power converter 20Y comprises an input-side smoothing capacitor 41, a snubber capacitor 46, an output-side smoothing capacitor 42, a re-g circuit 23A, and a boost reactor 43. The re-g circuit 23A is constructed by connecting an upper arm 21B and a lower arm 22B, each having a semiconductor switching element 50, in series.

[0283] In this case as well, overcurrent protection for the semiconductor switching element 50 can be implemented with high reliability without requiring an additional power supply. Therefore, even when the semiconductor switching element 50 and the gate drive unit of the semiconductor drive device 10 are spaced apart, overcurrent protection for the semiconductor switching element 50 can be implemented with high reliability, resulting in an inexpensive and highly reliable power converter 1.

[0284] Although the above example shows a boost converter, the method can also be applied to a buck converter, or a buck-boost converter that combines a boost converter and a buck converter. Furthermore, a wide-bandgap semiconductor material may be used for the semiconductor switching element 50, which speeds up the switching operation of the semiconductor switching element 50 and allows for miniaturization of the boost reactor 43. As the wide-bandgap semiconductor material, silicon carbide (SiC), gallium nitride, gallium oxide-based materials, or diamond can be used.

[0285] Figure 39 shows the configuration of a power converter according to yet another example of Embodiment 16. As shown in Figure 39, the power converter 1 comprises a main circuit (power converter) in which the power converter 20Y shown in Figure 38 is connected to the DC side of the power converter 20X shown in Figure 37, and a semiconductor drive device 10Z that drives each semiconductor switching element 50. In this case, the power converter 1 boosts the DC voltage of the DC power supply 60 using the power converter 20Y, and the boosted DC power is converted into AC power by the power converter 20X and supplied to the load 70 (AC motor).

[0286] This power converter 1 operates as a boost inverter system and is applied, for example, to electric vehicles. In this case as well, overcurrent protection for the semiconductor switching element 50 can be implemented with high reliability without requiring an additional power supply. Therefore, even when the semiconductor switching element 50 and the gate drive unit of the semiconductor drive unit 10X are spaced apart, overcurrent protection for the semiconductor switching element 50 can be implemented, resulting in an inexpensive and highly reliable power converter 1.

[0287] As shown in Figures 37 to 39, even with a power conversion device configuration that includes a smoothing capacitor and a snubber capacitor, it is possible to protect the semiconductor switching element from overvoltage when an overcurrent occurs. Furthermore, it goes without saying that even in a power conversion device that does not include a snubber capacitor, overcurrent protection of the semiconductor switching element can be implemented using the semiconductor drive device according to this embodiment.

[0288] Furthermore, the power converter 20X within the power conversion device 1 may be an inverter capable of multi-level voltage output. Also, the power converter 20Y within the power conversion device 1 is not limited to a boost converter, but may be a buck converter, or a buck-boost converter that combines a boost converter and a buck converter.

[0289] Furthermore, although the semiconductor switching element 50 is shown as an IGBT, other semiconductor switching elements having control terminals, such as MOSFETs, may also be used.

[0290] Furthermore, a multi-gate semiconductor switching element having multiple gate terminals may be used as the semiconductor switching element. Figure 40 shows an example of a power conversion device 1 using a double-gate semiconductor switching element 50wG. In the power conversion device 1 of Figure 40, for example, the semiconductor driving device 10 according to Embodiment 1 is applied as the semiconductor driving device 10, and as described in Embodiment 1, the semiconductor driving device 10 includes a gate driving unit 11 and an overcurrent protection unit 12 arranged between the double-gate semiconductor switching element 50wG and the gate driving unit 11. Also, as shown in Figure 40, the double-gate semiconductor switching element 50wG has two gate terminals G1 and G2, and by controlling the on / off timing of the two gate terminals G1 and G2, there are advantages such as improved turn-off speed.

[0291] In the single-gate conductor switching element described above, when the first overcurrent determination unit 13 detects an overcurrent, the gate voltage reduction unit 14 reduces the gate voltage Vge and the collector current Ic. In the double-gate semiconductor switching element 50wG, the gate terminals G1 and G2 can be controlled independently, so the voltage applied to each gate terminal can be controlled to reduce the voltage applied to the double-gate semiconductor switching element 50wG. For example, when an overcurrent is detected, the gate voltage Vge applied to the double-gate semiconductor switching element 50wG can be reduced and the collector current Ic reduced by reducing one gate terminal to below the gate threshold voltage Vth, or by turning off one gate terminal.

[0292] Similarly, when using a multi-gate semiconductor switching element, when overcurrent is detected, the gate voltage Vge applied to the multi-gate semiconductor switching element can be reduced by reducing the gate threshold voltage Vth or below at least one gate terminal, or by turning off at least one gate terminal, thereby reducing the collector current Ic. In this way, by using a semiconductor switching element with multiple gates, it becomes possible to finely control the gate voltage when an overcurrent occurs.

[0293] Furthermore, the off-gate current adjustment unit 18 can reduce the off-gate current flowing through each gate terminal, enabling more precise soft shutdown. Additionally, if the degree of reduction of the gate voltage Vge at each gate differs, it becomes possible to perform soft shutdown according to that reduction level.

[0294] Note that the power conversion device 1 in Figure 40 is not limited to the semiconductor drive device 10 according to Embodiment 1, but any of the semiconductor drive devices 10, 10C, 10D, 10E, 10F, or 10G according to Embodiments 2 to 7 may be used. Also, although Figure 40 shows an example in which the overcurrent protection unit 12 includes an off-gate current adjustment unit 18, the off-gate current adjustment unit 18 may be included in the gate drive unit 11. In this case, the power conversion device 1 in Figure 40 may be the semiconductor drive device 10G according to Embodiment 8.

[0295] Figure 41 shows another example of a power conversion device 1 using a double-gate semiconductor switching element 50 wG. In the power conversion device 1 of Figure 41, for example, the semiconductor driving device 10H according to Embodiment 9 is applied as the semiconductor driving device 10. As described in Embodiment 9, the semiconductor driving device 10 includes a gate driving unit 11 and an overcurrent protection unit 12 disposed between the switching element 50 wG and the gate driving unit 11.

[0296] Figure 41 shows the configuration of the power converter 20 of the power converter 1, specifically the semiconductor switching element of one arm, and simplifies the overall power converter 1. However, as in Embodiment 9, it goes without saying that a double-gate semiconductor switching element 50wG or a multi-gate semiconductor switching element may be used as the switching element in the power converter 20. When an overcurrent is detected flowing through the double-gate semiconductor switching element 50wG, the overcurrent protection unit 12 reduces the gate voltage applied to the two gate terminals G1 and G2, and the power converter 20 stops due to the output of the second overcurrent determination unit 17. The effects of the semiconductor drive device 10 in Figure 41 are the same as in Figure 40, so an explanation is omitted.

[0297] Note that the power converter 1 in Figure 41 is not limited to the semiconductor drive device 10H according to Embodiment 9, but may also be any of the semiconductor drive devices 10I, 10J, 10K, 10L, or 10M according to Embodiments 10 to 14. Also, although Figure 41 shows an example in which the overcurrent protection unit 12 includes an off-gate current adjustment unit 18, the off-gate current adjustment unit 18 may be included in the gate drive unit 11. In this case, the power converter 1 in Figure 41 applies the semiconductor drive device 10N according to Embodiment 15, and includes a protection operation detection unit 19 in the gate drive unit 11. Furthermore, in the power converter 1 in Figure 41, the second overcurrent determination unit 17 may be the second overcurrent determination unit 17A shown in Embodiment 10.

[0298] Furthermore, the power conversion device 1 shown in Figures 38 to 40 can also be configured using a double-gate type semiconductor switching element or a multi-gate type semiconductor switching element as the semiconductor switching element 50. Although an IGBT is shown as the double-gate type semiconductor switching element 50wG, other semiconductor switching elements having a gate terminal, such as a MOSFET, may also be used.

[0299] Figure 42 shows an example of the hardware configuration of the control unit 16 of the power converter 1 in the embodiments 1 to 16 described above. As shown in Figure 42, the control unit 16 includes, for example, a processor 1000 and a storage device 1100 as processing circuits.

[0300] The processor 1000 may include a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), an IC (Integrated Circuit), an FPGA (Field Programmable Gate Array), various logic circuits, and various signal processing circuits. Furthermore, the processor 1000 may consist of multiple processors of the same or different types, with each processor performing a portion of the processing.

[0301] The storage device 1100 includes a RAM (Random Access Memory) configured to allow data to be read from and written to the processor 1000, and a ROM (Read Only Memory) configured to allow data to be read from the processor 1000. The processor 1000 executes the program input from the storage device 1100, such as the ROM.

[0302] While this disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but are applicable individually or in various combinations to the embodiments. Accordingly, countless variations not illustrated are envisioned within the scope of the art disclosed in this specification. For example, these include modifying, adding or omitting at least one component, or even extracting at least one component and combining it with a component from another embodiment.

[0303] 1: Power converter, 10, 10C, 10D, 10E, 10F, 10G, 10H, 10I, 10J, 10K, 10L, 10M, 10N, 10X, 10Y, 10Z: Semiconductor drive unit, 11, 11G, 11H, 11N: Gate drive unit, 110, 110a, 110A, 110Aa, 110Ab, 110b: Output stage circuit, 12, 12a, 12b, 12A, 12B, 12C, 12Ca, 12D, 12Da, 12E, 12Ea, 12F, 12Fa, 12G: Overcurrent protection unit, 13, 13a, 13b, 13A, 13B, 13C, 13D, 13E, 13F: First overcurrent determination unit, 14, 14A: Gate voltage reduction unit, 15: Connection wiring, 16: Control unit, 17, 17A: Second overcurrent determination unit, 18, 18A, 18G: Off-gate current adjustment unit, 141, 141A: Drive circuit, 142, 142A: Amplification circuit, 19, 19b: Protection operation detection unit, 20, 20A, 20B, 20C, 20X, 20Y: Power converter, 21A, 21B: Upper arm, 22A, 22B: Lower arm, 23, 23A: Leg circuit, 40, 41, 42: Smoothing capacitor, 45, 46: Snubber capacitor, 50, 50A, 50B, 50a, 50b, 50Aa, 50Ab, 50Bb, 50C, 50Cb, 50wG: Semiconductor switching element, 60: DC power supply, 70, 70A: Load, 171: Logic synthesis unit, ICV, ICVa, ICVb: Isolated communication unit, CS: Collector sense terminal, CT: Current-voltage conversion element, D1, D1b: Clamp diode, D3, Dg1, Dg2, Dg5: Reverse current prevention diode, EEa, EEb: Current detection terminal, ES: Emitter control terminal, G, Ga, Gb, G1, G2: Gate terminal, OCD1, OCD2a, OCD2b: Decision signal, Q1, Q1b: First transistor, Q2, Q2b: Second transistor, Q3, Q3b: Third transistor, VA1, VA2: Input potential, (R, C1): Low-pass filter, (R, C1a): First low-pass filter, (R, C1b): Second low-pass filter, CRD: Constant current diode, (CRD, C1): Low-pass filter, LF1, LF2: Low-pass filter, Qg1: Transistor, RG1, RG1b, RG2, RG2b: Gate resistors, R10, RG3, RG4,RG4b: Resistor, Dg3: Protection diode, Dg4: Diode, VHD: First comparator, VLD: Second comparator, VHLD: Comparator, GDO, GDOa, GDOb: On / Off command signals.

Claims

A gate drive unit that applies a voltage to the control terminal of a semiconductor switching element to drive the semiconductor switching element on and off, The semiconductor switching element is protected by an overcurrent protection unit which includes a first overcurrent determination unit that receives a detection signal based on the voltage and current between the main terminals of the semiconductor switching element and determines an overcurrent flowing through the semiconductor switching element, a gate voltage reduction unit that reduces the voltage applied to the control terminal when the overcurrent is determined, and an off-gate current adjustment unit that adjusts the off-gate current flowing between the gate drive unit and the control terminal when the semiconductor switching element is turned off by the gate drive unit, The first overcurrent determination unit comprises a clamp diode that clamps the potential of the signal input section, which is the input section for the detection signal, to the potential of the control terminal, a first transistor to which the signal input section is connected, and a low-pass filter provided at the signal input section. When the potential of the signal input section reaches a set value, the first transistor turns on to determine the overcurrent of the semiconductor switching element. The off-gate current adjustment unit reduces the off-gate current when an overcurrent is detected by the first overcurrent detection unit, or when the voltage applied to the control terminal is reduced by the gate voltage reduction unit, in a semiconductor drive device. 　 A gate drive unit that applies a voltage to the control terminal of a semiconductor switching element to drive the semiconductor switching element on and off, The semiconductor switching element is protected by an overcurrent protection unit which includes a first overcurrent determination unit that receives a detection signal based on the voltage and current between the main terminals of the semiconductor switching element to determine the overcurrent flowing through the semiconductor switching element, and a gate voltage reduction unit that reduces the voltage applied to the control terminal when the overcurrent is determined. The first overcurrent determination unit comprises a clamp diode that clamps the potential of the signal input section, which is the input section for the detection signal, to the potential of the control terminal, a first transistor to which the signal input section is connected, and a low-pass filter provided at the signal input section. When the potential of the signal input section reaches a set value, the first transistor turns on to determine the overcurrent of the semiconductor switching element. The gate drive unit includes a protection operation detection unit that detects when the voltage applied to the control terminal is reduced, and an off-gate current adjustment unit that adjusts the off-gate current flowing between the gate drive unit and the control terminal when the semiconductor switching element is turned off. A semiconductor drive device in which, based on a signal from the protection operation detection unit, the off-gate current adjustment unit reduces the off-gate current and keeps the semiconductor switching element in the off state. 　 The semiconductor drive device according to claim 1, wherein the off-gate current adjustment unit has a parallel configuration of a second transistor and a first resistor connected in parallel, disposed between the gate drive unit and the control terminal of the semiconductor switching element, a first reverse current prevention diode is connected to the control terminal of the second transistor, and when an overcurrent determination signal is input by the first overcurrent determination unit via the first reverse current prevention diode, or when a signal of reduced voltage applied to the control terminal of the semiconductor switching element is input by the gate voltage reduction unit via the first reverse current prevention diode, the second transistor is turned off and the off-gate current flows through the first resistor. 　 The semiconductor drive device according to claim 3, wherein a second reverse current prevention diode is provided on the emitter side of the second transistor. 　 The gate voltage reduction unit has a series configuration in which a second resistor and a third transistor are connected in series. Upon receiving an overcurrent detection signal from the first overcurrent detection unit, the third transistor turns on and discharges the charge accumulated from the control terminal of the semiconductor switching element through the second resistor, thereby reducing the voltage applied to the control terminal of the semiconductor switching element. The semiconductor drive device according to claim 3 or 4, wherein the resistance value of the second resistor is smaller than the resistance value of the first resistor of the off-gate current adjustment unit. 　 The semiconductor driving device according to claim 5, wherein the value of the second resistor of the gate voltage reduction unit is greater than the resistance value of the on-gate resistor that limits the on-gate current of the gate driving unit. 　 The off-gate current adjustment unit has a second transistor connected in parallel to an off-gate resistor that limits the off-gate current of the gate drive unit, and a parallel configuration in which a first resistor is connected in parallel to the series configuration of the off-gate resistor and the second transistor, wherein the resistance value of the first resistor is greater than the resistance value of the off-gate resistor. The semiconductor drive device according to claim 2, wherein, based on the signal from the protection operation detection unit, the second transistor is turned off and the off-gate current flows through the first resistor. 　 The semiconductor drive device according to any one of claims 1 to 7, wherein the low-pass filter of the signal input section comprises a first low-pass filter that is clamped to the potential of the control terminal of the semiconductor switching element by the clamp diode, and a second low-pass filter that has a capacitance greater than that of the first low-pass filter and is not clamped to the potential of the control terminal of the semiconductor switching element. 　 The semiconductor drive device according to any one of claims 1 to 8, wherein the clamp diode clamps the potential of the input portion of the detection signal to the potential of the control terminal when the semiconductor switching element is in the off state. 　 The semiconductor drive device according to any one of claims 1 to 9, wherein the gate voltage reduction unit comprises a drive circuit that reduces the voltage applied to the control terminal of the semiconductor switching element, and an amplification circuit that amplifies the output signal from the first overcurrent determination unit to drive the drive circuit. 　 The amplification circuit of the gate voltage reduction unit has a fourth transistor, and the drive circuit of the gate voltage reduction unit has a third transistor. The first transistor, the third transistor, and the fourth transistor are each bipolar transistors, and when the first transistor is turned on, the fourth transistor turns on, and then the third transistor turns on, and the base currents of the first transistor, the fourth transistor, and the third transistor increase in that order. The voltage applied to the control terminal of the semiconductor switching element is reduced by the main terminal current of the third transistor. The semiconductor drive device according to claim 10. 　 The first overcurrent determination unit is: The voltage between the main terminals of the semiconductor switching element, The current detected by the current detection element for detecting the main terminal current of the semiconductor switching element or a similar small current, The voltage generated between the low-voltage main terminal and the control reference terminal of the semiconductor switching element, The overcurrent of the semiconductor switching element is determined by either the detection signal based on the voltage conversion of the rate of change of the main terminal current of the semiconductor switching element, or the detection signal based on the voltage conversion of the rate of change of the main terminal current of the semiconductor switching element. A semiconductor drive device according to any one of claims 1 to 11. 　 The semiconductor switching element is a multi-gate type semiconductor switching element having at least two control terminals, The semiconductor driving device according to any one of claims 1 to 12, wherein the gate voltage reduction unit reduces the voltage of at least one control terminal of the multi-gate semiconductor switching element to or below the gate threshold voltage when an overcurrent is determined by the first overcurrent determination unit. 　 A power converter comprising at least one leg circuit in which an upper arm and a lower arm, each having the aforementioned semiconductor switching element, are connected in series, A power conversion device comprising, for each of the semiconductor switching elements, a semiconductor driving device according to any one of claims 1 to 13 for driving the semiconductor switching element. 　 A power converter having at least one leg circuit formed by connecting the semiconductor switching elements in series, A power conversion device comprising a semiconductor drive device according to any one of claims 1 to 13, which applies a voltage to the control terminal of the semiconductor switching element to drive the semiconductor switching element on and off, The semiconductor drive device, A control unit that generates an on / off command signal that determines the on / off state of the semiconductor switching element and outputs it to the gate drive unit, The system further includes a second overcurrent determination unit that uses the power supply voltage of a DC power supply as a reference voltage and determines the overcurrent of the semiconductor switching element based on the potential of the output terminal of the REG circuit, The overcurrent determination in the first overcurrent determination unit precedes the overcurrent determination in the second overcurrent determination unit. The control unit controls at least the semiconductor switching elements of the leg circuit that have been determined to be overcurrent to be in an off state when the second overcurrent determination unit determines that an overcurrent has occurred, and is a power conversion device. 　 The first overcurrent determination unit and the second overcurrent determination unit each include a filter element that sets the time from the point in time when the signal input to them is in an overcurrent state until the first overcurrent determination unit and the second overcurrent determination unit determine that it is an overcurrent. The power conversion device according to claim 15, wherein the time constant of the second filter element provided in the second overcurrent determination unit is greater than the time constant of the first filter element provided in the first overcurrent determination unit, and the time from when an overcurrent state signal is input to the second overcurrent determination unit until an overcurrent determination is made is shorter than the short-circuit tolerance time determined by the short-circuit withstand capability of the semiconductor switching element. 　 The power conversion device according to claim 15 or 16, wherein the gate voltage reduction unit, when an overcurrent is determined by the first overcurrent determination unit, continues to reduce the voltage applied to the control terminal of the semiconductor switching element for a longer period than the time difference between the time the first overcurrent determination unit determines an overcurrent and the time the second overcurrent determination unit determines an overcurrent. 　 The second overcurrent determination unit is: The system comprises a first comparator that determines whether the potential of the output terminal of the leg circuit is near the positive potential of the DC power supply, and a second comparator that determines whether the potential of the output terminal of the leg circuit is near the negative potential of the DC power supply. A power conversion device according to any one of claims 15 to 17, wherein an overcurrent of the semiconductor switching element is determined based on the output signal of the first comparator, the output signal of the second comparator, and the on / off command signal generated by the control unit. 　 The control unit, The power conversion device according to claim 18, wherein the on / off command signal is generated using at least one of the output signal of the first comparator and the output signal of the second comparator. 　 The second overcurrent determination unit includes a third comparator that determines whether the potential of the output terminal of the REG circuit is near the positive or negative potential of the DC power supply. The power conversion device according to any one of claims 15 to 17, wherein, based on the on / off command signal generated by the control unit, the reference voltage input to the third comparator is switched between a voltage for detecting a potential near the positive electrode potential and a voltage for detecting a potential near the negative electrode potential. 　 The second overcurrent determination unit is: The power conversion device according to any one of claims 15 to 20, wherein, during the period when the semiconductor switching elements connected in series in the leg circuit are both turned off, an abnormality in the main breakdown voltage of the semiconductor switching elements is determined based on the potential of the output terminal of the leg circuit input to the second overcurrent determination unit. 　 An inverter that converts the DC voltage between the positive and negative terminals of the aforementioned leg circuit into an AC voltage. Alternatively, a boost or buck converter equipped with a reactor between the DC power supply and the reg circuit, Alternatively, the power conversion device according to any one of claims 15 to 21, which is a boost or buck inverter system combining the inverter and the boost or buck converter.

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