Wiring board, electronic device, and electronic module

Abstract

This wiring board comprises: a plate-shaped insulating base having a first surface, which has a mounting region of an integrated circuit, and a second surface opposite to the first surface; an electrode pad located in the mounting region; and a wiring conductor located inside the insulating base and electrically connected to the electrode pad. The wiring conductor includes a via conductor group in which a plurality of first via conductors connected to the electrode pad are gathered together. The wiring board further comprises a plurality of supplementary via conductors that are located on a side part of the via conductor group in a plan perspective view and do not have electrical connection with the wiring conductor except for a ground conductor.

Description

Wiring Board, Electronic Device, and Electronic Module

[0001] The present disclosure relates to a wiring board, an electronic device, and an electronic module.

[0002] Japanese Patent Application Laid-Open No. 2003-249750 describes a technique for reducing the warpage of a wiring board by alternately reversing the punching directions of a plurality of through holes through which via conductors pass.

[0003] The wiring board according to the present disclosure includes: a plate-like insulating substrate having a first surface with a mounting area for an integrated circuit and a second surface opposite to the first surface; electrode pads located in the mounting area; and wiring conductors located inside the insulating substrate and electrically connected to the electrode pads. The wiring conductors include a via conductor group in which a plurality of first via conductors connected to the electrode pads gather together, and further include a plurality of supplementary via conductors located on the side portions of the via conductor group in a planar perspective view and having no electrical connection with the wiring conductors except for a ground conductor.

[0004] The electronic device according to the present disclosure includes the above-described wiring board and an integrated circuit mounted on the wiring board.

[0005] The electronic module according to the present disclosure includes the above-described electronic device and a module substrate on which the electronic device is mounted.

[0006] This is a plan view showing a wiring board of Embodiment 1 of the present invention. This is a side view showing a wiring board of Embodiment 1 of the present invention. This is an enlarged plan view showing the main part of the wiring board of Embodiment 1. This is a side view showing the main part of the wiring board of Embodiment 1. This is a plan view illustrating the warp of the wiring board of Embodiment 1. This is a schematic diagram showing a cross-section of line B-B illustrating the warp of the wiring board of Embodiment 1. This is a plan view illustrating the warp of a wiring board of a comparative example. This is a schematic diagram showing a cross-section of line B-B illustrating the warp of a wiring board of a comparative example. This is a plan view showing a wiring board of Embodiment 2. This is a side view showing a wiring board of Embodiment 3. This is an enlarged plan view showing a wiring board of Embodiment 4. This is a side view showing a wiring board of Embodiment 4. This is an enlarged plan view showing a wiring board of Embodiment 5. This is a side view showing a wiring board of Embodiment 5. This is an enlarged plan view showing a wiring board of Embodiment 6. This is a side view showing a wiring board of Embodiment 6. This is a side view showing a wiring board of Embodiment 7. This is a side view showing a wiring board of Embodiment 8. This is a side view showing a wiring board of Embodiment 9. This is a diagram showing an electronic device and an electronic module of an embodiment of the present invention.

[0007] Each embodiment of this disclosure will be described in detail below with reference to the drawings. Hereinafter, the direction from the first surface S1 to the second surface S2 will be referred to as "downward," and the direction opposite to that direction will be referred to as "upward." Furthermore, the position below the first surface S1 will be referred to as "depth," and the direction along the first surface S1 will be referred to as the "horizontal direction."Hereinafter, "plane perspective" means perspective viewing from a direction perpendicular to the first surface S1.

[0008] (Embodiment 1) Figures 1A and 1B are a plan view and a side view, respectively, of a wiring board 1 according to Embodiment 1 of the present invention. Figures 2A and 2B are an enlarged plan view and a side view, respectively, of the main parts of the wiring board 1 according to Embodiment 1. In these figures, for components that have multiple parts, only a few are given reference numerals as representative. The same applies to the following drawings.

[0009] As shown in Figures 1A and 1B, the wiring board 1 of Embodiment 1 is a substrate having a mounting area A1 on which an integrated circuit 100, such as a semiconductor element, is connected via a flip-chip connection. The integrated circuit 100 has a plurality of electrodes 111 arranged in an array. The wiring board 1 has a plurality of electrode pads 21 in the mounting area A1 that are arranged in the same way as the electrodes 111 of the integrated circuit 100. The electrode pads 21 may be configured to be electrically connected to the electrodes 111 of the integrated circuit 100. Then, the plurality of electrodes 111 of the integrated circuit 100 are each connected to the plurality of electrode pads 21 of the wiring board 1 via a bonding material such as a solder bump.

[0010] As shown in Figures 2A and 2B, the wiring board 1 includes a plate-shaped insulating substrate 10 having a first surface S1 and a second surface S2, a plurality of electrode pads 21 located on the first surface S1, a wiring conductor 30 located inside the insulating substrate 10, and a plurality of supplementary via conductors 40 located inside the insulating substrate 10. The wiring board 1 may further include a plurality of electrode pads 51 located on the second surface S2.

[0011] The wiring board 1 may be mounted on another wiring board, such as a module board, with the mounting area A1 located on the first surface S1 and the second surface S2 connected to the other wiring board. The multiple electrode pads 21 on the first surface S1 may be arranged at a narrow pitch to match the electrodes 111 of the integrated circuit 100, while the multiple electrode pads 51 on the second surface S2 may be arranged at a wider pitch. The electrode pads 21 on the first surface S1 and the electrode pads 51 on the second surface S2 may be electrically connected by a wiring conductor 30. In this configuration, the wiring board 1 may be interposed between the module board and the integrated circuit 100, playing a role in electrically connecting the two. The wiring board 1 may also play a role in receiving heat from the integrated circuit 100 and dissipating that heat to the surrounding heat sink.

[0012] The insulating substrate 10 may have a plurality of laminated insulating layers 11, as shown in Figure 2B. The insulating substrate 10 may be an aluminum nitride sintered body, an aluminum oxide sintered body, a silicon carbide sintered body, a mullite sintered body, or a ceramic sintered body such as glass ceramics. Alternatively, the insulating substrate 10 may be an organic resin, or an organic resin containing an inorganic filler.

[0013] The wiring conductor 30 may include a plurality of film-like conductors 31 extending along one surface of the insulating layer 11 and a plurality of via conductors 32 penetrating the insulating layer 11. The via conductors 32 may include a first via conductor 321 connected to the electrode pad 21 and a second via conductor 322 that is physically connected to the film-like conductor 31 and physically separated from the electrode pad 21. The first via conductor 321 may be physically connected to the electrode pad 21. Furthermore, the wiring conductor 30 may have a via conductor group G1 in which a plurality of first via conductors 321 are clustered together. In the illustration, all of the plurality of first via conductors 321 belong to one via conductor group G1. However, the plurality of first via conductors 321 may include first via conductors 321 that are not included in the via conductor group G1 and are dispersed. Also, the wiring conductor 30 may have multiple sets of via conductor groups G1.

[0014] The via conductor 32 may be a conductor extending in a direction perpendicular to the first surface S1. The plurality of film conductors 31 and plurality of via conductors 32 may include conductors connected to the signal electrodes of the integrated circuit 100 and transmitting signals, and ground conductors connected to the ground potential. The first via conductor 321 corresponds to a via conductor 32 located so as to penetrate the uppermost insulating layer 11 or a plurality of insulating layers including the uppermost insulating layer 11. In the illustration, one first via conductor 321 is connected to one electrode pad 21. However, the plurality of electrode pads 21 may include large electrode pads, and a plurality of first via conductors 321 may be connected to one large electrode pad.

[0015] Furthermore, the via conductor group G1 may be a collection of thermal vias intended to draw heat away from the integrated circuit 100. In the case of a collection of thermal vias, the electrode pad 21 may have a large area, and a plurality of first via conductors 321, which are thermal vias, may be connected to one electrode pad 21. Also, the plurality of first via conductors 321, which are thermal vias, may be via conductors that extend from the first surface S1 to the second surface S2. When the via conductor group G1 is a collection of thermal vias, the wiring board 1 may have other via conductor groups that transmit signals from the integrated circuit 100.

[0016] <Supplementary via conductors> Multiple supplementary via conductors 40 are located on the side of the via conductor group G1 in a planar view. "Located on the side of the via conductor group G1 in a planar view" means that in a planar view, they are in the vicinity of the via conductor group G1 and located in at least a part of the periphery of the via conductor group G1. Multiple supplementary via conductors 40 may come together to form one or more supplementary via conductor groups (for example, a first supplementary via conductor group G40a and a second supplementary via conductor group G40b). In this case, "located on the side of the via conductor group G1 in a planar view" means that in a planar view, a part of the supplementary via conductor group is located in the vicinity of the via conductor group G1 and located in at least a part of the periphery of the via conductor group G1. "Nearby" is defined as the distance to the nearest first via conductor 321 included in the via conductor group G1 in a planar view being 80% or less of the width of the via conductor group G1 (i.e., the average width from the above side to the opposite side). The above definition of distance may be 50% or less, or 25% or less, of the above width.

[0017] The multiple supplemental via conductors 40 may be configured not to be electrically connected to the wiring conductor 30, as shown in Figure 2B. Supplemental via conductors 40 in this configuration may be called dummy via conductors. This configuration reduces the electrical interference that the supplemental via conductors 40 may cause to the integrated circuit 100. Although not shown in the figure, the multiple supplemental via conductors 40 may include one that is connected to a ground conductor. The ground conductor may be a ground conductor included in the wiring conductor 30. By connecting to a ground conductor, the electrical interference that the supplemental via conductors 40 may cause to the integrated circuit 100 can be reduced.

[0018] Some or all of the multiple supplemental via conductors 40 may form one or more groups that are clustered together in a planar perspective view. In the example shown in Figure 2A, the wiring board 1 has a first supplemental via conductor group G40a, which is a cluster of some of the multiple supplemental via conductors 40, and a second supplemental via conductor group G40b, which is a cluster of other parts of the multiple supplemental via conductors 40. The first supplemental via conductor group G40a is located on one side of the via conductor group G1, and the second supplemental via conductor group G40b is located on the other side of the via conductor group G1.

[0019] Figures 3A and 3B are a plan view illustrating the warp of the wiring board 1 of Embodiment 1 and a schematic diagram showing a cross-section along line B-B. Figures 4A and 4B are a plan view illustrating the warp of the wiring board 80 of the comparative example and a schematic diagram showing a cross-section along line B-B. Figures 3B and 4B depict the warp in an exaggerated manner. The wiring board 80 of the comparative example has the same configuration as the wiring board 1 of Embodiment 1, but without the supplementary via conductor 40.

[0020] In the absence of supplementary via conductors 40, as in the comparative example wiring board 80, a region P80 appears near the mounting area A1 of the integrated circuit 100 where the gradient of the distribution density of via conductors becomes steep. This causes warping in the region P80. As a result, as shown in Figure 4B, the amount of warping B80 of the wiring board 80 becomes relatively large, and the flatness of the mounting area A1 decreases. On the other hand, in the wiring board 1 of Embodiment 1, the multiple supplementary via conductors 40 are located on the side of the via conductor group G1, which allows the region where the gradient of the distribution density of via conductors becomes steep to be moved away from the mounting area A1, or the gradient of the distribution density of via conductors to be mitigated. Therefore, the amount of warping B1 of the wiring board 1 can be reduced, and the area that causes warping can be moved away from the mounting area A1, thereby improving the flatness of the mounting area A1.

[0021] <Details of Supplementary Via Conductors> As shown in Figure 2B, at least a portion of each of the multiple supplementary via conductors 40 may be located above half the depth D1 of the insulating substrate 10. In the wiring board 1, the density of via conductors 32 is high at a depth close to the first surface S1 of the mounting area A1 of the integrated circuit 100. Therefore, by positioning the supplementary via conductors 40 as described above, the gradient of the conductor distribution density can be made gentler at a depth close to the first surface S1. Consequently, the warping of the wiring board 1 in the vicinity of the mounting area A1 can be reduced.

[0022] The multiple supplemental via conductors 40 may be spaced apart from the first surface S1 and the second surface S2, as shown in Figure 2B. By being spaced apart from the first surface S1, it is possible to reduce the appearance of structures such as bulges caused by the supplemental via conductors 40 on the first surface S1. Therefore, interference between the integrated circuit 100 and the above structure can be reduced. Similarly, by being spaced apart from the second surface S2, it is possible to reduce the appearance of structures such as bulges caused by the supplemental via conductors 40 on the second surface S2. Therefore, interference between the above structure and a configuration connected on the second surface S2 side (for example, the module substrate 210 in Figure 13) can be reduced.

[0023] As shown in Figure 2B, the multiple supplementary via conductors 40 may have a length of 50% or more of the thickness T10 of the insulating substrate 10. With this configuration, the difference in the distribution density of conductors below the periphery of the mounting area A1 can be reduced over most of the depth direction of the wiring board 1. Therefore, the warping of the wiring board 1 in the mounting area A1 can be made smaller.

[0024] As shown in Figure 2A, the multiple supplemental via conductors 40 may have the same diameter φ40 and pitch Pch40 as the first via conductor 321, which has a diameter φ321 (e.g., 40 μm or more and 100 μm or less) and pitch Pch321 (e.g., 130 μm or more and 500 μm or less). Pitch refers to the distance between the centers of adjacent via conductors 32 (or adjacent pair of supplemental via conductors 40). "Same" is not limited to strictly identical, but includes cases where the error is within ±10%. This configuration makes it possible to bring the distribution density of conductors closer in the regions where the via conductor group G1 and the supplemental via conductors 40 are located. Therefore, the warping of the wiring board 1 in the mounting region A1 can be further reduced.

[0025] (Embodiment 2-9) Next, the wiring boards 1A to 1H of Embodiments 2 to 9 will be described. The wiring boards 1A to 1H of Embodiments 2 to 9 differ mainly in the configuration of a part of the supplementary via conductor 40, while the other configurations are the same as in Embodiment 1. The wiring boards 1B, 1F, 1G, and 1H of Embodiments 3, 7, 8, and 9 have a unique configuration when the supplementary via conductor 40 is viewed from the side, and the wiring boards 1A, 1C, 1D, and 1E of Embodiments 2, 4, 5, and 6 have a unique configuration when the supplementary via conductor 40 is viewed from above. The unique configurations shown in wiring boards 1B, 1F, 1G, and 1H may also be applied to wiring boards 1, 1A, 1C, 1D, and 1E. The unique configurations shown in wiring boards 1A, 1C, 1D, and 1E may also be applied to wiring boards 1, 1B, 1F, 1G, and 1H.

[0026] Figure 5 is a plan view showing a wiring board 1A according to Embodiment 2. The film-like conductor 31, the first via conductor 321, and the second via conductor 322, which are elements of the wiring conductor 30, are arranged according to the required wiring pattern, and may be unevenly distributed around the center of the mounting area A1. As a result, areas with high and low conductor distribution density occur unevenly in the mounting area A1 and below its periphery, which can make warping more likely to occur in the uneven areas of the mounting area A1 and its periphery. The example in Figure 5 shows a wiring board 1A in which warping is likely to occur in the area R11 to the right of the mounting area A1, assuming that the supplementary via conductor 40 is absent.

[0027] As described above, if the wiring conductor 30 is prone to warping in the biased region R11, a configuration may be adopted in which a supplementary via conductor 40 is located on one side of the via conductor group G1, while the supplementary via conductor 40 is not located on the remaining three sides of the via conductor group G1, as shown in Figure 5. By positioning the supplementary via conductor 40 in this biased arrangement, the effect of warping that would have occurred in the biased region R11 of the mounting area A1 if the supplementary via conductor 40 were not present can be neutralized, thereby reducing the overall warping in the mounting area A1.

[0028] In Figure 5, an example is shown where the supplementary via conductors 40 are located on only one of the four sides surrounding the mounting area A1. However, the areas prone to warping vary considerably depending on the wiring pattern of the wiring conductor 30 and the planar shape of the mounting area A1. Therefore, the arrangement of the supplementary via conductors 40 should be determined according to the areas prone to warping. For example, the supplementary via conductors 40 may be located on all four sides surrounding the mounting area A1 in a planar perspective view, or on the left and right sides as shown in Figure 1A, or on the top and bottom sides, or on either one of them. Furthermore, depending on the amount of force and the area prone to warping, supplementary via conductor groups of various sizes and shapes may be used.

[0029] Figure 6 is a side view showing a wiring board 1B according to Embodiment 3. The supplementary via conductor 40 may extend to the first surface S1, as shown in Figure 6. In this case, the supplementary via conductor 40 may be covered with an insulator 45 such as solder resist so as not to be exposed to the outside on the first surface S1. There may be no electrode pads connected to the supplementary via conductor 40 on the first surface S1. With this configuration, the supplementary via conductor 40 can be positioned near the first surface S1 where the density of the first via conductor 321 is high, while reducing the interference of the supplementary via conductor 40 with the integrated circuit 100. Therefore, the gradient of the conductor distribution density can be mitigated even at depths near the first surface S1, and the warping of the wiring board 1B in the mounting area A1 can be made smaller.

[0030] Although not shown in the diagram, the supplementary via conductor 40 may extend to the second surface S2. In this case, the supplementary via conductor 40 may be covered with an insulator such as solder resist so as not to be exposed to the outside on the second surface S2. There may be no electrode pads connected to the supplementary via conductor 40 on the second surface S2. With this configuration, the supplementary via conductor 40 can be positioned close to the second surface S2 while reducing interference with the configuration connected to the second surface S2 side of the wiring board 1B (for example, a module board). Therefore, when the density of the via conductor group G1 is high even at a depth close to the second surface S2, the supplementary via conductor 40 can mitigate the gradient of the conductor distribution density at that depth. Therefore, even in this case, the warping of the wiring board 1B can be reduced and the flatness of the mounting area A1 can be further improved.

[0031] Furthermore, the supplementary via conductor 40 may be configured to extend from the first surface S1 to the second surface S2.

[0032] Figures 7A and 7B are an enlarged plan view and a side view, respectively, of the wiring board 1C according to Embodiment 4. As shown in the figures, the supplemental via conductor 40 may have a larger diameter φ40c (e.g., 75 μm) and a larger pitch Pch40c (e.g., 200 μm) compared to the diameter φ321 (e.g., 50 μm) and pitch Pch321 (e.g., 150 μm) of the first via conductor 321. By increasing the pitch Pch40c, the complexity of the process of forming the supplemental via conductor 40 can be reduced, and productivity can be improved. Furthermore, by increasing the diameter φ40c, the distribution density of conductors can be brought closer in the regions where the via conductor group G1 and the supplemental via conductor 40 are located. Therefore, the gradient of the conductor density distribution can be mitigated, and the warping of the wiring board 1C in the mounting region A1 can be reduced.

[0033] Figures 8A and 8B are an enlarged plan view and a side view, respectively, of the wiring board 1D according to Embodiment 5. As shown in the figures, the supplemental via conductor 40 may have a smaller diameter φ40d (e.g., 50 μm) and a smaller pitch Pch40d (e.g., 150 μm) compared to the diameter φ321d (e.g., 75 μm) and pitch Pch321d (e.g., 200 μm) of the first via conductor 321. By reducing the pitch Pch40d, the change in the distribution density of conductors below the side of the via conductor group G1 can be smoothed out, enabling fine control of the stress applied to that area. Furthermore, by reducing the diameter, the distribution density of conductors can be brought closer in the regions where the via conductor group G1 and the supplemental via conductor 40 are located. Therefore, the gradient of the conductor distribution density can be mitigated, and the warping of the wiring board 1D in the mounting area A1 can be reduced.

[0034] Figures 9A and 9B are an enlarged plan view and a side view, respectively, of a wiring board 1E according to Embodiment 6. The pitch of the supplemental via conductor 40 may be a pitch Pch40e (e.g., 300 μm) which is n times the pitch Pch321 (e.g., 150 μm) of the first via conductor 321 (e.g., 150 μm), as shown in the figures. This configuration corresponds to a configuration in which some supplemental via conductors 40 are thinned out from a configuration in which multiple supplemental via conductors 40 are formed at the same pitch as the first via conductor 321 during the design phase. With this configuration, the conductor density in the region where the supplemental via conductor 40 is located can be easily adjusted at the design stage. Furthermore, by reducing the number of supplemental via conductors 40, the complexity of the process of forming the supplemental via conductors 40 is reduced, and productivity can be improved.

[0035] In addition, in the via conductor group G1 of the wiring boards 1C to 1E of Embodiments 4 to 6, a configuration in which the diameter and pitch of the first via conductor 321 differ depending on the location may be adopted. In this configuration, the diameter and pitch of the first via conductor 321 described above may be read as the diameter and pitch of the first via conductor 321 in a region of the via conductor group G1 that is adjacent to the supplementary via conductor 40 and has the same area as the supplementary via conductor group (specifically, the first supplementary via conductor group G40a or the second supplementary via conductor group G40b) in a planar perspective view.

[0036] Figure 10 is a side view showing a wiring board 1F according to Embodiment 7. At least one of the multiple supplementary via conductors 40 includes a plurality of series via conductors 41 arranged in a single row in the vertical direction, and the plurality of series via conductors 41 may be arranged with gaps 11a connected to one or more insulating layers 11 in between. As in the example of Figure 10, each of the plurality of series via conductors 41 has the length of one layer of the insulating layer 11, while the gaps 11a similarly have the length of one layer of the insulating layer 11, and the series via conductors 41 and gaps 11a may be arranged alternately with each layer of the insulating layer 11. Note that a configuration in which any of the series via conductors 41 have the length of two or more layers may be adopted. A configuration in which any of the gaps 11a have the length of two or more layers may be adopted.

[0037] This configuration allows for adjustment to slightly lower the distribution density of the conductors by inserting a gap 11a in the middle of the supplementary via conductor 40. Therefore, the distribution density of the supplementary via conductor 40 can be matched to the distribution density of the conductors below the via conductor group G1. As a result, the warping of the wiring board 1F in the mounting area A1 can be further reduced.

[0038] Figure 11 is a side view showing a wiring board 1G according to Embodiment 8. The multiple supplementary via conductors 40 may be configured to be located on the first surface S1 side from half the depth D1 of the insulating substrate 10, as shown in the figure, and not on the second surface S2 side from half the depth D1 of the insulating substrate 10. Below half the depth D1 of the insulating substrate 10, the density of via conductors 32 may decrease as the wiring conductors 30 spread out horizontally. Furthermore, in the region where the supplementary via conductors 40 are located, reducing the distribution density of conductors below half the depth D1 of the insulating substrate 10 may reduce the warping of the wiring board 1G. With the above configuration, the warping of the wiring board 1G in the mounting region A1 can be further reduced in response to this case.

[0039] Figure 12 is a side view showing a wiring board 1H according to Embodiment 9. At least one of the multiple supplementary via conductors 40 includes multiple series via conductors 41a, 41b arranged in a line vertically with a gap 11a in between, and the length L1 of the series via conductor 41a closer to the first surface S1 may be greater than the individual lengths L2 of the series via conductors 41b closer to the second surface S2. In the region where the supplementary via conductors 40 are located, increasing the distribution density of conductors on the first surface S1 side and slightly decreasing the distribution density of conductors on the second surface S2 side may reduce the warping of the wiring board 1H. With the above configuration, the warping of the wiring board 1H in the mounting region A1 can be further reduced in response to this case.

[0040] Furthermore, two or more of the supplementary via conductors 40 shown in Embodiments 1, 3, and 7-9 may be mixed together on a single wiring board 1. With this configuration, if there are differences in the distribution density of via conductors 32 that induce warping of the wiring board 1 at multiple locations in different positions in the horizontal direction, the distribution density of the supplementary via conductors 40 can be adjusted to reduce warping at each location in accordance with these differences.

[0041] (Electronic Device) Figure 13 is a side view showing an electronic device 150 and an electronic module 200 according to an embodiment of the present disclosure. The electronic device 150 of this embodiment comprises a wiring board 1 as shown in Embodiment 1 and an integrated circuit 100 mounted on the mounting area A1. The integrated circuit 100 has a plurality of electrodes on its lower surface and is flip-chip connected to a plurality of electrode pads 21 of the wiring board 1.

[0042] The electronic module 200 of this embodiment comprises a module substrate 210 and an electronic device 150 mounted on the module substrate 210. In addition to the electronic device 150, various types of electronic components, electrical components, etc., may be mounted on the module substrate 210.

[0043] The electronic device 150 has a plurality of electrode pads 51 on the second surface S2 of the wiring board 1, while the module board 210 has a plurality of connection terminals 212. The plurality of electrode pads 51 of the electronic device 150 are flip-chip connected to the plurality of connection terminals 212 of the module board 210 via a bonding material 230.

[0044] In the electronic device 150 and the electronic module 200 of the present embodiment, the wiring board 1 may be substituted for the wiring boards 1A to 1H of the other embodiments described above.

[0045] According to the electronic device 150 and the electronic module 200 of the present embodiment, since the warp of the wiring board 1 is reduced in the mounting area A1, the workability when mounting the integrated circuit 100 can be improved, and the reliability of the mounting can also be improved.

[0046] The embodiments of the present disclosure have been described above. However, the wiring board and the electronic device of the present disclosure are not limited to the above embodiments. The details shown in the embodiments can be appropriately changed without departing from the spirit of the invention.

[0047] Hereinafter, an embodiment of the present disclosure will be shown. In one embodiment, (1) The wiring board includes a plate-shaped insulating substrate having a first surface with a mounting area for an integrated circuit and a second surface opposite to the first surface, an electrode pad located in the mounting area, and a wiring conductor located inside the insulating substrate and electrically connected to the electrode pad. The wiring conductor includes a via conductor group in which a plurality of first via conductors connected to the electrode pad gather together, and further includes a plurality of supplementary via conductors located on the side of the via conductor group in a plan view and having no electrical connection with the wiring conductor except for the ground conductor.

[0048] (2) In the wiring board of (1) above, at least a part of each of the plurality of supplementary via conductors is located on the first surface side rather than half the depth of the insulating substrate.

[0049] (3) In the wiring board of (1) or (2) above, the plurality of supplementary via conductors are separated from the first surface and the second surface.

[0050] (4) In the wiring board of (1) or (2) above, the plurality of supplementary via conductors are located up to at least one of the first surface and the second surface, and further includes an insulating material covering the range where the supplementary via conductors are located on the first surface or the second surface.

[0051] (5) In any one of the wiring boards described in (1) to (4) above, the plurality of supplementary via conductors have the same diameter as each via conductor belonging to the via conductor group and are arranged at the same pitch in a planar perspective view.

[0052] (6) Any one of the wiring boards described in (1) to (4) above, wherein the diameter of the plurality of supplementary via conductors is greater than the diameter of each via conductor belonging to the via conductor group, and the pitch of the plurality of supplementary via conductors is greater than the pitch of the plurality of first via conductors belonging to the via conductor group.

[0053] (7) Any one of the wiring boards described in (1) to (4) above, wherein the diameter of the plurality of supplementary via conductors is smaller than the diameter of each via conductor belonging to the via conductor group, and the pitch of the plurality of supplementary via conductors is smaller than the pitch of the plurality of first via conductors belonging to the via conductor group.

[0054] (8) In any one of the wiring boards described in (1) to (4) above, the pitch of the plurality of supplementary via conductors is n times the pitch of the plurality of first via conductors belonging to the via conductor group (where n is an integer from 2 to 4).

[0055] (9) In any one of the wiring boards described in (1) to (8) above, the plurality of supplemental via conductors have a length of 50% or more of the thickness of the insulating substrate.

[0056] (10) Any one of the wiring boards described in (1) to (8) above, wherein the insulating substrate has a structure in which a plurality of insulating layers are stacked, at least one of the plurality of supplementary via conductors includes a plurality of series via conductors arranged in a row in the vertical direction, and the plurality of series via conductors are arranged with a gap connected to one or more of the insulating layers in between.

[0057] (11) In any one of the wiring boards described in (1) to (8) above, the plurality of supplementary via conductors are located on the first surface side from half the depth of the insulating substrate and not on the second surface side from half the depth of the insulating substrate.

[0058] In one embodiment, (12) the electronic device comprises one of the wiring boards described in (1) to (11) above, and an integrated circuit mounted on the wiring board.

[0059] In one embodiment, (13) the electronic module comprises the electronic device described in (12) above and a module substrate on which the electronic device is mounted.

[0060] This disclosure can be used in wiring boards, electronic devices, and electronic modules.

[0061] 1, 1A-1H Wiring board 10 Insulating substrate 11 Insulating layer 11a Gap 21, 51 Electrode pad 30 Wiring conductor 31 Film conductor 32 Via conductor 321 First via conductor 322 Second via conductor 40 Supplementary via conductor 41, 41a, 41b Series via conductor 45 Insulator 100 Integrated circuit 111 Electrode 150 Electronic device 200 Electronic module A1 Mounting area G1 Via conductor group G40a First supplementary via conductor group G40b Second supplementary via conductor group S1 First surface S2 Second surface φ40, φ40c, φ40d, φ321, φ321d Diameter Pch40, Pch40c, Pch40d, Pch40e, Pch321, Pch321d Pitch

Claims

1. A wiring board comprising: a plate-shaped insulating substrate having a first surface having a mounting area for an integrated circuit and a second surface opposite to the first surface; electrode pads located in the mounting area; and wiring conductors located inside the insulating substrate and electrically connected to the electrode pads, wherein the wiring conductors include a group of via conductors, each consisting of a plurality of first via conductors connected to the electrode pads, and further comprising a plurality of supplementary via conductors located on the side of the group of via conductors in a planar perspective view, and having no electrical connection to the wiring conductors except for a ground conductor.

2. The wiring board according to claim 1, wherein at least a portion of each of the plurality of supplemental via conductors is located on the first surface side of half the depth of the insulating substrate.

3. The wiring board according to claim 1 or claim 2, wherein the plurality of supplemental via conductors are separated from the first and second surfaces.

4. The wiring board according to claim 1 or 2, wherein the plurality of supplemental via conductors are located up to at least one of the first surface and the second surface, and further comprises an insulating material covering the area of ​​the first surface or the second surface in which the supplemental via conductors are located.

5. The wiring board according to any one of claims 1 to 4, wherein the plurality of supplemental via conductors have the same diameter as each via conductor belonging to the via conductor group and are arranged at the same pitch in a planar perspective view.

6. The wiring board according to any one of claims 1 to 4, wherein the diameter of the plurality of supplementary via conductors is greater than the diameter of each via conductor belonging to the via conductor group, and the pitch of the plurality of supplementary via conductors is greater than the pitch of the plurality of first via conductors belonging to the via conductor group.

7. The wiring board according to any one of claims 1 to 4, wherein the diameter of the plurality of supplementary via conductors is smaller than the diameter of each via conductor belonging to the via conductor group, and the pitch of the plurality of supplementary via conductors is smaller than the pitch of the plurality of first via conductors belonging to the via conductor group.

8. The wiring board according to any one of claims 1 to 4, wherein the pitch of the plurality of supplementary via conductors is n times the pitch of the plurality of first via conductors belonging to the via conductor group (where n is an integer from 2 to 4).

9. The wiring board according to any one of claims 1 to 8, wherein the plurality of supplemental via conductors have a length of 50% or more of the thickness of the insulating substrate.

10. The wiring board according to any one of claims 1 to 8, wherein the insulating substrate has a structure in which a plurality of insulating layers are stacked, at least one of the plurality of supplementary via conductors includes a plurality of series via conductors arranged in a row in the vertical direction, and the plurality of series via conductors are arranged with a gap connected to one or more of the insulating layers in between.

11. The wiring board according to any one of claims 1 to 8, wherein the plurality of supplemental via conductors are located on the first surface side from half the depth of the insulating substrate and are not located on the second surface side from half the depth of the insulating substrate.

12. An electronic device comprising: a wiring board according to any one of claims 1 to 11; and an integrated circuit mounted on the wiring board.

13. An electronic module comprising: an electronic device according to claim 12; and a module substrate on which the electronic device is mounted.

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