Display method, display apparatus and storage medium

Abstract

Provided in the present disclosure are a display method, a display apparatus and a storage medium. The display method in the present disclosure is applied to the display apparatus. The display apparatus comprises a plurality of data lines and a switch circuit, wherein the plurality of data lines are divided into a plurality of data line groups, and each data line group at least comprises a pair of a first data line and a second data line; and the switch circuit is used for controlling the connection or disconnection between the first data line and the second data line. The display method comprises: with respect to the scanning of a gate line of any row, acquiring a current-row first data signal of a first data line, a previous-row first data signal of the first data line, a current-row second data signal of a second data line, and a previous-row second data signal of the second data line; at least on the basis of the current-row first data signal, the previous-row first data signal, the current-row second data signal and the previous-row second data signal, determining a target sub-mode from among a plurality of sub-modes of charge sharing; and on the basis of the target sub-mode, driving a switch circuit, so as to drive sub-pixels to perform picture display.

Description

Display method, display device and storage medium Technical Field

[0001] This disclosure belongs to the field of display technology, and specifically relates to a display method, a display device, and a storage medium. Background Technology

[0002] Power consumption is a crucial indicator of display product performance. Lowering power consumption extends product lifespan, especially for mobile devices that require less frequent charging, making them more convenient and environmentally friendly. Furthermore, reducing overall product power consumption reduces battery load, thus lowering the performance requirements of the power supply. Summary of the Invention

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a display method, display device and storage medium.

[0004] In a first aspect, the technical solution adopted to solve the technical problem of this disclosure is a display method applied to a display device. The display device includes sub-pixels arranged in an array, gate lines and data lines connected to the sub-pixels, and a switching circuit. Multiple data lines are divided into multiple data line groups, each data line group including at least one pair of first data lines and a second data line. The data line groups are correspondingly arranged with the switching circuit. The switching circuit is used to control the connection or disconnection between the first data lines and the second data lines. The display method includes:

[0005] For scanning any row of the gate lines, acquire the first data signal of the current row of the first data line, the first data signal of the previous row of the first data line, the second data signal of the current row of the second data line, and the second data signal of the previous row of the second data line;

[0006] The target sub-mode is determined from multiple sub-modes of charge sharing based at least on the first data signal of the current row, the first data signal of the previous row, the second data signal of the current row, and the second data signal of the previous row.

[0007] The switching circuit is driven according to the target sub-mode to drive the sub-pixel to display the image.

[0008] In some embodiments, the plurality of sub-modes includes a first sub-mode and a second sub-mode;

[0009] Driving the switching circuit according to the target sub-mode includes:

[0010] When the target sub-mode is the first sub-mode, the switching circuit is driven to disconnect a pair of the first data lines and the second data lines;

[0011] When the target sub-mode is the second sub-mode, the switching circuit is driven to connect a pair of first data lines and second data lines with the same polarity in the data line group.

[0012] In some embodiments, the plurality of sub-modes further includes a third sub-mode;

[0013] Driving the switching circuit according to the target sub-mode includes:

[0014] When the target sub-mode is the third sub-mode, the switching circuit is driven to connect all the data lines electrically connected to the same color sub-pixel in the data line group.

[0015] In some embodiments, the plurality of sub-modes further includes a fourth sub-mode;

[0016] Driving the switching circuit according to the target sub-mode includes:

[0017] When the target sub-mode is the fourth sub-mode, the switching circuit is driven to connect a pair of first data lines and second data lines with opposite polarities in the data line group.

[0018] In some embodiments, determining the target sub-pattern from a plurality of charge-sharing sub-patterns based at least on the current row first data signal, the previous row first data signal, the current row second data signal, and the previous row second data signal includes:

[0019] The first charge amount of the first data line corresponding to each of the sub-modes is determined based at least on the first data signal of the current row, the first data signal of the previous row, the storage capacitor, the parasitic capacitor, and the number of pre-charged rows.

[0020] The second charge amount of the second data line corresponding to each of the sub-modes is determined based at least on the second data signal of the current row, the second data signal of the previous row, the storage capacitor, the parasitic capacitor, and the number of pre-charged rows.

[0021] The target sub-mode is determined from multiple sub-modes that share charge, based on the first charge amount of the first data line corresponding to each of the sub-modes and the second charge amount of the second data line corresponding to each of the sub-modes.

[0022] In some embodiments, determining the target sub-mode from multiple charge-sharing sub-modes based on the first charge amount of the first data line corresponding to each of the sub-modes and the second charge amount of the second data line corresponding to each of the sub-modes includes:

[0023] For any of the sub-modes, calculate the sum of the first charge and the second charge;

[0024] The summation results of each of the sub-patterns are compared, and the sub-pattern corresponding to the smallest summation result is taken as the target sub-pattern.

[0025] In some embodiments, the polarities of the data voltage signals transmitted by two adjacent data lines in the data line group at the same time are opposite; the first data line and the second data line are electrically connected to sub-pixels of the same color; the first data signal and the second data signal have the same polarity; the plurality of sub-modes includes a first sub-mode, a second sub-mode, and a third sub-mode;

[0026] The data line group includes n data lines; n is a positive integer greater than or equal to 9.

[0027] In some embodiments, n equals 12; for any color sub-pixel, each group of data lines includes two pairs of first data lines and second data lines, wherein one pair has positive polarity and the other pair has negative polarity; the switching circuit includes sub-circuits corresponding one-to-one with the color of the sub-pixel; for any sub-circuit, it includes a first switching unit, a second switching unit, and a third switching unit; the first switching unit is electrically connected to a pair of positive polarity first data lines and second data lines, the second switching unit is electrically connected to a pair of negative polarity first data lines and second data lines, and the third switching unit is electrically connected to at least one of the pair of positive polarity first data lines and second data lines and at least one of the pair of negative polarity first data lines and second data lines.

[0028] In some embodiments, the sub-mode is a first sub-mode;

[0029] The step of determining the first charge amount in the first sub-mode includes:

[0030] The first charge required for normal display of this row is determined based on the first data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows;

[0031] Based on the first data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the first data signal of the current row in the previous frame, determine the second charge remaining before the current row is charged;

[0032] The first charge amount of the first data line in the first sub-mode is determined based on the first charge and the second charge.

[0033] In some embodiments, the sub-mode is a first sub-mode;

[0034] The step of determining the second charge amount in the first sub-mode includes:

[0035] Based on the second data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows, determine the third charge required for normal display of this row;

[0036] Based on the second data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the second data signal of the current row in the previous frame, determine the fourth charge remaining before the current row is charged;

[0037] Based on the third charge and the fourth charge, the amount of the second charge corresponding to the second data line in the first sub-mode is determined.

[0038] In some embodiments, the sub-mode is a second sub-mode;

[0039] The steps for determining the first charge and the second charge in the second sub-mode include:

[0040] Based on the first data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows, determine the first charge required for normal display of this row;

[0041] Based on the first data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the first data signal of the current row in the previous frame, determine the second charge remaining before the current row is charged;

[0042] The third charge required for normal display of this row is determined based on the second data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows;

[0043] Based on the second data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the second data signal of the current row in the previous frame, determine the fourth charge remaining before the current row is charged;

[0044] Half of the sum of the second charge and the fourth charge is taken as the fifth charge;

[0045] Based on the first charge and the fifth charge, determine the first charge amount of the first data line in the second sub-mode;

[0046] The second charge amount of the second data line in the second sub-mode is determined based on the third charge and the fifth charge.

[0047] In some embodiments, the sub-mode is a third sub-mode;

[0048] The steps for determining the first charge and the second charge in the third sub-mode include:

[0049] For a pair of first data lines and second data lines, the first charge required for normal display of the current line is determined based on the first data signal of the current line, the storage capacitor, the parasitic capacitance, and the number of pre-charged lines; the second charge remaining before charging of the current line is determined based on the first data signal of the previous line, the storage capacitor, the parasitic capacitance, the number of pre-charged lines, and the first data signal of the current line in the previous frame; the third charge required for normal display of the current line is determined based on the second data signal of the current line, the storage capacitor, the parasitic capacitance, and the number of pre-charged lines; and the fourth charge remaining before charging of the current line is determined based on the second data signal of the previous line, the storage capacitor, the parasitic capacitance, the number of pre-charged lines, and the second data signal of the current line in the previous frame.

[0050] For two pairs of the first data lines and the second data lines, the average of the sums of the two second charges and the two fourth charges is taken as the sixth charge;

[0051] For a pair of first data lines and second data lines, the first charge amount of the first data line in the third sub-mode is determined based on the first charge and the sixth charge; the second charge amount of the second data line in the third sub-mode is determined based on the third charge and the sixth charge.

[0052] In some embodiments, the switching circuit includes a fourth switching unit; the fourth switching unit is electrically connected to a first data line and a last data line in the display device; the display method further includes:

[0053] When the sub-pixel arrangement is determined to be the target architecture, for any sub-mode, the fourth switching unit is driven to connect the first data line and the last data line;

[0054] The target architecture has two gate lines between two adjacent rows of sub-pixels, and sub-pixels in every two columns of sub-pixels are electrically connected to the same data line.

[0055] In some embodiments, the display device further includes a source driver, the source driver being electrically connected to the sub-pixel via the data line; the display method further includes:

[0056] Based on the first charge amount corresponding to the first data line and the second charge amount corresponding to the second data line in the target sub-mode, determine a first target PWRC gear corresponding to a pair of the first data line and the second data line;

[0057] The source driver is controlled to output the first data signal and the second data signal according to the first target PWRC setting.

[0058] In some embodiments, the polarities of the data voltage signals transmitted by two adjacent data lines in the data line group at the same time are opposite; the polarities of the first data signal and the second data signal are the same or opposite; the plurality of sub-modes include a first sub-mode, a second sub-mode, and a fourth sub-mode.

[0059] In some embodiments, determining the target sub-pattern from a plurality of charge-sharing sub-patterns based at least on the current row first data signal, the previous row first data signal, the current row second data signal, and the previous row second data signal includes:

[0060] Determine the first difference between the first data signal in the current row and the first data signal in the previous row, and the second difference between the second data signal in the current row and the second data signal in the previous row;

[0061] If both the first difference and the second difference are less than the first preset threshold, the target sub-mode is determined to be the first sub-mode.

[0062] In some embodiments, the first data signal and the second data signal have the same polarity; the display method further includes:

[0063] If at least one of the first difference and the second difference is greater than or equal to the first preset threshold, based on the first data signal of the current row, the first data signal of the previous row, the second data signal of the current row, and the second data signal of the previous row, it is determined whether the first preset condition is met; the first preset condition includes a first sub-condition, a second sub-condition, a third sub-condition, and a fourth sub-condition;

[0064] If at least one of the first sub-condition, the second sub-condition, the third sub-condition, and the fourth sub-condition is satisfied, the target sub-pattern is determined to be the second sub-pattern; if none of the first, second, third, and fourth sub-conditions are satisfied, the target sub-pattern is determined to be the first sub-pattern.

[0065] The first sub-condition includes a`>a, c`<c, a`>(a+c) / 2, c`>(a+c) / 2; the second sub-condition includes a`>a, c`<c, a`>(a+c) / 2, c`<(a+c) / 2, c>a; the third sub-condition includes a`>a, c`<c, a`<(a+c) / 2, c`>(a+c) / 2, -2(a`-c`)+ac<0; the fourth sub-condition includes a`>a, c`<c, a`<(a+c) / 2, c`<(a+c) / 2;

[0066] Wherein, a` represents the first data signal of the current row, a represents the first data signal of the previous row, c` represents the second data signal of the current row, and c represents the second data signal of the previous row.

[0067] In some embodiments, the first data signal and the second data signal have opposite polarities, with the first data signal being positive and the second data signal being negative; the display method further includes:

[0068] If at least one of the first difference and the second difference is greater than or equal to the first preset threshold, based on the first data signal of the current row, the first data signal of the previous row, the second data signal of the current row, and the second data signal of the previous row, it is determined whether the second preset condition is met; the second preset condition includes a fifth sub-condition, a sixth sub-condition, and a seventh sub-condition;

[0069] If at least one of the fifth, sixth, and seventh sub-conditions is satisfied, the target sub-pattern is determined to be the fourth sub-pattern; if none of the fifth, sixth, and seventh sub-conditions are satisfied, the target sub-pattern is determined to be the first sub-pattern.

[0070] The fifth sub-condition includes a`<a, |b`|<|b|, a`>(a+b) / 2, b`>(a+b) / 2; the sixth sub-condition includes a`<a, |b`|<|b|, a`>(a+b) / 2, b`<(a+b) / 2, 2(a`-b`)+ba<0; the seventh sub-condition includes a`<a, |b`|<|b|, a`<(a+b) / 2, b`<(a+b) / 2;

[0071] Wherein, a` represents the first data signal of the current row, a represents the first data signal of the previous row, b` represents the second data signal of the current row, and b represents the second data signal of the previous row.

[0072] In some embodiments, the data line group includes an i-th pair of first data signals and a second data signal and a j-th pair of first data signals and a second data signal; wherein the i-th pair of first data signals and the second data signal have the same polarity, the j-th pair of first data signals and the second data signal have opposite polarities, and the first data signal in the i-th pair is the same as the first data signal in the j-th pair; the display method further includes:

[0073] When the target sub-mode of the i-th pair of first data signals and second data signals is the second sub-mode, and the target sub-mode of the j-th pair of first data signals and second data signals is the fourth sub-mode, the target sub-mode of the i-th pair of first data signals and second data signals is determined to be the second sub-mode, and the target sub-mode of the j-th pair of first data signals and second data signals is updated to the first sub-mode.

[0074] In some embodiments, the data line group includes n data lines; n is equal to 3 or 4.

[0075] In some embodiments, n equals 4; each group of data lines includes two pairs of first data lines and second data lines with the same polarity, and two pairs of first data lines and second data lines with opposite polarities; wherein, of the two pairs of first data lines and second data lines with the same polarity, one pair is positive and the other pair is negative; the switching circuit includes a first sub-circuit, a second sub-circuit, a third sub-circuit, and a fourth sub-circuit; the first sub-circuit is electrically connected to a pair of first data lines and second data lines with positive polarity, the second sub-circuit is electrically connected to a pair of first data lines and second data lines with negative polarity, the third sub-circuit is electrically connected to a pair of first data lines and second data lines with opposite polarities, and the fourth sub-circuit is electrically connected to another pair of first data lines and second data lines with opposite polarities.

[0076] In some embodiments, the display device further includes a source driver, the source driver being electrically connected to the sub-pixel via the data line; the display method further includes:

[0077] For any data line in the data line group, determine the difference between the current row data voltage signal and the previous row data voltage signal of the data line;

[0078] For the data cable group, if the difference between any of the data cables is less than a second preset threshold, the second target PWRC level corresponding to the data cable group is determined.

[0079] The source driver is controlled to output the first data signal and the second data signal according to the second target PWRC setting.

[0080] In some embodiments, the sub-pixel arrangement is a target architecture; the target architecture has two gate lines between two adjacent rows of sub-pixels, and sub-pixels in every two columns of sub-pixels are electrically connected to the same data line; the display method further includes:

[0081] When scanning the i-th row of the gate lines, the data voltage signal of the i-th row and the data voltage signal of the (i-2)-th row of the data lines are obtained; i is a positive integer greater than 2, and i is less than or equal to the number of the gate lines;

[0082] When the data voltage signal of the i-th row and the data voltage signal of the (i-2)-th row are the same and i is an odd number, the data voltage signal of the (i-2)-th row stored in the first memory is obtained as the data voltage signal of the current row of the data line to drive the sub-pixel to display the image;

[0083] When the data voltage signal of the i-th row and the data voltage signal of the (i-2)-th row are the same and i is an even number, the data voltage signal of the (i-2)-th row stored in the second memory is obtained as the data voltage signal of the current row of the data line to drive the sub-pixel to display the image.

[0084] In some embodiments, the display method further includes:

[0085] When the voltage signal of the i-th row of data and the voltage signal of the (i-2)-th row of data are different, the sub-pixel is driven to display the image according to the voltage signal of the i-th row of data.

[0086] When i is an odd number, the voltage signal of the i-th row of data is stored in the first memory;

[0087] When i is an odd number, the voltage signal of the i-th row of data is stored in the second memory.

[0088] In some embodiments, the display method further includes:

[0089] When i equals 1, the sub-pixel is driven to display the image according to the first row of data voltage signal, and the first row of data voltage signal is stored in the first memory;

[0090] When i equals 2, the sub-pixel is driven to display the image according to the second row of data voltage signal, and the second row of data voltage signal is stored in the second memory.

[0091] Secondly, embodiments of this disclosure also provide a display device configured to perform the display method as described in any one of the first aspects.

[0092] Thirdly, embodiments of this disclosure also provide a computer non-transient readable storage medium, wherein a computer program is stored on the computer non-transient readable storage medium, and the computer program is executed by a processor to perform the steps of the display method as described in any one of the first aspects. Attached Figure Description

[0093] Figure 1 is a schematic diagram of a polarity switching method for a liquid crystal display;

[0094] Figure 2 is a schematic diagram of the voltage change of a data line in Figure 1 between two frames;

[0095] Figure 3 is a schematic diagram of a charge sharing method;

[0096] Figures 4a and 4b are schematic diagrams of the polarity flipping and charge sharing method of adjacent sub-pixels in Example 1 provided by the embodiments of this disclosure;

[0097] Figure 5 is a flowchart of a display method provided in an embodiment of this disclosure;

[0098] Figure 6 is a flowchart of Example 1, which describes the determination of a target sub-pattern, provided in an embodiment of this disclosure.

[0099] Figure 7 is a local equivalent circuit diagram of the sub-pixel arrangement shown in Figure 4a;

[0100] Figure 8 is a scan timing diagram of the three pre-filled rows under the sub-pixel arrangement shown in Figure 4a;

[0101] Figure 9 is a flowchart illustrating the determination of the first charge quantity under the first sub-mode provided in an embodiment of this disclosure.

[0102] Figure 10 is a detailed flowchart of determining the first charge quantity in the second sub-mode according to an embodiment of this disclosure;

[0103] Figure 11 is a detailed flowchart of determining the first charge quantity under the third sub-mode according to an embodiment of this disclosure;

[0104] Figure 12 is a detailed flowchart of determining the second charge quantity under the first sub-mode provided in an embodiment of this disclosure;

[0105] Figure 13 is a detailed flowchart of determining the second charge quantity under the second sub-mode provided in an embodiment of this disclosure;

[0106] Figure 14 is a detailed flowchart of determining the second charge quantity under the third sub-mode provided in an embodiment of this disclosure;

[0107] Figure 15 is a flowchart of the switching circuit driven according to the target sub-mode in Example 1 provided by the embodiments of this disclosure;

[0108] Figure 16 is a schematic diagram of the sub-pixel arrangement using a dual-gate architecture and the charge sharing method of the first and last data lines provided in an embodiment of this disclosure;

[0109] Figure 17 is a detailed flowchart of PWRC gear control in Example 1 provided by the embodiments of this disclosure;

[0110] Figure 18a is a schematic diagram of the 8b / 10b encoding method provided in the embodiments of this disclosure;

[0111] Figure 18b is a schematic diagram of a newly added control bit in a group of data lines in Example 1 provided by the embodiments of this disclosure;

[0112] Figure 19 is a schematic diagram of the charge sharing method of Example 2 provided in the embodiments of this disclosure;

[0113] Figure 20 is a schematic diagram of the power consumption variation of the same polarity CS in Example 2 provided in the embodiments of this disclosure;

[0114] Figure 21 is a schematic diagram of the power consumption change of the reverse polarity CS in Example 2 provided in the embodiments of this disclosure;

[0115] Figure 22 is an overall architecture diagram of Example 2, which describes the determination of the target sub-mode and the control of the PWRC gear position, provided in the embodiments of this disclosure.

[0116] Figure 23 is a flowchart of the switching circuit driven according to the target sub-mode in Example 2 provided in the embodiments of this disclosure;

[0117] Figure 24 is a detailed flowchart of PWRC gear control in Example 2 provided in the embodiments of this disclosure;

[0118] Figure 25 is a schematic diagram of a newly added control bit in a group of data lines in Example 2 provided in the embodiments of this disclosure;

[0119] Figure 26 is a schematic diagram of the sub-pixel arrangement in a 6-bit color depth product provided in an embodiment of this disclosure;

[0120] Figure 27 is a schematic diagram of the sub-pixel arrangement of the dual-gate architecture provided in the embodiments of this disclosure;

[0121] Figure 28 is a schematic diagram of the data voltage signal sent by the data line when two adjacent rows of sub-pixels are arranged in the gate line scanning according to an embodiment of the present disclosure;

[0122] Figure 29 is a comparison diagram of the data voltage signals of each row provided in the embodiments of this disclosure;

[0123] Figure 30 is an overall flowchart of the driver chip self-refreshing scheme provided in the embodiments of this disclosure. Detailed Implementation

[0124] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0125] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0126] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0127] In the field of Liquid Crystal Display (LCD), to prevent the polarization of liquid crystal molecules, pixel driving circuits typically employ AC driving, as shown in Figure 1. This means that for data lines electrically connected to the same column of sub-pixels, the polarity is opposite in the current frame and the next frame; within the same frame, the polarity of the data voltage signals transmitted by adjacent columns of data lines is opposite. This results in the data lines needing to counteract the polarity effect when charging the panel, consuming more charging charge. However, the more charging charge consumed, the greater the power consumption of the product. As shown in Figure 2, for example, if the data voltage of a certain data line in the current frame is -5V, and the data voltage of the same data line in the next frame is +5V, when switching between the two frames, it is necessary to charge from -5V to +5V, with a charging charge of [+5 - (-5)] × C (where C represents the storage capacitor in the pixel driving circuit). It is evident that the design scheme to prevent the polarization of liquid crystal molecules increases the charging charge of the data lines, thereby increasing power consumption and affecting product lifespan.

[0128] The related Charge Sharing (CS) method can reduce charging charge and power consumption to a certain extent, as shown in Figure 3. Its design principle is as follows: The TP signal represents the timing signal indicating whether the source driver outputs a data voltage signal. The high-level phase of the TP signal indicates the preparation phase before the output data voltage signal, and the low-level phase indicates the output phase. CS control is executed according to the TP signal. Specifically, in the preparation phase, by briefly shorting two adjacent data lines, the charge along the entire path of the adjacent data lines is shared. If the shared voltage is closer to the charging voltage required by the current row's sub-pixel, the charging charge of the current sub-pixel can be reduced, thus lowering power consumption. For example, if the charging voltage of row n is +5V and the charging voltage of row n+1 is -5V, CS is implemented in the preparation phase between their output phases, making the shared voltage on the data lines 0V, which is closer to the -5V charging voltage required by the current row's sub-pixel. Therefore, the charging charge of the current sub-pixel can be reduced, thus lowering power consumption. However, the related CS technology can only achieve power saving by sharing charge across the entire frame or row, and cannot achieve fine-grained control.

[0129] In view of this, the present disclosure provides a display method, which essentially groups multiple data lines and controls each group of data lines individually. For example, it matches the most power-saving charge-sharing sub-mode (i.e., target sub-mode) to the paired first and second data lines in each group of data lines, so as to drive the built-in switching circuit according to the target sub-mode, control the first and second data lines to be connected or disconnected, thereby achieving the driving of sub-pixels with the lowest power consumption.

[0130] The display method provided in this disclosure can be applied to a display device, as shown in FIG4a or FIG4b. The display device includes sub-pixels arranged in an array, gate lines (Gate) and data lines (data) connected to the sub-pixels, and a switching circuit 01. Multiple data lines (data) are divided into multiple data line groups, each data line group including at least one pair of first data lines (data1) and second data lines (data2). The multiple data line groups are arranged side-by-side along the extension direction of the gate lines (i.e., the X direction), and multiple data lines (data) in each data line group are arranged side-by-side along the extension direction of the gate lines, and the multiple data lines (data) are multiple consecutive parallel lines along the extension direction of the gate lines. The data line groups are correspondingly arranged with the switching circuit 01; the switching circuit 01 is used to control the connection or disconnection between the first data lines (data1) and the second data lines (data2). Exemplarily, the number of data line groups and the number of switching circuits 01 are the same, and the data line groups and switching circuits 01 are arranged in a one-to-one correspondence. Each sub-pixel includes a light-emitting unit and a pixel driving circuit for driving the light-emitting unit. Exemplarily, the pixel driving circuit includes a switching transistor T0 and a storage capacitor Cst. The control electrode of the switching transistor T0 is electrically connected to the gate line Gate, the first electrode of the switching transistor T0 is electrically connected to the data line data, and the second electrode of the switching transistor T0 is electrically connected to the first plate of the storage capacitor Cst. The second plate of the storage capacitor Cst can be grounded. The data line data writes its transmitted data voltage signal into the switching transistor T0 to charge the storage capacitor Cst when the switching transistor T0 is turned on. Optionally, the display device is a liquid crystal display (LCD).

[0131] As shown in Figures 4a and 4b, in order to prevent the polarization of liquid crystal molecules, the polarity of the data lines (data) electrically connected to the same column of sub-pixels is opposite in the current frame and the next frame; in the same frame, the polarity of the data voltage signals transmitted by the data lines (data) of adjacent columns is opposite.

[0132] This disclosure provides a display method, as shown in FIG5, including steps S100 to S300.

[0133] S100. For scanning any row of grid lines, acquire the first data signal of the current row of the first data line, the first data signal of the previous row of the first data line, the second data signal of the current row of the second data line, and the second data signal of the previous row of the second data line.

[0134] The first data signal refers to the data voltage signal transmitted by the first data line. Taking the i-th row as an example, the first data signal in this row refers to the data voltage signal transmitted by the first data line when scanning the i-th row of gate lines. Similarly, taking the (i-1)-th row as an example, the first data signal in the previous row refers to the data voltage signal transmitted by the first data line when scanning the (i-1)-th row of gate lines. The second data signal refers to the data voltage signal transmitted by the second data line. Taking the i-th row as an example, the second data signal in this row refers to the data voltage signal transmitted by the second data line when scanning the i-th row of gate lines. Similarly, taking the (i-1)-th row as an example, the second data signal in the previous row refers to the data voltage signal transmitted by the second data line when scanning the (i-1)-th row of gate lines. i is a positive integer greater than 1, and i is less than the total number of gate lines.

[0135] S200, at least based on the first data signal of this row, the first data signal of the previous row, the second data signal of this row, and the second data signal of the previous row, determine the target sub-mode from multiple sub-modes of charge sharing.

[0136] Charge sharing refers to the CS mode, which includes multiple sub-modes. Different sub-modes indicate whether charge sharing or non-sharing is controlled on different data lines.

[0137] Optionally, the multiple sub-modes include a first sub-mode and a second sub-mode, wherein the first sub-mode may be a mode that does not implement charge sharing. The second sub-mode may be a mode that implements charge sharing for a pair of first and second data lines with the same polarity.

[0138] Optionally, the multiple sub-modes may also include a third sub-mode. The third sub-mode may be a mode that enables charge sharing among all data lines that electrically connect sub-pixels of the same color in the data line group. Here, "same polarity" means either all positive polarity or all negative polarity.

[0139] Optionally, the multiple sub-modes may also include a fourth sub-mode. The fourth sub-mode may be a mode that enables charge sharing between a pair of first and second data lines with opposite polarities in the data line group. Here, opposite polarities means that one is positive and the other is negative.

[0140] Optionally, for a set of data lines, the target sub-mode may correspond to a sub-mode to be executed corresponding to a pair of first data lines and second data lines, or it may correspond to a sub-mode to be executed corresponding to at least two pairs of first data lines and second data lines. This depends on the data lines involved in the calculation of the target sub-mode during the determination process. If the calculation of the target sub-mode relies on a pair of first data lines and second data lines, then the determined target sub-mode corresponds to the pair of first data lines and second data lines involved in the calculation, as in the cases of the first sub-mode, second sub-mode, and fourth sub-mode listed below. If the calculation of the target sub-mode relies on multiple pairs of first data lines and second data lines, then the determined target sub-mode corresponds to multiple pairs of first data lines and second data lines involved in the calculation, as in the case of the third sub-mode listed below.

[0141] S300: Drive the switching circuit according to the target sub-mode to drive the sub-pixels for image display.

[0142] A switching circuit is used to control the connection or disconnection between the first data line and the second data line. Switching circuits include, but are not limited to, transistors or other electronic components with switching characteristics.

[0143] The switching circuit is driven according to the indication of the target sub-mode. Taking a switching circuit including a transistor as an example, the first electrode of the transistor is electrically connected to the first data line, and the second electrode is electrically connected to the second data line. If the target sub-mode indicates that the first data line and the second data line are connected, then in response to a valid control signal in the target sub-mode, the transistor is turned on, connecting the first data line and the second data line, and realizing charge sharing between them. Similarly, if the target sub-mode indicates that the first data line and the second data line are disconnected, then in response to an invalid control signal in the target sub-mode, the transistor is turned off, thereby disconnecting the first data line and the second data line. Optionally, multiple transistors can also be used to realize the electrical connection between the first data line and the second data line. For example, as shown in Figure 4a or Figure 4b, the first electrode of the first transistor T1 is electrically connected to the first data line data1, and the second electrode is electrically connected to the data lead (first data lead 021 or second data lead 022); the first electrode of the second transistor T2 is electrically connected to the second data line data2, and the second electrode is electrically connected to the same data lead (first data lead 021 or second data lead 022). The control electrodes of the first transistor T1 and the second transistor T2 are electrically connected via the same control lead (first control lead 031 or second control lead 032), which is used to transmit the gate control signal. In response to a valid control signal, both transistors T1 and T2 are turned on simultaneously, at which point the first data line data1 and the second data line data2 are connected via the data lead. In response to an invalid control signal, both transistors T1 and T2 are turned off simultaneously, at which point the first data line data1 is isolated from the data lead, and the second data line data2 is isolated from the data lead. This design, which isolates both data lines, helps prevent signal crosstalk.

[0144] This disclosure pre-groups multiple data lines. During the execution of S100 to S300, each group of data lines can be controlled individually. Compared with the traditional technology of sharing charge across the entire frame or line, this disclosure achieves refined control of charge sharing. For any pair or at least one pair of first and second data lines in any group of data lines, the most power-saving charge sharing sub-mode (i.e., target sub-mode) is matched to it. The built-in switching circuit is driven according to the target sub-mode to control the connection or disconnection of the first and second data lines, thereby achieving the driving of sub-pixels with the lowest power consumption, thereby saving the overall power consumption of the product and extending its lifespan.

[0145] In some embodiments, the step of determining the target sub-pattern for S200, as shown in FIG6, specifically includes S2-1 to S2-3.

[0146] S2-1. Determine the first charge amount of the first data line corresponding to each sub-mode based at least on the first data signal of the current row, the first data signal of the previous row, the storage capacitor, the parasitic capacitor, and the number of pre-charged rows.

[0147] S2-2. Determine the second charge amount of the second data line corresponding to each sub-mode based at least on the second data signal of the current row, the second data signal of the previous row, the storage capacitor, the parasitic capacitor, and the number of pre-charged rows.

[0148] S2-3. Determine the target sub-mode from multiple sub-modes that share charge based on the first charge of the first data line corresponding to each sub-mode and the second charge of the second data line corresponding to each sub-mode.

[0149] It should be noted that, as shown in Figure 7, the storage capacitor Cst refers to the capacitor electrically connected to the switching transistor T0 in the pixel driving circuit. The parasitic capacitance Cds refers to the equivalent coupling capacitance generated by the first and second terminals of the switching transistor T0. As shown in Figure 8, the number of pre-charge rows refers to the number of gate lines scanned simultaneously when multiple rows of gate lines are scanned to charge multiple rows of sub-pixels simultaneously (or it can also be understood as the number of rows of sub-pixels being charged simultaneously). This embodiment uses a pre-charge row count of 3 rows as an example. As shown in Figure 8, data01 is the data on the data line when Gate1 is turned on, and so on.

[0150] The first charge represents the amount of charge required to complete the charging phase of the first data line, i.e., the charging charge. The second charge represents the amount of charge required to complete the charging phase of the second data line, i.e., the charging charge. Specifically, using a preset algorithm (as shown in Formula 1 below), the input variables are the first data signal of the current row, the first data signal of the previous row, the storage capacitor, the parasitic capacitor, and the number of pre-charged rows, and the output result is the first charge; using a preset algorithm (as shown in Formula 1 below), the input variables are the second data signal of the current row, the second data signal of the previous row, the storage capacitor, the parasitic capacitor, and the number of pre-charged rows, and the output result is the second charge. Alternatively, using a preset algorithm (as shown in Formula 1 below), the input variables are the first data signal of the current row and the first data signal of the previous row, and the output result is the first charge; using a preset algorithm (as shown in Formula 1 below), the input variables are the second data signal of the current row and the second data signal of the previous row, and the output result is the second charge. Among them, the storage capacitor, the parasitic capacitor, and the number of pre-charged rows are fixed parameters of the preset algorithm. Under the premise that the sub-pixel scanning method (such as the number of pre-charged rows) and the design specifications (such as the storage capacitor and the parasitic capacitor) are fixed, the fixed parameters of the preset algorithm remain unchanged.

[0151] Different sub-modes calculate the first and second charges differently, thus the results may also differ. Optionally, for any sub-mode, the sum of the first and second charges can be calculated; then, the sums of the sub-modes are compared, and the sub-mode with the smallest sum is selected as the target sub-mode. Optionally, the magnitudes of the first charges in each sub-mode can be compared to select the sub-mode that consumes the least amount of power, which is then selected as the target sub-mode. Optionally, the magnitudes of the second charges in each sub-mode can be compared to select the sub-mode that consumes the least amount of power, which is then selected as the target sub-mode.

[0152] This embodiment calculates the charging charge of the data lines corresponding to each sub-mode to reflect the power consumption, and selects the mode with the least power consumption from multiple sub-modes to reduce power consumption.

[0153] Optionally, as shown in Figure 4a or Figure 4b, the polarities of the data voltage signals transmitted by adjacent data lines in the data line group at the same time are opposite; the first data line data1 and the second data line data2 are electrically connected to sub-pixels of the same color. This disclosure uses the example of the first data line data1 and the second data line data2 being electrically connected to a red sub-pixel. The first data signal and the second data signal have the same polarity, which can be positive or negative; the multiple sub-modes include the first sub-mode, the second sub-mode, and the third sub-mode; the data line group includes n data lines; n is a positive integer greater than or equal to 9. For example, n takes the values ​​9, 12, 15, ..., and so on, with each subsequent term increasing by 3 compared to the previous term, representing the number of sub-pixels in the pixel, which is three: red, green, and blue.

[0154] Optionally, as shown in Figure 4a or Figure 4b, n equals 12; for any color sub-pixel, taking red as an example, each data line group includes two pairs of first data lines data1 and second data lines data2, with one pair having positive polarity and the other pair having negative polarity. The switching circuit 01 includes sub-circuits that correspond one-to-one with the color of the sub-pixel, such as the first sub-circuit 011 corresponding to red, the second sub-circuit (not shown in the figure) corresponding to green, and the third sub-circuit (not shown in the figure) corresponding to blue. Only the first sub-circuit 011 is shown in the figure; the electrical connection relationships of the other sub-circuits are the same as those of the first sub-circuit, and repeated parts will not be described again. For any sub-circuit (the first sub-circuit 011), it includes a first switching unit 0111, a second switching unit 0112, and a third switching unit 0113; the first switching unit 0111 is electrically connected to a pair of positive first data lines data1 and data2, the second switching unit 0112 is electrically connected to a pair of negative first data lines data1 and data2, and the third switching unit 0113 is electrically connected to at least one of the pair of positive first data lines data1 and data2 and at least one of the pair of negative first data lines data1 and data2. For example, the first switching unit 0111 includes a first transistor T1 and a second transistor T2, the second switching unit 0112 includes a third transistor T3 and a fourth transistor T4, and the third switching unit 0113 includes a fifth transistor T5. The first transistor T1 has its first electrode electrically connected to the positive first data line data1, and its second electrode electrically connected to the first data lead 021. The second transistor T2 has its first electrode electrically connected to the positive second data line data2, and its second electrode electrically connected to the first data lead 021. The control electrodes of the first transistor T1 and the second transistor T2 are electrically connected through the first control lead 031. When both transistors T1 and T2 are turned on simultaneously, the positive first data line data1 and the second data line data2 can be connected, thus achieving charge sharing between them. Alternatively, when both transistors T1 and T2 are turned off simultaneously, the first data line data1 is isolated from the first data lead 021, and the second data line data2 is isolated from the first data lead 021. This design, where both are isolated, helps prevent signal crosstalk. The first electrode of the third transistor T3 is electrically connected to the negative first data line data1, and the second electrode of the third transistor T3 is electrically connected to the second data lead 022; the first electrode of the fourth transistor T4 is electrically connected to the negative second data line data2, and the second electrode of the fourth transistor T4 is electrically connected to the second data lead 022; the control electrode of the third transistor T3 and the control electrode of the fourth transistor T4 are electrically connected through the second control lead 032.At this point, if the third transistor T3 and the fourth transistor T4 are turned on simultaneously, the negative pair of first data lines data1 and data2 can be connected, thus achieving charge sharing between them. Here, the third transistor T3 and the fourth transistor T4 are turned off simultaneously, isolating the first data line data1 from the second data lead 022, and isolating the second data line data2 from the second data lead 022; this design of isolating both is beneficial to preventing signal crosstalk. The first electrode of the third transistor T3 is electrically connected to the first data lead 021, and the second electrode of the third transistor T3 is electrically connected to the second data lead 022; the control electrode of the third transistor T3 responds to a valid control signal and turns on, at which point the first data lead 021 and the second data lead 022 are connected. If, on this basis, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned on, then the positive pair of first data lines data1 and data2 and the negative pair of first data lines data1 and data2 are connected to each other, achieving charge sharing among the four data lines.

[0155] Based on this, the first charge and the second charge are determined, that is, the charging charge Q is determined. A The specific process includes determining the required charge Q. B and residual charge QC; and then determine Q A＝ Q B+ Q C .

[0156] Required charge Q B This refers to the total charge of all equivalent capacitors within the display panel when the current row is displayed normally. Since all four rows of grid lines are in scanning mode at the same time, and there is the influence of the equivalent coupling capacitance Cds (i.e., parasitic capacitance), the total charge Q required for the nth row to be displayed is... B As shown in Formula 1. Q B =Cst×data(n)×4+Cds×data(n)..........................Formula 1

[0157] Where Cst represents the storage capacitor; data(n) represents the data voltage signal of this row (i.e., the nth row); Cds represents the parasitic capacitance; 4 represents the parameter determined based on the number of precharge rows. Specifically, the number of precharge rows is 3, as shown in Figure 8. For this row (the fourth row), at the same time, the four adjacent gate lines are all in the scanning state, thus the parameter is determined to be 4.

[0158] Residual charge Q CThis refers to the amount of charge in each equivalent capacitor within the display panel before the current row is charged. It mainly consists of two parts: one part is the charge of the material from the previous frame in the storage capacitor, denoted as the first part of the residual charge. Since the polarity needs to be switched in the current frame, the first part of the residual charge is –Cst×data(n'); the other part is the charge remaining in the storage capacitor and parasitic capacitor during the previous row's charging, denoted as the second part of the residual charge. Since the correct data needs to be rewritten in this row, the second part of the residual charge is Cst×data(n-1)×3+Cds×data(n-1). Based on this, the residual charge Q... C The calculation is shown in Formula 2. Q C =Cst×data(n-1)×3+Cds×data(n-1)–Cst×data(n').......Formula 2

[0159] Where data(n-1) represents the data voltage signal of the previous row; 3 represents the previous row of parameter 4 determined based on the number of precharged rows, i.e., 4-1=3; data(n') represents the data voltage signal of the current row of the previous frame.

[0160] Charging charge Q A See Formula 3 for calculation. Q A =Q B- Q C =[Cst×data(n)×4+Cds×data(n)]–[Cst×data(n-1)×3+Cds×data(n-1)–Cst×data(n')].................................................Formula 3

[0161] In one optional implementation, the sub-mode is a first sub-mode; for step S2-1 above, the first charge quantity Q under the first sub-mode is determined. Aa The specific steps include S2-1-11 to S2-1-13, as shown in Figure 9.

[0162] S2-1-11. Based on the first data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows, determine the first charge required for normal display of this row.

[0163] Specifically, according to Formula 1, by substituting the first data signal data(n) of the current row (i.e., the nth row), while keeping parameters such as storage capacitance Cst, parasitic capacitance Cds, and the number of pre-charged rows constant, the first charge Q can be calculated. Ba .

[0164] S2-1-12. Based on the first data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the first data signal of the current row in the previous frame, determine the second charge remaining before the current row is charged.

[0165] Specifically, the first residual charge can be determined based on the first data signal and storage capacitance of the current row in the previous frame; then, the second residual charge can be determined based on the first data signal of the previous row, storage capacitance, parasitic capacitance, and the number of pre-charged rows; the sum of the first and second residual charges is recorded as the second residual charge remaining before charging the current row. For example, according to Formula 2, by substituting the first data signal data(n-1) of the previous row and the first data signal data(n') of the current row in the previous frame, while keeping parameters such as storage capacitance Cst, parasitic capacitance Cds, and the number of pre-charged rows constant, the second charge Q can be calculated. Ca .

[0166] S2-1-13. Determine the first charge amount of the first data line in the first sub-mode based on the first charge and the second charge.

[0167] Specifically, the first charge Q in the first sub-mode Aa It is the first charge Q Ba Subtract the second charge Q Ca The result, i.e. Q Aa＝ Q Ba- Q Ca For specific parameters, please refer to Formula 3.

[0168] In one optional implementation, the sub-mode is a second sub-mode; for step S2-1 above, the first charge quantity Q under the second sub-mode is determined. Aa The steps include S2-1-21 to S2-1-25, as shown in Figure 10.

[0169] S2-1-21. Based on the first data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows, determine the first charge required for normal display of this row.

[0170] This step determines the first charge Q. Ba The execution process is the same as S2-1-11 above. For details, please refer to the detailed explanation of S2-1-11 above. Repeated parts will not be repeated.

[0171] S2-1-22. Based on the first data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the first data signal of the current row in the previous frame, determine the second charge remaining before the current row is charged.

[0172] This step determines the second charge Q. CaThe execution process is the same as S2-1-12 above. For details, please refer to the detailed explanation of S2-1-12 above. Repeated parts will not be repeated.

[0173] S2-1-23. Based on the second data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the second data signal of the current row in the previous frame, determine the fourth charge remaining before the current row is charged.

[0174] Specifically, the third residual charge can be determined based on the second data signal and storage capacitance of the current row in the previous frame; then, the fourth residual charge can be determined based on the second data signal of the previous row, storage capacitance, parasitic capacitance, and the number of pre-charged rows; the sum of the third and fourth residual charges is recorded as the fourth residual charge remaining before charging the current row. For example, according to Formula 2, by substituting the second data signal data(n-1) of the previous row and the second data signal data(n') of the current row in the previous frame, while keeping parameters such as storage capacitance Cst, parasitic capacitance Cds, and the number of pre-charged rows constant, the fourth charge Q can be calculated. Cb .

[0175] S2-1-24. Take half of the sum of the second and fourth charges as the fifth charge.

[0176] The calculation of the fifth charge Q' is shown in Formula 4, which represents the residual charge Q on the first data line. Ca With the residual charge Q on the second data line Cb The average value, i.e., the residual charge after the two charges are shared. Q'=(Q Ca+ Q Cb ) / 2…………………….…….Formula 4

[0177] S2-1-25. Based on the first charge and the fifth charge, determine the first charge amount of the first data line in the second sub-mode.

[0178] Specifically, the first charge Q in the second sub-mode Aa It is the first charge Q Ba The result of subtracting the fifth charge Q' is Q Aa＝ Q Ba- Q', see Formula 3 for specific parameters.

[0179] In an optional implementation, the sub-mode is a third sub-mode; here, as shown in Figure 4a or Figure 4b, taking an example where n equals 12, and two pairs of identical polarity first data lines data1 and data2 are electrically connected to the red sub-pixel. For step S2-1 above, the first charge Q in the third sub-mode is determined. Aa The steps include S2-1-31 to S2-1-35, as shown in Figure 11.

[0180] S2-1-31. For a pair of first data lines and second data lines, determine the first charge required for normal display of the current line based on the first data signal of the current line, the storage capacitor, the parasitic capacitance, and the number of pre-charged lines.

[0181] Here, the pair of first and second data lines are exemplified by the pair of positive data lines data1 and data2 in Figure 4a.

[0182] This step determines the first charge Q. Ba The execution process is the same as S2-1-11 above. For details, please refer to the detailed explanation of S2-1-11 above. Repeated parts will not be repeated.

[0183] S2-1-32. For a pair of first data lines and second data lines, determine the second charge remaining before charging of the current line based on the first data signal of the previous line, the storage capacitor, the parasitic capacitor, the number of pre-charged lines, and the first data signal of the current line in the previous frame.

[0184] Here, the pair of first and second data lines are exemplified by the pair of positive data lines data1 and data2 in Figure 4a.

[0185] This step determines the second charge Q. Ca The execution process is the same as S2-1-12 above. For details, please refer to the detailed explanation of S2-1-12 above. Repeated parts will not be repeated.

[0186] S2-1-33. For a pair of first data lines and second data lines, determine the fourth charge remaining before charging of the current line based on the second data signal of the previous line, the storage capacitor, the parasitic capacitor, the number of pre-charged lines, and the second data signal of the current line in the previous frame.

[0187] Here, the pair of first and second data lines are exemplified by the pair of positive data lines data1 and data2 in Figure 4a.

[0188] This step determines the fourth charge Q. Cb The execution process is the same as S2-1-23 above. For details, please refer to the detailed explanation of S2-1-23 above. Repeated parts will not be repeated.

[0189] S2-1-34. For two pairs of first and second data lines, the average value of the sum of the two second charges and the two fourth charges is taken as the sixth charge.

[0190] The two pairs of first and second data lines here include a pair of positive first data lines data1 and data lines data2 in Figure 4a, and a pair of negative first data lines data1 and data lines data2.

[0191] The calculation of the sixth charge Q is given in Formula 5, which represents the residual charge Q on the two pairs of first data lines. Ca With the residual charge Q on the second data line Cb The average value, i.e., the residual charge after the four data lines share the charge. Q”=(Q Ca_1+ Q Cb_1 +Q Ca_2 +Q Cb_2 ) / 2……………….…….Formula 5

[0192] To distinguish the second charge Q of the two pairs of first and second data lines Ca and the fourth charge Q Cb This public Q Ca_1 and Q Cb_1 Q represents the second and fourth charges of the first and second data lines, which are of positive polarity. Ca_2 and Q Cb_2 The second and fourth charges represent the first and second data lines, which are another pair of negative polarities.

[0193] S2-1-35. For a pair of first data lines and second data lines, determine the first charge amount of the first data line in the third sub-mode based on the first charge and the sixth charge.

[0194] Here, the pair of first and second data lines are exemplified by the pair of positive data lines data1 and data2 in Figure 4a.

[0195] Specifically, the first charge Q in the third sub-mode Aa It is the first charge Q Ba The result of subtracting the sixth charge Q is Q Aa =Q Ba "-Q", please refer to Formula 3 for specific parameters.

[0196] The above three implementation methods are all illustrated using the data line electrically connected to the red sub-pixel as an example, as shown in Figure 4a, where n=12. The implementation process for the blue and green sub-pixels is similar, and repeated parts will not be described again. The above three optional implementation methods respectively calculate the first charge Q of the first data line in the first sub-mode, the second sub-mode, and the third sub-mode. Aa .

[0197] In one optional implementation, the sub-mode is a first sub-mode; for step S2-2 above, the second charge quantity Q under the first sub-mode is determined. Ab The specific steps include S2-2-11 to S2-2-13, as shown in Figure 12.

[0198] S2-2-11. Based on the second data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows, determine the third charge required for normal display of this row.

[0199] Specifically, according to Formula 1, by substituting the second data signal data(n) of the current row (i.e., the nth row), while keeping parameters such as storage capacitance Cst, parasitic capacitance Cds, and the number of pre-charged rows constant, the third charge Q can be calculated. Bb .

[0200] S2-2-12. Based on the second data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the second data signal of the current row in the previous frame, determine the fourth charge remaining before the current row is charged.

[0201] Specifically, the third residual charge can be determined based on the second data signal and storage capacitance of the current row in the previous frame; then, the fourth residual charge can be determined based on the second data signal of the previous row, storage capacitance, parasitic capacitance, and the number of pre-charged rows; the sum of the third and fourth residual charges is recorded as the fourth residual charge remaining before charging the current row. For example, according to Formula 2, by substituting the second data signal data(n-1) of the previous row and the second data signal data(n') of the current row in the previous frame, while keeping parameters such as storage capacitance Cst, parasitic capacitance Cds, and the number of pre-charged rows constant, the fourth charge Q can be calculated. Cb .

[0202] S2-2-13. Based on the third charge and the fourth charge, determine the second charge amount corresponding to the second data line in the first sub-mode.

[0203] Specifically, the second charge Q in the first sub-mode Ab It is the third charge Q Bb Subtract the fourth charge Q Cb The result, i.e. Q Ab＝ Q Bb- Q Cb For specific parameters, please refer to Formula 3.

[0204] In one optional implementation, the sub-mode is a second sub-mode; for step S2-2 above, the second charge quantity Q under the second sub-mode is determined. Ab The steps include S2-2-21 to S2-2-25, as shown in Figure 13.

[0205] S2-2-21. Based on the second data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows, determine the third charge required for normal display of this row.

[0206] This step determines the third charge Q. Bb The execution process is the same as S2-2-11 above. For details, please refer to the detailed explanation of S2-2-11 above. Repeated parts will not be repeated.

[0207] S2-2-22. Based on the first data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the first data signal of the current row in the previous frame, determine the second charge remaining before the current row is charged.

[0208] This step determines the second charge Q. Ca The execution process is the same as S2-1-12 above. For details, please refer to the detailed explanation of S2-1-12 above. Repeated parts will not be repeated.

[0209] S2-2-23. Based on the second data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the second data signal of the current row in the previous frame, determine the fourth charge remaining before the current row is charged.

[0210] This step determines the fourth charge Q. Cb The execution process is the same as S2-2-12 above. For details, please refer to the detailed explanation of S2-2-12 above. Repeated parts will not be repeated.

[0211] S2-2-24. Take half of the sum of the second and fourth charges as the fifth charge.

[0212] The process of determining the fifth charge Q' in this step is the same as that in S2-1-24 above. For details, please refer to the detailed explanation of S2-1-24 above. Repeated parts will not be repeated.

[0213] S2-2-25. Based on the third charge and the fifth charge, determine the second charge amount of the second data line in the second sub-mode.

[0214] Specifically, the second charge Q in the second sub-mode Ab It is the third charge Q Bb The result of subtracting the fifth charge Q' is Q Ab =Q Bb -Q', see Formula 3 for specific parameters.

[0215] In an optional implementation, the sub-mode is a third sub-mode; here, as shown in Figure 4a, taking an example where n equals 12, and two pairs of first and second data lines with the same polarity are electrically connected to the red sub-pixel. For step S2-2 above, the second charge Q in the third sub-mode is determined.Ab The steps include S2-2-31 to S2-2-35, as shown in Figure 14.

[0216] S2-2-31. For a pair of first data lines and second data lines, determine the third charge required for normal display of the current line based on the second data signal of the current line, the storage capacitor, the parasitic capacitance, and the number of pre-charged lines.

[0217] Here, the pair of first and second data lines are exemplified by the pair of positive data lines data1 and data2 in Figure 4a.

[0218] This step determines the third charge Q. Bb The execution process is the same as S2-2-11 above. For details, please refer to the detailed explanation of S2-2-11 above. Repeated parts will not be repeated.

[0219] S2-2-32. For a pair of first data lines and second data lines, determine the second charge remaining before charging of the current line based on the first data signal of the previous line, the storage capacitor, the parasitic capacitor, the number of pre-charged lines, and the first data signal of the current line in the previous frame.

[0220] Here, the pair of first and second data lines are exemplified by the pair of positive data lines data1 and data2 in Figure 4a.

[0221] This step determines the second charge Q. Ca The execution process is the same as S2-1-12 above. For details, please refer to the detailed explanation of S2-1-12 above. Repeated parts will not be repeated.

[0222] S2-2-33. For a pair of first data lines and second data lines, determine the fourth charge remaining before charging of the current line based on the second data signal of the previous line, the storage capacitor, the parasitic capacitor, the number of pre-charged lines, and the second data signal of the current line in the previous frame.

[0223] Here, the pair of first and second data lines are exemplified by the pair of positive data lines data1 and data2 in Figure 4a.

[0224] This step determines the fourth charge Q. Cb The execution process is the same as S2-2-12 above. For details, please refer to the detailed explanation of S2-2-12 above. Repeated parts will not be repeated.

[0225] S2-2-34. For two pairs of first and second data lines, the average of the sum of the two second charges and the two fourth charges is taken as the sixth charge.

[0226] The two pairs of first and second data lines here include a pair of positive first data lines data1 and data lines data2 in Figure 4a, and a pair of negative first data lines data1 and data lines data2.

[0227] The process of determining the sixth charge Q in this step is the same as that in S2-1-34 above. For details, please refer to the detailed explanation of S2-1-34 above. Repeated parts will not be repeated.

[0228] S2-2-35. For a pair of first data lines and second data lines, determine the second charge amount of the second data line in the third sub-mode based on the third charge and the sixth charge.

[0229] Here, the pair of first and second data lines are exemplified by the pair of positive data lines data1 and data2 in Figure 4a.

[0230] Specifically, the second charge Q in the third sub-mode Ab It is the third charge Q Bb The result of subtracting the sixth charge Q is Q Ab =Q Bb "-Q", please refer to Formula 3 for specific parameters.

[0231] The above three implementation methods are all illustrated using the data line electrically connected to the red sub-pixel as an example, as shown in Figure 4a, where n=12. The implementation process for the blue and green sub-pixels is similar, and repeated parts will not be described again. The above three optional implementation methods respectively calculate the second charge Q of the second data line in the first sub-mode, the second sub-mode, and the third sub-mode. Ab .

[0232] Regarding steps S2-3, the first charge Q of the first data line calculated according to the above six embodiments in the first sub-mode, second sub-mode, and third sub-mode is... Aa The second data line shows the second charge quantity Q in the first sub-mode, second sub-mode, and third sub-mode. Ab The total charging charge (Q) under the same sub-mode is respectively performed. Aa +Q Ab By comparing the sizes, the sub-mode corresponding to the minimum charging charge is selected as the target sub-mode.

[0233] Based on this, for step S300, the switching circuit is driven according to the target sub-mode, specifically including S31 to S33, as shown in Figure 15.

[0234] S31. When the target sub-mode is the first sub-mode, drive the switching circuit to disconnect a pair of first data lines and second data lines.

[0235] The first sub-mode can be a mode that does not achieve charge sharing. Therefore, when the target sub-mode is the first sub-mode, the switching circuit is driven to respond to an invalid control signal, thereby isolating the first and second data lines of the same polarity. As shown in Figure 4a, when n equals 9, there is only one pair of data lines electrically connected to the red sub-pixel with the same polarity, namely, a pair of positive polarity first data lines data1 and second data lines data2. When n equals 12, there are two pairs of data lines electrically connected to the red sub-pixel with the same polarity, namely, a pair of positive polarity first data lines data1 and second data lines data2, and a pair of negative polarity first data lines data1 and second data lines data2. The driving switching circuit 01 isolates the pair of positive polarity first data lines data1 and second data lines data2, and the pair of negative polarity first data lines data1 and second data lines data2, to isolate all data lines electrically connected to the same color in the data group.

[0236] Optionally, regarding step S31 above, the switching circuit is driven according to the target sub-mode. For the positive first data line data1 and the second data line data2 in the data line group, if the target sub-mode is the first sub-mode, then the first switching unit 0111 is driven according to the first sub-mode. The first transistor T1 and the second transistor T2 respond to the invalid control signal and disconnect a pair of positive first data lines data1 and data2. For the negative first data line data1 and the second data line data2 in the data line group, if the target sub-mode is the first sub-mode, then the second switching unit 0112 is driven according to the first sub-mode. The third transistor T3 and the fourth transistor T4 respond to the invalid control signal and disconnect a pair of negative first data lines data1 and data2.

[0237] S32. When the target sub-mode is the second sub-mode, drive the switching circuit to connect a pair of first and second data lines with the same polarity in the data line group.

[0238] The second sub-mode can be a mode that achieves charge sharing between a pair of first and second data lines with the same polarity. Specifically, as shown in Figure 4a, when the target sub-mode is the second sub-mode, the switching circuit is driven to connect a pair of first and second data lines with the same polarity electrically connected to the same color sub-pixel (red sub-pixel) in the data line group. For example, when n equals 9, the switching circuit is driven to connect a pair of positive polarity first data lines data1 and data2 electrically connected to the red sub-pixel in the data line group. When n equals 12, the switching circuit is driven to connect a pair of positive polarity first data lines data1 and data2 electrically connected to the red sub-pixel in the data line group, and also connect a pair of negative polarity first data lines data1 and data2 electrically connected to the red sub-pixel in the data line group.

[0239] Optionally, in step S32 above, the switching circuit is driven according to the target sub-mode. Specifically, for the positive first data line data1 and the second data line data2 in the data line group, if the target sub-mode is the second sub-mode, then the first switching unit 0111 is driven according to the second sub-mode. The first transistor T1 and the second transistor T2 respond to the valid control signal and connect a pair of positive first data lines data1 and data2. For the negative first data line data1 and the second data line data2 in the data line group, if the target sub-mode is the second sub-mode, then the second switching unit 0112 is driven according to the second sub-mode. The third transistor T3 and the fourth transistor T4 respond to the valid control signal and connect a pair of negative first data lines data1 and data2.

[0240] S33. When the target sub-mode is the third sub-mode, drive the switching circuit to connect all data lines electrically connected to the same color sub-pixel in the data line group.

[0241] The third sub-mode can be a mode that enables charge sharing among all data lines electrically connected to the same color sub-pixel in the data line group. Specifically, as shown in Figure 4a, when the target sub-mode is the third sub-mode, the switching circuit is driven to connect the three data lines electrically connected to the same color sub-pixel (red sub-pixel) in the data line group. When n equals 12, the switching circuit is driven to connect the two pairs of first data lines (data1) and second data lines (data2) with opposite polarities electrically connected to the red sub-pixel in the data line group, thus achieving charge sharing among the four data lines.

[0242] Optionally, regarding step S33 above, the switching circuit is driven according to the target sub-mode. Specifically, for the positive first data line data1 and second data line data2 and the negative first data line data1 and second data line data2 in the data line group, if the target sub-mode is the third sub-mode, then the first switching unit 0111, the second switching unit 0112, and the third switching unit 0113 are driven according to the third sub-mode. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 simultaneously respond to the valid control signal, connecting a pair of positive first data lines data1 and second data lines data2, connecting a pair of negative first data lines data1 and second data lines data2, and connecting a pair of positive first data lines data1 and second data lines data2. According to one of the data lines 021 and 022, and one of the negative data lines 01 and 022, for example, the fifth transistor T5 is turned on, connecting the first data line 021 and the second data line 022. The first data line 021 is simultaneously electrically connected to the positive data line 021 and the second data line 022, and the second data line 022 is simultaneously electrically connected to the negative data line 021 and the second data line 022. Therefore, when the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 simultaneously respond to the effective control signal, the positive data line 021 and the second data line 022, as well as the negative data line 021 and the second data line 022, are interconnected with each other.

[0243] In some embodiments, as shown in FIG16, the sub-pixel arrangement is a target architecture, namely a dual-gate architecture, in which two gate lines are provided between two adjacent rows of sub-pixels, and sub-pixels in every two columns of sub-pixels are electrically connected to the same data line. Optionally, in this target architecture, multiple data lines are also divided into multiple data line groups, and the division method is the same as in the embodiment of FIG4a. In the data line group, the polarities of the data voltage signals transmitted by two adjacent data lines at the same time are opposite; the first data line and the second data line are electrically connected to sub-pixels of the same color; the first data signal and the second data signal have the same polarity; the multiple sub-modes include the first sub-mode, the second sub-mode, and the third sub-mode; the data line group includes n data lines; n is a positive integer greater than or equal to 9. For example, n equals 12; for any color sub-pixel, each data line group includes two pairs of first data lines and second data lines with the same polarity, and one pair has a positive polarity and the other pair has a negative polarity; the switching circuit includes a sub-circuit corresponding one-to-one with the color of the sub-pixel; for any sub-circuit, it includes a first switching unit, a second switching unit, and a third switching unit; the first switching unit is electrically connected to a pair of positive polarity first data lines and second data lines, the second switching unit is electrically connected to a pair of negative polarity first data lines and second data lines, and the third switching unit is electrically connected to at least one of the pair of positive polarity first data lines and second data lines and at least one of the pair of negative polarity first data lines and second data lines.

[0244] Optionally, as shown in Figure 16, the switching circuit further includes a fourth switching unit 0114; the fourth switching unit 0114 is electrically connected to the first data line S1 and the last data line Sn in the display device; when the sub-pixel arrangement is determined to be the target architecture, for any sub-mode, the fourth switching unit 0114 is driven to connect the first data line S1 and the last data line Sn.

[0245] Optionally, the sub-pixel arrangement is the target architecture. Regardless of which sub-mode is selected, the first and last data lines in the display panel are electrically connected, and the two can be connected into a single structure using a third data lead.

[0246] In this embodiment, the sub-pixel arrangement is the target architecture. The grouping of data lines and the selection of target sub-mode in its display method are the same as in the above embodiment, and the repeated parts will not be described again.

[0247] In some embodiments, the display device further includes a source driver, which is electrically connected to the sub-pixel via a data line; the display method further includes PWRC level adjustment, specifically including steps S201 to S202, as shown in FIG17.

[0248] S201. Based on the first charge quantity corresponding to the first data line and the second charge quantity corresponding to the second data line in the target sub-mode, determine the first target PWRC gear corresponding to a pair of first data lines and second data lines.

[0249] The target sub-mode is the most power-efficient operating sub-mode selected above, based on the first charge Q under this target sub-mode. Aa Second charge Q Ab Determine the first target PWRC gear. For example, determine the first charge quantity Q. Aa Second charge Q Ab If the sum of the charges is greater than or equal to the preset charging charge, then the higher PWRC level is selected as the first target PWRC level; otherwise, the lower PWRC level is selected as the first target PWRC level. Compared to traditional PWRC, which can only set fixed levels for different projects and cannot be adjusted for different screens, this embodiment can dynamically adjust the PWRC level, saving power consumption.

[0250] S202, Control the source driver to output the first data signal and the second data signal according to the first target PWRC gear.

[0251] The preset PWRC settings include two settings: a high setting and a low setting. The high setting controls the source driver's output capability to be high, which can be manifested as a high drive current; the low setting controls the source driver's output capability to be low, which can be manifested as a low drive current.

[0252] In some embodiments, multiple data lines are divided into multiple data line groups, each group being controlled by a separate register. Each data line group includes n data lines; n equals 12. As shown in Figure 18a, the 1 bit added to each data line in the 8b / 10b encoding method can be used to make each data line group have 12 available bits. As shown in Figure 18b, the high 6 bits are selected as the CS control bits, where every two bits represent the same color and polarity configuration. For example, the 2-bit CS control signal is used to control the charge sharing state of a pair of positive and a pair of negative data lines electrically connected to the red sub-pixel R (also representing the target sub-mode), the 2-bit CS control signal is used to control the charge sharing state of a pair of positive and a pair of negative data lines electrically connected to the green sub-pixel G, and the 2-bit CS control signal is used to control the charge sharing state of the data lines electrically connected to the blue sub-pixel B. Furthermore, the lower 6 bits are selected as the PWRC control bits. Each pair of bits represents a configuration with the same color and polarity. For example, a 2-bit PWRC control signal is used to control the PWRC settings of a pair of positive and a pair of negative data lines electrically connected to the red sub-pixel R, a 2-bit PWRC control signal is used to control the PWRC settings of a pair of positive and a pair of negative data lines electrically connected to the green sub-pixel G, and a 2-bit PWRC control signal is used to control the PWRC settings of a pair of positive and a pair of negative data lines electrically connected to the blue sub-pixel B.

[0253] In some embodiments, as shown in FIG19, the polarities of the data voltage signals transmitted by two adjacent data lines in the data line group at the same time are opposite; the polarities of the first data signal and the second data signal are the same or opposite; the multiple sub-modes include a first sub-mode, a second sub-mode, and a fourth sub-mode.

[0254] Optionally, regardless of whether the polarities of the first data signal and the second data signal are the same or opposite, the first data line data1 and the second data line data2 are electrically connected to sub-pixels of different colors.

[0255] As shown in Figure 19, the data line group includes n data lines; n equals 4. The data line group includes four pairs of first data lines (data1) and second data lines (data2). The first pair includes a positively polarized first data line S1+ connected to a red sub-pixel and a positively polarized second data line S3+ connected to a blue sub-pixel; the second pair includes a negatively polarized first data line S2- connected to a green sub-pixel and a negatively polarized second data line S4- connected to a red sub-pixel; the third pair includes a positively polarized first data line S1+ connected to a red sub-pixel and a negatively polarized second data line S2- connected to a green sub-pixel; and the fourth pair includes a positively polarized first data line S3+ connected to a blue sub-pixel and a negatively polarized second data line S4- connected to a red sub-pixel.

[0256] In a group of four data lines, for any given data line, comparing the voltage signal of the current data line with the voltage signal of the previous data line results in 16 possible scenarios, as shown in the table below, each corresponding to a different power consumption change. Here, ↑ indicates that the voltage signal of the current data line increases compared to the previous data line; ↓ indicates that the voltage signal of the current data line decreases compared to the previous data line.

[0257] Table 1

[0258] The determination of power consumption changes can be obtained through experimental testing, as shown in Figure 20. Taking case 1 as an example, the current row data voltage signals of data lines S1+, S2-, S3+, and S4- are all increased compared to the previous row data voltage signal. For the CS determination of the same polarity first data line S1+ and second data line S3+, specifically, after performing CS on the first data signal m1 of the previous row on the first data line S1+ and the second data signal m3 of the previous row on the second data line S3+, the average value is taken, i.e., (m1-m3) / 2. This average value may be closer to the target value or farther from the target value, depending on the magnitude of the target value. The "target value" refers to the current row data voltage signal, which needs to be calculated. Assuming the target value of the first data line S1+ (the first data signal m1' of this row) is the same as the target value of the second data line S3+ (the second data signal m3' of this row), as shown in Figure (a), the average value of the first data line S1+ after CS is farther from its first data signal m1', while the average value of the second data line S3+ after CS is closer to its second data signal m3'. Since m1'-(m1-m3) / 2 and m3'-(m1-m3) / 2 are the same, it means that the power consumption before and after CS remains unchanged. As shown in Figure (b), m1' is greater than m3', the average value of the first data line S1+ after CS is farther from its first data signal m1', and the average value of the second data line S3+ after CS is farther from its second data signal m3'. Therefore, the power consumption after CS actually increases. As shown in Figure (c), m1' is greater than m3'. The average value after CS of the first data line S1+ is farther from the first data signal m1' of its row, while the average value after CS of the second data line S3+ is closer to the second data signal m3' of its row. Considering the overall increase in power consumption a (e.g., x+y) of S1+ is greater than the decrease in power consumption (xy) of S3+, the overall distance from the target value is greater, resulting in increased power consumption. Therefore, for the same polarity CS in case 1, the power consumption may remain unchanged or increase, so charge sharing (CS) should not be performed in case 1. As shown in Figure 21, taking case 1 as an example, the data voltage signals of the current row of data lines S1+, S2-, S3+, and S4- are all increased compared to the data voltage signal of the previous row. For the CS judgment of the first data line S1+ and the second data line S2- with opposite polarity, specifically, after the first data signal m1 above the first data line S1+ and the second data signal m2 above the second data line S2- are CS, the average value of the two is taken, that is, (m1-m2) / 2. This average value is farther away from the target value, so the power consumption is higher after the CS judgment, so charge sharing (CS) should not be performed.

[0259] For the cases in Table 1 above where power consumption is "unchanged, increased, or decreased," specific calculations are needed to determine whether charge sharing (CS) should be performed. For other cases, such as power consumption being "unchanged or increased," or "increased," no calculation is required, and charge sharing (CS) should not be performed. Based on the above rules, the following first and second preset conditions are set. The first preset condition includes a first sub-condition, a second sub-condition, a third sub-condition, and a fourth sub-condition; the second preset condition includes a fifth sub-condition, a sixth sub-condition, and a seventh sub-condition; the first sub-condition includes a`>a, c`<c, a`>(a+c) / 2, c`>(a+c) / 2; the second sub-condition includes a`>a, c`<c, a`>(a+c) / 2, c`<(a+c) / 2, c>a; the third sub-condition includes a`>a, c`<c, a`<(a+c) / 2, c`>(a+c) / 2, -2(a`-c`). +ac<0; The fourth sub-condition includes a`>a, c`<c, a`<(a+c) / 2, c`<(a+c) / 2; The fifth sub-condition includes a`<a, |b`|<|b|, a`>(a+b) / 2, b`>(a+b) / 2; The sixth sub-condition includes a`<a, |b`|<|b|, a`>(a+b) / 2, b`<(a+b) / 2, 2(a`-b`)+ba<0; The seventh sub-condition includes a`<a, |b`|<|b|, a`<(a+b) / 2, b`<(a+b) / 2. Where a` represents the first data signal of the current row, a represents the first data signal of the previous row, c` represents the second data signal of the current row, and c represents the second data signal of the previous row.

[0260] For S2, the steps to determine the target sub-pattern specifically include S20-1 to S20-3.

[0261] S20-1. Determine the first difference between the first data signal of this row and the first data signal of the previous row, and the second difference between the second data signal of this row and the second data signal of the previous row.

[0262] The first and second data lines here can be any of the first to fourth pairs mentioned above.

[0263] Here, the first difference and the second difference can also be understood as grayscale difference.

[0264] S20-2. Determine whether both the first difference and the second difference are less than the first preset threshold. If yes, execute S20-3. If either is not, execute S21-1 and S22-1.

[0265] S20-3. If both the first difference and the second difference are less than the first preset threshold, the target sub-mode is determined to be the first sub-mode.

[0266] If the grayscale difference does not reach the first preset threshold, such as 10 grayscale, it is determined that CS will not be performed. Therefore, the target sub-mode is determined to be the first sub-mode, and the first data line and the second data line can be disconnected according to the first sub-mode.

[0267] Optionally, the first data signal and the second data signal have the same polarity, as shown by S1+ and S3+ in Figure 19; or, S2- and S4-, to determine the target sub-mode, specifically including S21-1 to S21-3.

[0268] S21-1. If at least one of the first difference and the second difference is greater than or equal to the first preset threshold, determine whether the first preset condition is met based on the first data signal of the current row, the first data signal of the previous row, the second data signal of the current row, and the second data signal of the previous row. If all are met, then execute S21-2; otherwise, execute S21-3.

[0269] In this step, the first preset condition includes a first sub-condition, a second sub-condition, a third sub-condition, and a fourth sub-condition; the first sub-condition includes a`>a, c`<c, a`>(a+c) / 2, c`>(a+c) / 2; the second sub-condition includes a`>a, c`<c, a`>(a+c) / 2, c`<(a+c) / 2, c>a; the third sub-condition includes a`>a, c`<c, a`<(a+c) / 2, c`>(a+c) / 2, -2(a`-c`)+ac<0; the fourth sub-condition includes a`>a, c`<c, a`<(a+c) / 2, c`<(a+c) / 2; where a` represents the first data signal of the current row, a represents the first data signal of the previous row, c` represents the second data signal of the current row, and c represents the second data signal of the previous row. Meeting the first preset condition means meeting at least one of the first, second, third, and fourth sub-conditions. Not meeting the first preset condition means that none of the first, second, third, and fourth sub-conditions are met.

[0270] S21-2. Determine the target sub-pattern as the second sub-pattern.

[0271] S21-3. Determine the target sub-pattern as the first sub-pattern.

[0272] Optionally, the first data signal and the second data signal have opposite polarities, as shown by S1+ and S2- in Figure 19; or, S3+ and S4-, to determine the target sub-mode, specifically including S22-1 to S22-3.

[0273] S22-1. If at least one of the first difference and the second difference is greater than or equal to the first preset threshold, determine whether the second preset condition is met based on the first data signal of the current row, the first data signal of the previous row, the second data signal of the current row, and the second data signal of the previous row. If all are met, then execute S22-2; otherwise, execute S22-3.

[0274] In this step, the second preset condition includes the fifth, sixth, and seventh sub-conditions; the fifth sub-condition includes a`<a, |b`|<|b|, a`>(a+b) / 2, b`>(a+b) / 2; the sixth sub-condition includes a`<a, |b`|<|b|, a`>(a+b) / 2, b`<(a+b) / 2, 2(a`-b`)+ba<0; the seventh sub-condition includes a`<a, |b`|<|b|, a`<(a+b) / 2, b`<(a+b) / 2; where a` represents the first data signal of the current row, a represents the first data signal of the previous row, b` represents the second data signal of the current row, and b represents the second data signal of the previous row. Satisfying the second preset condition means satisfying at least one of the fifth, sixth, and seventh sub-conditions. Not satisfying the first preset condition means that none of the fifth, sixth, and seventh sub-conditions are satisfied.

[0275] S22-2. Determine the target sub-pattern as the fourth sub-pattern.

[0276] S22-3. Determine the target sub-pattern as the first sub-pattern.

[0277] Optionally, the data line group includes an i-th pair of first and second data signals and a j-th pair of first and second data signals; wherein the i-th pair of first and second data signals has the same polarity, the j-th pair of first and second data signals has opposite polarities, and the first data signal in the i-th pair is the same as the first data signal in the j-th pair; as shown in Figure 19, i is 1 and j is 2; the first pair of first and second data signals refers to S1+ and S3+, and the second pair of first and second data signals refers to S1+ and S2-. There is a duplicate data line S1+ in both pairs; the i-th pair is a pair of the same polarity, and the j-th pair is a pair of opposite polarities, both of which may save power.

[0278] Specifically, when the target sub-mode of the i-th pair of first and second data signals is the second sub-mode, and the target sub-mode of the j-th pair of first and second data signals is the fourth sub-mode, it means that data line S1+ has a power-saving target sub-mode regardless of whether it is the same polarity with S3+ or the opposite polarity with S2-. In this case, each data line can only select one power-saving sub-mode, so the same polarity CS is selected first, that is, the second sub-mode is selected as the target sub-mode. After that, the target sub-mode of S1+ and S2- needs to be updated to the first sub-mode, that is, CS is not performed.

[0279] The above describes the CS judgment for a single pair of the first and second data lines in a data line group. However, in the actual calculation and control process, the timing controller needs to determine the unique CS situation of each data line in each data line group, including S1+ and S3+, S2- and S4- of the same polarity, and S1+ and S2-, S3+ and S4- of opposite polarity, and filter out the unique target sub-pattern of the data line, and further encode it to form a CS mode of a data line group, as shown in Table 2.

[0280] Table 2

[0281] Condition ①, also known as the first sub-condition: a'>a, c'<c, a'>(a+c) / 2, c'>(a+c) / 2; Condition ②, also known as the second sub-condition: a'>a, c'<c, a'>(a+c) / 2, c'<(a+c) / 2, c>a; Condition ③, also known as the third sub-condition: a'>a, c'<c, a'<(a+c) / 2, c'>(a+c) / 2, -2(a'-c')+ac<0; Condition ④, also known as the fourth sub-condition: a'>a, c'<c, a'< (a+c) / 2, c`<(a+c) / 2; Condition ⑤, also known as the fifth sub-condition: a`<a, |b`|<|b|, a`>(a+b) / 2, b`>(a+b) / 2; Condition ⑥, also known as the sixth sub-condition: a`<a, |b`|<|b|, a`>(a+b) / 2, b`<(a+b) / 2, 2(a`-b`)+ba<0; Condition ⑦, also known as the seventh sub-condition: a`<a, |b`|<|b|, a`<(a+b) / 2, b`<(a+b) / 2.

[0282] Based on Table 1 above, if at least one of the first difference and the second difference is greater than or equal to the first preset threshold, as shown in Figure 22, if the case is 1, 6, or 11, it is directly determined that CS does not save power. In this case, the CS mode is "7", and the code 110 can be directly output. Data lines S1, S2, S3, and S4 are all disconnected from each other. If the case is 2, 3, 5, 7, 9, or 10, it means that same-polarity CS may save power. Only it is determined whether condition ①, ②, ③, or ④ is met, and the unique code corresponding to output CS mode 1, 2, 3, or 7 is selected based on the result. If the case is 16, it means that opposite-polarity CS may save power. Only it is determined whether condition ⑤, ⑥, or ⑦ is met, and the unique code corresponding to CS mode 4, 5, 6, or 7 is selected based on the result. If the conditions are 4, 8, 12, 13, 14, or 15, it means that both same-polarity CS and opposite-polarity CS may save power. In this case, determine whether condition ①, ②, ③, ④, ⑤, ⑥, or ⑦ is met, and select the unique code corresponding to CS mode 1, 2, 3, 4, 5, 6, or 7 based on the result. If the power-saving conditions for both same-polarity CS and opposite-polarity CS are met, then same-polarity CS is performed first.

[0283] Optionally, the data cable group includes n data cables; n is equal to 3 or 4.

[0284] Optionally, n equals 4; as shown in Figure 19, each data line group includes two pairs of first data lines data1 and second data lines data1 with the same polarity, such as S1+&S3+ and S2-&S4-, and two pairs of first data lines data1 and second data lines data1 with opposite polarities, such as S1+&S2- and S3+&S4-; among the two pairs of first data lines data1 and second data lines data1 with the same polarity, one pair has a positive polarity (i.e., S1+&S3+) and the other pair has a negative polarity (i.e., S2-&S4-). The switching circuit includes a first sub-circuit 031, a second sub-circuit 032, a third sub-circuit 033, and a fourth sub-circuit 034. The first sub-circuit 031 is electrically connected to a pair of positive data lines S1+ and S3+; the second sub-circuit 032 is electrically connected to a pair of negative data lines S2- and S4-; the third sub-circuit 033 is electrically connected to a pair of opposite polarities of first data lines S1+ and S2-; and the fourth sub-circuit 034 is electrically connected to another pair of opposite polarities of first data lines S3+ and S4-. For example, the first sub-circuit 031 includes a sixth transistor T6, the second sub-circuit 032 includes a seventh transistor T7, the third sub-circuit 033 includes an eighth transistor T8, and the fourth sub-circuit 034 includes a ninth transistor T9. The first terminal of the sixth transistor T6 is electrically connected to S1+, and the second terminal of the sixth transistor T6 is electrically connected to S3+. In response to a valid control signal, the control terminal of the sixth transistor T6 connects S1+ and S3+; in response to an invalid control signal, it disconnects S1+ and S3+. The first terminal of the seventh transistor T7 is electrically connected to S2-, and the second terminal of the seventh transistor T7 is electrically connected to S4-. In response to a valid control signal, the control terminal of the seventh transistor T7 connects S2- and S4-; in response to an invalid control signal, it disconnects S2- and S4-. The first terminal of the eighth transistor T8 is electrically connected to S1+, and the second terminal of the eighth transistor T8 is electrically connected to S2-. In response to a valid control signal, the control terminal of the eighth transistor T8 connects S1+ and S2-; in response to an invalid control signal, it disconnects S1+ and S2-. The first terminal of the ninth transistor T9 is electrically connected to S3+, and the second terminal of the ninth transistor T9 is electrically connected to S4-; the control terminal of the ninth transistor T9 connects S3+ and S4- in response to a valid control signal; the control terminal of the ninth transistor T9 disconnects S3+ and S4- in response to an invalid control signal.

[0285] Based on this, for step S300, the switching circuit is driven according to the target sub-mode, specifically including S41 to S43, as shown in Figure 23.

[0286] S41. When the target sub-mode is the first sub-mode, drive the switching circuit to disconnect a pair of first data lines and second data lines.

[0287] The first sub-mode can be a mode that does not achieve charge sharing. Therefore, when the target sub-mode is the first sub-mode, the switching circuit is driven to respond to an invalid control signal, thereby isolating a pair of first and second data lines.

[0288] Optionally, the target sub-mode is a first sub-mode; the first sub-circuit is driven according to the first sub-mode, isolating a pair of positive first and second data lines; and / or, the second sub-circuit is driven according to the first sub-mode, isolating a pair of negative first and second data lines; and / or, the third sub-circuit is driven according to the first sub-mode, isolating a pair of first and second data lines with opposite polarities; and / or, the third sub-circuit is driven according to the first sub-mode, isolating another pair of first and second data lines with opposite polarities. For example, as shown in FIG19, when n equals 4, it includes S1+&S3+, S2-&S4-, S1+&S2-, and S3+&S4-. When the target sub-mode of S1+&S3+ is the first sub-mode, the sixth transistor, in response to an invalid control signal, isolates S1+ and S3+. When the target sub-mode of S2-&S4- is the first sub-mode, the seventh transistor, in response to an invalid control signal, isolates S2- and S4-. When the target sub-mode of S1+ & S2- is the first sub-mode, the eighth transistor responds to the invalid control signal and disconnects S1+ and S2-. When the target sub-mode of S3+ & S4- is the first sub-mode, the ninth transistor responds to the invalid control signal and disconnects S3+ and S4-.

[0289] S42. When the target sub-mode is the second sub-mode, drive the switching circuit to connect a pair of first and second data lines with the same polarity in the data line group.

[0290] The second sub-mode can be a mode that enables charge sharing between a pair of first and second data lines with the same polarity.

[0291] Optionally, the target sub-mode is the second sub-mode; the first sub-circuit is driven according to the second sub-mode, connecting a pair of positive first and second data lines; and / or, when the target sub-mode is the second sub-mode, the second sub-circuit is driven, connecting a pair of negative first and second data lines. For example, as shown in FIG19, when n equals 4, it includes S1+&S3+, S2-&S4-, S1+&S2-, and S3+&S4-. When the target sub-mode of S1+&S3+ is the second sub-mode, the sixth transistor connects S1+ and S3+ in response to a valid control signal. When the target sub-mode of S2-&S4- is the second sub-mode, the seventh transistor connects S2- and S4- in response to a valid control signal.

[0292] S43. When the target sub-mode is the fourth sub-mode, drive the switching circuit to connect a pair of first and second data lines with opposite polarities in the data line group.

[0293] The fourth sub-mode can be a mode that enables charge sharing between a pair of first and second data lines with opposite polarities.

[0294] Optionally, when the target sub-mode is the fourth sub-mode, the third sub-circuit is driven, connecting a pair of first and second data lines with opposite polarities; and / or, when the target sub-mode is the fourth sub-mode, the fourth sub-circuit is driven, connecting another pair of first and second data lines with opposite polarities. For example, as shown in FIG19, when n equals 4, this includes S1+&S3+, S2-&S4-, S1+&S2-, and S3+&S4-. When the target sub-mode of S1+&S2- is the fourth sub-mode, the eighth transistor connects S1+ and S2- in response to a valid control signal. When the target sub-mode of S3+&S4- is the fourth sub-mode, the ninth transistor connects S3+ and S4- in response to a valid control signal.

[0295] It should be noted that if S1+ & S3+ is the second sub-pattern in S42, and S1+ & S2- is the fourth sub-pattern in S43, then the target sub-pattern of S1+ & S2- is updated to the first sub-pattern, and only the unique target sub-pattern of the duplicate S1+ is retained.

[0296] In some embodiments, the display device further includes a source driver, which is electrically connected to the sub-pixel via a data line; the display method further includes PWRC level control, specifically including S301 to S303, as shown in FIG24.

[0297] S301. For any data line in the data line group, determine the difference between the current row data voltage signal and the previous row data voltage signal.

[0298] As shown in Figures 19 and 22, the differences between the current row data voltage signal and the previous row data voltage signal of data lines S1+, S2-, S3+, and S4- are calculated respectively to obtain the grayscale difference of S1+, S2-, S3+, and S4-.

[0299] S302. For a data cable group, if the difference between any data cable is less than the second preset threshold, determine the second target PWRC level corresponding to the data cable group.

[0300] For example, as shown in Figure 22, the second preset threshold is 10. Dynamic bias control is performed based on the judgment results of whether the gray level difference S1+, S2-, S3+, and S4- reaches 10 gray levels. For example, if any one of the gray level difference S1+, S2-, S3+, and S4- reaches 10 gray levels, the PWRC level corresponding to the entire data line group is determined to be a high level; otherwise, it is a low level, and the second target PWRC level is output. This allows for real-time dynamic adjustment of the PWRC level, saving power consumption.

[0301] S303 controls the source driver to output the first data signal and the second data signal according to the second target PWRC setting.

[0302] This embodiment can dynamically adjust the PWRC level and adjust it according to the data cable group. Compared with the traditional PWRC, which can only set the level for different projects and cannot be adjusted for different screens, this disclosure can save power consumption.

[0303] In some embodiments, multiple data lines are divided into multiple data line groups, each controlled by a separate register. Each data line group includes n data lines; n equals 4. The 1 bit added to each data line in the 8b / 10b encoding method can be used, so that each data line group has 4 available bits, as shown in Figure 25. The high 3 bits are selected as the CS control bit, each bit used to hold the aforementioned encoded value, i.e., 000~110, to individually control the CS mode of each data line group. The last bit is used as the PWRC control bit, used to control the PWRC setting of the entire data line group (i.e., including each data line) during the output stage.

[0304] In some embodiments, as shown in Figure 26, the subpixel arrangement in a 6-bit color depth product is such that multiple data lines are also divided into multiple data line groups, with each data line group containing n data lines, where n equals 3. The 1 bit added to each data line in the 8b / 10b encoding method can be used to provide 3 available bits for each data line group, all of which are used as CS control bits to accommodate the aforementioned encoded values, i.e., 000 to 110, to individually control the CS mode of each data line group. No PWRC control bits are set, meaning no PWRC level adjustment is performed.

[0305] In some embodiments, as shown in Figure 27, the sub-pixel arrangement is the target architecture, namely a dual-gate architecture. Two gate lines are provided between two adjacent rows of sub-pixels, and the sub-pixels in every two columns of sub-pixels are electrically connected to the same data line. As shown in Figure 28, with the sub-pixel arrangement in adjacent rows, the data line sends the corresponding data voltage signal during gate line scanning. Based on the target architecture, according to the comparison of the interlaced data voltage signals in Figure 29, that is, according to the comparison of the adjacent two rows of data voltage signals actually sent by the source driver, the source driver needs two memories (such as latch line latch-1 and latch line latch-2) to store data.

[0306] Optionally, when scanning the i-th row of gate lines, the data voltage signal of the i-th row and the data voltage signal of the (i-2)-th row of data lines are acquired; i is a positive integer greater than 2, and i is less than or equal to the number of gate lines; if the data voltage signal of the i-th row and the data voltage signal of the (i-2)-th row are the same and i is odd, the data voltage signal of the (i-2)-th row stored in the first memory is acquired as the data voltage signal of the data line for this row, so as to drive the sub-pixel to display the image; if the data voltage signal of the i-th row and the data voltage signal of the (i-2)-th row are the same and i is even, the data voltage signal of the (i-2)-th row stored in the second memory is acquired as the data voltage signal of the data line for this row, so as to drive the sub-pixel to display the image. Here, it is necessary to compare the acquired data voltage signal of the i-th row with the data voltage signal of the (i-2)-th row to determine whether the two data voltage signals are consistent. If they are consistent, it means that the timing controller will send the same data voltage signal for two consecutive rows. In this regard, this disclosure stops the timing controller from sending the same data voltage signal to the source driver and calls the data voltage signal of the previous row stored in the first or second memory built into the source driver as the data voltage signal of the current row, so as to reduce the power consumption of repeatedly sending the same data voltage signal.

[0307] Optionally, when the data voltage signal of the i-th row is different from the data voltage signal of the (i-2)-th row, the sub-pixels are driven to display the image according to the data voltage signal of the i-th row; when i is odd, the data voltage signal of the i-th row is stored in the first memory; when i is odd, the data voltage signal of the i-th row is stored in the second memory. When i equals 1, the sub-pixels are driven to display the image according to the data voltage signal of the 1-th row, and the data voltage signal of the 1-th row is stored in the first memory; when i equals 2, the sub-pixels are driven to display the image according to the data voltage signal of the 2-th row, and the data voltage signal of the 2-th row is stored in the second memory. Here, when the data voltage signal of the i-th row is different from the data voltage signal of the (i-2)-th row, the sub-pixels are normally driven to display the image according to the data voltage signal of this row, but the data voltage signal of this row is stored in the corresponding memory for later retrieval in the next row.

[0308] Here, the first memory and the second memory can be latches or registers, such as latch line latch-1 and latch line latch-2.

[0309] For example, to facilitate understanding, the overall process of the driver self refresh (DSR) scheme under the dual gate architecture when scanning the i-th row of gate lines is described below, as shown in Figure 30, including S51 to S515.

[0310] S51, Receive the i-th row of data voltage signal from the data line.

[0311] S52. Determine if i is greater than 2; if yes, execute S53; otherwise, execute S512.

[0312] Obtain the data voltage signal of the i-th row and the data voltage signal of the (i-2)-th row of the data line.

[0313] S53. Obtain the data voltage signal of the (i-2)th row of the data line.

[0314] S54. Determine if the voltage signal of the data in row i is the same as the voltage signal of the data in row i-2. If they are the same, execute S55; otherwise, execute S58.

[0315] S55. Determine whether i is odd or even. If it is odd, execute S56; if it is even, execute S57.

[0316] S56. Obtain the data voltage signal of the (i-2)th row stored in the first memory, and use it as the data voltage signal of the data line for this row to drive the sub-pixel to display the image.

[0317] S57. Obtain the (i-2)th row data voltage signal stored in the second memory, and use it as the data voltage signal for this row of the data line to drive the sub-pixel to display the image.

[0318] S58. Drive the sub-pixels to display the image according to the voltage signal of the i-th row of data, and execute S59 in sequence.

[0319] S59. Determine whether i is odd or even. If it is odd, execute S510; if it is even, execute S511.

[0320] S510, Store the voltage signal of the i-th row of data into the first memory.

[0321] S511. Store the voltage signal of the i-th row of data into the second memory.

[0322] S512, drive the sub-pixels to display the image according to the data voltage signal of the i-th row, and execute S513 in sequence.

[0323] S513. Determine whether i is odd or even. If it is odd, execute S514; if it is even, execute S515.

[0324] S514. Store the voltage signal of the i-th row of data into the first memory.

[0325] S515. Store the voltage signal of the i-th row of data into the second memory.

[0326] The implementation of the overall DSR scheme in the above S511 to S515 processes can be based on the control execution of the timing controller (Tcon).

[0327] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0328] In addition, this disclosure also provides a display device corresponding to the display method, which is configured to execute any of the above embodiments and combinations thereof. Since the principle by which the display device solves the problem is similar to the above-described display method, the implementation of the display device can refer to the implementation of the method, and repeated details will not be elaborated further. This display device can be, for example, any product with a display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure.

[0329] Furthermore, according to embodiments of this disclosure, a computer non-transient readable storage medium is also provided. This computer non-transient readable storage medium stores a computer program, which, when executed by a processor, implements the steps of any of the display methods described in the above embodiments.

[0330] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a machine-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), it performs the functions defined above in the system of this disclosure.

[0331] It should be noted that the computer-readable non-transient readable medium disclosed herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. Computer-readable storage media may be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. The transmitted data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any non-transient readable computer storage medium other than a computer-readable storage medium, which can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the non-transient readable computer storage medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0332] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two adjacent blocks may actually represent substantially parallel execution, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0333] The circuits or sub-circuits described in the embodiments of this disclosure can be implemented in software or hardware. The described circuits or sub-circuits can also be housed in a processor; for example, it can be described as: a processor including: a receiving circuit and a processing circuit, the processing module including a writing sub-circuit and a reading sub-circuit. The names of these circuits or sub-circuits do not necessarily constitute a limitation on the circuit or sub-circuit itself; for example, a receiving circuit can also be described as "receiving video signals".

[0334] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display method applied to a display device, the display device comprising sub-pixels arranged in an array, gate lines and data lines connected to the sub-pixels, and a switching circuit; the plurality of data lines are divided into a plurality of data line groups, each data line group comprising at least one pair of first data lines and second data lines, the data line groups being correspondingly arranged with the switching circuit; the switching circuit being used to control the connection or disconnection between the first data lines and the second data lines; the display method comprising: For scanning any row of the gate lines, acquire the first data signal of the current row of the first data line, the first data signal of the previous row of the first data line, the second data signal of the current row of the second data line, and the second data signal of the previous row of the second data line; The target sub-mode is determined from multiple sub-modes of charge sharing based at least on the first data signal of the current row, the first data signal of the previous row, the second data signal of the current row, and the second data signal of the previous row. The switching circuit is driven according to the target sub-mode to drive the sub-pixel to display the image.

2. The display method according to claim 1, wherein The plurality of sub-patterns includes a first sub-pattern and a second sub-pattern; Driving the switching circuit according to the target sub-mode includes: When the target sub-mode is the first sub-mode, the switching circuit is driven to disconnect a pair of the first data lines and the second data lines; When the target sub-mode is the second sub-mode, the switching circuit is driven to connect a pair of first data lines and second data lines with the same polarity in the data line group.

3. The display method according to claim 2, wherein, The multiple sub-patterns also include a third sub-pattern; Driving the switching circuit according to the target sub-mode includes: When the target sub-mode is the third sub-mode, the switching circuit is driven to connect all the data lines electrically connected to the same color sub-pixel in the data line group.

4. The display method according to claim 2, wherein The plurality of sub-patterns also includes a fourth sub-pattern; Driving the switching circuit according to the target sub-mode includes: When the target sub-mode is the fourth sub-mode, the switching circuit is driven to connect a pair of first data lines and second data lines with opposite polarities in the data line group.

5. The display method according to any one of claims 1 to 3, wherein The step of determining the target sub-mode from multiple charge-sharing sub-modes based at least on the current row's first data signal, the previous row's first data signal, the current row's second data signal, and the previous row's second data signal includes: The first charge amount of the first data line corresponding to each of the sub-modes is determined based at least on the first data signal of the current row, the first data signal of the previous row, the storage capacitor, the parasitic capacitor, and the number of pre-charged rows. The second charge amount of the second data line corresponding to each of the sub-modes is determined based at least on the second data signal of the current row, the second data signal of the previous row, the storage capacitor, the parasitic capacitor, and the number of pre-charged rows. The target sub-mode is determined from multiple sub-modes that share charge, based on the first charge amount of the first data line corresponding to each of the sub-modes and the second charge amount of the second data line corresponding to each of the sub-modes.

6. The display method according to claim 5, wherein The step of determining the target sub-mode from multiple charge-sharing sub-modes based on the first charge amount of the first data line corresponding to each of the sub-modes and the second charge amount of the second data line corresponding to each of the sub-modes includes: For any of the sub-modes, calculate the sum of the first charge and the second charge; The summation results of each of the sub-patterns are compared, and the sub-pattern corresponding to the smallest summation result is taken as the target sub-pattern.

7. The display method according to claim 5, wherein In the data line group, the polarities of the data voltage signals transmitted by two adjacent data lines at the same time are opposite; the first data line and the second data line are electrically connected to sub-pixels of the same color; the polarities of the first data signal and the second data signal are the same; the multiple sub-modes include a first sub-mode, a second sub-mode, and a third sub-mode; The data line group includes n data lines; n is a positive integer greater than or equal to 9.

8. The display method according to claim 7, wherein n equals 12; for any color sub-pixel, each group of data lines includes two pairs of first data lines and second data lines, where one pair has positive polarity and the other pair has negative polarity; the switching circuit includes sub-circuits corresponding one-to-one with the color of the sub-pixel; for any sub-circuit, it includes a first switching unit, a second switching unit, and a third switching unit; the first switching unit is electrically connected to a pair of positive polarity first data lines and second data lines, the second switching unit is electrically connected to a pair of negative polarity first data lines and second data lines, and the third switching unit is electrically connected to at least one of the pair of positive polarity first data lines and second data lines and at least one of the pair of negative polarity first data lines and second data lines.

9. The display method according to claim 5, wherein, The sub-pattern is the first sub-pattern; The step of determining the first charge amount in the first sub-mode includes: The first charge required for normal display of this row is determined based on the first data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows; Based on the first data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the first data signal of the current row in the previous frame, determine the second charge remaining before the current row is charged; The first charge amount of the first data line in the first sub-mode is determined based on the first charge and the second charge.

10. The display method according to claim 5, wherein The sub-pattern is the first sub-pattern; The step of determining the second charge amount in the first sub-mode includes: Based on the second data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows, determine the third charge required for normal display of this row; Based on the second data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the second data signal of the current row in the previous frame, determine the fourth charge remaining before the current row is charged; Based on the third charge and the fourth charge, the amount of the second charge corresponding to the second data line in the first sub-mode is determined.

11. The display method according to claim 5, wherein, The sub-pattern is the second sub-pattern; The steps for determining the first charge and the second charge in the second sub-mode include: Based on the first data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows, determine the first charge required for normal display of this row; Based on the first data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the first data signal of the current row in the previous frame, determine the second charge remaining before the current row is charged; The third charge required for normal display of this row is determined based on the second data signal of this row, the storage capacitor, the parasitic capacitance, and the number of pre-charged rows; Based on the second data signal of the previous row, the storage capacitor, the parasitic capacitor, the number of pre-charged rows, and the second data signal of the current row in the previous frame, determine the fourth charge remaining before the current row is charged; Half of the sum of the second charge and the fourth charge is taken as the fifth charge; Based on the first charge and the fifth charge, determine the first charge amount of the first data line in the second sub-mode; The second charge amount of the second data line in the second sub-mode is determined based on the third charge and the fifth charge.

12. The display method according to claim 5, wherein, The sub-pattern is the third sub-pattern; The steps for determining the first charge and the second charge in the third sub-mode include: For a pair of first data lines and second data lines, the first charge required for normal display of the current line is determined based on the first data signal of the current line, the storage capacitor, the parasitic capacitance, and the number of pre-charged lines; the second charge remaining before charging of the current line is determined based on the first data signal of the previous line, the storage capacitor, the parasitic capacitance, the number of pre-charged lines, and the first data signal of the current line in the previous frame; the third charge required for normal display of the current line is determined based on the second data signal of the current line, the storage capacitor, the parasitic capacitance, and the number of pre-charged lines; and the fourth charge remaining before charging of the current line is determined based on the second data signal of the previous line, the storage capacitor, the parasitic capacitance, the number of pre-charged lines, and the second data signal of the current line in the previous frame. For two pairs of the first data lines and the second data lines, the average of the sums of the two second charges and the two fourth charges is taken as the sixth charge; For a pair of first data lines and second data lines, the first charge amount of the first data line in the third sub-mode is determined based on the first charge and the sixth charge; the second charge amount of the second data line in the third sub-mode is determined based on the third charge and the sixth charge.

13. The display method according to claim 1, wherein, The switching circuit includes a fourth switching unit; the fourth switching unit is electrically connected to the first data line and the last data line in the display device; the display method further includes: When the sub-pixel arrangement is determined to be the target architecture, for any sub-mode, the fourth switching unit is driven to connect the first data line and the last data line; The target architecture has two gate lines between two adjacent rows of sub-pixels, and sub-pixels in every two columns of sub-pixels are electrically connected to the same data line.

14. The display method according to claim 1, wherein, The display device further includes a source driver, which is electrically connected to the sub-pixel via the data line; The display method further includes: Based on the first charge amount corresponding to the first data line and the second charge amount corresponding to the second data line in the target sub-mode, determine a first target PWRC gear corresponding to a pair of the first data line and the second data line; The source driver is controlled to output the first data signal and the second data signal according to the first target PWRC setting.

15. The display method according to any one of claims 1, 2, and 4, wherein, The data voltage signals transmitted by two adjacent data lines in the data line group at the same time have opposite polarities; the first data signal and the second data signal have the same or opposite polarities; the multiple sub-modes include a first sub-mode, a second sub-mode, and a fourth sub-mode.

16. The display method according to claim 15, wherein, The step of determining the target sub-mode from multiple charge-sharing sub-modes based at least on the current row's first data signal, the previous row's first data signal, the current row's second data signal, and the previous row's second data signal includes: Determine the first difference between the first data signal in the current row and the first data signal in the previous row, and the second difference between the second data signal in the current row and the second data signal in the previous row; If both the first difference and the second difference are less than the first preset threshold, the target sub-mode is determined to be the first sub-mode.

17. The display method according to claim 16, wherein, The first data signal and the second data signal have the same polarity; The display method further includes: If at least one of the first difference and the second difference is greater than or equal to the first preset threshold, based on the first data signal of the current row, the first data signal of the previous row, the second data signal of the current row, and the second data signal of the previous row, it is determined whether the first preset condition is met; the first preset condition includes a first sub-condition, a second sub-condition, a third sub-condition, and a fourth sub-condition; If at least one of the first sub-condition, the second sub-condition, the third sub-condition, and the fourth sub-condition is satisfied, the target sub-pattern is determined to be the second sub-pattern; if none of the first, second, third, and fourth sub-conditions are satisfied, the target sub-pattern is determined to be the first sub-pattern. The first sub-condition includes a`>a, c`<c, a`>(a+c) / 2, c`>(a+c) / 2; the second sub-condition includes a`>a, c`<c, a`>(a+c) / 2, c`<(a+c) / 2, c>a; the third sub-condition includes a`>a, c`<c, a`<(a+c) / 2, c`>(a+c) / 2, -2(a`-c`)+ac<0; the fourth sub-condition includes a`>a, c`<c, a`<(a+c) / 2, c`<(a+c) / 2; Wherein, a` represents the first data signal of the current row, a represents the first data signal of the previous row, c` represents the second data signal of the current row, and c represents the second data signal of the previous row.

18. The display method according to claim 16, wherein, The first data signal and the second data signal have opposite polarities, with the first data signal being positive and the second data signal being negative. The display method further includes: If at least one of the first difference and the second difference is greater than or equal to the first preset threshold, based on the first data signal of the current row, the first data signal of the previous row, the second data signal of the current row, and the second data signal of the previous row, it is determined whether the second preset condition is met; the second preset condition includes a fifth sub-condition, a sixth sub-condition, and a seventh sub-condition; If at least one of the fifth, sixth, and seventh sub-conditions is satisfied, the target sub-pattern is determined to be the fourth sub-pattern; if none of the fifth, sixth, and seventh sub-conditions are satisfied, the target sub-pattern is determined to be the first sub-pattern. The fifth sub-condition includes a`<a, |b`|<|b|, a`>(a+b) / 2, b`>(a+b) / 2; the sixth sub-condition includes a`<a, |b`|<|b|, a`>(a+b) / 2, b`<(a+b) / 2, 2(a`-b`)+ba<0; the seventh sub-condition includes a`<a, |b`|<|b|, a`<(a+b) / 2, b`<(a+b) / 2; Wherein, a` represents the first data signal of the current row, a represents the first data signal of the previous row, b` represents the second data signal of the current row, and b represents the second data signal of the previous row.

19. The display method according to claim 17 or 18, wherein, The data line group includes an i-th pair of first data signals and a j-th pair of first data signals and second data signals; wherein the i-th pair of first data signals and second data signals has the same polarity, the j-th pair of first data signals and second data signals has opposite polarities, and the first data signal in the i-th pair is the same as the first data signal in the j-th pair; the display method further includes: When the target sub-mode of the i-th pair of first data signals and second data signals is the second sub-mode, and the target sub-mode of the j-th pair of first data signals and second data signals is the fourth sub-mode, the target sub-mode of the i-th pair of first data signals and second data signals is determined to be the second sub-mode, and the target sub-mode of the j-th pair of first data signals and second data signals is updated to the first sub-mode.

20. The display method of claim 15, wherein, The data line group includes n data lines; n is equal to 3 or 4.

21. The display method according to claim 20, wherein, n equals 4; each group of data lines includes two pairs of first data lines and second data lines with the same polarity, and two pairs of first data lines and second data lines with opposite polarities; wherein, of the two pairs of first data lines and second data lines with the same polarity, one pair is positive and the other pair is negative; the switching circuit includes a first sub-circuit, a second sub-circuit, a third sub-circuit, and a fourth sub-circuit; the first sub-circuit is electrically connected to a pair of first data lines and second data lines with positive polarity, the second sub-circuit is electrically connected to a pair of first data lines and second data lines with negative polarity, the third sub-circuit is electrically connected to a pair of first data lines and second data lines with opposite polarities, and the fourth sub-circuit is electrically connected to another pair of first data lines and second data lines with opposite polarities.

22. The display method according to claim 1, wherein, The display device further includes a source driver, which is electrically connected to the sub-pixel via the data line; The display method further includes: For any data line in the data line group, determine the difference between the current row data voltage signal and the previous row data voltage signal of the data line; For the data cable group, if the difference between any of the data cables is less than a second preset threshold, the second target PWRC level corresponding to the data cable group is determined. The source driver is controlled to output the first data signal and the second data signal according to the second target PWRC setting.

23. The display method according to claim 1, wherein, The sub-pixel arrangement is a target architecture; the target architecture has two gate lines between two adjacent rows of sub-pixels, and sub-pixels in every two columns of sub-pixels are electrically connected to the same data line; the display method further includes: When scanning the i-th row of the gate lines, the data voltage signal of the i-th row and the data voltage signal of the (i-2)-th row of the data lines are obtained; i is a positive integer greater than 2, and i is less than or equal to the number of the gate lines; When the data voltage signal of the i-th row and the data voltage signal of the (i-2)-th row are the same and i is an odd number, the data voltage signal of the (i-2)-th row stored in the first memory is obtained as the data voltage signal of the current row of the data line to drive the sub-pixel to display the image; When the data voltage signal of the i-th row and the data voltage signal of the (i-2)-th row are the same and i is an even number, the data voltage signal of the (i-2)-th row stored in the second memory is obtained as the data voltage signal of the current row of the data line to drive the sub-pixel to display the image.

24. The display method according to claim 23, wherein, The display method further includes: When the voltage signal of the i-th row of data and the voltage signal of the (i-2)-th row of data are different, the sub-pixel is driven to display the image according to the voltage signal of the i-th row of data. When i is an odd number, the voltage signal of the i-th row of data is stored in the first memory; When i is an odd number, the voltage signal of the i-th row of data is stored in the second memory.

25. The display method according to claim 23, wherein The display method further includes: When i equals 1, the sub-pixel is driven to display the image according to the first row of data voltage signal, and the first row of data voltage signal is stored in the first memory; When i equals 2, the sub-pixel is driven to display the image according to the second row of data voltage signal, and the second row of data voltage signal is stored in the second memory.

26. A display device configured to perform the display method as claimed in any one of claims 1 to 25.

27. A computer non-transitory readable storage medium, wherein, The computer non-transient readable storage medium stores a computer program that, when executed by a processor, performs the steps of the display method as described in any one of claims 1 to 25.

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