Hybrid manufacturing method

Abstract

The invention regards a hybrid manufacturing method for processing multiple wafers in parallel, the method comprising: providing at least two wafers, each wafer comprising at least one trench, wherein the at least one trench is etched from a first side to a second side of the wafer and wherein an electrical insulation layer is arranged on the 5 first side and the second side of the wafer and on the inner sides of the at least one trench; arranging the at least two wafers on a panel carrier substrate; arranging a first redistribution layer on the first side of each of the at least two wafers; flipping the at least two wafers; filling the at least one trench in each of the at least two wafers with an electrically conductive material; and arranging a second redistribution layer on the 10 second side of each of the at least two wafers. The application further relates to a system for processing multiple wafers in parallel.

Description

[0001] P7462PC00

[0002] 1

[0003] Hybrid Manufacturing Method

[0004] The present disclosure relates to a hybrid manufacturing method for processing multiple wafers in parallel that combines cleanroom-based semiconductor techniques with panel-based processing typically used in printed circuit board (PCB) production.

[0005] Background

[0006] The current state of the art in semiconductor wafer manufacturing for high-performance applications, such as power interposers, involves intricate cleanroom-based processes designed to ensure precise etching, insulation, and electrical performance. These processes, typically executed in a controlled cleanroom environment, achieve high precision but are also resource-intensive. They rely on complex steps like deep reactive ion etching (DRIE), physical vapor deposition (PVD) or atomic layer deposition (ALD). These steps require a cleanroom setting to maintain the accuracy and quality needed for semiconductor structures, which are highly sensitive to contamination. Consequently, these production steps demand dedicated semiconductor facilities, which are costly to establish and operate.

[0007] However, such cleanroom-specific processes exhibit significant drawbacks in terms of scalability and cost-effectiveness, particularly for applications where ultra-fine feature sizes and sub-micron tolerances are unnecessary. The necessity of extensive cleanroom conditions, combined with the high costs of proprietary equipment, restricts production flexibility and limits the opportunity to adapt processes to alternative, lower- cost manufacturing setups. This dependency on cleanroom environments for even non- critical features translates to high operational costs and limits the potential for cost reductions, which is especially disadvantageous in applications targeting cost-sensitive markets like consumer electronics or industrial components.

[0008] Further, conventional wafer manufacturing methods present constraints in terms of throughput and adaptability. These processes generally treat each silicon wafer individually, with minimal opportunity for batch processing, making them time-intensive and further increasing the per-unit production cost. As global demand for powerefficient and low-cost wafers grows, existing methods lack the agility needed to expand production without substantial investment, hampering efforts to make semiconductor components more economically accessible for high-volume applications. P7462PC00

[0009] 2

[0010] It is therefore an objective of the present disclosure to provide an improved manufacturing method for wafers that reduces reliance on cleanroom-specific processing, lowers costs, and increases scalability by integrating alternative, more versatile manufacturing techniques.

[0011] Summary

[0012] The present disclosure relates to a hybrid manufacturing method for processing multiple wafers in parallel, the method comprising: providing at least two wafers, each wafer comprising at least one trench, wherein the at least one trench is etched from a first side to a second side of the wafer and wherein an electrical insulation layer is arranged on the first side and the second side of the wafer and on the inner sides of the at least one trench; arranging the at least two wafers on a panel carrier substrate; arranging a first redistribution layer on the first side of each of the at least two wafers; flipping the at least two wafers; filling the at least one trench in each of the at least two wafers with an electrically conductive material; and arranging a second redistribution layer on the second side of each of the at least two wafers.

[0013] A “wafer” is a substantially planar substrate of semiconductor material, typically in the form of a thin disk, on or in which integrated circuits are fabricated. The wafer may comprise a single-crystal semiconductor (e.g., silicon) and provides a base for forming device structures and interconnect layers prior to singulation into individual dies. The wafers may thus be a silicon wafers. The wafers may include a plurality of integrated- circuit dies, for example at least tens, hundreds, or thousands of dies formed on each wafer. The wafer may carry a two-dimensional array of dies.

[0014] The present disclosure introduces a hybrid manufacturing approach that can integrate semiconductor manufacturing processes with panel-based processing techniques or PCB-based manufacturing techniques, enabling efficient fabrication of wafers. The method begins by preparing multiple wafers simultaneously, arranging them on a panel carrier substrate to facilitate parallel processing. This configuration reduces the complexity and cost typically associated with individual wafer handling in conventional semiconductor fabrication. By using a panel carrier substrate, the method supports the simultaneous processing of multiple wafers, enhancing throughput and scalability.

[0015] One or more trenches may be formed through each wafer, each trench extending from a first side of the wafer to an opposite second side. P7462PC00

[0016] 3

[0017] After formation of the one or more trenches, an electrical insulation layer may be deposited on the wafer. The electrical insulation layer is preferably a substantially conformal dielectric coating that covers at least the first side of the wafer around the trench opening, the second side of the wafer around the trench opening, and inner sidewalls of the trench along its depth. In other words, the insulation layer lines the trench and simultaneously overlies the surfaces of the wafer.

[0018] The electrical insulation layer may be applied as a continuous layer over substantially the entire exposed wafer surface, including the trench sidewalls, before any conductive fill is introduced. The electrical insulation layer may thus define an electrically insulating liner for the trench and an insulating surface on both wafer sides.

[0019] The step of depositing / arranging the electrical insulation layer on the first side and the second side of the wafer and on the inner sides of the at least one trench may be performed before the step of arranging the at least two wafers on the panel carrier substrate. In other words, the electrical insulation layer may be deposited before wafer mounting.

[0020] The method may incorporate the use of electrical insulation layers that are deposited on both sides of the wafers and within the at least one trench. The electrical insulation layer ensures effective electrical isolation, which may be critical for maintaining the performance of the through-wafer vias, particularly in high-power applications. A seed layer can be applied to at least the first side of the wafers, serving as a conductive foundation for subsequent metal deposition processes. The wafers are then arranged on the panel carrier substrate, which may include a conductive base to preferably provide a direct current path, optimizing the plating process and enhancing uniformity in further metal deposition.

[0021] Further steps may be performed in a panel-based environment.

[0022] Flipping the wafers can allow access to the second side of the wafers for further processing. After flipping, the method can fill the at least one trench with an electrically conductive material using a bottom-up plating approach, ensuring that the through- wafer vias are completely filled without voids. This technique can enhance the structural and electrical integrity of the through-wafer vias, providing reliable conductive pathways suitable for power applications. The final step can involve arranging a second P7462PC00

[0023] 4 redistribution layer on the second side of the wafers, completing the routing network necessary for integrating the wafers into electronic assemblies.

[0024] In a further aspect, the present disclosure discloses a wafer for power applications that is manufactured according to the disclosed method. The wafer features robust through- wafer vias and thick redistribution layers, making it ideal for high-current applications where efficient power distribution and thermal management are critical. The use of thick copper layers for the redistribution network reduces electrical resistance and supports higher current-carrying capacity, enhancing the wafer’s suitability for use in consumer electronics, industrial devices, and loT systems.

[0025] In a third aspect, the present disclosure relates to a system for manufacturing the power wafer, that may comprise a panel carrier substrate, a dry-film resist lamination unit, a photolithography unit, and a control unit. The panel carrier substrate is configured to support one or more wafers during the process, allowing for parallel processing and increased production efficiency. The dry-film resist lamination unit can apply a resist layer to define the patterns for the redistribution layers, while the photolithography unit precisely aligns and patterns the resist. The conductive base, preferably included in the panel carrier substrate, enables efficient current distribution during plating, ensuring uniform deposition of conductive materials. The control unit manages the sequence of operations, executing the steps of the hybrid manufacturing method as disclosed herein to achieve a consistent and high-quality wafer output.

[0026] This hybrid approach, which leverages both cleanroom and panel-based technologies, provides a scalable and cost-effective solution for manufacturing power wafers. By reducing dependency on cleanroom-specific processes and enabling high-throughput panel-based processing, the disclosed method significantly lowers production costs while maintaining the performance required for demanding power applications.

[0027] Description of the drawings

[0028] In the following embodiment and examples will be described in greater detail with reference to the accompanying drawings:

[0029] Figs. 1 A-H show schematic views of embodiments of the different steps of the method as disclosed herein, wherein Figs. 1 A-D show schematic views of embodiments of process steps that are performed in a cleanroom-environment, and P7462PC00

[0030] 5 wherein Figs. 1 E-H show schematic views of embodiments of process steps that are performed in a panel-based environment, and

[0031] Figs. 2A-F show schematic views of embodiments of the different steps of the method as disclosed herein, wherein at least one conductive foil is used, and wherein the schematic views of embodiments of the process steps are performed in a panelbased environment. The embodiments of the process steps as shown in Figs. 2A-F are following the embodiments of the process steps performed in a cleanroom-environment of Figs. 1A-D.

[0032] Detailed description

[0033] The present disclosure can relate to a method of processing a power interposer comprising at least one through-interposer via with a hybrid manufacturing process. The method may comprise: providing at least two interposers comprising at least one trench, wherein the at least one trench is etched from a first side to a second side of the at least two interposers and wherein an electrical insulation layer is arranged on the first side and the second side of the at least two interposers and on the inner sides of the at least one trench, and wherein a seed layer can be arranged on at least the first side of the at least two interposers; arranging the at least two interposers on a panel carrier substrate; arranging a first redistribution layer on the first side of the at least two interposers; flipping the at least two interposers; filling the at least one trench with an electrically conductive material; and arranging a second redistribution layer on the second side of the at least two interposers. More specifically, the method may be a hybrid manufacturing method for processing multiple wafers in parallel, the method comprising: providing at least two wafers, each wafer comprising at least one trench, wherein the at least one trench is etched from a first side to a second side of the wafer and wherein an electrical insulation layer is arranged on the first side and the second side of the wafer and on the inner sides of the at least one trench; arranging the at least two wafers on a panel carrier substrate; arranging a first redistribution layer on the first side of each of the at least two wafers; flipping the at least two wafers; filling the at least one trench in each of the at least two wafers with an electrically conductive material; and arranging a second redistribution layer on the second side of each of the at least two wafers.

[0034] “Hybrid” may refer to that some steps of the method may be carried out in a cleanroomenvironment, while other steps may be carried out in a panel-based environment. P7462PC00

[0035] 6

[0036] The present skilled in the art would understand that while the method steps as disclosed herein are presented in a specific sequence, this order is not intended to be limiting. The steps of the method may be performed in any suitable order or simultaneously. In various embodiments, certain steps may be omitted, repeated, or rearranged without departing from the scope of the present disclosure.

[0037] As described herein, a cleanroom is a controlled environment that can maintain extremely low levels of airborne particles and precise control over parameters such as temperature, humidity, and air pressure. Cleanroom environments are typically classified based on the number of particles per cubic meter, with strict standards such as Class 10, Class 100, or Class 1000, where lower numbers indicate higher cleanliness. In the context of semiconductor manufacturing, cleanrooms are used for processes that require high precision and contamination control, such as deep reactive ion etching (DRIE) for creating through-silicon vias (TSVs), chemical vapor deposition (CVD) for thin films, and photolithography with liquid photoresist for high-resolution patterning. These processes demand sub-micron precision, nanometer-scale roughness, and absolute flatness to ensure the quality and reliability of semiconductor devices. Cleanroom processes may often be associated with processing steps that involve stringent contamination control, high-resolution patterning, and the use of specialized semiconductor equipment.

[0038] On the other hand, panel-based technology is derived from printed circuit board (PCB) manufacturing and operates in environments that do not require the same level of cleanliness as semiconductor cleanrooms. Panel-based processing uses standard equipment to perform tasks such as copper electroplating or electroplating of any other suitable metals, dry-film resist patterning, and assembly or manufacture of redistribution layers (RDLs). The criteria for panel-based technology emphasize costefficiency, high throughput, and the ability to process large areas or multiple wafers simultaneously. This technology may not require sub-micron precision and can tolerate higher particle levels, making it more suitable for applications where extreme precision is not necessary, such as in power interposers used for surface-mount technology (SMT).

[0039] In the present disclosure, the term “through-interposer via” can be used interchangeably with “through-wafer via” or “through-silicon via” (TSV). This P7462PC00

[0040] 7 terminology does not restrict the through-interposer via, through-wafer via and / or through-silicon via to silicon wafers; it may be applied to wafers processed in or comprising other materials.

[0041] In one embodiment of the present disclosure, the at least two interposers can be at least two silicon wafers. In this embodiment, the wafer is a silicon-based substrate, which offers specific advantages for thermal and electrical performance. Silicon wafers are commonly used in semiconductor applications due to their high electrical conductivity, compatibility with existing semiconductor processing technologies, and thermal stability. The use of silicon allows the wafer to achieve efficient heat dissipation, which is particularly beneficial in power applications where thermal management can be essential. The choice of silicon as a substrate also enables compatibility with a wide range of electronic components and packaging formats, facilitating integration into existing systems. In some implementations, the silicon wafer may be of varying diameters, including standard industry sizes such as 6, 8, or 12 inches, or larger if needed for specific applications. The thickness of the silicon wafer may also vary based on the desired thermal properties, mechanical strength, or through-silicon vias (TSVs) depth required. This variability supports adaptability across different manufacturing environments and application requirements.

[0042] In another embodiment of the present disclosure, the method further comprises depositing a second seed layer on the second side of the at least two wafers. This step involves the application of a second seed layer onto the second side of the wafers. This step can be performed together with the deposition of the seed layer arranged on at least the first side. Preferably, this step can be performed at any stage before depositing further material on the second side of the at least two wafers. Similar to the seed layer, the second seed layer can provide a foundation for further metal deposition and facilitates the formation of a uniform second redistribution layer. The deposition of the second seed layer may be carried out using various techniques, such as physical vapor deposition (PVD), sputtering, or evaporation. Each technique may be selected based on the specific requirements of the wafer, such as the desired thickness, conductivity, and material properties. The second seed layer may ensure a consistent conductive surface across the second side of the wafers, supporting efficient and reliable metal plating during the formation of the second redistribution layer. This layer also enhances adhesion between the conductive material and the underlying wafer P7462PC00

[0043] 8 surface, reducing the risk of delamination or mechanical failure during subsequent processing and usage.

[0044] The second seed layer can have the same properties as the seed layer. By specifying that the second seed layer shares the same properties as the seed layer, it ensures uniformity in the conductive surfaces on both sides of the wafer. This uniformity is advantageous for achieving consistent electrical performance, as it minimizes variations in conductivity or adhesion between the first and second sides. The same properties may refer to aspects such as material composition, thickness, and deposition technique. For example, if the seed layer comprises copper with a specific thickness applied via sputtering, the second seed layer may also be copper of the same thickness, deposited using a similar sputtering process. This approach can simplify the manufacturing workflow, reducing the need for additional material adjustments or equipment changes.

[0045] The use of identical properties for both seed layers, which are the seed layer and the second seed layer, may also improve the structural balance of the wafer, reducing mechanical stresses that could arise from differences in material expansion or contraction during thermal cycling. In applications where the wafer is exposed to varying temperatures, such as power electronics, maintaining consistent seed layer properties can help ensure long-term reliability and performance. In other embodiments, the seed layers may be tailored to specific operational requirements, such as enhanced corrosion resistance or thermal stability, depending on the intended use of the wafer. For instance, a nickel-copper alloy could be employed for both seed layers if the wafer is designed for use in harsh environmental conditions where oxidation resistance is needed.

[0046] This approach, which can maintain consistency between the seed layers on both sides of the wafer, also streamlines the process of forming the second redistribution layer, as it allows the plating parameters to remain consistent throughout the process. This consistency can reduce the likelihood of defects, such as uneven metal deposition or delamination, which can compromise the performance and reliability of the wafer in high-power or high-frequency applications.

[0047] In a preferred embodiment of the present disclosure, the electrical insulation layer can comprise a dielectric layer and / or a diffusion barrier layer. The electrical insulation layer may serve dual functions, acting both as an insulating dielectric layer and as a diffusion P7462PC00

[0048] 9 barrier. When configured as a dielectric, the electrical insulation layer insulates the conductive components within the wafer, reducing the risk of electrical interference and enhancing the reliability of the signal transmission across the TSVs. As a diffusion barrier, the electrical insulation layer may prevent the migration of conductive material, such as copper, from the TSVs into the surrounding silicon substrate or wafer, thus preserving the integrity of the wafer’s structure and ensuring the longevity of its electrical properties. The electrical insulation layer may be formed by thermal oxidation, providing strong adhesion to the silicon surface and maintaining stability under high thermal and electrical loads. Implementing this feature can vary, as the dielectric and diffusion barrier layer roles may be combined in a single layer or provided by distinct layers. For example, in some cases, a silicon oxide layer may be formed as a single structure fulfilling both roles, while in others, an additional barrier material may be added to enhance diffusion resistance.

[0049] In another embodiment of the present disclosure, the dielectric layer may comprise silicon and / or aluminum, such as SiO2, Si3N4, AI2O3, and / or AIN. The dielectric layer can comprise at least one dielectric layer material, such as silicon dioxide (SiO2), silicon nitride (SisN^ , aluminum oxide (AI2O3), and / or aluminum nitride (AIN). The dielectric layer materials are chosen based on their insulating properties and thermal performance. SiO2, for instance, is widely used due to its high thermal stability and compatibility with silicon, providing an excellent insulating layer that minimizes electrical interference. AI2O3and AIN may offer similar benefits, with AI2O3providing high resistance to chemical reactions and AIN adding superior thermal conductivity, which can be advantageous in power applications where heat dissipation is critical. These materials can be selectively applied depending on the desired electrical insulation and thermal conductivity characteristics of the wafer. For example, in configurations where higher thermal conductivity is required, AIN may be used over SiO2. This flexibility in material choice can allow for customization based on specific operational environments, such as high-power applications that generate more heat.

[0050] In one embodiment of the present disclosure, the diffusion barrier layer can comprise titanium, tantalum and / or silicon, such as TaN, Ta, and / or Si3N4. The diffusion barrier layer materials, including tantalum nitride (TaN), tantalum (Ta), and silicon nitride (Si3N4), can be selected for their effectiveness in preventing the diffusion of metals, particularly copper, into the silicon substrate. The diffusion barrier layer enhances the reliability and durability of the wafer by preserving the isolation between conductive P7462PC00

[0051] 10

[0052] TSVs and the surrounding silicon. TaN, for example, is a robust choice for high-stress environments, offering excellent adhesion to silicon and resilience under thermal cycling, which is common in power applications. Si3N4serves as an alternative or complement, providing strong chemical stability and dielectric properties. In certain configurations, a multi-layer diffusion barrier may be applied, with a combination of Ta and TaN to maximize adhesion and diffusion resistance. This structure can support TSV integrity, especially in high-temperature or high-current applications, by ensuring the conductive materials remain confined within the TSVs.

[0053] In a preferred embodiment of the present disclosure, the dielectric layer can be arranged on the at least one wafer and the diffusion barrier layer may be arranged on the dielectric layer. This layered structure, where the dielectric layer is directly applied to the wafer and the diffusion barrier layer is subsequently applied on top of the dielectric, provides enhanced insulation and protection against diffusion. By positioning the diffusion barrier over the dielectric layer, this configuration allows the dielectric to act as the primary insulating layer, reducing any risk of conductive leakage from the TSVs to the surrounding silicon. The diffusion barrier layer, in turn, prevents migration of conductive materials from the TSVs, such as copper, through the dielectric layer and into the wafer, thus improving the device's long-term reliability. This arrangement can be optimized by adjusting the thickness of each layer to suit specific operational requirements, such as increased thermal stability or additional protection in high-power applications. In some implementations, multiple dielectric layers could be used beneath the diffusion barrier to further enhance electrical isolation, especially in wafers subject to high-voltage stresses.

[0054] The dielectric layer may have a dielectric layer thickness, wherein the dielectric layer thickness can be comprised between 50 nm and 1 pm, such as between 50 nm and 100 nm, such as between 50 nm and 500 nm. The diffusion barrier layer may have a diffusion barrier layer thickness, wherein the diffusion barrier layer thickness can be comprised between 5 nm and 1 pm, such as between 5 nm and 10 nm, such as between 5 nm and 50 nm, such as between 5 nm and 100 nm, such as between 5 nm and 500 nm.

[0055] In one embodiment of the present disclosure, the seed layer is deposited with a physical vapor deposition (PVD) method, such as an evaporation method, wherein the evaporation method is directional such that the seed layer is deposited on the first side P7462PC00

[0056] 11 and / or the second side of the at least two wafers. PVD techniques, including evaporation, are well-suited for seed layer deposition due to their ability to provide a controlled and uniform application of material. Directional evaporation in particular offers a significant advantage by allowing the deposition process to be precisely targeted, minimizing undesired deposition on non-target surfaces, such as the inner sides of the at least one trench formed in the wafer. This level of control is achieved by directing the vaporized material predominantly towards the horizontal surfaces of the wafer, ensuring that the seed layer is applied primarily to the first and / or second side, while avoiding excessive buildup on the vertical sidewalls of the trench.

[0057] The use of directional evaporation can enhance the overall efficiency of the manufacturing process. By limiting deposition to the intended surfaces, material waste is reduced, leading to cost savings and more efficient use of deposition materials. Additionally, the precision of this method supports consistent layer thickness, which is important for subsequent metal plating steps. A uniform and well-defined seed layer promotes reliable adhesion of the redistribution layer, thereby improving the structural integrity and electrical performance of the wafer. In one embodiment, the thickness of the seed layer can be adjusted based on the specific requirements of the wafer, with typical thicknesses ranging from a few nanometers to several micrometers, depending on the desired electrical and mechanical properties.

[0058] By employing a directional evaporation method, the seed layer is advantageously deposited on the first side and / or the second side of the wafer, while deposition on the inner sides of the trench is minimized. This selective deposition approach is particularly beneficial for the formation of through-wafer vias (TSVs), as it ensures that the conductive pathway remains confined to the intended areas, reducing the risk of unintended short circuits or electrical leakage. The minimized deposition within the trench also facilitates the subsequent filling process, allowing the electrically conductive material to form a uniform and complete fill from the bottom up. This configuration helps achieve a low-resistance electrical path through the TSV, which is crucial for high-current applications and power wafers.

[0059] In one embodiment, the PVD method may involve additional variations, such as sputtering or ion-assisted deposition, to further enhance the quality and uniformity of the seed layer. Sputtering, for instance, may be used when a conformal seed layer is required, providing enhanced adhesion and improved electrical contact. The choice of P7462PC00

[0060] 12 deposition method and parameters can be tailored based on the specific materials used for the seed layer, such as copper, titanium, tantalum, or chromium, each offering distinct advantages in terms of conductivity, adhesion, and thermal stability. These material choices allow the method to be adapted for different applications, ranging from consumer electronics to industrial power modules, while maintaining consistent manufacturing quality and performance.

[0061] In one embodiment of the present disclosure, the seed layer can comprise an adhesion layer and / or a seed conductive layer. Structuring the seed layer with distinct functional sub-layers, which are an adhesion layer and a seed conductive layer, can provide improved bonding between the TSVs and the redistribution layers, as disclosed herein. The adhesion layer can serve to secure the seed layer to the substrate material, preventing issues like delamination under thermal or mechanical stresses. The seed conductive layer may provide the necessary electrical properties for further metallization processes, such as electroplating, which rely on a conductive foundation. This dual-layer seed structure can enhance the durability and electrical connectivity of the wafer, especially under conditions involving repeated thermal cycling or mechanical stress. Additionally, variations in the thickness and material composition of each sublayer may be applied to customize the wafer’s performance to meet specific electrical or structural requirements.

[0062] The adhesion layer can comprise chrome, titanium, and / or tantalum. The choice of materials for the adhesion layer, such as chrome (Cr), titanium (Ti), or tantalum (Ta), provides robust adhesion properties suited to various substrate types and processing conditions. Chrome is known for its durability and corrosion resistance, making it ideal for high-stress environments. Titanium offers excellent adhesion and thermal stability, particularly advantageous for applications involving significant temperature fluctuations. Tantalum, similarly, provides strong adhesion and is also highly resistant to thermal and chemical degradation, making it an excellent choice for power wafers. These materials may be applied individually or in combination to further optimize adhesion properties based on the specific requirements of the wafer. For example, a layered adhesion structure of Ti and Ta may offer a balance of both high adhesion and thermal resilience, suitable for wafers in power electronics or other high-demand applications.

[0063] In a preferred embodiment of the present disclosure, the seed conductive layer can comprise aluminum, copper, and / or gold. The materials chosen for the seed conductive P7462PC00

[0064] 13 layer, such as aluminum (Al), copper (Cu), or gold (Au), provide varied options for optimizing the conductivity, thermal properties, and cost-effectiveness of the wafer. Copper is a common choice for its excellent electrical conductivity and cost efficiency, making it well-suited for high-power applications. Gold, although more costly, can offer superior resistance to oxidation and corrosion, which may be beneficial in environments with high humidity or exposure to corrosive agents. Aluminum, though less conductive than copper or gold, provides a lightweight and thermally efficient option that can be advantageous in applications where weight and thermal management are key considerations. These materials may be selected individually or in combination, allowing customization of the seed conductive layer to align with the specific requirements of the wafer, such as conductivity needs, environmental resilience, and manufacturing costs.

[0065] The at least two wafers may have a standard wafer thickness, such as 750 nm. The at least one trench can be etched from a first side of the at least two wafers, wherein the at least one trench depth may be lower than the wafer thickness, wherein the electrical insulation layer can be arranged on the first side and on the inner sides of the at least one trench, wherein the at least two wafers can be thinned and / or polished from the second side of the at least two wafers, such that the at least one trench is extended through the wafer thickness of the at least two wafers, and wherein the at least two wafers can be flipped and the electrical insulation layer may be arranged on the second side of the at least two wafers. This embodiment describes a method for creating the at least one trench in the at least two wafers while optimizing the manufacturing process through selective thinning and polishing. By etching the at least one trench only partially from the first side, the method avoids excessive etching depths that may compromise accuracy or increase processing time. The trench depth is specifically controlled to remain less than the thickness of the wafer, leaving a residual layer at the bottom of the trench for further processing.

[0066] After etching the trench from the first side, an electrical insulation layer can be deposited or arranged on the first side of the wafers and along the inner surfaces of the trench. The electrical insulation layer ensures proper electrical isolation of the trench walls, which can be essential for reliable electrical performance in the completed wafer. The second side of the wafers can then be subjected to a thinning and / or polishing process. This step may reduce the wafer thickness and removes the residual material at the bottom of the trench, extending the trench through the entire wafer thickness to P7462PC00

[0067] 14 form a through-trench. Thinning may involve mechanical grinding, chemical mechanical polishing (CMP), or a combination of these techniques, allowing precise control over the final wafer thickness and trench dimensions. This controlled thinning process can ensure that the trench is fully opened while maintaining the structural integrity of the wafer.

[0068] Once the trenches are fully extended, the wafers can be flipped to expose the second side. The electrical insulation layer can then be deposited or arranged on the second side and along the newly exposed surfaces of the trench. This additional insulation ensures that both sides of the wafer and the entire trench are electrically isolated, providing a robust dielectric barrier that is crucial for high-power or high-frequency applications. This step can use the same deposition methods and materials as those employed for the first side, ensuring consistency in insulation properties.

[0069] By dividing the trench formation process into partial etching from the first side followed by thinning and polishing from the second side, the method reduces the overall complexity and time required for deep trench etching. The selective application of the electrical insulation layer ensures comprehensive isolation while minimizing material waste. Furthermore, the flipping step facilitates efficient processing of both sides of the wafer, enabling symmetrical dielectric coverage and improving the wafer's performance and reliability. This approach supports the production of high-quality through-wafer vias with enhanced scalability, making it suitable for power wafers in demanding applications such as power electronics, industrial systems, and advanced semiconductor packaging.

[0070] In one embodiment of the present disclosure, the method further comprises arranging a resist patterning, wherein the resist patterning defines a first patterning for arranging the first redistribution layer. This resist patterning method can enable a precise layout for the redistribution layer by using resist materials, these resist materials can be typically associated with printed circuit board (PCB) fabrication but not limited to PCB fabrication. This approach offers a cost-effective and scalable alternative to traditional semiconductor lithography, allowing patterns to be defined with sufficient accuracy for applications that do not require sub-micron resolution. The resist patterning can be adjusted to accommodate various designs for the redistribution layer, providing flexibility for different wafer configurations and applications. This adaptability allows the patterning to be tailored to meet the electrical and structural requirements of the wafer, P7462PC00

[0071] 15 ensuring proper alignment and connectivity for subsequent plating or deposition processes.

[0072] In another embodiment of the present disclosure, the resist patterning can be performed by using a dry-film lamination, wherein a dry-film resist is arranged or laminated on the first side and / or the second side of the at least one wafer. Using a dry-film lamination method provides several advantages, such as ease of application, uniformity, and cost savings compared to liquid resists. Dry-film resist can be applied rapidly and with a consistent thickness across the wafer surface, which are the first side and / or the second side of the wafer, improving the overall quality of the resist pattern. This uniformity is beneficial when creating redistribution layers, as it reduces the risk of defects or misalignments in the pattern. Furthermore, dry-film lamination is well-suited for batch processing, allowing multiple wafers to be patterned simultaneously, thus increasing throughput. This technique also enhances environmental control, as the dry-film resist minimizes exposure to airborne contaminants that could affect the pattern quality.

[0073] In one embodiment of the present disclosure, the resist patterning is performed by using a laminated dry-film roll of liquid resist, wherein the laminated dry-film roll of liquid resist is applied on the first side and / or the second side of the at least two wafers by spin coating, screen printing, and / or spray coating. This approach can leverage the flexibility and versatility of liquid resist application techniques combined with the advantages of using a laminated dry-film roll. The laminated dry-film roll provides a stable resist material that can be precisely applied across the wafer surface, while the liquid resist offers excellent conformity and adhesion, even on uneven or complex topographies.

[0074] In one embodiment, the laminated dry-film roll of liquid resist may be applied using spin coating. Spin coating involves dispensing the liquid resist onto the rotating wafer surface, creating a uniform and thin layer through centrifugal forces. This technique is well-suited for achieving consistent resist thicknesses, which is important for fine patterning and precise definition of the redistribution layers. Spin coating can be adjusted by varying the rotation speed, resist viscosity, and deposition time, allowing for control over the final resist thickness, typically ranging from a few micrometers to tens of micrometers, depending on the application requirements. P7462PC00

[0075] 16

[0076] In another embodiment, screen printing may be used to apply the laminated dry-film roll of liquid resist. Screen printing involves forcing the liquid resist through a patterned mesh screen onto the wafer surface. This method is advantageous for applications requiring thicker resist layers or when a specific pattern needs to be directly applied without additional photolithography steps. Screen printing can accommodate a wide range of resist viscosities and provides a high degree of flexibility in pattern design, making it suitable for larger feature sizes and high-throughput manufacturing scenarios. This technique also allows for the application of resist on both the first side and the second side of the wafers, facilitating simultaneous processing and reducing manufacturing time.

[0077] In one embodiment, spray coating may be employed as an alternative method for applying the laminated dry-film roll of liquid resist. Spray coating disperses the liquid resist in a fine mist onto the wafer surface, covering both large areas and intricate details with a uniform layer. This method is particularly effective for covering irregular surfaces or wafers with complex topographies, as the spray can reach recessed features and sidewalls that may be difficult to coat using other methods. Spray coating can be precisely controlled by adjusting parameters such as spray pressure, distance, and nozzle configuration, ensuring consistent coverage and resist thickness.

[0078] The use of a laminated dry-film roll of liquid resist in combination with these application techniques offers several advantages. The dry-film roll provides a consistent supply of high-quality resist material, minimizing variations in resist properties and ensuring uniform application. The liquid nature of the resist allows it to conform to the wafer’s surface, improving adhesion and reducing the risk of defects, such as air bubbles or delamination, during subsequent processing steps.

[0079] Arranging the first redistribution layer and / or the second redistribution layer can be performed according to a redistribution layer (RDL) plating method. The use of an RDL plating method enables the deposition of conductive materials on the patterned resist, allowing the redistribution layer to be precisely formed in alignment with the underlying pattern. This process can facilitate reliable electrical pathways that link various components on the wafer, enhancing its functionality. The RDL plating process may be tailored to different materials and thicknesses, providing flexibility for applications with specific electrical or mechanical requirements. By choosing appropriate plating conditions, such as solution composition and current density, the plating method can P7462PC00

[0080] 17 be optimized to improve layer adhesion and conductivity, supporting consistent performance across high volumes of wafers.

[0081] In one embodiment of the present disclosure, the RDL plating method can be an electroplating or an electroless plating method. Both electroplating and electroless plating offer distinct advantages for RDL formation. Electroplating involves applying an electric current to deposit conductive materials onto the wafer surface, providing fine control over the thickness and uniformity of the deposition. This method is advantageous in applications where high precision and layer uniformity are needed, as well as for metals like copper, which is commonly used in wafers. Electroless plating, on the other hand, may not require an external current, allowing deposition on non- conductive areas, which can be useful for uniformly coating complex or irregular structures. Electroless plating also enables consistent layer deposition across varying geometries, which may be beneficial for wafers with diverse structural requirements. Each method can be selected based on specific operational conditions, such as desired conductivity, adhesion strength, and compatibility with other materials in the wafer.

[0082] In a preferred embodiment of the present disclosure, the first redistribution layer and / or the second redistribution layer have a redistribution layer thickness comprised between 1 and 125 pm. The range of 1 to 125 pm for the redistribution layer thickness is selected to accommodate a balance between electrical conductivity and structural stability. Thicker layers within this range can enhance current-carrying capacity, making them suitable for power applications, whereas thinner layers allow for more precise routing and increased space for additional layers or components. This thickness range also provides flexibility in choosing the deposition method, as both electroplating and electroless plating can be adjusted to achieve the desired layer thickness. By maintaining the redistribution layer thickness within this specified range, the wafer can meet various electrical and mechanical requirements, supporting robust performance across a range of applications.

[0083] In one embodiment of the present disclosure, the first redistribution layer and / or the second redistribution layer may be formed as a first redistribution multilayer and / or a second redistribution multilayer, respectively. The first redistribution multilayer and the second redistribution multilayer may each include multiple stacked redistribution layers, such as a single redistribution layer, at least two redistribution layers, or three or more P7462PC00

[0084] 18 redistribution layers, depending on the design requirements. The redistribution layers can be sequentially deposited, with an internal passivation layer arranged between each successive layer to provide electrical insulation and protect against material diffusion. The layers within the first redistribution multilayer can be interconnected using at least one first interlayer via, while the layers within the second redistribution multilayer may be interconnected using at least one second interlayer via. This configuration supports efficient electrical routing and increases the overall density of the redistribution network, allowing for enhanced performance in complex power wafer applications.

[0085] In another embodiment of the present disclosure, the method may further comprise arranging a first passivation layer on the first redistribution layer and / or arranging a second passivation layer on the second redistribution layer. The addition of a passivation layer over the redistribution layers can serve to protect the redistribution layers from environmental factors, such as moisture, contaminants, and mechanical wear. By forming a protective barrier, the passivation layer helps maintain the integrity of the redistribution layers, ensuring stable electrical performance over time. The passivation layer can also enhance the thermal durability of the wafer, reducing risks of oxidation or material degradation under elevated temperatures. The passivation layer may be applied selectively to either or both redistribution layers, such as the first and / or the second redistribution layer, depending on specific operational requirements, such as exposure conditions or mechanical stress. In some embodiments, additional protective layers may be combined with the passivation layer to further reinforce the redistribution layers and extend the device's operational lifespan.

[0086] The first passivation layer and / or the second passivation layer can comprise silicon and / or aluminum, such as silicon nitride (Sial^ ) , silicon oxide (SiO2), and / or aluminum oxide (AI2O3). The materials for the passivation layer are selected based on their insulating properties and thermal stability. Silicon nitride (Sial^ ) offers a strong barrier against moisture and provides robust protection for the redistribution layers in high- humidity or corrosive environments. Silicon oxide (SiO2) is widely used for its excellent thermal stability and compatibility with silicon-based substrates, making it suitable for environments with varying temperatures. Aluminum oxide (AI2O3) provides similar advantages, with the additional benefit of high resistance to chemical attack, making it effective in applications where exposure to harsh chemicals may occur. The choice of these materials provides flexibility, allowing for the selection of a passivation layer that P7462PC00

[0087] 19 matches specific durability and environmental protection requirements. In some variations, a combination of these materials may be used to optimize protection, ensuring the redistribution layers are shielded under diverse operational conditions.

[0088] In a preferred embodiment of the present disclosure, filling the at least one trench with the electrically conductive material is performed by using a bottom-up plating. Bottom- up plating is advantageous for through-silicon via (TSV) filling as it ensures that the conductive material fills the trench from the bottom to the top, from the first side to the second side of the wafer, or from the second side to the first side of the wafer, minimizing voids or gaps within the TSV structure. This approach allows for a more uniform distribution of the conductive material, which is essential for achieving low resistance and reliable electrical performance. Bottom-up plating can be carefully controlled to ensure even filling, enhancing the structural stability of the TSV. By using this method, the wafer benefits from consistent conductivity across the entire TSV, which is particularly beneficial in power applications where uniform current distribution is required. Bottom-up plating also supports adaptability in material choices, allowing for the use of various conductive materials that meet specific electrical and thermal requirements of the wafer.

[0089] Figs. 1 A-H show schematic views of embodiments of the different steps of the method as disclosed herein, wherein Figs. 1A-D show schematic views of embodiments of process steps that are performed in a cleanroom-environment, and wherein Figs. 1E-H show schematic views of embodiments of process steps that are performed in a panelbased environment. Fig. 1A illustrates a wafer 1 with an etching hard mask 2 applied to its surface or its first side. The etching hard mask is designed to define areas for subsequent etching processes. A photoresist layer 3 is applied over the etching hard mask, serving as a mask during patterning. Beneath the photoresist is an etch stop layer 4, which controls the etching depth and protects underlying layers during the etching process. The etch stop layer is preferably a conductive metal layer, which helps and assists the etching process. The wafer can be etched with or without a carrier substrate. By bonding an etch stop layer to the carrier substrate, wafer warpage can be avoided when manufacturing the at least one through-wafer via within the wafer. The etch stop layer may prevent the notching effect. Notching effect may refer to a small groove or notch that can form at the edge of a patterned feature during the photolithography process. It can happen because when light shines through the photomask or stencil to create the pattern, some of it bends or scatters around nearby P7462PC00

[0090] 20 features, creating an unintended mark at the edge of the pattern. This can broaden the through-wafer vias diameter towards the bottom of the via etching hole in the wafer, especially if the etch stop layer is non electrically conductive. Such effect can be the result of the reflection of the etching ions at the end of the trenches where the through- wafer vias may be created, into the material of the wafer. By using an electrically conductive etch stop layer, these etching ions can be absorbed by the electrically conductive etch stop layer and may allow for a creation of an even diameter throughout the trench where the through-wafer via may be arranged or deposited.

[0091] Advantageously, this may drastically increase the through-wafer via density since the pitch between the through-wafer vias can be smaller and the risk of shorting the through-wafer vias together is strongly limited. The carrier substrate 5 is shown as the base that supports the wafer throughout processing.

[0092] In Fig. 1 B, the trench 6 is etched into the wafer 1 through the openings defined by the etching hard mask 2 and photoresist 3. The etching process stops at the etch stop layer 4, ensuring the trench depth is controlled. The trench is now prepared for further processing steps, such as dielectric layer deposition. Fig. 1C shows the trench 6 after the dielectric layer 7 has been deposited along its inner walls and on the first side and the second side of the wafer. This dielectric layer acts as an insulator within the trench. A diffusion barrier layer 8 is then applied over the dielectric layer, preventing any migration of materials from the through-wafer via 14 that will later fill the trench. The presence of both the dielectric and diffusion barrier layers ensures that electrical isolation and structural integrity are maintained. In Fig. 1 D, the seed layer 9 is deposited over the diffusion barrier layer 8 on the first side of the wafer 1. The seed layer provides a conductive surface necessary for the subsequent metal deposition that will be deposited on the first side of the wafer, forming the through-wafer via 14. The wafer 1 is now prepared for further metallization steps. These metallization steps can be advantageously performed in a panel-based environment, as disclosed in the present disclosure.

[0093] Fig. 1E depicts the wafer 1 arranged on a panel carrier substrate 12. A dry-film resist 10 is laminated onto the wafer to define areas for patterning through photolithography. The photolithography-based patterning 11 defines the precise layout or patterning to deposit the first redistribution layer 13 on the first side of the wafer 1. In Fig. 1 F, the first redistribution layer is deposited or plated on the first side of the wafer 1, by using the RDL plating methods as disclosed in the present disclosure. Advantageously, by using P7462PC00

[0094] 21 plating methods, the first redistribution layer 13 can be deposited in the first side of the wafer 1 without having to realise this deposition step in a cleanroom environment.

[0095] Fig. 1G shows the through-wafer via 14 that is formed within the trench 6, providing an electrical pathway through the wafer 1. From the process step shown in Fig. 1 F, the wafer 1 is preferably flipped such that the first side is in contact with the conductive base 15 comprised in the panel carrier substrate 12. The through-wafer via is filled with an electrical conductive material, and the through-wafer via is bottom-up filled, with a plating process, as described herein. The panel carrier substrate comprises a conductive base, that assists the process of plating, especially electroplating, by applying a current to the conductive base. In Fig. 1 H, the wafer 1 is depicted with the complete redistribution layer network, both the first and the second redistribution layer, wherein the second redistribution layer is deposited on the second side of the wafer with a process similar to the process used to deposit the first redistribution layer, as described in the precedent paragraphs. The dry-film resist 16 are applied to further build the second redistribution layer 17. The panel carrier substrate 12 supports the wafer 1 , while a conductive base 15 is provided to enable controlled current paths during electroplating processes, facilitating uniform deposition of the conductive layers, especially the second redistribution layer 17 in this specific process step.

[0096] In one embodiment of the present disclosure, the method further comprises applying a surface finishing to the first passivation layer, the second passivation layer, the first redistribution layer, and / or the second redistribution layer. Surface finishing serves to enhance the durability and environmental resistance of the exposed layers, providing a polished or protected surface that mitigates potential wear from handling or operational exposure. This finishing process can involve treatments such as polishing, coating, or etching to achieve the desired surface quality. For example, polishing can create a smooth finish, reducing the risk of electrical arcing or contact wear in high-power applications. Coatings, such as protective films or oxidation-resistant materials, can be applied to further protect the underlying layers from corrosion or oxidation. Surface finishing also enhances the visual quality of the wafer, which may be beneficial in applications where the component is exposed or needs to meet specific aesthetic standards. The surface finishing may be tailored to meet specific requirements based on the wafer's intended use, ensuring durability and sustained performance in diverse environments. P7462PC00

[0097] 22

[0098] In another embodiment of the present disclosure, the first and / or the second redistribution layer comprises at least one pad. Including at least one pad in the redistribution layer provides a designated contact area that facilitates connections to external components or substrates. The pad can serve as an electrical interface, allowing for reliable and consistent connections that support signal transmission or power distribution. This design feature enhances the functionality of the wafer by creating defined points for bonding, soldering, or other attachment methods. In addition, having pads on the redistribution layer can improve the ease of alignment and connection in automated assembly processes, which is particularly advantageous in high-volume manufacturing environments. The number, layout, and size of pads can be customized based on application requirements, providing flexibility in supporting various configurations for different electrical or mechanical interfaces.

[0099] The at least one pad can be substantially squared, substantially circular, substantially annular, or substantially polygonal. The option to design the pads in various shapes allows for tailoring the contact areas to meet specific requirements of electrical performance, attachment method, or component integration. For instance, circular and squared pads are commonly used for general-purpose soldering or bonding, as their regular shapes facilitate alignment and connection stability. Annular pads, which form ring-like structures, can be beneficial in applications where precise alignment around a central opening is required, such as in via structures or coaxial interfaces. Polygonal pads, such as hexagonal or octagonal shapes, may offer increased surface area for bonding without occupying excessive space, allowing for optimized pad layout on the redistribution layer. These shape variations provide additional design flexibility, enabling the wafer to meet unique demands of various applications, including high- density layouts or enhanced thermal management.

[0100] A pad-finish layer can be arranged on the at least one pad. The pad-finish layer may be used to protect the at least one pad from undesired oxidation or corrosion. In the microelectronics industry standards, most of the pads are fabricated or processed with copper or a material that can easily oxidize, thereby deteriorate with time, which would render the pad unusable. By arranging a pad-finish layer on the at least one pad, a protection of the exposed part and a better solderable surface of the at least one pad is provided. The pad-finish layer may comprise a pad-finish layer material, wherein the pad-finish layer material can comprise nickel and / or gold. Nickel and / or gold can be used as finish layers for the at least one pad since they present excellent electrical P7462PC00

[0101] 23 conductivity, corrosion resistance and solderability. Both nickel and gold are highly conductive metals. Nickel and gold are relatively inert metals, meaning that they are resistant to corrosion when exposed to moisture, oxygen, and other environmental factors. This resistance helps maintain the integrity of the connection of the at least one pad over time, ensuring long-term reliability and stability of the electronic device. Both nickel and gold can form strong bonds with solder. This property may ensure that components can be securely attached to the at least one pad.

[0102] The pad-finish layer can be configured to be deposited with an electroless nickel immersion fold (ENIG) process, with an ENEPIG process, and / or with a hot air solder levelling (HASL) process. HASL process may be one of the predominant surface finish used in the industry. The process consists of immersing the wafer in a molten pot of a tin / lead alloy and then removing the excess solder by using “air knives”, which blow hot air across the surface of the wafer. ENIG process is a two-layer metallic coating of gold and nickel. The nickel acts as a barrier to the material used to process the at least one pad, such as copper, and nickel may be the surface to which components can be soldered to. The gold may protect the nickel during storage and can provide the low contact resistance required for the thin gold deposits. ENEPIG is a three-layer metallic coating of nickel, palladium, and gold, and may provide an option of rendering the at least one pad bondable. ENEPIG advantageously demonstrates the best performance on after-assembly corrosion level.

[0103] In one embodiment of the present disclosure, the at least one wafer can comprise silicon, silicon oxide, and / or aluminum nitride. Selecting materials like silicon, silicon oxide, and aluminum nitride for the wafer offers specific advantages in terms of thermal conductivity, electrical insulation, and mechanical robustness. Silicon is well-suited for applications requiring effective thermal management and electrical conductivity, as it allows for efficient heat dissipation and structural compatibility with other semiconductor components. Silicon oxide is commonly used as an insulating layer, providing strong dielectric properties that prevent undesired electrical interference, which can be essential in maintaining the integrity of signal paths within the wafer. Aluminum nitride, known for its high thermal conductivity and insulation properties, is advantageous in power applications where heat dissipation is critical, as it combines the benefits of thermal management with electrical insulation. By incorporating these materials, the wafer can support a range of applications with varied thermal, electrical, and mechanical demands. P7462PC00

[0104] 24

[0105] The at least one wafer can have a substantially circular shape. The wafer may have a diameter comprised between 6 and 12 inches. The option for a circular wafer with a diameter in the range of 6 to 12 inches aligns with common wafer sizes in semiconductor manufacturing, facilitating integration into existing processing equipment and production lines. Circular wafers provide a symmetric layout, which can be advantageous for uniform material distribution and thermal expansion characteristics, reducing the risk of stress-related defects during processing and use. This diameter range also allows for flexibility in adapting the wafer size to specific application requirements, whether for compact electronic devices or larger-scale power modules. The use of circular shapes can optimize the layout for components arranged in radial configurations, which may be beneficial for certain applications where circular symmetry supports more efficient thermal or signal routing paths.

[0106] In a preferred embodiment of the present disclosure, the at least one wafer has a substantially rectangular shape, and the first side and / or the second side of the at least one wafer can have a surface area up to 0.2 m2. A rectangular wafer with a surface area up to 0.2 m2provides a larger area that supports higher component density and increased routing options, which is particularly advantageous in applications requiring extensive interconnectivity or substantial power distribution. The rectangular shape aligns with standard panel and PCB manufacturing techniques, making it compatible with high-volume production processes that can benefit from the larger area for component placement and interconnection. This shape also enables the use of gridbased layouts for components and vias, facilitating efficient routing in complex designs. By supporting such a significant surface area, the wafer can be tailored for diverse applications, including those requiring multiple layers of redistribution or extensive electrical and thermal management.

[0107] The wafer thickness can be comprised between 50 and 500 pm. The range of 50 to 500 pm for the wafer thickness allows for a balance between structural strength and compatibility with microelectronic applications. A thinner wafer, closer to 50 pm, can be advantageous for applications requiring lightweight components or compact stacking, as thinner wafers enable reduced height in multi-chip packages. Conversely, an wafer thickness toward the upper limit of 500 pm offers increased mechanical stability, which can be beneficial in power applications or scenarios where physical durability is essential. This range also supports compatibility with through-silicon vias (TSVs) of various depths, accommodating both shallow and deeper TSVs as required by different P7462PC00

[0108] 25 applications. The flexibility in thickness allows manufacturers to tailor the wafer to meet specific performance and design constraints, such as mechanical rigidity, heat dissipation, or size limitations.

[0109] In one embodiment of the present disclosure, the method further comprises using a photolithography-based patterning to dissolve a first redistribution layer area and / or a second redistribution layer area on the dry-film resist, such that a first redistribution layer pattern and / or a second redistribution layer pattern is arranged in the dry-film resist. Photolithography-based patterning offers precise control over the redistribution layer pattern, ensuring accurate alignment and high-resolution features on the wafer. By selectively dissolving areas of the dry-film resist, photolithography enables detailed patterning that aligns with the requirements of fine-pitch interconnections, allowing the redistribution layer to connect with specific points on the wafer. This method is compatible with high-density wafer designs, where multiple connections must be made within a compact area. Photolithography also supports scalability, as it can be adapted for batch processing, which is beneficial in high-volume production. Adjustments in the exposure and development parameters of the photolithography process allow further refinement of the patterning resolution to meet the design needs of specific applications.

[0110] In another embodiment of the present disclosure, the method further comprises removing or dissolving the first redistribution layer pattern and / or the second redistribution pattern arranged in the dry-film resist. The removal or dissolution of the redistribution layer pattern, either the first, the second, or both, from the dry-film resist enables a clean surface for the final formation of the redistribution layer, ensuring high- quality layer deposition in subsequent steps. This removal process may involve chemical dissolution or mechanical methods, depending on the resist material and processing environment. Removing the redistribution layer pattern ensures that only the desired conductive paths remain, reducing the likelihood of defects or unwanted connections that could compromise the wafer’s performance. This step may also improve layer adhesion and electrical performance by providing a smooth surface for further metallization, facilitating reliable and consistent connectivity across the wafer’s functional areas.

[0111] In a preferred embodiment of the present disclosure, the method further comprises arranging the at least two wafers on a panel carrier substrate, wherein the panel carrier P7462PC00

[0112] 26 substrate is a multilayer fiberglass (FR4), a machined substrate, a ceramic substrate, a metal substrate such as an aluminium substrate or a copper substrate, a polymer substrate such as polyimide substrate or polyether ether ketone (PEEK) substrate and / or a glass substrate. Using a panel carrier substrate, such as multilayer fiberglass (FR4) or a machined substrate, provides stability and support during the processing steps, allowing multiple wafers to be handled simultaneously. FR4, a widely used PCB material, offers excellent electrical insulation and mechanical stability, making it suitable for secure handling and alignment of wafers during the manufacturing process. A machined substrate, on the other hand, can be customized in terms of thickness, material composition, and surface finish to meet specific handling or processing requirements. Arranging the wafer on such a substrate facilitates batch processing and alignment in panel-based manufacturing, enabling higher throughput and more efficient use of equipment. Additionally, the panel carrier substrate provides a platform for integrating multiple wafers in a single processing step, which is beneficial for scalable manufacturing.

[0113] The panel carrier substrate can have a panel carrier surface. The panel carrier surface can be at least 0.05 m2, such as at least 0.1 m2, such at least 0.2 m2, such as at least 0.3 m2, such as at least 0.4 m2, such as at least 0.5 m2, such as at least 0.6 m2, such as at least 0.7 m2, such as at least 0.8 m2.

[0114] In one embodiment of the present disclosure, the panel carrier substrate can comprise a conductive base. Incorporating a conductive base within the panel carrier substrate supports efficient heat dissipation and may provide a grounding path, which is advantageous in applications requiring effective thermal management or stable electrical performance. Additionally, the conductive base can facilitate plating processes, including electroplating and electroless plating, particularly in the case of electroplating, by enabling controlled current distribution across the wafer first side and / or second side. This controlled distribution is critical for achieving uniform metal deposition, enhancing layer adhesion, and ensuring the formation of high-quality conductive paths.

[0115] In plating processes, uniformity is a significant factor, especially in applications with intricate redistribution layer patterns or through-silicon vias (TSVs). For electroplating specifically, the conductive base acts as a direct current path, enabling the controlled application of current across the entire wafer surface. This uniform current flow helps to P7462PC00

[0116] 27 manage the deposition rate, reducing the risk of defects such as overplating or underplating in localized areas. By facilitating a stable current path, the conductive base allows for precise thickness control across the plated layer, ensuring that metal deposition occurs evenly, which is essential for maintaining the wafer’s overall performance and reliability.

[0117] In the case of electroless plating, where chemical reduction rather than direct current drives the deposition process, the conductive base still plays a crucial role by providing a stable and conductive foundation that supports uniform deposition initiation. This is particularly valuable when the wafer’s surface has complex geometries or when consistent layer thickness is required over large areas. The conductive base helps to maintain the plating bath’s chemical balance, enhancing the deposition rate across the wafer and reducing plating time.

[0118] The choice of material for the conductive base, such as copper, aluminum, or other conductive alloys, can be adapted to match specific requirements of the plating process, including conductivity, thermal properties, and compatibility with the wafer materials. Copper, for example, offers high conductivity and thermal efficiency, supporting both stable current paths in electroplating and rapid heat dissipation during the plating process. Aluminum provides a lightweight alternative with moderate conductivity and strong thermal properties, useful for applications where weight constraints are a consideration. These material choices allow for tailoring the conductive base to balance factors such as electrical performance, thermal management, and mechanical stability, ultimately enhancing the quality and efficiency of the plating process across the wafer surface.

[0119] The conductive base can be in contact with the first side and / or the second side of the at least two wafers. By placing the conductive base in direct contact with one or both sides of the at least two wafers, this configuration primarily provides a direct current path for electroplating, enabling precise control over the plating process and ensuring uniform metal deposition. This direct current path facilitates the efficient formation of conductive layers by supplying a stable and consistent electrical connection, which is essential for achieving high-quality plating results. Additionally, the contact arrangement can contribute to heat dissipation, as the conductive base may serve as a secondary heat sink to disperse thermal energy generated during operation. The contact configuration can be adjusted according to specific manufacturing and P7462PC00

[0120] 28 operational requirements, ensuring both effective electroplating and thermal management based on the design needs of the wafer.

[0121] The conductive base can comprise a conductive base material. The conductive base material may comprise copper, aluminum, copper-clad laminates, and / or metal alloys. The choice of materials for the conductive base, such as copper, aluminum, copper- clad laminates, and various metal alloys, offers flexibility in balancing cost, thermal conductivity, and weight. Copper may be well-suited for applications requiring high thermal and electrical conductivity, providing an efficient means of heat dissipation and stable grounding. Aluminum, while less conductive than copper, offers a lightweight alternative with good thermal properties, making it ideal for applications sensitive to weight or requiring efficient cooling. Copper-clad laminates and metal alloys, such as aluminum-copper composites, provide intermediate options that combine the advantages of each metal, allowing manufacturers to tailor the conductive base material to the specific operational conditions of the wafer. These materials support compatibility with diverse manufacturing environments, accommodating a range of power, thermal, and mechanical requirements.

[0122] In another embodiment of the present disclosure, the bottom-up plating is performed by applying a direct current to the conductive base, such that the electrically conductive material fills the trench. By applying a direct current to the conductive base, the method ensures a controlled and uniform deposition of the electrically conductive material, starting from the bottom of the trench and progressing upwards. This approach helps to minimize voids and defects within the through-silicon via (TSV), resulting in a continuous, low-resistance conductive path. The direct current provides a stable electrical field that facilitates the consistent plating of metal, such as copper, within the trench, enhancing the structural integrity and electrical performance of the through- wafer via. This technique is particularly advantageous for high-current applications, as it supports the formation of a robust and reliable conductive pathway through the wafer.

[0123] In one embodiment of the present disclosure, the method further comprises arranging a dry-film resist and a conductive foil on the first side of the at least one wafer. This configuration, where a dry-film resist is combined with a conductive foil, enhances the versatility of the patterning process by providing a stable base for metallization. The dry-film resist defines the desired pattern, while the conductive foil ensures that the wafer can be plated efficiently in subsequent steps. This method allows for precise P7462PC00

[0124] 29 control over the shape and location of conductive pathways, enabling the formation of detailed patterns that align with the wafer’s design requirements. The use of a conductive foil in conjunction with dry-film resist also provides the flexibility to create complex layer configurations, such as multilayer redistribution paths, which are beneficial for wafers requiring dense interconnections or specific electrical performance characteristics.

[0125] The dry-film resist can be arranged or laminated on the seed layer, and the conductive foil may be arranged or laminated on the dry-film resist. By layering the dry-film resist on the seed layer and subsequently applying the conductive foil, this arrangement supports efficient deposition and patterning for subsequent electroplating or other metallization processes. The seed layer can provide a conductive foundation for metal deposition, while the dry-film resist serves as a temporary mask that defines the conductive areas. The conductive foil, laminated on top of the resist, can enable straightforward plating of the exposed areas after the resist is selectively removed, ensuring precise control over layer formation. This layered structure allows for high- quality pattern transfer while minimizing misalignment or defects, supporting the formation of robust and uniform redistribution layers on the wafer. This technique is advantageous in applications that demand consistent electrical performance, as it helps create well-defined conductive paths with reliable connectivity.

[0126] In one embodiment of the present disclosure, the conductive foil can comprise a conductive foil layer and / or a multilayer comprising at least two conductive foil layers. The use of a multilayer conductive foil allows for enhanced customization of the electrical and thermal properties of the redistribution layers. By incorporating multiple conductive foil layers, different materials or thicknesses can be used to meet specific conductivity, durability, or thermal management requirements. For example, an inner layer could be formed from copper to provide high conductivity, while an outer layer could be composed of a corrosion-resistant material, such as nickel or gold, to protect the wafer from environmental factors. The multilayer can be used to selectively remove at least one layer using selective wet etchant, and wherein the selective wet etchant is designed to selectively remove the at least one layer while preserving the other layers comprised in the at least two conductive foil layers.

[0127] In another embodiment of the present disclosure, the at least two conductive foil layers comprise a first and a second conductive foil layer, and the first and second conductive P7462PC00

[0128] 30 foil layers can comprise copper, aluminum, nickel, and / or tin. The choice of materials for the foil layers, such as copper, aluminum, nickel, and tin, provides flexibility in achieving desired electrical, thermal, and protective properties. Copper, known for its high electrical conductivity, can be used in the first foil layer to ensure efficient current distribution during electroplating, supporting uniform metal deposition. Aluminum, with its lightweight and good thermal properties, may serve as a complementary layer to manage heat dissipation. Nickel and tin can enhance corrosion resistance and adhesion, offering durability under varying environmental conditions. These material choices allow for a multilayer conductive foil that supports specific functional requirements, such as optimized electroplating current paths, enhanced mechanical stability, or improved resilience to oxidation.

[0129] In a preferred embodiment of the present disclosure, the first and the second conductive foil layers comprise respectively copper (Cu) and aluminum (Al), Cu and Sn, Cu and Ni, Al and Ni, or Al and Cu. This arrangement of specific material pairs within the multilayer conductive foil provides a balanced combination of conductivity, durability, and thermal properties. A pairing of copper and nickel or copper and tin can offer strong adhesion and corrosion resistance, enhancing the robustness of the conductive foil layers. The selection of these material combinations allows for customization based on the operational demands of the wafer, ensuring that each layer contributes specific advantages, such as stable current flow, resistance to environmental degradation, or compatibility with further metallization processes.

[0130] The first conductive foil layer can be arranged on the second conductive foil layer, and the second conductive foil layer may be arranged on the dry-film resist. Arranging the conductive foil layers in this sequence can allow for efficient electroplating control, with the second layer in contact with the dry-film resist, providing a stable base for current distribution. The first conductive foil layer, applied over the second layer, then serves as the primary conductive path, optimizing current flow during electroplating and supporting uniform metal deposition on the redistribution layer. This layered configuration enhances the precision of the electroplating process by ensuring that the current is directed evenly across the wafer, minimizing the risk of uneven deposition or defects. The arrangement of these conductive layers in contact with the dry-film resist also allows for easier pattern removal after plating, improving the clarity and alignment of the final conductive paths. By having two different conductive foils, each having a different electrically conductive materials, a selective etching can be performed. For P7462PC00

[0131] 31 example, if the first conductive foil is made of copper, and the second conductive foil is made of aluminum, the first conductive foil can be removed by selectively etching copper, which would preserve the second conductive foil made of aluminum.

[0132] In one embodiment, the dry-film resist acts as a temporary bonding layer for the at least two conductive foil layers. This temporary bonding layer can be essential for providing adherence of the at least two conductive foil layers to the at least two wafers. This adherence can be crucial for achieving uniform plating, as it can ensure that the electrically conductive material fills into the at least one trench only and not on the first side and / or on the second side of the at least two wafer. By creating a temporary but robust bond, the dry-film resist prevents the electrically conductive material from spreading across unintended areas, improving the precision and reliability of the through-wafer via filling process. The resist also simplifies the subsequent removal of the conductive foil, as it facilitates a clean separation after the selective etching step. This capability further enhances the manufacturability of the wafer by maintaining the integrity of the redistribution layer and TSV structures during the process. By combining the benefits of the layered conductive foils and the temporary bonding properties of the dry-film resist, this approach supports efficient and precise manufacturing of wafers.

[0133] In another embodiment of the present disclosure, the at least one wafer is flipped and arranged on a panel carrier substrate comprising a conductive base, and wherein the dry-film resist is removed or dissolved at the bottom of the at least one trench, preferably down to the surface of the conductive foil. Flipping the wafer onto the panel carrier substrate allows for access to both sides of the wafer for further processing, particularly for depositing redistribution layers or filling trenches. The conductive base on the panel carrier provides a stable current path for electroplating, while the dry-film resist is removed or dissolved at the trench bottom to create an open path for conductive material deposition. This configuration enables precise filling of the TSVs from the bottom up, reducing voids and ensuring a consistent and reliable conductive path. By accessing both sides of the wafer, this method supports the formation of complete redistribution layers and TSVs, enhancing the electrical and structural integrity of the wafer.

[0134] In one embodiment of the present disclosure, a first portion through-wafer metal is arranged in the at least one trench, and wherein the first portion of through-wafer metal height is substantially lower than the at least one trench height. By initially filling the P7462PC00

[0135] 32 trench with a first portion of metal that does not fully occupy the trench, this method allows for a gradual build-up of conductive material, which can enhance layer adhesion and reduce stress within the TSV structure. The first portion of metal can serve as a foundation for additional metal deposition, improving the overall consistency and uniformity of the conductive path. This stepwise filling approach helps to prevent issues such as voids or cracks in the TSV, which can compromise electrical performance. The controlled deposition of the first metal portion provides a base that facilitates subsequent filling stages, resulting in a stable and reliable conductive pathway through the wafer.

[0136] In one embodiment of the present disclosure, the first portion through-wafer metal may comprise nickel, tin, gold, and / or silver. These materials are selected for their distinct properties, which enhance the overall performance and reliability of the wafer. Nickel offers excellent adhesion and strong resistance to oxidation, making it a suitable choice for the foundational layer within the through-silicon via (TSV). Tin is often chosen for its good solderability and corrosion resistance, providing a stable base layer that can facilitate subsequent metallurgical bonding processes. Gold, known for its superior resistance to oxidation and high conductivity, can enhance the stability and electrical performance of the TSV, particularly in environments prone to oxidation or requiring high reliability. Silver is also included for its exceptional electrical conductivity, contributing to efficient current flow, especially in applications where high currentcarrying capacity is needed.

[0137] By using a combination of these materials for the first portion through-wafer metal, it can provide a stable, low-resistance foundation for further metal filling of the trench. The presence of nickel, tin, gold, and / or silver ensures that the trench is partially filled with a robust conductive base, which supports reliable electrical performance. The choice of material can be tailored based on the specific application requirements; for instance, tin may be preferred when improved solderability is needed for downstream assembly processes, while gold or silver may be selected for applications requiring low resistance and high oxidation resistance.

[0138] This first portion through-wafer metal layer may also play a role in facilitating the subsequent filling of the trench with additional conductive material. The initial layer establishes a solid base for further metal deposition, which can include copper or other conductive metals, ensuring complete and uniform filling of the through-wafer via. The P7462PC00

[0139] 33 first portion through-wafer metal layer can be safely removed from the opposite side of the wafer by selective etching without damaging the main conductive path of the through-wafer via. This selective etching process is facilitated by the distinct material properties of the first portion through-wafer metal, allowing it to be differentiated from the subsequent metal layer. The use of materials such as nickel, tin, gold, and silver for the first portion enhances the stability of the TSV, even under thermal cycling, ensuring that the conductive path maintains its integrity and conductivity across varying temperatures and operating conditions.

[0140] In one embodiment of the present disclosure, the at least one trench is filled with a second portion of electrically conductive material. Filling the remaining portion of the trench with a second electrically conductive material enables the creation of a complete conductive path through the TSV. This second portion can be selected based on specific conductivity, durability, or cost requirements, allowing flexibility in material choice. For example, copper may be used as the second conductive material due to its high conductivity and cost-effectiveness, providing a low-resistance path that complements the first portion. The use of two different materials for the trench fill enables a hybrid approach, where the initial layer ensures adhesion and stability, while the second layer focuses on optimal electrical performance. The use of two different materials can be used to effectively etch the first portion through-wafer metal from the other side of the wafer. Since the first portion through-wafer metal and the second portion of electrically conductive metal are formed or deposited with two different metals, one can be selectively etched without etching the other, thereby limiting the etching to one or the other portion.

[0141] The second portion of electrically conductive material can comprise copper, silver, and / or aluminum. Copper is often selected for its high electrical conductivity and costeffectiveness, making it an ideal choice for filling the through-silicon via (TSV) and forming a low-resistance conductive path. Silver, known for its superior conductivity, can further enhance the efficiency of current flow, particularly in applications that demand high power delivery or low signal loss. Aluminum offers a lightweight alternative with good conductivity and excellent thermal properties, making it suitable for applications where reduced weight and effective heat dissipation are priorities. The choice of copper, silver, or aluminum for the second portion of electrically conductive material allows the method to be adapted based on the specific electrical, thermal, and mechanical requirements of the wafer, ensuring a reliable and consistent performance P7462PC00

[0142] 34 across a variety of high-power and high-frequency applications. Advantageously, the second portion of electrically conductive material may be of a different material or metal composition than the first portion through-wafer metal, mainly for the reasons described above, in the present disclosure, such as to perform an effective selective etching.

[0143] Figs. 2A-F show schematic views of embodiments of the different steps of the method as disclosed herein, wherein at least one conductive foil is used, and wherein the schematic views of embodiments of the process steps are performed in a panel-based environment. The embodiments of the process steps as shown in Figs. 2A-F are following the embodiments of the process steps performed in a cleanroom-environment of Figs. 1A-D. Fig. 2A shows the wafer 1 positioned on the panel carrier substrate 12. A dry-film resist 10 is laminated onto the first side of the wafer, and a multilayer conductive foil 18 is arranged on top of the dry-film resist. The multilayer conductive foil consists of a first conductive foil 19 and a second conductive foil 20, which are layered to enhance the electrical and mechanical properties of the foil structure. This configuration prepares the wafer for precise metal deposition during subsequent plating processes, with the dry-film resist serving as a mask to define specific plating regions. Fig. 2B illustrates the wafer 1 with the dry-film resist 10 partially or completely removed or dissolved at the bottom of the trench. This etching or removal step exposes the underlying areas necessary for further processing, such as metal deposition to fill the through-wafer via 14. The removal of the dry-film resist ensures that only the areas designated for conductive path formation remain open, facilitating precise and efficient plating or deposition in subsequent steps. This process step is crucial for creating well- defined electrical connections through the wafer. The wafer 1 is flipped compared to the disposition of the wafer in Fig. 2A, and is advantageously arranged on a panel carrier substrate 12 with a conductive base 15, allowing efficient plating processes in the following steps.

[0144] Fig. 2C illustrates the integration of the through-wafer via 14 by depositing an electrical conductive material within the trench. A first portion of through-wafer metal 21 is deposited within the trench, forming a foundational conductive path through the wafer, wherein the first portion of through-wafer metal comprises a secondary electrical conductive material, which is not necessarily the electrical conductive material of the through-wafer via. This initial metal deposition step ensures that the trench is partially filled with an electrical conductive metal, and that the first portion of through-wafer metal can be safely removed from the other side without removing the electrical P7462PC00

[0145] 35 conductive metal of the through-wafer via, in the subsequent steps described in the next figures. In Fig. 2D, the first redistribution layer 13 is deposited on the second side of the wafer 1 , aligned with the pattern defined by the dry-film resist 10. The dry-film resist facilitates selective metal deposition, allowing the first redistribution layer to be formed precisely according to the required layout. This second redistribution layer establishes the initial network for electrical routing on the wafer, enabling connections between different regions or components. Fig. 2E shows the wafer 1 after the conductive foil layers, including both the first conductive foil 19 and the second conductive foil 20, have been removed from the surface of the wafer. Additionally, the first portion of through-wafer metal 21 has been removed, which exposes the trench and allows the through-silicon via 14 to be completely filled up to the surface. This removal step ensures that the trench is prepared for final filling with conductive material, resulting in a uniform and continuous through-wafer via 14 that extends from the bottom to the top of the wafer. This process step is essential to finalize the through- wafer via structure, providing a reliable and robust electrical pathway through the wafer.

[0146] Fig. 2F illustrates the wafer 1 with the second redistribution layer 17 arranged on the top surface of the wafer. The second redistribution layer 17 is formed using a dry-film resist 16, which has been laminated onto the top surface or the first side of the wafer to define the precise pattern of the second redistribution layer. The dry-film resist serves as a mask, guiding the deposition process to ensure that the second redistribution layer follows the required layout for electrical connections. Once the second redistribution layer is deposited, the dry-film resist is removed, leaving a well-defined and structured redistribution network. This step completes the wafer’s routing configuration, ensuring that it is ready for integration into advanced electronic assemblies requiring complex interconnects.

[0147] In one embodiment of the present disclosure, the at least two wafers comprise at least three wafers, at least four wafers, at least five wafers, at least six wafers, at least seven wafers, at least eight wafers, at least nine wafers, or at least ten wafers.

[0148] The present disclosure relates to an wafer being manufactured by the method as disclosed herein. The wafer may be used for power applications, thereby the wafer as disclosed herein can be a power wafer. The through-wafer vias and redistribution layers as disclosed herein make the power wafer particularly well-suited for high- P7462PC00

[0149] 36 current and high-power applications. The wafer can accommodate a high density of through-silicon vias (TSVs) or through-wafer vias, which provides efficient and reliable vertical electrical pathways capable of carrying significant current loads. Furthermore, the thick redistribution layers, which can be fabricated using cost-effective copper electroplating techniques in a panel-based environment, offer low electrical resistance and high thermal conductivity. This design minimizes power losses and efficiently dissipates heat, crucial for maintaining performance and reliability in power electronics. The use of these thick, robust layers also reduces manufacturing costs, as the process does not require the same level of precision or expensive materials typically associated with finer redistribution layers, making the wafer ideal for consumer, industrial, and loT power applications.

[0150] In another aspect of the present disclosure, a system for processing or manufacturing a power wafer comprising at least one through-wafer via, and a redistribution layer is disclosed. The system can comprise a panel carrier substrate configured to support at least one wafer; a dry-film resist lamination unit configured to laminate a dry-film resist onto a first side and / or a second side of the at least one wafer; a photolithography unit configured to apply photolithography-based patterning to the dry-film resist to define a redistribution layer pattern; a conductive base comprised in the panel carrier substrate; and a control unit configured to process and execute the steps of the method as disclosed herein.

[0151] The system further may comprise a second panel carrier substrate, wherein the second panel carrier substrate can comprise the conductive base.

[0152] Further details

[0153] 1. A method of processing a power interposer comprising at least one through- interposer via with a hybrid manufacturing process, the method comprising: providing at least two interposers comprising at least one trench, wherein the at least one trench is etched from a first side to a second side of the at least two interposers and wherein an electrical insulation layer is arranged on the first side and the second side of the at least two interposers and on the inner sides of the at least one trench; arranging the at least two interposers on a panel carrier substrate; arranging a first redistribution layer on the first side of the at least two interposers; P7462PC00

[0154] 37 flipping the at least two interposers; filling the at least one trench with an electrically conductive material; and arranging a second redistribution layer on the second side of the at least two interposers.

[0155] 2. The method according to item 1 , wherein a seed layer is arranged on at least the first side of the at least two interposers.

[0156] 3. The method according to any one of the preceding items, wherein the at least two interposers have an interposer thickness.

[0157] 4. The method according to any one of the preceding items, wherein the at least one trench is etched from a first side of the at least two interposers, wherein the at least one trench depth is lower than the interposer thickness, wherein the electrical insulation layer is arranged on the first side and on the inner sides of the at least one trench, wherein the at least two interposers is thinned and / or polished from the second side of the at least two interposers, such that the at least one trench is extended through the interposer thickness of the at least two interposers, and wherein the at least two interposers are flipped and the electrical insulation layer is arranged on the second side of the at least two interposers.

[0158] 5. The method according to any one of the preceding items, wherein the at least two interposers are at least two silicon wafers.

[0159] 6. The method according to any one of the preceding items, wherein the method further comprises depositing a second seed layer on the second side of the at least two interposers.

[0160] 7. The method according to any one of the preceding items, wherein the second seed layer has the same properties than the seed layer.

[0161] 8. The method according to any one of the preceding items, wherein the electrical insulation layer comprise a dielectric layer and / or a diffusion barrier layer. P7462PC00

[0162] 38

[0163] 9. The method according to item 8, wherein the dielectric layer comprises silicon and / or aluminium, such as SiC>2, Sisl^ , AI2O3 and / or AIN.

[0164] 10. The method according to item 8, wherein the diffusion barrier layer comprises titanium, tantalum and / or silicon, such as TiC>2, TaN, Ta and / or SiaN^

[0165] 11. The method according to item 8, wherein the dielectric layer is arranged on the at least two interposers and the diffusion barrier layer is arranged on the dielectric layer.

[0166] 12. The method according to any one of the preceding items, wherein the seed layer is deposited with a physical vapor deposition (PVD) method, such as an evaporation method, wherein the evaporation method is directional such that the seed layer is deposited on the first side and / or the second side of the at least two interposers.

[0167] 13. The method according to item 12, wherein the PVD method is a sputtering method, wherein the seed layer is deposited on the first side and on the inner sides of the at least one trench.

[0168] 14. The method according to any one of the preceding items, wherein the seed layer comprises an adhesion layer and / or a seed conductive layer.

[0169] 15. The method according to item 14, wherein the adhesion layer comprises chrome, titanium and / or tantalum.

[0170] 16. The method according to any one of items 14-15, wherein the seed conductive layer comprises aluminium, copper and / or gold.

[0171] 17. The method according to any one of the preceding items, further comprising arranging a resist patterning, wherein the resist patterning defines a first patterning for arranging the first redistribution layer. P7462PC00

[0172] 39

[0173] 18. The method according to item 17, wherein the resist patterning is performed by using a dry-film lamination, wherein a dry-film resist is arranged or laminated on the first side and / or the second side of the at least two interposers.

[0174] 19. The method according to item 17, wherein the resist patterning is performed by using a laminated dry-film roll of liquid resist, wherein the laminated dry-film roll of liquid resist is applied on the first side and / or the second side of the at least two interposers by spin coating, screen printing and / or spray coating.

[0175] 20. The method according to any one of the preceding items, wherein arranging the first redistribution layer and / or the second redistribution layer is performed according to a redistribution layer (RDL) plating method.

[0176] 21. The method according to item 20, wherein the RDL plating method is an electroplating or an electroless plating method.

[0177] 22. The method according to any one of the preceding items, wherein the first redistribution layer and / or the second redistribution layer have a redistribution layer thickness comprised between 1 and 125 pm.

[0178] 23. The method according to any one of the preceding items, further comprising arranging a first passivation layer on the first redistribution layer and / or arranging a second passivation layer on the second redistribution layer.

[0179] 24. The method according to item 23, wherein the first passivation layer and / or the second passivation layer comprises silicon and / or aluminium, such as silicon nitride (SisN^ , silicon oxide (SiCh) and / or aluminium oxide (AI2O3).

[0180] 25. The method according to any one of the preceding items, wherein filling the at least one trench with the electrically conductive material is performed by using a bottom-up plating.

[0181] 26. The method according to any one of the preceding items, wherein the panel carrier substrate is a multilayer fiber glass (FR4), a machined substrate, a ceramic substrate, a metal substrate such as an aluminium substrate or a P7462PC00

[0182] 40 copper substrate, a polymer substrate such as polyimide substrate or polyether ether ketone (PEEK) substrate and / or a glass substrate.

[0183] 27. The method according to any one of the preceding items, wherein the panel carrier substrate has a panel carrier surface, and wherein the panel carrier surface is at least 0.05 m2, such as at least 0.1 m2, such at least 0.2 m2, such as at least 0.3 m2, such as at least 0.4 m2, such as at least 0.5 m2, such as at least 0.6 m2, such as at least 0.7 m2, such as at least 0.8 m2.

[0184] 28. The method according to any one of the preceding items, wherein the panel carrier substrate comprises a conductive base.

[0185] 29. The method according to item 28, wherein the conductive base is in contact with the first side and / or the second side of the at least two interposers.

[0186] 30. The method according to any one of items 28-29, wherein the conductive base comprises a conductive base material, and wherein the conductive base material comprises copper, aluminium, copper-clad laminates and / or metal alloys.

[0187] 31. The method according to any one of the preceding items, wherein the bottom- up plating is performed by applying a direct current to the conductive base, such that the electrically conductive material fills the trench.

[0188] 32. The method according to any one of the preceding items, further comprising applying a surface finishing to the first passivation layer, the second passivation layer, the first redistribution layer and / or the second redistribution layer.

[0189] 33. The method according to any one of the preceding items, wherein the first and / or the second redistribution layer comprises at least one pad.

[0190] 34. The method according to item 33, wherein the at least one pad is substantially squared, substantially circular, substantially annular or substantially polygonal. P7462PC00

[0191] 41

[0192] 35. The method according to any one of the preceding items, wherein the at least two interposers comprise silicon, silicon oxide and / or aluminium nitride.

[0193] 36. The method according to any one of the preceding items, wherein the at least two interposers have a substantially circular shape, and wherein the at least two interposers have a diameter comprised between 6 and 12 inches.

[0194] 37. The method according to any one of the preceding items, wherein the at least two interposers have a substantially rectangular shape, and wherein the first side and / or the second side of the at least two interposers have a surface area up to 0.2 m2.

[0195] 38. The method according to any one of the preceding items, wherein the interposer thickness is comprised between 50 and 500 pm.

[0196] 39. The method according to any one of the preceding items, further comprising using a photolithography-based patterning to dissolve a first redistribution layer area and / or a second redistribution layer area on the dry-film resist, such that a first redistribution layer pattern and / or a second redistribution layer pattern is arranged in the dry-film resist.

[0197] 40. The method according to any one of the preceding items, further comprising removing or dissolving the first redistribution layer pattern and / or the second redistribution layer pattern arranged in the dry-film resist.

[0198] 41. The method according to any one of the preceding items, wherein the method further comprises arranging a dry-film resist and a conductive foil on the first side of the at least two interposers.

[0199] 42. The method according to item 41, wherein the dry-film resist is arranged or laminated on the seed layer, and where the conductive foil is arranged or laminated on the dry-film resist. P7462PC00

[0200] 42

[0201] 43. The method according to any one of items 41-42, wherein the conductive foil comprises a conductive foil layer and / or a multilayer comprising at least two conductive foil layers.

[0202] 44. The method according to any one of items 41-43, wherein the at least two conductive foil layers comprises a first and a second conductive foil layers, and wherein the first and the second conductive foil layers comprises copper, aluminium, nickel, and / or tin.

[0203] 45. The method according to any one of items 41-44, wherein the first and the second conductive foil layers comprise respectively copper (Cu) and aluminium (Al), Cu and Sn, Cu and Ni, Al and Ni or, Al and Cu.

[0204] 46. The method according to any one of items 41-45, wherein the first conductive foil layer is arranged on the second conductive foil layer, and wherein the second conductive foil layer is arranged on the dry-film resist.

[0205] 47. The method according to any one of items 41-46, wherein the at least two interposers are flipped and arranged on a panel carrier substrate comprising a conductive base, and wherein the dry-film layer resist is removed or dissolved at the bottom of the at least one trench, preferably down to the surface of the conductive foil.

[0206] 48. The method according to any one of items 41-47, wherein a first portion through-interposer metal is arranged in the at least one trench, and wherein the first portion of through-interposer metal height is substantially lower than the at least one trench height.

[0207] 49. The method according to any one of items 41-48, wherein the first portion through-interposer metal comprises nickel, tin, gold, and / or silver.

[0208] 50. The method according to any one of items 41-49, wherein the at least one trench is filled with a second portion of electrically conductive material. P7462PC00

[0209] 43

[0210] 51. The method according to item 50, wherein the second portion of electrically conductive material comprises copper, silver and / or aluminium.

[0211] 52. The method according to any one of the preceding items, wherein the at least two interposers are at least three interposers, at least four interposers, at least five interposers, at least six interposers, at least seven interposers, at least eight interposers, at least nine interposers or at least ten interposers.

[0212] 53. The method according to any one of the preceding items, further comprising arranging a first secondary redistribution layer and / or a second secondary redistribution layer, wherein the first secondary redistribution layer is arranged on the first redistribution layer and the second secondary redistribution layer is arranged on the second redistribution layer, such as the at least two interposers comprise a multi-redistribution layer on the first side and / or the second side of the at least two interposers.

[0213] 54. An interposer for power applications, wherein the interposer is manufactured according to any one of items 1-53.

[0214] 55. A system for processing or manufacturing a power interposer comprising at least one through-interposer via, and a redistribution layer, the system comprising: a panel carrier substrate configured to support at least one interposer; a dry-film resist lamination unit configured to laminate a dry-film resist onto a first side and / or a second side of the at least one interposer; a photolithography unit configured to apply photolithography-based patterning to the dry-film resist to define a redistribution layer pattern; a conductive base preferably comprised in the panel carrier substrate; and a control unit configured to process and execute the steps of the method according to any one of items 1-53.

[0215] 56. The system according to item 55, wherein the system further comprises a second panel carrier substrate, wherein the second panel carrier substrate comprises the conductive base. P7462PC00

[0216] 44

[0217] Reference list

[0218] 1 - wafer

[0219] 2 - etching hard mask

[0220] 3 - photoresist

[0221] 4 - etch stop

[0222] 5 - carrier substrate

[0223] 6 - trench

[0224] 7 - dielectric layer

[0225] 8 - diffusion barrier layer

[0226] 9 - seed layer

[0227] 10 - dry-film resist

[0228] 11 - photolithography-based patterning

[0229] 12 - panel carrier substrate

[0230] 13 - first redistribution layer

[0231] 14 - trough-interposer via

[0232] 15 - conductive base

[0233] 16 - dry-film resist

[0234] 17 - second redistribution layer

[0235] 18 - multilayer conductive foil

[0236] 19 - first conductive foil

[0237] 20 - second conductive foil

[0238] 21 - first portion through-interposer metal

Claims

P7462PC0045Claims1. A hybrid manufacturing method for processing multiple wafers in parallel, the method comprising: providing at least two wafers, each wafer comprising at least one trench, wherein the at least one trench is etched from a first side to a second side of the wafer and wherein an electrical insulation layer is arranged on the first side and the second side of the wafer and on the inner sides of the at least one trench; arranging the at least two wafers on a panel carrier substrate; arranging a first redistribution layer on the first side of each of the at least two wafers; flipping the at least two wafers; filling the at least one trench in each of the at least two wafers with an electrically conductive material; and arranging a second redistribution layer on the second side of each of the at least two wafers.

2. The method according to claim 1, wherein a seed layer is arranged on at least the first side of the at least two wafers.

3. The method according to any one of the preceding claims, wherein the at least one trench is etched from a first side of the at least two wafers, wherein the at least one trench depth is lower than the waferthickness, wherein the electrical insulation layer is arranged on the first side and on the inner sides of the at least one trench, wherein the at least two wafersis thinned and / or polished from the second side of the at least two wafers, such that the at least one trench is extended through the wafer thickness of the at least two wafers, and wherein the at least two wafersare flipped and the electrical insulation layer is arranged on the second side of the at least two wafers.

4. The method according to any one of the preceding claims, wherein the method further comprises depositing a second seed layer on the second side of the at least two wafers, and wherein the second seed layer has the same properties than the seed layer.P7462PC00465. The method according to any one of the preceding claims, wherein the electrical insulation layer comprise a dielectric layer and / or a diffusion barrier layer, wherein the dielectric layer is arranged on the at least two wafersand the diffusion barrier layer is arranged on the dielectric layer.

6. The method according to any one of the preceding claims, further comprising arranging a resist patterning, wherein the resist patterning defines a first patterning for arranging the first redistribution layer, wherein the resist patterning is performed by using a laminated dry-film roll of liquid resist, wherein the laminated dry-film roll of liquid resist is applied on the first side and / or the second side of the at least two wafersby spin coating, screen printing and / or spray coating.

7. The method according to any one of the preceding claims, wherein arranging the first redistribution layer and / or the second redistribution layer is performed according to a redistribution layer (RDL) plating method, and wherein the RDL plating method is an electroplating or an electroless plating method.

8. The method according to any one of the preceding claims, wherein filling the at least one trench with the electrically conductive material is performed by using a bottom-up plating.

9. The method according to any one of the preceding claims, wherein the panel carrier substrate comprises a conductive base, and wherein the conductive base is in contact with the first side and / or the second side of the at least two wafers.

10. The method according to claim 8, wherein the bottom-up plating is performed by applying a direct current to the conductive base, such that the electrically conductive material fills the trench.

11. The method according to any one of the preceding claims, further comprising using a photolithography-based patterning to dissolve a first redistribution layer area and / or a second redistribution layer area on the dry-film resist, such that aP7462PC0047 first redistribution layer pattern and / or a second redistribution layer pattern is arranged in the dry-film resist.

12. The method according to claim 1 , wherein the method further comprises arranging a dry-film resist and a conductive foil on the first side of the at least two wafers, and wherein the conductive foil comprises a conductive foil layer and / or a multilayer comprising at least two conductive foil layers, and wherein the first conductive foil layer is arranged on the second conductive foil layer, and wherein the second conductive foil layer is arranged on the dry-film resist.

13. The method according to claim 12, wherein the at least two wafersare flipped and arranged on the panel carrier substrate comprising a conductive base, and wherein the dry-film layer resist is removed or dissolved at the bottom of the at least one trench, preferably down to the surface of the conductive foil.

14. The method according to any one of claims 12-13, wherein a first portion through-wafer metal is arranged in the at least one trench, and wherein the first portion of through-wafer metal height is substantially lower than the at least one trench height, and wherein the at least one trench is subsequently filled with a second portion of electrically conductive material.

15. A system for processing multiple wafers in parallel, the system comprising: a panel carrier substrate configured to support at least two wafers; a dry-film resist lamination unit configured to laminate a dry-film resist onto a first side and / or a second side of the at least two wafers; a photolithography unit configured to apply photolithography-based patterning to the dry-film resist to define a redistribution layer pattern; a conductive base preferably comprised in the panel carrier substrate; and a control unit configured to process and execute the steps of the method according to any one of claims 1-14.