Quantum state transfer architecture and implementation

Abstract

A novel and useful scalable quantum state transfer architecture for silicon spin qubit quantum computing systems, enabling qubit interaction, high fidelity readout, quantum measurement, and short shuttling of quantum states in a manufacturable and tileable layout. The invention provides a quantum state transfer structure comprising charge sensors positioned at the periphery of the structure that serve as charge carrier reservoirs and detectors for sensing a fraction of a single electron, ancilla quantum dots dedicated to spin-to-charge conversion, storage quantum dots configured to stably hold individual spin qubits and support high-fidelity single-qubit gate operations, state transport quantum dots dedicated to coherent shuttling of qubit states between distant physical locations, and interaction islands that enable controllable qubit–qubit exchange interaction, entanglement generation, and execution of single- and two- qubit quantum gates. The architecture enables extended interaction graphs for qubits by facilitating interactions via short state shuttling and compatibility with existing semiconductor fabrication processes.

Description

[0001] 12485.0116

[0002] QUANTUM STATE TRANSFER ARCHITECTURE AND IMPLEMENTATION

[0003] REFERENCE TO PRIORITY APPLICATION

[0004] This application claims the benefit of U.S. Provisional Application No. 63 / 728,824, filed December 6, 2024, entitled “Quantum State Transfer Architecture And Implementation” incorporated herein by reference in its entirety.

[0005] FIELD OF THE DISCLOSURE

[0006] The subject matter disclosed herein relates generally to the field of quantum computing systems and more particularly relates to quantum state transfer architectures for multi-qubit quantum processors and associated control and interconnection systems for optimizing qubit interaction, manipulation, and scalability.

[0007] BACKGROUND OF THE INVENTION

[0008] Quantum computing holds the promise of solving certain classes of problems that are intractable for classical computers, including factorization of large numbers, simulation of quantum mechanical systems, optimization problems, and machine learning tasks. Practical realization of this promise, however, requires the construction of quantum processors comprising large numbers of physical qubits that can be initialized, manipulated, and measured with extremely high fidelity while maintaining sufficiently long coherence times.

[0009] One of the primary challenges in designing scalable quantum computers is developing an architecture that supports a robust and extended interaction graph for qubits. Unlike classical bits, which can be routed arbitrarily through classical wiring with negligible penalty, physical qubits typically interact only with a limited number of nearest neighbors as dictated by the underlying physical implementation (e.g., superconducting transmons coupled via microwave resonators or capacitive coupling, trapped ions coupled via shared motional modes, neutral atoms coupled via Rydberg interactions, spin qubits in semiconductor quantum dots coupled via exchange or dipole interactions, photonic qubits coupled via interferometric networks, etc.). This limited native connectivity gives rise to sparse interaction graphs that deviate significantly from the all-to-all connectivity required for efficient execution of many quantum algorithms.

[0010] To execute quantum circuits that demand interactions between logically distant qubits, existing systems rely heavily on sequences of SWAP gates or equivalent multi-step coupling operations to shuttle quantum states across the processor. Each such operation introduces additional two-qubit gate infidelities, prolongs circuit depth, increases susceptibility to 12485.0116 decoherence, and ultimately reduces the overall computational success probability. As the number of qubits grows from tens to hundreds and eventually to thousands or millions, the overhead associated with these state-shuttling operations becomes prohibitive, severely limiting algorithmic performance and practical utility. Numerous approaches have been proposed to mitigate the connectivity bottleneck.

[0011] These include modular architectures in which smaller quantum processing units are interconnected via photonic links or ion shuttling, reconfigurable coupler networks, long-range direct coupling mechanisms, and compiler techniques that optimize qubit placement and routing. Despite these efforts, achieving a sufficiently dense and flexible interaction graph while simultaneously preserving qubit coherence, minimizing control complexity, reducing cryogenic or vacuum hardware requirements, and maintaining compatibility with high-fidelity gate operations remains a central unsolved problem in the field.

[0012] Accordingly, there remains a need for quantum computing architectures and associated fabrication, control, and interconnection techniques that enable robust, extensible, and high- connectivity interaction graphs without incurring unacceptable penalties in gate fidelity, coherence time, hardware overhead, or operational complexity.

[0013] 12485.0116

[0014] SUMMARY OF THE INVENTION

[0015] The present invention is a novel and useful scalable quantum state transfer architecture for silicon based spin qubit quantum computing systems, enabling long range qubit interaction, high fidelity readout, quantum nondestructive measurement, and efficient shuttling of quantum states in a manufacturable and tileable layout.

[0016] In one aspect, the invention provides a quantum state transfer structure comprising (1) highly sensitive charge sensors (e.g., single-electron transistors or single-electron boxes) positioned at the periphery of the structure and serving both as reservoirs of charge carriers and as detectors capable of sensing a fraction of a single electron; (2) one or more ancilla quantum dots dedicated to spin-to-charge conversion; (3) one or more storage quantum dots configured to stably hold individual spin qubits and support high-fidelity single-qubit gate operations; (4) one or more state transport quantum dots dedicated to coherent shuttling of qubit states between distant physical locations; and (5) one or more interfacing interaction islands that enable controllable qubit-qubit exchange interaction, entanglement generation, and execution of single- and two-qubit quantum gates.

[0017] Readout and initialization are preferably performed via spin dependent tunneling between a storage dot and an ancilla dot, exploiting Pauli blockade: matching spins prevent tunneling, while opposite spins allow charge transfer that is subsequently detected by the charge sensor, yielding logical “1” or “0”. The tunneled charge is then returned to its original storage dot, enabling quantum non-destructive measurement and real-time error detection.

[0018] Single qubit operations are achieved by resonant microwave pulses individually addressed to storage dots or interaction islands through unique frequency responses. Two-qubit gates are executed within the interfacing interaction islands, preferably assisted by local magnetic field gradients (e.g., from micromagnets or mesoscale magnetic arrays) in n-type devices or by direct electric-field control in p-type devices.

[0019] One feature is the use of dedicated state transport dots that shuttle spin qubit states from storage locations to a central interaction island for multi-qubit operations and back, thereby allowing non-adjacent qubits to interact without requiring direct nearest-neighbor coupling.

[0020] The quantum dots may be electrostatically defined in fully depleted silicon-on-insulator (FD-SOI) substrates or in Si / SiGe heterostructures, and the charge sensors may operate in RF reflectometry or DC mode.

[0021] In one embodiment, the invention provides an elementary cell comprising an X-shaped (or cross-shaped) silicon channel with a central interfacing interaction island and four branches extending therefrom. Each branch contains a linear array of quantum dots that can be 12485.0116 configured as ancilla, storage, or transport dots, controlled by polysilicon or metal tunneling gates and plunger electrodes. Charge sensing structures or electrometers coupled to the ancilla dots provide high-sensitivity readout. One or more branches may be extended to satisfy fabrication design rules while preserving full functionality.

[0022] A plurality of such elementary cells can be tiled and interconnected via state transport dots or shared interaction islands to form linear, branched, V-shaped, two-dimensional, or honeycomb-lattice arrays, wherein each interaction island retains connectivity to up to four storage branches, creating a rich and extensible qubit interaction graph suitable for fault- tolerant quantum computing.

[0023] In an alternative embodiment realized in a two-dimensional electron gas (2DEG) heterostructure, accumulation gates load carriers, screening and barrier / plunger gates define the quantum dot arrays, and Y-shaped or multi -branch elementary units similarly enable shuttling of spin states to central interaction islands for multi-qubit operations, with multiple units interconnectable into linear chains or honeycomb lattices.

[0024] The disclosed architecture thereby achieves scalable, manufacturable silicon spin-qubit quantum processors with long-range coherent qubit coupling, fast and non-destructive readout, live error detection capability, and flexible topology while remaining compatible with existing CMOS, FD-SOI, and Si / SiGe fabrication processes.

[0025] There is thus provided in accordance with the invention, a quantum state transfer structure for a quantum computing system, comprising a charge sensor positioned at edges of said structure and operative both as a source of charge carriers and as a sensor capable of detecting the presence or absence of a fraction of a single electron, one or more ancilla dots configured for spin-to-charge conversion, one or more storage dots operative to hold a single spin qubit and to support single-qubit operations, one or more state transport dots operative to transport qubit quantum states between different physical locations within said structure, and one or more interaction islands configured to enable qubit to qubit interaction and entanglement and to support single and two qubit quantum operations.

[0026] There is also provided in accordance with the invention, an elementary cell of a scalable quantum state transfer architecture, comprising an X-shaped silicon channel comprising at least one horizontal section and a plurality of sections rotated at 45 degrees, an interaction island located at the center of said X-shaped channel, four branches extending from said interaction island, each branch containing one or more quantum dots designated as ancilla dots, storage dots, or state transport dots, a plurality of polysilicon or metal tunneling gates overlying a channel and configured to control tunneling rates between adjacent quantum dots, a plurality 12485.0116 of plunger electrodes configured to control the potential energy or chemical potential of individual quantum dots, and charge sensing structures or electrometers coupled to at least one ancilla dot and operative both as a charge carrier reservoir and as a charge detector capable of sensing a fraction of a single electron. There is further provided in accordance with the invention, a quantum state transfer device, comprising a heterostructure constructed from a two-dimensional electron gas by application of voltage to one or more accumulation electrodes, a plurality of screening gates configured to electrostatically define quantum dot arrays within said two-dimensional electron gas, one or more accumulation gates configured to load charge carriers into said device, a plurality of barrier gates and plunger gates configured to define and control individual quantum dots and interdot tunneling, one or more single electron transistors or single electron boxes serving as charge sensors positioned proximate to ancilla dots, at least one Y-shaped or multibranch elementary unit comprising an interaction island and multiple branches containing storage dots, ancilla dots, and state transport dots, and wherein said device is configured to shuttle spin qubit states along the branches to the interaction island for multi-qubit operations and back to storage dots for storage.

[0027] 12485.0116

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention is explained in further detail in the following exemplary embodiments and with reference to the figures, where identical or similar elements may be partly indicated by the same or similar reference numerals, and the features of various exemplary embodiments being combinable. It should be expressly understood that the drawings are included for illustrative purposes and do not represent the scope of the present system. It is to be understood that the figures may not be drawn to scale. Further, the relation between objects in a figure may not be to scale and may have a reverse relationship as to size. In the accompanying drawings, like reference numbers in different drawings may designate identical or similar elements, portions of similar elements and / or elements with similar functionality. The present system is explained in further detail, and by way of example, with reference to the accompanying drawings which show features of various exemplary embodiments that may be combinable and / or severable wherein:

[0030] Fig. 1 is a high level block diagram illustrating a first example quantum computer system constructed in accordance with the present invention;

[0031] Fig. 2 is a diagram illustrating key components of the short shuttling quantum state transfer architecture of the present invention;

[0032] Fig. 3 is a diagram illustrating an example of spin detection by the spin-to-charge conversion in ancilla dot;

[0033] Fig. 4 is a diagram illustrating example single qubit operations in storage dots with application of microwave pulses;

[0034] Fig. 5 is a diagram illustrating example state transfer dots transferring qubit state from storage dots to interaction islands;

[0035] Fig. 6 is a diagram illustrating example interaction islands facilitating two-qubit operations;

[0036] Fig. 7 is a diagram illustrating example combined storage dots / interaction islands with application of microwave pulses;

[0037] Fig. 8 is a diagram illustrating a first example elementary cell realization of the short shuttling architecture of the present invention using FD-SOI technology;

[0038] Fig. 9 is a diagram illustrating a first example layout constructed by scaling the first example short shuttling FD-SOI device;

[0039] Fig. 10 is a diagram illustrating a second example layout constructed by scaling the first example short shuttling FD-SOI device; 12485.0116

[0040] Fig. 11 is a diagram illustrating a third example layout constructed by scaling the first example short shuttling FD-SOI device;

[0041] Fig. 12 is a diagram illustrating a second example elementary cell realization of the short shuttling architecture of the present invention using FD-SOI technology;

[0042] Fig. 13 is a diagram illustrating a third example elementary cell realization of the short shuttling architecture of the present invention using Si / SiGe technology;

[0043] Fig. 14 is a diagram illustrating a fourth example elementary cell realization of the short shuttling architecture of the present invention using FD-SOI technology;

[0044] Fig. 15 is a diagram illustrating an example layout constructed by scaling the fourth example short shuttling FD-SOI device;

[0045] Fig. 16 is a diagram illustrating an example connectivity map of the elementary cell of the short shuttling architecture;

[0046] Fig. 17 is a diagram illustrating an example connectivity map of the first example layout of the short shuttling device;

[0047] Fig. 18 is a diagram illustrating a generalized example connectivity map of the short shuttling device layouts disclosed herein;

[0048] Fig. 19 is a diagram illustrating an example elementary cell realization of the short shuttling architecture of the present invention implemented in Si / SiGe heterostructure; and

[0049] Fig. 20 is a diagram illustrating an example layout constructed by scaling the example elementary cell realization implemented in Si / SiGe heterostructure.

[0050] 12485.0116

[0051] DETAILED DESCRIPTION

[0052] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be understood by those skilled in the art, however, that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

[0053] Among those benefits and improvements that have been disclosed, other objects and advantages of this invention will become apparent from the following description taken in conjunction with the accompanying figures. Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the invention that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the invention which are intended to be illustrative, and not restrictive.

[0054] The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.

[0055] The figures constitute a part of this specification and include illustrative embodiments of the present invention and illustrate various objects and features thereof. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. In addition, any measurements, specifications and the like shown in the figures are intended to be illustrative, and not restrictive. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

[0056] Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention. 12485.0116

[0057] Any reference in the specification to a method should be applied mutatis mutandis to a system capable of executing the method. Any reference in the specification to a system should be applied mutatis mutandis to a method that may be executed by the system.

[0058] Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The phrases “in one embodiment,” “in an example embodiment,” and “in some embodiments” as used herein do not necessarily refer to the same embodiment s), though it may. Furthermore, the phrases “in another embodiment,” “in an alternative embodiment,” and “in some other embodiments” as used herein do not necessarily refer to a different embodiment, although it may. Thus, as described below, various embodiments of the invention may be readily combined, without departing from the scope or spirit of the invention.

[0059] In addition, as used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and / or,” unless the context clearly dictates otherwise. The term “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise. In addition, throughout the specification, the meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

[0060] The following definitions apply throughout this document.

[0061] A quantum particle is defined as any atomic or subatomic particle suitable for use in achieving the controllable quantum effect. Examples include electrons, holes, ions, photons, atoms, molecules, artificial atoms. A carrier is defined as an electron or a hole in the case of semiconductor electrostatic qubit. Note that a particle may be split and present in multiple quantum dots. Thus, a reference to a particle also includes split particles. Qubits may comprise position based qubits, electrostatic based qubits, and / or charge based qubits. Furthermore, qubits can be hybrid, meaning they can explore a magnetic spin of the quantum particle in addition to its position (i.e. electrostatic or charge nature).

[0062] A qubit or quantum bit is defined as a two state (two level) quantum structure and is the basic unit of quantum information. A qudit is defined as a d-state (d-level) quantum structure. A qubyte is a collection of eight qubits.

[0063] In quantum computing, the qubit is the basic unit of quantum information, i.e. the quantum version of the classical binary bit physically realized with a two-state device. A qubit is a two state quantum mechanical system in which the states can be in a superposition. Examples include (1) the spin of the particle (e.g., electron, hole) in which the two levels can be taken as spin up and spin down; (2) the polarization of a single photon in which the two states can be taken to be the vertical polarization and the horizontal polarization; and (3) the 12485.0116 position of the particle (e.g., electron) in a structure of two quantum dots or qdots, in which the two states correspond to the particle being in one qdot or the other. In a classical system, a bit is in either one state or the other. Quantum mechanics, however, allows the qubit to be in a coherent superposition of both states simultaneously, a property fundamental to quantum mechanics and quantum computing. Multiple qubits can be further entangled with each other.

[0064] A quantum dot or qdot (also referred to in literature as QD) is a nanometer-scale structure where an addition or removal of a particle changes its properties is some ways. In one embodiment, quantum dots are constructed in silicon semiconductor material having typical dimension in nanometers. The position of a particle in a qdot can attain several states. Qdots are used to form qubits and qudits where multiple qubits or qudits are used as a basis to implement quantum processors and computers.

[0065] A quantum interaction gate is defined as a basic quantum logic circuit operating on a small number of qubits or qudits. They are the building blocks of quantum circuits, just like the classical logic gates are for conventional digital circuits.

[0066] A quantum structure or circuit is a plurality of quantum interaction gates. A quantum computing core is a plurality of quantum structures. A quantum computer is a circuit having one or more computing cores. A quantum fabric is a collection of quantum structures, circuits, or interaction gates arranged in a grid like matrix where any desired signal path can be configured by appropriate configuration of access control gates placed in access paths between qdots and structures that make up the fabric.

[0067] Throughout this document, a representation of the state of the one-qubit quantum state in spherical coordinates includes two angles q and j. The state of the one-qubit system is completely described by a normalized vector Y in the two dimensional complex Hilbert space. Taking into account that the global phase of a quantum state is not measurable, the vector Y can be described in spherical coordinates with two angles q and j. The angle q is between the vector Y and the z-axis and the angle j is the angle between the projection of the vector on the XY plane and the x-axis. Thus, any position on the sphere is described by these two angles q and j. Note that for one qubit the spherical representation is two dimensional. For multiple qubits the dimensionality will grow nonlinearly and two angles will not be enough.

[0068] Quantum Computer Architecture

[0069] A high-level block diagram illustrating a first example quantum computer system constructed in accordance with the present invention is shown in Figure 1. The quantum computer, generally referenced 10, comprises a conventional (i.e. not a quantum circuit) 12485.0116 external support unit 12, software unit 20, cryostat unit 36, quantum processing unit 38, clock generation units 33, 35, and one or more communication busses between the blocks. The external support unit 12 comprises operating system (OS) 18 coupled to communication network 76 such as LAN, WAN, PAN, etc., decision logic 16, and calibration block 14. Software unit 20 comprises control block 22 and digital signal processor (DSP) 24 blocks in communication with the OS 18, calibration engine / data block 26, and application programming interface (API) 28.

[0070] Quantum processing unit 38 comprises a plurality of quantum core circuits 60 supporting, inter alia, the execution of the quantum portion of the hybrid quantum-classical mechanism of estimating geometric entanglement of a quantum system, classical computer coprocessor 41 for supporting, inter alia, the execution of the classical portion of the hybrid quantum-classical mechanism of estimating geometric entanglement of a quantum system, high speed interface 58, detectors / samplers / output buffers 62, quantum error correction (QEC) 64, digital block 66, analog block 68, correlated data sampler (CDS) 70 coupled to one or more analog to digital converters (ADCs) 74 as well as one or more digital to analog converters (DACs, not shown), clock / divider / pulse generator circuit 42 coupled to the output of clock generator 35 which comprises high frequency (HF) generator 34. The quantum processing unit 38 further comprises serial peripheral interface (SPI) low speed interface 44, cryostat software block 46, microcode 48, command decoder 50, software stack 52, memory 54, and pattern generator 56. The clock generator 33 comprises low frequency (LF) generator 30 and power amplifier (PA) 32, the output of which is input to the quantum processing unit (QPU) 38. Clock generator 33 also functions to aid in controlling the spin of the quantum particles in the quantum cores 60.

[0071] The cryostat unit 36 is the mechanical system that cools the QPU down to cryogenic temperatures. Typically, it is made from metal and it can be fashioned to function as a cavity resonator 72. It is controlled by cooling unit control 40 via the external support unit 12. The cooling unit control 40 functions to set and regulate the temperature of the cryostat unit 36. By configuring the metal cavity appropriately, it is made to resonate at a desired frequency. A clock is then driven via a power amplifier which is used to drive the resonator which creates a magnetic field. This magnetic field can function as an auxiliary magnetic field to aid in controlling one or more quantum structures in the quantum core.

[0072] The external support unit / software units may comprise any suitable computing device or platform such as an FPGA / SoC board. In one embodiment, it comprises one or more general purpose CPU cores and optionally one or more special purpose cores (e.g., DSP core, floating 12485.0116 point, etc.) that that interact with the software stack that drives the hardware, i.e. the QPU. The one or more general purpose cores execute general purpose opcodes while the special purpose cores execute functions specific to their purpose. Main memory comprises dynamic random access memory (DRAM) or extended data out (EDO) memory, or other types of memory such as ROM, static RAM, flash, and non-volatile static random access memory (NV SRAM), bubble memory, etc. The OS may comprise any suitable OS capable of running on the external support unit and software units, e.g., Windows, MacOS, Linux, QNX, NetBSD, etc. The software stack includes the API, the calibration and management of the data, and all the necessary controls to operate the external support unit itself.

[0073] The clock generated by the high frequency clock generator 35 is input to the clock divider 42 that functions to generate the signals that drive the QPU. Low frequency clock signals are also input to and used by the QPU. A slow serial / parallel interface (SPI) 44 functions to handle the control signals to configure the quantum operation in the QPU. The high speed interface 58 is used to pump data from the classic computer, i.e. the external support unit, to the QPU. The data that the QPU operates on is provided by the external support unit.

[0074] Non-volatile memory may include various removable / non-removable, volatile / nonvolatile computer storage media, such as hard disk drives that reads from or writes to non-removable, nonvolatile magnetic media, a magnetic disk drive that reads from or writes to a removable, nonvolatile magnetic disk, an optical disk drive that reads from or writes to a removable, nonvolatile optical disk such as a CD ROM or other optical media. Other removable / non-removable, volatile / nonvolatile computer storage media that can be used in the exemplary operating environment include, but are not limited to, magnetic tape cassettes, flash memory cards, digital versatile disks, digital video tape, solid state RAM, solid state ROM, and the like.

[0075] The computer may operate in a networked environment via connections to one or more remote computers. The remote computer may comprise a personal computer (PC), server, router, network PC, peer device or other common network node, or another quantum computer, and typically includes many or all of the elements described supra. Such networking environments are commonplace in offices, enterprise-wide computer networks, intranets and the Internet.

[0076] When used in a LAN networking environment, the computer is connected to the LAN via network interface 76. When used in a WAN networking environment, the computer includes a modem or other means for establishing communications over the WAN, such as the 12485.0116

[0077] Internet. The modem, which may be internal or external, is connected to the system bus via user input interface, or other appropriate mechanism.

[0078] Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++, C# or the like, conventional procedural programming languages, such as the “C” programming language, and functional programming languages such as Python, Matlab, Prolog and Lisp, machine code, assembler or any other suitable programming languages.

[0079] Also shown in Figure 1 is the optional data feedback loop between the quantum processing unit 38 and the external support unit 12 provided by the partial quantum data read out. The quantum state is stored in the qubits of the one or more quantum cores 60. The detectors 62 function to measure / collapse / detect some of the qubits and provide a measured signal through appropriate buffering to the output ADC block 74. The resulting digitized signal is sent to the decision logic block 16 of the external support unit 12 which functions to reinject the read out data back into the quantum state through the high speed interface 58 and quantum initialization circuits. In an alternative embodiment, the output of the ADC is fed back to the input of the QPU.

[0080] In one embodiment, quantum error correction (QEC) is performed via QEC block 64 to ensure no errors corrupt the read out data that is reinjected into the overall quantum state. Errors may occur in quantum circuits due to noise or inaccuracies similarly to classic circuits. Periodic partial reading of the quantum state functions to refresh all the qubits in time such that they maintain their accuracy for relatively long time intervals and allow the complex computations required by a quantum computing machine.

[0081] It is appreciated that the architecture disclosed herein can be implemented in numerous types of quantum computing machines. Examples include semiconductor quantum computers, superconducting quantum computers, magnetic resonance quantum computers, optical quantum computers, etc. Further, the qubits used by the quantum computers can have any nature, including charge qubits, spin qubits, hybrid spin-charge qubits, etc.

[0082] In one embodiment, the quantum structure disclosed herein is operative to process a single particle at a time. In this case, the particle can be in a state of quantum superposition, i.e. distributed between two or more locations or charge qdots. In an alternative embodiment, the quantum structure processes two or more particles at the same time that have related spins. In such a structure, the entanglement between two or more particles could be realized. Complex quantum computations can be realized with such a quantum interaction gate / structure or circuit. 12485.0116

[0083] In alternative embodiments, the quantum structure processes (1) two or more particles at the same time having opposite spin, or (2) two or more particles having opposite spins but in different or alternate operation cycles at different times. In the latter embodiment, detection is performed for each spin type separately.

[0084] Short Shuttling Quantum State Transfer Architecture

[0085] As discussed supra, one of the primary challenges in designing scalable quantum computers is developing an architecture that supports a robust and extended interaction graph for qubits. The architecture of the present invention is structured to optimize qubit interaction, manipulation, and scalability. This architecture integrates several key components, each designed to perform specific functions within the quantum computing process. In particular, the quantum state transfer architecture integrates components to support qubit initialization, manipulation, storage, transport, entanglement, and readout. The architecture comprises a network of quantum dots electrostatically defined within a semiconductor channel, interconnected to form functional regions. These regions include initialization and readout segments, storage segments, interfacing segments for quantum operations, and state transport paths for moving qubit states between locations.

[0086] The architecture operates on spin qubits, where the spin state of a single electron or hole (e.g., spin-up or spin-down) encodes quantum information. Qubits are manipulated using microwave pulses for single qubit gates, exchange interactions for two qubit gates, and controlled tunneling for readout and transport. The architecture provides for the separation of qubit functions into dedicated dots, allowing non-adjacent qubits to interact via shuttling, thereby overcoming limitations of nearest neighbor coupling in traditional arrays. This results in a semi-dense qubit array with enhanced connectivity, supporting fault tolerant quantum computations.

[0087] The device enhances qubit sensing capabilities by incorporating highly sensitive charge detectors, enabling measurement of multiple qubits with minimal decoherence. Implementations in FD-SOI and Si / SiGe provide manufacturability advantages, such as compatibility with CMOS processes and the ability to form two-dimensional (2D) electron or hole gases for quantum dot confinement.

[0088] A diagram illustrating key components of the short shuttling quantum state transfer architecture of the present invention is shown in Figure 2. The quantum circuit, generally referenced 80, comprises several components that are used to build the circuit, including charge 12485.0116 sensors (CS) 82, ancilla quantum dots (A) 84, storage quantum dots (S) 86, transfer quantum dots (T) 88, and interaction island quantum dots (I) 89.

[0089] The charge sensor (CS) is a key component of the quantum state transfer architecture. The charge sensor plays a dual role as charge carrier source and detector (e.g., single electron transistor or CCD), sensing fractional electrons. They are typically positioned at the edges or periphery of the structure and comprise one or more reservoirs connected to quantum dots within the quantum dot array via tunnel barriers. This configuration allows the charge sensor to fulfill two essential roles: (1) providing a source of charge carriers to the quantum dot array; and (2) acting as a highly sensitive sensor capable of detecting the presence or absence of a fraction of a single electron. Note that the ability to detect such minute charge differences is critical for the initialization and continuous monitoring of qubit states within the quantum device. In one embodiment, the CS operates as a single electron transistor (SET) or single electron box (SEB) in radio frequency (RF) reflectometry or direct current (DC) mode, providing high sensitivity for spin state detection.

[0090] The ancilla dot (A) is utilized for spin-to-charge conversion and readout via spindependent tunneling which is essential for spin state detection (i.e. Pauli blockade where tunneling indicates opposite spins, yielding logical ‘ 1’ or ‘0’). This quantum dot is a part of the initialization and readout mechanism, where the successful tunneling of an electron to the ancilla dot signifies a specific spin state, facilitating proper initial state definition and accurate measurement of the qubit’s spin. The ancilla dot is typically proximately coupled to the CS for charge detection.

[0091] The storage dot (S) is configured to host initialized spin qubits that comprise one or several charge carriers, such as an electron or hole, and in the context of spin qubits, it holds a single qubit. This quantum dot can also be used for single-qubit operations, where precise control of the qubit state is achieved via microwave pulses for rotations like X-gates. Note that the storage dot is a central element in maintaining qubit coherence during idle periods and ensuring that qubits are available for operations when needed utilizing connections to other components for transport and interaction.

[0092] The state transport dot (T) is an optional component that can be added to the architecture to facilitate coherent shuttling of qubit states between different non-adjacent physical locations within the device thereby extending interaction graphs. By sequentially adjusting gate voltages, the spin state is coherently transferred along a chain of transport dots, preserving quantum information. This capability is crucial for enabling interactions between qubits that 12485.0116 are not adjacent, effectively extending the interaction graph and enhancing the device’s computational power.

[0093] The interaction island (I) is a central region comprising one or more quantum dots designated for entangling qubits and it can also facilitate qubit-qubit interactions, single qubit operations, two qubit operations, quantum gates, and qubit storage. This area consists of quantum dots configured to facilitate single-qubit and two-qubit gates, enabling qubits to interact and perform essential quantum operations (e.g., CNOT, entanglement via exchange coupling, etc.), controllable by central gates and optionally assisted by micromagnets / RF lines in n-type devices or electric fields in p-type devices. The interaction islands are interconnected with other interaction, storage or state transport dots via tunnel barriers and gates, creating a flexible and scalable quantum computing architecture that allows qubits to be moved, operated on, and measured as needed.

[0094] Note that the five components described supra are physically similar quantum dots but they are differentiated by function where the differences are mainly due to from fabrication constraints (e.g., larger islands due to gate cuts). Operations include initialization / readout (nondestructive, error detecting), single qubit manipulations, state transport for nonadj acent interactions, and two qubit gates.

[0095] Quantum State Transfer Architecture Operational Flow

[0096] In one embodiment, the quantum state transfer architecture operates by leveraging the specific functionalities of its components to perform various quantum operations, including qubit initialization, single-qubit gates, qubit state transport, entanglement, and readout. The following describes the operational flow and interaction between these various components.

[0097] A diagram illustrating example single-qubit operations in storage dots is shown in Figure 3. The example quantum circuit, generally referenced 90, comprises charge sensors (CS) 92, ancilla dots (A) 94, storage dots (S) 96, transfer dots (T) 98, and interaction island dots (I) 99. The qubit initialization and readout processes within the quantum state transfer architecture are seamlessly integrated through the use of the charge sensor and the ancilla dot. Spin dependent tunneling from a storage dot to the ancilla dot exploits the Pauli exclusion principle where matching spins (e.g., both up or both down) block tunneling, while opposite spins allow charge transfer. The CS detects this tunneling event and records the spin state. Postreadout, the charge is returned to the storage dot, enabling quantum nondestructive measurement and real time error detection. This process initializes qubits by confirming their 12485.0116 states, allowing adjustments to gate sequences. The non-demolition nature supports live monitoring without state collapse, enhancing system reliability.

[0098] The ancilla dot is used during readouts by facilitating spin-to-charge conversion, allowing the spin state of each qubit in the storage dots to be directly measured through statedependent tunneling of a charge carrier from the storage dot to the ancilla dot. The tunneling event is contingent upon the compatibility of the spin states and serves as a direct indicator of a qubit’s spin state. If tunneling to the ancilla dot is successful (arrow 93), the classical register records a ‘ 1’, otherwise if tunneling is not successful (arrow 94) it records a ‘0’ as shown in Figure 3. After the readout procedure, all successfully tunneled spins are returned to their respective storage dots, preserving their state. This mechanism not only reveals but also confirms the spin states of all qubits in the system, effectively initializing them. Knowing the initial spin states enables necessary adjustments to be made to the quantum gate sequences performed on the array.

[0099] In addition, the use of ancilla dots for quantum non-demolition (i.e. nondestructive) measurements enables live error detection within the system. This method allows for the continuous monitoring of qubits without disrupting their quantum state, providing real-time feedback and enabling immediate correction of errors. This capability is important for maintaining quantum coherence and fidelity across extended quantum computations, significantly enhancing the reliability and efficiency of the architecture.

[0100] Note that that the ability of the charge sensor to detect very small changes in charge, i.e. down to a fraction of an electron, is essential. By monitoring the act of tunneling, and thus the spin state of the qubits in the storage dots, the charge sensor ensures that the system is correctly initialized and that the qubit states are accurately determined before proceeding with further quantum operations.

[0101] Single-qubit operations in interfacing and storage dots will now be described in more detail. A diagram illustrating example single qubit operations in storage dots with application of microwave pulses is shown in Figure 4. The example quantum circuit, generally referenced 100, comprises charge sensors (CS) 102, ancilla dots (A) 104, storage dots (S) 106, transfer dots (T) 108, and interaction island dots (I) 109. In one embodiment, single-qubit operations are carried out in the interaction dots and storage dots by applying microwave pulses. Each quantum dot within this segment has a unique frequency response allowing selective manipulation of individual qubits. For example, arbitrary X-rotation gates can be applied to specific qubits within the array, such as storage dots within branches ‘b’ and ‘c’, enabling precise control of their quantum states without crosstalk. 12485.0116

[0102] Regarding qubit quantum state transport, state transport dots are used to shuttle (i.e. transfer) qubit state from distant storage branches to the interaction islands for entablement and interaction with other qubits and then returned. This extends the interaction graph, allowing non-local operations while minimizing decoherence during transport. Various transfer scenarios are possible, such as qubits stored in branches ‘a’ and ‘b’ being moved to an interaction island for entanglement, or the entangled state being transported to interact with another qubit, stored in the branch ‘d’. After the necessary operations, the results can be transferred back to the storage dots for measurement. This is illustrated in Figure 5 which is a diagram showing example state transfer dots transferring qubit state from storage dots to interaction islands. The example quantum circuit, generally referenced 110, comprises charge sensors (CS) 112, ancilla dots (A) 114, storage dots (S) 116, transfer dots (T) 118, and interaction island dots (I) 119.

[0103] A diagram illustrating example interaction islands facilitating two-qubit operations is shown in Figure 6. The example quantum circuit, generally referenced 120, comprises charge sensors (CS) 122, ancilla dots (A) 124, storage dots (S) 126, transfer dots (T) 128, and interaction island dots (I) 129. In one embodiment, the interaction islands facilitate single- and two-qubit operations, such as generic two-qubit gates or specific gates like CNOT. Gates like CNOT are facilitated by modulating inter-dot coupling with gates. In n-type (NMOS) devices, local magnetic field gradients from micromagnets or mesoscale arrays assist operations whereas in p-type (PMOS) devices, electric fields are sufficient. This enables entanglement and multi-qubit computations.

[0104] For example, qubits stored in branches ‘a’ and ‘b’ may undergo entanglement. Alternatively, qubits stored in branches ‘c’ and ‘d’ may undergo entanglement after shuttling to the interaction island. Qubits stored in branches ‘a’ and ‘d’ and ‘c’ and ‘b’ may also undergo entanglement after shuttling through respective dots in each path. The addressability of these interactions may be enhanced by local magnetic field gradients, which can be generated by micromagnets or a mesoscale magnetic array for NMOS devices, where qubits are defined by electrons spin states. For PMOS devices, where qubits are defined as a spin state of a hole, addressability is provided by the electric modulation of a quantum dot.

[0105] An example of this is shown in Figure 7 which illustrates example combined storage dots / interaction islands with application of microwave pulses. The example quantum circuit, generally referenced 130, comprises charge sensors (CS) 132, ancilla dots (A) 134, combined storage and interaction dots (I, S) 136, and transfer dots (T) 138. As described supra, single- 12485.0116 qubit operations are carried out in the interaction dots and storage dots by applying microwave pulses 139.

[0106] The structure of the quantum computing device incorporating spin based qubits will now be described in more detail. The quantum device of the present invention provides enhanced connectivity between qubits with the ability to sense more qubits, provide a semi- dense qubit array, and include implementations in both SiGe and FDSOI semiconductor processes.

[0107] In one embodiment, the quantum computing device utilizes spin based qubits formed within electrically defined quantum dots on a fully depleted silicon-on-insulator (FD-SOI) substrate. The device is structured according to a quantum state transfer architecture and comprises three primary functional components: (1) initialization and readout, (2) storage, (3) interaction regions, and (4) quantum state transfer regions and paths. These components are interconnected and coordinated to facilitate precise qubit operations, including initialization, manipulation, and readout.

[0108] Quantum dots are electrically defined by applying voltages to gates overlying a semiconductor channel, creating potential wells that confine single charge carriers. In FD-SOI implementations, the top silicon layer is etched into nanowires containing a 2D electron / hole gas. Polysilicon or metal gates form tunnel barriers and plungers, with back-gate voltage for additional confinement. In one embodiment, the channel in which the quantum dots are formed is defined by first processing the top silicon layer of the FD-SOI substrate into interconnected nanowires. These nanowires serve to contain a two-dimensional (2D) electron (or hole) gas, which is important for the operation of spin based qubits. The quantum dots (QDs) are defined between a set of polysilicon or metal gates, typically oriented vertically, which constitute the first gate layer of the device. By applying specific voltages to these gates, local depletion of the 2D electron gas occurs within the silicon nanowires, thereby creating tunnel barriers and discrete quantum wells that trap single electrons and form the quantum dots.

[0109] In one embodiment, the quantum device is divided into three interconnected segments, namely the initialization and readout segment, the storage segment, and the interaction segment. Each segment is described in more detail infra.

[0110] The initialization and readout segment includes a straight series of quantum dots and a single electron box (SEB) configuration designed for spin state initialization and detection. The SEB is employed in a readout procedure to measure the spin state of the qubits through detecting spin dependent tunneling, which differentiates between spin-up and spin-down states. This readout procedure inherently results in an initialization process due to the quantum 12485.0116 properties of the spin states in the system. This segment is optimized for high fidelity initialization and readout, ensuring accurate and repeatable qubit preparation and measurement.

[0111] The storage segment functions as the repository for qubits between operations, preserving their spin states with minimal decoherence and can be used for single qubit operations. This segment connects the initialization and readout segment to the interaction segment. Each storage segment is configured to maintain the spin state coherence over extended periods, with quantum dots configured to isolate qubits from external perturbations.

[0112] The interaction segment, configured as a straight segment, facilitates qubit interaction, particularly for two-qubit gate operations and can be used for single-qubit gates as well. It comprises a series of double quantum dots, where qubit-qubit interactions are mediated. By configuring the gate voltages appropriately, the coupling between neighboring quantum dots is modulated, enabling controlled exchange interaction necessary for entangling operations.

[0113] The highly interconnected nature of the interaction segments allows each segment to be connected to up to four different storage segments, creating a robust 2D qubit array. This interconnectivity facilitates efficient qubit transport and parallel operations, making the device architecture scalable and adaptable to complex quantum computations. Qubit transport involves sequential gate voltage adjustments, moving spin states while maintaining coherence.

[0114] The interaction region’s direct connection to multiple storage segments allows qubits to be brought together for interaction and then quickly moved back to a storage segment, preserving their coherence. This configuration supports flexible and efficient quantum operation sequences, where qubits can be initialized, manipulated, and read out across different regions of the device.

[0115] Regarding state transport and qubit movement, qubit states are transferred between the initialization and readout, storage, and interaction segments with charge carriers (electrons or holes) by sequentially adjusting the gate voltages thereby effectively moving the spin states through the device. The diagonal (i.e. 45 degree) segments, which function as storage, provide a pathway for qubits to transition between the various segments while preserving their spin state. The transport mechanism is designed to maintain qubit coherence, ensuring that the quantum information is intact throughout the operation process.

[0116] Quantum operations within the device include both single-qubit and two-qubit gates. Single-qubit operations can be performed in the storage segment, where isolated qubits can be manipulated without interference from neighboring qubits. Two-qubit operations and also single qubit operations are executed in the interaction segment, where qubits are brought together under controlled conditions to enable entangling operations. The transfer of qubit 12485.0116 states between segments allows for flexible operation sequences, where qubits can be initialized, manipulated, and read out in different regions of the device as needed.

[0117] FD-SOI Quantum State Transfer Device

[0118] A diagram illustrating a first example elementary cell realization of the short shuttling architecture of the present invention using FD-SOI technology is shown in Figure 8. The quantum cell, generally referenced 140, comprises a plurality of gates including silicon channel 142, raised source / drain structures with vertical electrodes (VIAs) 144, tunneling gates 146, 150, 154, 158, 162, plunger gates or electrodes 148, 152, 156, 160, interaction island 166, and 45 degree sections 164. In one embodiment, the elementary cell 140 of a scalable quantum state transfer architecture is implemented using 22FDX technology. The silicon channel 142 features an “X” shaped structure, comprising both horizontal sections and sections 164 rotated at 45 degrees. At the center of the structure is an interaction island 166. A plurality of tunneling gates 146, 150, 154, 158, 162 regulate the tunneling rate between neighboring quantum dots and are constructed as polysilicon gates positioned atop the channel controlled by the voltage applied to them. Plunger electrodes 148, 152, 156, 160 manage the energy (i.e. chemical potential) of each quantum dot, and can be made of metal in the Ml layer or replaced by polysilicon gates if the technology pitch is reduced. Confinement is independently controlled by a voltage applied to the common back gate of the device. Electrodes 144 serve both as the source of electrons or holes and as the contact to the detecting device.

[0119] The charge in the ancilla dot can be detected using either a single electron transistor or a charge coupled device (CCD) sensor connected to the source. Quantum dots formed in the branches of the device 140 are used as ancilla dots, storage dots, or state transport dots, with the possibility of increasing the number of state transport dots if required by technological constraints. The interaction island 166 facilitates spin-qubit interactions, with the central gate 162 controlling the interaction between dots. The number of dots within the interaction island 166 and in the branches 164 can be increased if needed to accommodate technological limitations. Note that alternatively, the gate 162 may also cut in the middle if it is required by the particular process limitations.

[0120] Several possible examples of structures of arrays of cells constructed from the elemental cell as basic building block shown in Figure 8 will now be described. A diagram illustrating a first example layout constructed by scaling the first example short shuttling FD- SOI device is shown in Figure 9. A diagram illustrating a second example layout constructed by scaling the first example short shuttling FD-SOI device is shown in Figure 10. The example 12485.0116 structures 170 and 180 illustrate a mechanism for scaling the quantum state transfer device. Configuration 170 comprises three interconnected “X”-shaped structures that are linked via state transport dots. Similarly, configuration 180 comprises six interconnected “X”-shaped structures that are linked via state transport dots. It is appreciated that this linear arrangement of structures is extendable to any arbitrary length thereby enabling scalable expansion of the device.

[0121] The device of Figure 8 can be extended in a nonlinear manner as well. A diagram illustrating a third example layout constructed by scaling the first example short shuttling FD- SOI device is shown in Figure 11. The structure, generally referenced 190, is one example array comprising nine elementary cells with nonlinear placement that extends the quantum state transfer architecture in 22FDX technology. In this configuration, a plurality of “X”- shaped structures are arranged in “ V”-shape. Note that in order to relax the possible design rule check (DRC) issues, one of the state transport branches 192 is extended. It is appreciated that additional configurations and shapes can be constructed without departing from the scope of the invention.

[0122] A diagram illustrating a second example elementary cell realization of the short shuttling architecture using FD-SOI technology of the present invention is shown in Figure 12. An alternative realization of an X-shaped cell architecture, generally referenced 210, comprises a silicon channel 212, electrodes 214, tunneling gates 216, 220, 224, 228, plunger gates or electrodes 218, 222, 226, and interaction island 230. The interaction island 230 comprises a single quantum dot located at the intersection of multiple branches. This configuration enables spin qubit interactions between qubits located in the interaction island 232 and state transport dots 226. The components of the device 210 function similarly to corresponding components of the device of Figure 8.

[0123] A diagram illustrating a fourth example elementary cell realization of the short shuttling architecture of the present invention using FD-SOI technology is shown in Figure 14. The quantum cell, generally referenced 350, comprises a plurality of gates including FD-SOI channel 384, electrodes 382, tunneling gates 386, 390, 394, 398, 402, 406, 410, 414, 418, plunger gates or electrodes 388, 392, 396, 400, 404, 408, 412, 416, interaction island 422, and 45 degree sections 420. In this configuration, two Y-shapes are linked via interaction islands (I). This arrangement allows the cell to be combined into more complex honeycomb shaped arrangements which enables a scalable quantum dot array with an extended interaction graph for qubit operations. 12485.0116

[0124] A diagram illustrating an example layout constructed by scaling the fourth example short shuttling FD-SOI device is shown in Figure 15. In this example, the layout configuration, generally referenced 430, comprises three elementary cells shown in Figure 14 combined to form a more complex layout providing an extended interaction graph for qubits. It is appreciated that layouts using additional cells can be constructed in similar fashion.

[0125] Si / SiGe Heterostructure Quantum State Transfer Device

[0126] The elementary cell of the scalable quantum state transfer architecture can also implemented in Si / SiGe heterostructure technology. A diagram illustrating a third example elementary cell realization of the short shuttling architecture of the present invention using Si / SiGe technology is shown in Figure 13. The cell, generally referenced 450, fabricated using Si / SiGe heterostructure technology, comprises screening gate 452, charge sensor 454 that includes accumulation gate 456, barrier gates 458, 462, plunger gates 460, 464). The Si / SiGe elementary cell also includes ancilla (A) dots (e.g., under gate 472), storage (S) dots (e.g., under gate 474), transfer (T) dots (e.g., under gate 470), and interaction island (I) dots (e.g., under gate 468. Areas 466 between branches are magnetic gradients generated by micromagnets. The area outside the four branches provide a dual function of screening gates and RF electron dipole spin resonance (EDSR) lines.

[0127] A diagram illustrating an example connectivity map of the elementary cell of the short shuttling architecture is shown in Figure 16. The connectivity map, generally referenced 200, comprises four eye symbols 202 representing quantum dots connected via a plurality of lines 204 that indicate possible state transport paths for shuttling and interaction. This example connectivity map 200 is equivalent to the elementary cells 140, 210, and 450 shown in Figures 8, 12, and 13, respectively, which shows full connectivity between all four quantum dots 202.

[0128] A diagram illustrating an example connectivity map of the first example layout of the short shuttling device is shown in Figure 17. The connectivity map, generally referenced 440, comprises eight eye symbols 442 representing quantum dots connected via a plurality of lines 444 that indicate possible state transport paths for shuttling and interaction. This example connectivity map 440 is equivalent to the scaled layout 170 of Figure 9, which includes full connectivity between all eight quantum dots 442.

[0129] A diagram illustrating a generalized example connectivity map of the short shuttling device layouts disclosed herein is shown in Figure 18. The connectivity map, generally referenced 480, comprises a plurality of eye symbols 442 representing quantum dots connected via a plurality of lines 484 that indicate possible state transport paths for shuttling and 12485.0116 interaction. This connectivity diagram of the quantum state transfer architecture covers layouts having arbitrary length via the ‘all to all’ cloud 486.

[0130] Note that the connectivity map corresponding to the elementary cell layout 380 of Figure 14 comprises two eye symbols connected together with two state transfer lines representing the upper and lower paths qubits can take.

[0131] A diagram illustrating an example elementary cell realization of the short shuttling architecture of the present invention implemented in Si / SiGe heterostructure is shown in Figure 19. This elementary cell, generally referenced 240, implements a quantum state transfer architecture element utilizing Si / SiGe heterostructure as a substrate. A 2D electron gas is contained in the quantum well of the substrate. The architecture comprises screening gates 267, 288, 305, 292, 293, 290 that electrostatically shape a 2D electron gas in the quantum well into quantum dot arrays 282, 284, 286 and single electron boxes (SEB) or transistors 276, 280, 278 which function as charge sensors. In one embodiment, in this technology, ohmic contacts that serve as the electron source, can be positioned approximately 0.5 to 1 micrometer from the device. Charge accumulation is achieved through the application of voltage to dedicated accumulation gates 266, 274, 308, 307, 291, 306. The tunneling rate within the single electron transistors 276, 280, 278 is regulated by barrier gates 268, 272, 304, 300, 298, 294, while the energy (i.e. chemical potential) of quantum dots, formed under plunger gates 270, 302, 296, is controlled by the voltage applied to these plunger gates. Charge sensing (310, 312, 314) occurs via changes in the current through the single electron transistor in response to the presence of an additional charge in a nearby ancilla dot or change in reflected RF power in case of an SEB.

[0132] The quantum dot arrays 282, 284, 286 are managed by barrier gates 316, 320, 324, 328, 332, 336, 242, 246, 250, 256, 260, 264 with the energy of the quantum dots controlled by plunger gates 318, 322, 326, 330, 334, 244, 248, 254, 258, 262. In this technology, the gate stack consists of several conductive layers isolated by high-k dielectrics. The bottom layer predominantly consists of the screening gates 267, 288, 305, 292, 293, 290. The other layers predominantly comprise plunger, accumulation, and barrier gates. Note that an alternative realization requires advanced manufacturing technology and utilizes all gates at the same level contacted through vias to conductive layers at the higher metallization levels. Each quantum dot array segment 282, 284, 286 can be extended to adjust device operation in large qubit arrays.

[0133] A diagram illustrating an example layout constructed by scaling the example elementary cell realization implemented in Si / SiGe heterostructure is shown in Figure 20. The layout, generally referenced 340, is an example of scaling a quantum state transfer device on a 12485.0116

[0134] Si / SiGe heterostructure. The configuration comprises two interconnected “Y”-shaped elementary cells, linked through state transport dots. It is appreciated by one skilled in the art that this linear structure can be extended to an arbitrary length by repeating segment 350 and terminating with segment 352 thereby enabling scalable expansion of the elementary cell device of Figure 19.

[0135] In operation, particles (e.g., electrons) can be loaded into the device using accumulation gates 344, 354 and barrier gates 346, 356 positioned at the edges of the array. In addition, screening gates 342, 358 are placed along the sides of the array to confine the 2D electron gas within the quantum dots in the quantum well. The quantum dot arrays are managed by barrier gates 364, 368, 372, 376 with the energy of the quantum dots controlled by plunger gates 366, 370, 374, 378.

[0136] The architecture of the present invention thus provides a versatile, scalable platform for quantum computing, enabling complex operations with high coherence and manufacturability. It is appreciated that variations of the architecture may include increased dot counts per branch or alternative gate materials, without departing from the scope of the invention.

[0137] One advantage of the short shuttling architecture described herein is that it provides for 2D structures via diagonal gates / channels which enables the use of relatively short shuttling paths for efficient qubit interactions without nearest neighbor limits. This is in contrast to prior art linear ID quantum dot connectivity that required long racetracks for qubit shuttling paths.

[0138] Another advantage is that the short shuttling architecture of the present invention provides diagonals to connect branches to central interaction islands (I) thereby allowing qubits from multiple storage sites to shuttle to ‘I’ dots for qubit operations and return which minimizes decoherence.

[0139] A further advantage is the short shuttling architecture is scalable which enables the realization of modular cells (e.g., X-shaped in FD-SOI, Y-shaped in Si / SiGe) interconnected to form linear, V-shaped, or honeycomb lattices as described in more detail infra. The included connectivity maps show quantum dots and transport lines.

[0140] Scalability is achieved by interconnecting cells via transport dots into linear arrays, X- shaped configurations, Y-shaped configurations, V-shaped configurations, or larger networks. Elementary cells can be linked via transport dots into linear arrays with an arbitrary number of repeatable segments or via interfacing islands forming honeycomb shaped lattices for extended qubit graphs.

[0141] Those skilled in the art will recognize that the boundaries between logic and circuit blocks are merely illustrative and that alternative embodiments may merge logic blocks or 12485.0116 circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.

[0142] Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermediary components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.

[0143] Furthermore, those skilled in the art will recognize that boundaries between the above described operations are merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

[0144] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0145] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first,” “second,” etc. are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually 12485.0116 different claims does not indicate that a combination of these measures cannot be used to advantage.

[0146] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

[0147] The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. As numerous modifications and changes will readily occur to those skilled in the art, it is intended that the invention not be limited to the limited number of embodiments described herein. Accordingly, it will be appreciated that all suitable variations, modifications and equivalents may be resorted to, falling within the spirit and scope of the present invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

12485.0116CLAIMS1. A quantum state transfer structure for a quantum computing system, comprising: a charge sensor positioned at edges of said structure and operative both as a source of charge carriers and as a sensor capable of detecting the presence or absence of a fraction of a single electron; one or more ancilla dots configured for spin-to-charge conversion; one or more storage dots operative to hold a single spin qubit and to support singlequbit operations; one or more state transport dots operative to transport qubit quantum states between different physical locations within said structure; and one or more interaction islands configured to enable qubit to qubit interaction and entanglement and to support single and two qubit quantum operations.

2. The structure according to claim 1, wherein said charge sensor comprises one or more reservoirs connected to one or more quantum dots via tunnel barriers.

3. The structure according to claim 1, wherein readout and initialization are performed by: coupling a target spin to an ancilla quantum dot whose charge configuration shifts in a spin-dependent manner; and wherein if the spins in an ancilla dot and a target dot match up or down, charge cannot tunnel to an ancilla dot due to the Pauli principle while nonmatching spins allow a charge to tunnel thereby enabling a charge state of the ancilla dot to be read out via a charge sensor to reveal the target spin state.

4. The structure according to claim 3, wherein said tunneling is detected by said charge sensor and tunneled charge is subsequently returned to its original storage dot, thereby enabling quantum measurement and live error detection.

5. The structure according to claim 1, wherein single qubit operations are performed by applying microwave pulses to selected storage dots or interfacing islands, each dot having a unique frequency response for individual addressability.

6. The structure according to claim 1, wherein two qubit gates are performed in the interaction islands and are assisted by local magnetic field gradients generated by either12485.0116 micromagnets or a mesoscale magnetic array for n-type metal oxide semiconductor (NMOS) devices while for p-type (PMOS) devices, quantum operations are implemented by direct application of one or more electric fields.

7. The structure according to claim 1 , wherein said state transport dots enable nonadj acent qubits to interact by shuttling quantum states from storage dots to an interaction island and back.

8. The structure according to claim 1, wherein said quantum dots are electrically defined in a fully depleted silicon-on-insulator (FD-SOI) channel or in a silicon / silicon germanium (Si / SiGe) heterostructure.

9. The structure according to claim 1, wherein said charge sensor is a single electron transistor or a single electron box operating in radio frequency (RF) reflectometry mode or direct current (DC) measurement mode.

10. The structure according to claim 1, wherein said one or more interfacing islands comprise a plurality of quantum dots controllable by a central gate that modulates interdot exchange interaction.

11. An elementary cell of a scalable quantum state transfer architecture, comprising: an X-shaped silicon channel comprising at least one horizontal section and a plurality of sections rotated at 45 degrees; an interaction island located at the center of said X-shaped channel; four branches extending from said interaction island, each branch containing one or more quantum dots designated as ancilla dots, storage dots, or state transport dots; a plurality of polysilicon or metal tunneling gates overlying a channel and configured to control tunneling rates between adjacent quantum dots; a plurality of plunger electrodes configured to control the potential energy or chemical potential of individual quantum dots; and charge sensing structures or electrometers coupled to at least one ancilla dot and operative both as a charge carrier reservoir and as a charge detector capable of sensing a fraction of a single electron.12485.011612. The elementary cell according to claim 11, wherein said charge in said ancilla dot is sensed by a single electron transistor or a charge-coupled device (CCD) sensor connected to said charge sensing electrodes.

13. The elementary cell according to claim 11, wherein said interaction island comprises multiple quantum dots and a central tunneling gate that controls qubit to qubit interaction strength.

14. The elementary cell according to claim 11, wherein at least one of said four branches is extended to accommodate design rule constraints while maintaining functionality.

15. A scalable quantum computing device comprising a plurality of elementary cells of claim 11 interconnected via state transport dots to form a linear, branched, V-shaped, or two-dimensional array.

16. The scalable quantum computing device according to claim 15, wherein an interconnection pattern provides each interaction island with connectivity to up to four storage branches, thereby creating an extended qubit interaction graph.

17. The scalable quantum computing device according to claim 15, configured as a honeycomb like lattice of interconnected elementary cells.

18. A quantum state transfer device, comprising: a heterostructure constructed from a two-dimensional electron gas by application of voltage to one or more accumulation electrodes; a plurality of screening gates configured to electrostatically define quantum dot arrays within said two-dimensional electron gas; one or more accumulation gates configured to load charge carriers into said device; a plurality of barrier gates and plunger gates configured to define and control individual quantum dots and interdot tunneling; one or more single electron transistors or single electron boxes serving as charge sensors positioned proximate to ancilla dots; at least one Y-shaped or multi -branch elementary unit comprising an interaction island and multiple branches containing storage dots, ancilla dots, and state transport dots; and12485.0116 wherein said device is configured to shuttle spin qubit states along the branches to the interaction island for multi-qubit operations and back to storage dots for storage.

19. The device according to claim 18, comprising a plurality of Y-shaped elementary units interconnected either via state transport dots in a linear or branched chain or via interaction islands to form a honeycomb lattice.

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