Solar cell and preparation method therefor
By forming doped structures and passivation antireflection layers in solar cells, the optical loss problem caused by parasitic absorption in polycrystalline silicon materials is solved, thereby improving photoelectric conversion efficiency and cell performance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- POPSOLAR TECHNOLOGY (JIANGMEN) CO LTD
- Filing Date
- 2025-01-16
- Publication Date
- 2026-06-18
AI Technical Summary
In tunnel oxide passivated back contact solar cells, optical losses are caused by parasitic absorption of polycrystalline silicon materials, which affects photoelectric conversion efficiency.
A doped structure is formed on a semiconductor substrate, including a tunneling layer, an intrinsic layer, first and second doped structures, and an isolation structure. A passivation and antireflection material layer is formed on its surface. The passivation and antireflection layer and conductive parts are formed by annealing to ensure selective carrier transport and passivated contacts of the doped polycrystalline silicon.
It improves the photoelectric conversion efficiency of solar cells, reduces optical losses, enhances passivation and electrical contact, and improves cell performance.
Smart Images
Figure CN2025072742_18062026_PF_FP_ABST
Abstract
Description
A solar cell and its preparation method
[0001] Cross-references to related applications
[0002] This disclosure claims priority to Chinese Patent Application No. 2024118097861, filed on December 9, 2024, entitled “A Solar Cell and a Method for Preparing the Same”, the entire contents of which are incorporated herein by reference. Technical Field
[0003] This disclosure relates to the field of solar cell technology, and in particular to a solar cell and a method for its fabrication. Background Technology
[0004] In tunneling oxide passivated back contact solar cells, the selective carrier transport of the tunneling oxide and intrinsic polycrystalline silicon passivation layer and the doped polycrystalline silicon passivation contact are of great significance for realizing high-efficiency solar cells.
[0005] However, due to the parasitic absorption of polycrystalline silicon materials, tunnel oxide passivated back contact solar cells suffer from significant optical losses, which in turn affect the photoelectric conversion efficiency of the solar cells. Summary of the Invention
[0006] According to various embodiments of this disclosure, a solar cell and a method for preparing the same are provided.
[0007] According to various embodiments of this disclosure, a method for preparing a solar cell is provided, comprising the following steps:
[0008] Provide a semiconductor substrate;
[0009] A doped structure is formed on the lower surface of the semiconductor substrate. The doped structure includes a tunneling layer, an intrinsic layer, and a first doped structure, a second doped structure, and an isolation structure located in the intrinsic layer. The isolation structure isolates the first doped structure from the second doped structure, and the first doped structure and the second doped structure have opposite conductivity types.
[0010] Passivation and antireflection material layers are formed on the upper surface of the semiconductor substrate and the lower surface of the doped structure, respectively;
[0011] The passivation antireflection material layer located on the lower surface of the first doped structure and the second doped structure is removed to form a passivation antireflection layer, the passivation antireflection layer including a first passivation antireflection layer located on the lower surface of the isolation structure and a second passivation antireflection layer located on the upper surface of the semiconductor substrate;
[0012] A first conductive portion is formed that at least covers the lower surface of the first doped structure, and a second conductive portion is formed that at least covers the lower surface of the second doped structure, wherein the end of the first conductive portion near the isolation structure and the end of the second conductive portion near the isolation structure are spaced apart.
[0013] In some embodiments,
[0014] Forming the doped structure on the lower surface of the semiconductor substrate includes the following steps:
[0015] The tunneling layer and the intrinsic layer are formed sequentially on the lower surface of the semiconductor substrate;
[0016] A first doped initial structure and a second doped initial structure are formed on the lower surface of the intrinsic layer, wherein the first doped initial structure and the second doped initial structure are spaced apart and have opposite conductivity types.
[0017] The intrinsic layer after the first doped initial structure and the second doped initial structure are formed on the lower surface is annealed. After annealing, the first doped initial structure forms the first doped structure in the intrinsic layer, and the first doped initial structure forms the second doped structure in the intrinsic layer. The undoped intrinsic layer between the first doped structure and the second doped structure serves as the isolation structure.
[0018] In some embodiments,
[0019] Before forming the passivation and antireflection material layer on the upper surface of the semiconductor substrate, the method further includes:
[0020] A textured surface structure is formed on the upper surface of the semiconductor substrate.
[0021] In some embodiments,
[0022] Forming the textured structure on the upper surface of the semiconductor substrate includes the following steps:
[0023] A protective layer is formed on the lower surface of the doped structure;
[0024] The upper surface of the semiconductor substrate is wet-etched to form the textured structure;
[0025] Remove the protective layer.
[0026] In some embodiments,
[0027] After forming the passivation and antireflection material layer on the upper surface of the semiconductor substrate and the lower surface of the doped structure, and before removing the passivation and antireflection material layer located on the lower surfaces of the first doped structure and the second doped structure, the method further includes:
[0028] The passivated antireflective material layer is annealed.
[0029] In some embodiments, the passivation antireflection material layer comprises a first passivation material and a second passivation material stacked sequentially.
[0030] In some embodiments, the first passivation material includes Al x O y The second passivation material includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.
[0031] In some embodiments, the method for removing the passivation and antireflection material layer located on the lower surface of the first doped structure and the second doped structure includes laser etching.
[0032] In some embodiments, the first conductive portion and the second conductive portion extend to the lower surface of the first passivation antireflection layer.
[0033] In some embodiments, the first conductive portion or the second conductive portion extends to the lower surface of the first passivation antireflection layer.
[0034] In some embodiments,
[0035] Forming a first conductive portion that at least covers the lower surface of the first doped structure, and forming a second conductive portion that at least covers the lower surface of the second doped structure, includes the following steps:
[0036] A conductive material layer is formed covering the exposed surfaces of the first doped structure, the second doped structure, and the first passivation antireflection layer;
[0037] An isolation trench is formed in the conductive material layer, the isolation trench penetrating the conductive material layer and the opening width of the isolation trench not greater than the width of the isolation structure, so as to form a first conductive portion that at least covers the lower surface of the first doped structure and a second conductive portion that at least covers the lower surface of the second doped structure.
[0038] In some embodiments, the conductive material layer comprises a transparent conductive oxide.
[0039] In some embodiments, the method of forming the isolation trench includes laser etching.
[0040] In some embodiments,
[0041] Before forming the doped structure on the lower surface of the semiconductor substrate, the method further includes:
[0042] The semiconductor substrate is then cleaned.
[0043] In some embodiments,
[0044] The semiconductor substrate is cleaned, including the following steps:
[0045] The surface of the semiconductor substrate is pre-polished;
[0046] The surface of the semiconductor substrate after pre-polishing is pre-cleaned;
[0047] The surface of the semiconductor substrate after pre-cleaning is subjected to hydrophobic treatment;
[0048] The surface of the semiconductor substrate after hydrophobic treatment is dried.
[0049] In some embodiments,
[0050] After forming the first conductive portion that at least covers the lower surface of the first doped structure, and after forming the second conductive portion that at least covers the lower surface of the second doped structure, the method further includes:
[0051] A first lead-out electrode is formed on the lower surface of the first conductive portion, and a second lead-out electrode is formed on the lower surface of the second conductive portion.
[0052] According to various embodiments of this disclosure, a solar cell is also provided, which is prepared by the solar cell preparation method described in any of the above embodiments.
[0053] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description
[0054] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0055] Figure 1 is a flowchart of a method for fabricating a solar cell provided in one embodiment;
[0056] Figure 2 is a schematic cross-sectional view of the structure after the formation of the tunneling layer and the intrinsic layer in the fabrication method of the solar cell provided in one embodiment;
[0057] Figure 3 is a schematic cross-sectional view of the first doped initial structure and the second doped initial structure formed in the fabrication method of a solar cell provided in one embodiment;
[0058] Figure 4 is a schematic cross-sectional view of the solar cell fabrication method provided in one embodiment after forming the first doped structure, the second doped structure and the isolation structure;
[0059] Figure 5 is a schematic cross-sectional view of the semiconductor structure after the protective layer is formed in a method for fabricating a semiconductor structure provided in one embodiment;
[0060] Figure 6 is a schematic cross-sectional view of the solar cell fabrication method provided in one embodiment after the formation of the textured surface structure;
[0061] Figure 7 is a schematic cross-sectional view of the structure after the passivation antireflection material layer is formed in the fabrication method of the solar cell provided in one embodiment;
[0062] Figure 8 is a schematic cross-sectional view of the structure after the passivation antireflection layer is formed in the fabrication method of the solar cell provided in one embodiment;
[0063] Figure 9 is a schematic cross-sectional view of the structure after the conductive material layer is formed in the method for fabricating a solar cell provided in one embodiment;
[0064] Figure 10 is a schematic cross-sectional view of the structure after the formation of the first conductive part and the second conductive part in a method for fabricating a solar cell provided in one embodiment.
[0065] Figure 11 is a schematic cross-sectional view of the structure after the first lead-out electrode and the second lead-out electrode are formed in a method for fabricating a solar cell provided in one embodiment.
[0066] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood. Detailed Implementation
[0067] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0069] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.
[0070] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0071] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0072] The related structures of the embodiments of this disclosure should not be limited to the specific shapes of the structures shown in the accompanying drawings, but should include shape deviations due to, for example, manufacturing techniques.
[0073] In one embodiment, referring to Figure 1, a method for fabricating a solar cell is provided, comprising the following steps:
[0074] S1: Provide a semiconductor substrate 1;
[0075] S2: A doped structure 2 is formed on the lower surface of the semiconductor substrate 1. The doped structure 2 includes a tunneling layer 21, an intrinsic layer 22, and a first doped structure 23, a second doped structure 24, and an isolation structure 25 located in the intrinsic layer 22. The isolation structure 25 isolates the first doped structure 23 and the second doped structure 24, and the first doped structure 23 and the second doped structure 24 have opposite conductivity types.
[0076] S3: Passivation and antireflection material layers 31 are formed on the upper surface of semiconductor substrate 1 and the lower surface of doped structure 2, respectively;
[0077] S4: Remove the passivation and antireflection material layer 31 located on the lower surface of the first doped structure 21 and the second doped structure 22 to form a passivation and antireflection layer 3. The passivation and antireflection layer 3 includes a first passivation and antireflection layer 32 located on the lower surface of the isolation structure 25 and a second passivation and antireflection layer 33 located on the upper surface of the semiconductor substrate 1.
[0078] S5: A first conductive portion 4 is formed that at least covers the lower surface of the first doped structure 23, and a second conductive portion 5 is formed that at least covers the lower surface of the second doped structure 24. The first conductive portion 4 is spaced apart from the end of the isolation structure 25 near the first conductive portion 4 and the end of the second conductive portion 5 near the second conductive structure 25.
[0079] Step S1 is performed, providing a semiconductor substrate 1. The semiconductor substrate 1 may be made of monocrystalline silicon, polycrystalline silicon, compound semiconductors (e.g., gallium nitride, gallium arsenide, etc.), but may also include one or more other semiconductor materials. In this embodiment, the semiconductor substrate 1 is made of monocrystalline silicon, and the semiconductor substrate 1 is also doped with N-type or P-type doping elements.
[0080] In some embodiments, before forming the doped structure 2 on the lower surface of the semiconductor substrate 1, step S1 further includes a step S11 of cleaning the semiconductor substrate 1, wherein cleaning the semiconductor substrate 1 includes the following steps S111 to S114:
[0081] S111: Pre-polishing treatment is performed on the surface of semiconductor substrate 1; the pre-polishing treatment of semiconductor substrate 1 involves cleaning and pre-polishing the mechanically cut damage layer, metal ions, dirt and impurities of substrate 1 with chemical reagents to modify semiconductor substrate 1 into a relatively smooth interface; wherein, the reagents used for pre-polishing treatment of semiconductor substrate 1 include at least one of NH4OH, NaOH, KOH, H2O or other suitable reagents, the pre-polishing temperature range is 65℃~80℃, and the pre-polishing treatment time range is 180s~300s.
[0082] S112: Pre-cleaning the surface of the pre-polished semiconductor substrate 1 effectively removes impurities from the surface of the pre-polished semiconductor substrate 1. The reagents used for pre-cleaning the surface of the pre-polished semiconductor substrate 1 include one of NaOH, KOH, H2O2, and H2O, or other suitable reagents. When using NaOH for pre-cleaning, the concentration range of NaOH is 45wt% to 55wt%, the concentration range of KOH is 45wt% to 55wt%, the concentration range of H2O2 is 25wt% to 35wt%, the pre-cleaning temperature range is approximately 55℃ to 65℃, and the pre-cleaning time range is 120s to 180s.
[0083] S113: Performing hydrophobic treatment on the surface of the pre-cleaned semiconductor substrate 1 can ensure the cleanliness of the semiconductor substrate 1 surface and improve the anti-contamination ability of the semiconductor substrate 1 surface. The reagents used for hydrophobic treatment of the semiconductor substrate 1 surface include at least one of HF, HCl, and H2O. When using HF for hydrophobic treatment, the concentration range of HF is 45wt% to 55wt%. When using HCl for hydrophobic treatment, the concentration range of HCl is 30wt% to 40wt%. The hydrophobic treatment is carried out at room temperature, and the hydrophobic treatment time range is 120s to 360s.
[0084] S114: The surface of the hydrophobic treated semiconductor substrate 1 is dried to fully remove moisture impurities from the surface of the semiconductor substrate 1, which is beneficial to the subsequent processes. The drying process of the semiconductor substrate 1 is carried out in an inert gas atmosphere, including nitrogen or other suitable inert gases, and the drying time ranges from 480s to 800s.
[0085] Please refer to Figures 2 to 4. Step S2 is performed to form a doped structure 2 on the lower surface of the semiconductor substrate 1. The doped structure 2 includes a tunneling layer 21, an intrinsic layer 22, and a first doped structure 23, a second doped structure 24, and an isolation structure 25 located in the intrinsic layer 22. The isolation structure 25 isolates the first doped structure 23 and the second doped structure 24, and the first doped structure 23 and the second doped structure 24 have opposite conductivity types.
[0086] In some embodiments, step S2 further includes steps S21 to S23 of forming the doped structure 2, including:
[0087] S21: A tunneling layer 21 and an intrinsic layer 22 are sequentially stacked on the lower surface of the semiconductor substrate 1; the tunneling layer 21 and the intrinsic layer 22 are used to achieve efficient passivation of the back side and selective collection of charge carriers, wherein the material of the tunneling layer 21 includes SiO xThe method for forming the tunneling layer 21 includes thermal oxidation, nitric acid oxidation, ozone oxidation, or other suitable methods, and the thickness of the tunneling layer 21 ranges from 1 nm to 3 nm; the intrinsic layer 22 is made of amorphous silicon or other suitable materials, and the intrinsic layer 22 made of amorphous silicon is formed by the decomposition of silane. The method for forming the intrinsic layer 22 includes low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable methods, and the thickness of the intrinsic layer 22 ranges from 40 nm to 80 nm.
[0088] S22: A first doped initial structure 26 and a second doped initial structure 27 are formed on the lower surface of the intrinsic layer 22, respectively. The first doped initial structure 26 and the second doped initial structure 27 are spaced apart and have opposite conductivity types. The first doped initial structure 26 includes boron, and the second doped initial structure 27 includes phosphorus. The first doped initial structure 26 is formed by brushing a slurry. When the first doped initial structure 26 is formed by brushing a slurry, the solid content of the first doped initial structure 26 is in the range of 20% to 55%, and the viscosity is in the range of 2. The method for forming the second doped initial structure 27 by brushing a slurry at a pressure of 0 Pa to 50 Pa is as follows: when forming the second doped initial structure 27 by brushing the slurry, the solid content of the second doped initial structure 27 is in the range of 15% to 35%, the viscosity is in the range of 20 Pa to 50 Pa, the width of the first doped initial structure 26 is in the range of 600 nm to 800 nm, the width of the second doped initial structure 27 is in the range of 400 nm to 600 nm, and the ratio of the width of the first doped initial structure 26 to the width of the second doped initial structure 27 is in the range of 3:2 to 4:3.
[0089] S23: The intrinsic layer 22 after the formation of the first doped initial structure 26 and the second doped initial structure 27 on the lower surface is annealed. After annealing, the first doped initial structure 26 forms the first doped structure 23 in the intrinsic layer 27, and the second doped initial structure 27 forms the second doped structure 24 in the intrinsic layer 22. The undoped region of the intrinsic layer 22 between the first doped structure 23 and the second doped structure 24 serves as the isolation structure 25. Annealing the intrinsic layer 22 after the formation of the first doped initial structure 26 and the second doped initial structure 27 on the lower surface realizes the transformation of the intrinsic layer 25 into a doped structure. The presence of the tunneling layer 21 and the low surface concentration ensure the activity of the interface, providing a large space for passivation of the existing thin intrinsic layer 22. During this process, a portion of the intrinsic layer 22 without any element doping is retained as the isolation structure 25 to prevent the formation of a back "leakage current" channel. Furthermore, the first doped structure 23, the second doped structure 24, and the isolation structure 25 are directly formed through annealing, greatly simplifying the process flow. The annealing process is performed under a nitrogen or oxygen atmosphere, with a temperature range of 850℃ to 1050℃ and a time range of 10 min to 30 min. For example, the width of the first doped structure 23 is greater than the width of the second doped structure 24. The width of the first doped structure 23 may also be less than or equal to the width of the second doped structure 24, depending on the specific circumstances.
[0090] Please refer to Figures 5 to 7. Perform step S3 to form passivation and antireflection material layers 31 on the upper surface of semiconductor substrate 1 and the lower surface of doped structure 2, respectively.
[0091] In some embodiments, step S3 further includes step S31, that is, before forming the passivation antireflection material layer 31 on the upper surface of the semiconductor substrate 1, the step further includes forming a textured structure 11 on the upper surface of the semiconductor substrate 1. The textured structure 11 is a tiny pyramid-shaped structure or other microstructure formed on the upper surface of the semiconductor substrate 1, which increases the surface area above the semiconductor substrate 1, thereby improving the absorption of sunlight.
[0092] In some embodiments, forming a textured structure 11 on the upper surface of the semiconductor substrate 1 includes the following steps S311 to S313:
[0093] S311: A protective layer 6 is formed on the lower surface of the doped structure 2; the protective layer 6 is used to protect the lower surface of the doped structure 2 when the textured structure 11 is formed on the upper surface of the semiconductor substrate 1. The material of the protective layer 6 includes at least one of silicon oxide, silicon oxynitride, and borosilicate glass, or other suitable materials. The method for forming the protective layer 6 includes low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, catalytic chemical vapor deposition, atomic layer deposition, or other suitable methods. The thickness of the formed protective layer 6 ranges from 2 nm to 50 nm.
[0094] S312: Wet etching is performed on the upper surface of the semiconductor substrate 1 to form a textured structure 11. The reagent used for wet etching of the upper surface of the semiconductor substrate 1 includes at least one of NaOH, KOH, and H2O. For example, when the reagent used is a mixed solution of NaOH or KOH and H2O, the volume ratio of NaOH or KOH to H2O is 1:15, the processing temperature ranges from 75°C to 83°C, and the processing time ranges from 360s to 420s. In addition, the reflectivity of the upper surface of the semiconductor substrate 1 after forming the textured structure 11 ranges from 8% to 11%.
[0095] S313: Removing the protective layer 6 ensures the smooth progress of subsequent processes. The actual reagent used to remove the protective layer 6 includes at least one of HF and H2O. For example, when the reagent used is a mixed solution of HF and H2O, the volume ratio of HF to H2O is 1:20, and the time range for removing the protective layer 6 is 100s to 400s.
[0096] In some embodiments, the passivation antireflection material layer 31 includes a first passivation material and a second passivation material stacked sequentially, wherein the first passivation material includes Al. x O y The second passivation material includes at least one of silicon nitride, silicon oxide, and silicon oxynitride. Al is used. x O y As the primary passivation material, Al x O y The negative charge effect ensures efficient passivation, better saturating dangling bonds on the silicon surface. The second passivation material effectively protects the first passivation material and achieves efficient defect center repair through chemical passivation. For example, the first passivation material is Al. x O yThe first passivation material is formed based on the reaction of trimethylaluminum and H2O or trimethylaluminum and O3. The thickness of the first passivation material ranges from 3 nm to 10 nm. The method for forming the first passivation material includes plasma-enhanced atomic layer deposition, atomic layer deposition, physical vapor deposition, or other suitable methods. The thickness of the second passivation material ranges from 70 nm to 110 nm, and the refractive index of the second passivation material ranges from 2.0% to 2.4%.
[0097] Step S3 further includes step S32, which, after forming the passivation antireflection material layer 31 on the upper surface of the semiconductor substrate 1 and the lower surface of the doped structure 2, and before removing the passivation antireflection material layer 31 located on the lower surfaces of the first doped structure 23 and the second doped structure 24, includes annealing the passivation antireflection material layer 31. The annealing of the passivation antireflection material layer 31 is performed at a medium-high temperature, and the annealing of the passivation antireflection material layer 31 allows free hydrogen in the passivation antireflection material layer 31 to diffuse into the interior of the first doped structure 23, the second doped structure 24, and the tunneling layer 21, repairing defect centers, neutralizing dangling bonds, and ultimately improving the quality of the first doped structure 23, the second doped structure 24, and the tunneling layer 21.
[0098] Please refer to Figure 8. Perform step S4 to remove the passivation and antireflection material layer 31 located on the lower surface of the first doped structure 23 and the second doped structure 24 to form a passivation and antireflection layer 3. The passivation and antireflection layer 3 includes a first passivation and antireflection layer 32 located on the lower surface of the isolation structure 25 and a second passivation and antireflection layer 33 located on the upper surface of the semiconductor substrate 1.
[0099] In some embodiments, the width of the first passivation antireflection layer 32 is smaller than the difference between the width of the first doped structure 23 and the width of the second doped structure 24. That is, the second passivation antireflection layer 32 is formed on the upper surface of the isolation structure 25, ensuring good interface passivation and isolation between the first doped structure 23 and the second doped structure 24, while also achieving good electrical contact. By forming the second passivation antireflection layer 33 on the upper surface of the textured structure 11, light absorption can be improved and carrier recombination losses on the front side can be reduced, increasing the open-circuit voltage and short-circuit current of the battery, thereby achieving higher conversion efficiency.
[0100] In some embodiments, the method for removing the passivation and antireflection material layer 31 located on the lower surface of the first doped structure 23 and the second doped structure 24 includes laser etching or other suitable methods. Removing the passivation and antireflection material layer 31 located on the lower surface of the first doped structure 23 and the second doped structure 24 by laser etching achieves high-precision and high-efficiency processing, reduces errors and losses in the production process, avoids affecting the first doped structure 23 and the second doped structure 24, and improves the yield of solar cells. When using laser etching to remove the passivation and antireflection material layer 31 located on the lower surface of the first doped structure 23 and the second doped structure 24, the laser wavelength used is 355nm and the power range is 50W to 120W.
[0101] Please refer to Figures 9 and 10. Step S5 is performed to form a first conductive portion 4 that at least covers the lower surface of the first doped structure 23, and a second conductive portion 5 that at least covers the lower surface of the second doped structure 24. The end of the first conductive portion 4 near the isolation structure 25 and the end of the second conductive portion 5 near the isolation structure 25 are spaced apart.
[0102] In some embodiments, step S5 further includes S51 to S52, namely, forming a first conductive portion 4 that at least covers the lower surface of the first doped structure 23, and forming a second conductive portion 5 that at least covers the lower surface of the second doped structure 24, including the following steps:
[0103] S51: Form a conductive material layer 7 covering the exposed surfaces of the first doped structure 23, the second doped structure 24, and the first passivation antireflection layer 32;
[0104] S52: An isolation trench 8 is formed in the conductive material layer 7. The isolation trench 8 penetrates the conductive material layer 7 and the opening width of the isolation trench 8 is not greater than the width of the isolation structure 25, so as to form a first conductive portion 4 that at least covers the lower surface of the first doped structure 23 and a second conductive portion 5 that at least covers the lower surface of the second doped structure 24. By forming the first conductive portion 4 covering the lower surface of the first doped structure 23 and the second conductive portion 5 covering the lower surface of the second doped structure 24, the first conductive portion 4 and the second conductive portion 5 have good conductivity, which can achieve high transmittance, low resistivity and efficient carrier collection, thereby improving the performance of the solar cell. Moreover, the first conductive portion 4 covers the lower surface of the first doped structure 23 and the second conductive portion 5 covers the lower surface of the second doped structure 24, that is, the first conductive portion 4 and the second conductive portion 5 do not contact each other, which ensures the conduction of lateral current while achieving isolation between the first doped structure 23 and the second doped structure 24. The method for forming the conductive material layer 7 includes magnetron sputtering or other suitable methods, and when forming the conductive material layer 7 by magnetron sputtering, the working atmosphere gas used includes argon, the working pressure range is 0.2 Pa to 10 Pa, and the power density range is 60 W to 500 W.
[0105] In some embodiments, the method for forming the isolation trench 8 includes laser etching or other suitable methods; the isolation trench 8 is formed in the conductive material layer 7, and the opening width of the isolation trench 8 is not greater than the width of the isolation structure 25, thus avoiding the exposure of the first doped structure 23 and the second doped structure 24 while realizing the lateral current conduction of the solar cell. For example, the opening width of the isolation trench 8 is 60μm to 300μm. Laser etching technology can achieve high-precision and high-efficiency processing, reduce errors and losses in the production process, avoid affecting the isolation structure 25 and the first passivation antireflection layer 32, and improve the yield of the solar cell. When forming the isolation trench 8 using laser etching, the laser wavelength includes 355nm and 532nm, which can be selected according to the actual situation, and the laser power range is 40W to 80W.
[0106] In some embodiments, the conductive material layer 7 comprises a transparent conductive oxide. Using a transparent conductive oxide as the conductive material layer 7 to fabricate the first conductive portion 4 and the second conductive portion 5 enables the achievement of high light transmittance and electrical conductivity, thereby significantly improving the photoelectric conversion efficiency of the battery.
[0107] In some embodiments, the first conductive portion 4 and the second conductive portion 5 extend to the lower surface of the first passivation antireflection layer 32.
[0108] In other embodiments, the first conductive portion 4 or the second conductive portion 5 extends to the lower surface of the first passivation antireflection layer 32. That is, the first conductive portion 4 and the second conductive portion 5, or the first conductive portion 4 or the second conductive portion 5, also cover a portion of the lower surface of the first passivation antireflection layer 32, and the first conductive portion 4 and the second conductive portion 5 do not contact each other, which ensures lateral current conduction while improving the isolation effect of the first doped structure 23 and the second doped structure 24.
[0109] Referring to Figure 11, in some embodiments, the method for fabricating a solar cell further includes step S6, which involves forming a first conductive portion 4 covering the lower surface of the first doped structure 23 and a second conductive portion 5 covering the lower surface of the second doped structure 24. Following this step, a first lead-out electrode 9 is formed on the lower surface of the first conductive portion 4, and a second lead-out electrode 10 is formed on the lower surface of the second conductive portion 5. The first lead-out electrode 9 and the second lead-out electrode 10 serve as the positive electrode and negative electrode, respectively, for conducting current.
[0110] The formation of the first lead-out electrode 9 and the second lead-out electrode 10 includes the following steps S61 to S62:
[0111] S61: A first electrode material (not shown) is formed on the lower surface of the first conductive part 4, and a second electrode material (not shown) is formed on the lower surface of the second conductive part 5; wherein, the method of forming the first electrode material includes slurry brushing, and the material of the first electrode material includes silver, aluminum, copper or other suitable conductive materials; the method of forming the second electrode material includes slurry brushing, and the material of the second electrode material includes silver, aluminum, copper or other suitable conductive materials.
[0112] S62: The first electrode material and the second electrode material are cured to form the first lead-out electrode 9 and the second lead-out electrode 10. The method used to cure the first electrode material and the second electrode material includes sintering, and when the first electrode material and the second electrode material are cured by sintering, the sintering temperature range is 150℃~1000℃, and the processing time is about 60s~600s.
[0113] It should be understood that although the steps in the flowchart of Figure 1 are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in Figure 1 may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.
[0114] Please refer to Figure 11. A solar cell is also provided, and the solar cell is prepared using the solar cell preparation method described above. It includes: a semiconductor substrate 1, a doped structure 2, a passivation and antireflection layer 3, a first conductive portion 4, and a second conductive portion 5. The doped structure 2 is located on the lower surface of the semiconductor substrate 1. The doped structure 2 includes a tunneling layer 21, an intrinsic layer 22, and a first doped structure 23, a second doped structure 24, and an isolation structure 25 separating the first doped structure 23 and the second doped structure 24, which are stacked sequentially. The first doped structure 23 and the second doped structure 24 have opposite conductivity types. The passivation and antireflection layer 3 includes a first passivation and antireflection layer 32 located on the lower surface of the isolation structure 25 and a second passivation and antireflection layer 33 located on the upper surface of the semiconductor substrate 1. The first conductive portion 4 at least covers the lower surface of the first doped structure 23, and the second conductive portion 5 at least covers the lower surface of the second doped structure 24. The end of the first conductive portion 4 near the isolation structure 25 and the end of the second conductive portion 5 near the isolation structure 25 are spaced apart.
[0115] In some embodiments, the upper surface of the semiconductor substrate 1 is further provided with a textured structure 11, and the second passivation antireflection layer 33 covers the upper surface of the textured structure 11.
[0116] In some embodiments, the first conductive portion 4 and the second conductive portion 5 extend to the lower surface of the first passivation antireflection layer 32.
[0117] In other embodiments, the first conductive portion 4 or the second conductive portion 5 extends to the lower surface of the first passivation antireflection layer 32. That is, the first conductive portion 4 and the second conductive portion 5, or the first conductive portion 4 or the second conductive portion 5, also cover a portion of the lower surface of the first passivation antireflection layer 32.
[0118] In some embodiments, the solar cell further includes a first lead-out electrode 9 and a second lead-out electrode 10, wherein the first lead-out electrode 9 is located on the lower surface of the first conductive portion 4, and the second lead-out electrode 10 is located on the lower surface of the second conductive portion 5.
[0119] In the description of this specification, references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0120] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0121] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for preparing a solar cell, comprising the following steps: Provide a semiconductor substrate; A doped structure is formed on the lower surface of the semiconductor substrate. The doped structure includes a tunneling layer, an intrinsic layer, and a first doped structure, a second doped structure, and an isolation structure located in the intrinsic layer. The isolation structure isolates the first doped structure from the second doped structure, and the first doped structure and the second doped structure have opposite conductivity types. Passivation and antireflection material layers are formed on the upper surface of the semiconductor substrate and the lower surface of the doped structure, respectively; The passivation antireflection material layer located on the lower surface of the first doped structure and the second doped structure is removed to form a passivation antireflection layer, the passivation antireflection layer including a first passivation antireflection layer located on the lower surface of the isolation structure and a second passivation antireflection layer located on the upper surface of the semiconductor substrate; A first conductive portion is formed that at least covers the lower surface of the first doped structure, and a second conductive portion is formed that at least covers the lower surface of the second doped structure, wherein the end of the first conductive portion near the isolation structure and the end of the second conductive portion near the isolation structure are spaced apart.
2. The method for preparing a solar cell according to claim 1, wherein, Forming the doped structure on the lower surface of the semiconductor substrate includes the following steps: The tunneling layer and the intrinsic layer are formed sequentially on the lower surface of the semiconductor substrate; A first doped initial structure and a second doped initial structure are formed on the lower surface of the intrinsic layer, wherein the first doped initial structure and the second doped initial structure are spaced apart and have opposite conductivity types. The intrinsic layer after the first doped initial structure and the second doped initial structure are formed on the lower surface is annealed. After annealing, the first doped initial structure forms the first doped structure in the intrinsic layer, and the first doped initial structure forms the second doped structure in the intrinsic layer. The undoped intrinsic layer between the first doped structure and the second doped structure serves as the isolation structure.
3. The method for preparing a solar cell according to claim 1, wherein, Before forming the passivation and antireflection material layer on the upper surface of the semiconductor substrate, the method further includes: A textured surface structure is formed on the upper surface of the semiconductor substrate.
4. The method for preparing a solar cell according to claim 3, wherein, Forming the textured structure on the upper surface of the semiconductor substrate includes the following steps: A protective layer is formed on the lower surface of the doped structure; The upper surface of the semiconductor substrate is wet-etched to form the textured structure; Remove the protective layer.
5. The method for preparing a solar cell according to claim 1, wherein, After forming the passivation and antireflection material layer on the upper surface of the semiconductor substrate and the lower surface of the doped structure, and before removing the passivation and antireflection material layer located on the lower surfaces of the first doped structure and the second doped structure, the method further includes: The passivated antireflective material layer is annealed.
6. The method for preparing a solar cell according to claim 1, wherein, The passivation and antireflection material layer comprises a first passivation material and a second passivation material stacked sequentially.
7. The method for preparing a solar cell according to claim 6, wherein, The first passivation material includes Al x O y The second passivation material includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.
8. The method for preparing a solar cell according to claim 1, wherein, The method for removing the passivation and antireflection material layer located on the lower surface of the first doped structure and the second doped structure includes laser etching.
9. The method for preparing a solar cell according to claim 1, wherein, The first conductive portion and the second conductive portion extend to the lower surface of the first passivation antireflection layer.
10. The method for preparing a solar cell according to claim 1, wherein, The first conductive portion or the second conductive portion extends to the lower surface of the first passivation antireflection layer.
11. The method for preparing a solar cell according to claim 1, wherein, Forming a first conductive portion that at least covers the lower surface of the first doped structure, and forming a second conductive portion that at least covers the lower surface of the second doped structure, includes the following steps: A conductive material layer is formed covering the exposed surfaces of the first doped structure, the second doped structure, and the first passivation antireflection layer; An isolation trench is formed in the conductive material layer, the isolation trench penetrating the conductive material layer and the opening width of the isolation trench not greater than the width of the isolation structure, so as to form a first conductive portion that at least covers the lower surface of the first doped structure and a second conductive portion that at least covers the lower surface of the second doped structure.
12. The method for preparing a solar cell according to claim 11, wherein, The conductive material layer comprises a transparent conductive oxide.
13. The method for preparing a solar cell according to claim 11, wherein, The method for forming the isolation trench includes laser etching.
14. The method for preparing a solar cell according to claim 1, wherein, Before forming the doped structure on the lower surface of the semiconductor substrate, the method further includes: The semiconductor substrate is then cleaned.
15. The method for preparing a solar cell according to claim 14, wherein, The semiconductor substrate is cleaned, including the following steps: The surface of the semiconductor substrate is pre-polished; The surface of the semiconductor substrate after pre-polishing is pre-cleaned; The surface of the semiconductor substrate after pre-cleaning is subjected to hydrophobic treatment; The surface of the semiconductor substrate after hydrophobic treatment is dried.
16. The method for preparing a solar cell according to claim 1, wherein, After forming the first conductive portion that at least covers the lower surface of the first doped structure, and after forming the second conductive portion that at least covers the lower surface of the second doped structure, the method further includes: A first lead-out electrode is formed on the lower surface of the first conductive portion, and a second lead-out electrode is formed on the lower surface of the second conductive portion.
17. A solar cell, said solar cell being prepared by the method for preparing a solar cell as described in any one of claims 1 to 16.