Data processing methods, data processing apparatuses and data transmission system

Abstract

Provided in at least one embodiment of the present disclosure are data processing methods, data processing apparatuses and a data transmission system. A data processing method comprises: on the basis of original data, performing an encoding operation to generate N independent error correction codewords, wherein each of the N independent error correction codewords comprises a data code and a check code, and N is an integer and N≥2; performing interleaving on the data codes and check codes comprised in the N independent error correction codewords, in order to obtain interleaved data; and sending the interleaved data. The data processing method can effectively reduce the complexity of encoding and decoding and error correction, thereby shortening the corresponding time for encoding and decoding and error correction, and thus reducing the data transmission latency.

Description

Data processing methods, data processing devices, and data transmission systems

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411806114.5, filed on December 9, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a data processing method, a data processing apparatus, and a data transmission system. Background Technology

[0004] In modern communication systems, the reliability of data transmission is crucial to ensuring information integrity. However, channel noise and interference often lead to errors during data transmission. To address this issue, error correction coding techniques are widely used in data transmission. Summary of the Invention

[0005] At least one embodiment of this disclosure provides a data processing method, comprising: performing an encoding operation on raw data to generate N independent error correction codewords, each of the N independent error correction codewords including a data code and a check code, where N is an integer and N≥2; interleaving the data code and check code included in the N independent error correction codewords to obtain interleaved data; and sending the interleaved data.

[0006] At least one embodiment of this disclosure provides a data processing method, comprising: receiving interleaved data to obtain read-back data codes and read-back error correction codes, wherein the interleaved data is obtained by generating N independent error correction codewords based on encoding operations on the original data, and interleaving the data codes and check codes included in the N independent error correction codewords, each of the N independent error correction codewords including data codes and check codes, where N is an integer and N≥2; deinterleaving the read-back data codes and read-back error correction codes to obtain N independent read-back error correction codewords; and performing decoding and error correction operations on the N independent read-back error correction codewords.

[0007] At least one embodiment of this disclosure provides a data processing apparatus, comprising: an error correction codeword generation unit configured to generate N independent error correction codewords by performing an encoding operation based on original data, each of the N independent error correction codewords including a data code and a check code, wherein N is an integer and N≥2; an interleaving unit configured to interleave the data code and check code included in the N independent error correction codewords to obtain interleaved data; and a transmission unit configured to transmit the interleaved data to a data receiving end.

[0008] At least one embodiment of this disclosure provides a data processing apparatus, comprising: a receiving unit configured to receive interleaved data to obtain read-back data codes and read-back error correction codes, wherein the interleaved data is obtained by generating N independent error correction codewords based on encoding operations on the original data, and interleaving the data codes and check codes included in the N independent error correction codewords, each of the N independent error correction codewords including data codes and check codes, where N is an integer and N≥2; a deinterleaving unit configured to deinterleave the read-back data codes and read-back error correction codes to obtain N independent read-back error correction codewords; and a decoding and error correction unit configured to perform decoding and error correction operations on the N independent read-back error correction codewords.

[0009] At least one embodiment of this disclosure provides a data transmission system, including: any of the data processing apparatus described above.

[0010] At least one embodiment of this disclosure provides an electronic device, including: at least one processor; and at least one memory storing instructions thereon, wherein, when executed by the processor, the instructions cause the processor to perform the data processing method described above.

[0011] At least one embodiment of this disclosure provides a computer-readable storage medium storing computer-readable instructions thereon, wherein, when executed by a processor, the computer-readable instructions cause the processor to perform the data processing method described above. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments of this disclosure will be briefly described below. Clearly, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit the scope of this disclosure.

[0013] Figure 1 shows a schematic diagram of an exemplary end-to-end serial link system;

[0014] Figure 2 shows a flowchart of a data processing method according to at least one embodiment of the present disclosure;

[0015] Figure 3 shows a flowchart of a data processing method according to at least one embodiment of the present disclosure;

[0016] Figure 4 shows a schematic diagram of a data processing apparatus according to at least one embodiment of the present disclosure;

[0017] Figure 5 shows a schematic diagram of a data processing apparatus according to at least one embodiment of the present disclosure;

[0018] Figure 6 shows a schematic diagram of a data transmission system according to at least one embodiment of the present disclosure;

[0019] Figure 7 illustrates a schematic diagram of a decoding and error correction process according to at least one embodiment of the present disclosure;

[0020] Figure 8 shows a block diagram of an adjoint calculation according to at least one embodiment of the present disclosure;

[0021] Figure 9 shows a block diagram of key equations according to at least one embodiment of the present disclosure;

[0022] Figure 10 shows a schematic diagram of a money search circuit according to at least one embodiment of the present disclosure;

[0023] Figure 11 shows a schematic diagram of a four-way interleaving structure according to at least one embodiment of the present disclosure;

[0024] Figure 12 shows a schematic diagram of a four-way deinterleaving structure according to at least one embodiment of the present disclosure;

[0025] Figure 13 illustrates a four-way interleaved data structure diagram according to at least one embodiment of the present disclosure;

[0026] Figure 14 shows a schematic diagram of an electronic device according to at least one embodiment of the present disclosure;

[0027] Figure 15 illustrates a schematic diagram of a computer-readable storage medium according to at least one embodiment of the present disclosure; and

[0028] Figure 16 shows a schematic diagram of another electronic device according to at least one embodiment of the present disclosure. Detailed Implementation

[0029] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. Rather, it is intended to cover variations, modifications, and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0030] To enable those skilled in the art to better understand this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of this disclosure to the specific shapes, hardware, connections, operations, values, conditions, data, sequences, etc., shown and described. Those skilled in the art can utilize the concepts of this disclosure to construct further embodiments not mentioned herein by reading this specification.

[0032] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0033] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0034] First, the abbreviations and related terms involved in this application are defined and explained.

[0035] ECC (Error Correction Code): Error correction code or error correction coding refers to a coding technology that can realize error checking and correction, which can improve the reliability of the system.

[0036] CE (Correctable Error): Errors that can be corrected.

[0037] UE (Uncorrectable Error): An error that cannot be corrected.

[0038] Symbols, also known as code elements, are the smallest units used in ECC error correction. They are typically available in x4 and x8 increments, corresponding to 4 bits and 8 bits of data, respectively.

[0039] SERDES (Serializer / Deserializer): A digital communication interface technology used to convert parallel data into serial data and vice versa. It plays an important role in high-speed communication systems.

[0040] Forward error correction (FEC) is a method for detecting and correcting errors in data transmission. It uses redundant bits to store checksum information during data encoding. When an error occurs during data transmission, the checksum information can be used to determine the error location and correct it.

[0041] Link equalization: a technique used to eliminate distortion and noise in signal transmission.

[0042] Reed-Solomon (RS) coding algorithm: An error-correcting coding algorithm, it is a non-binary block code commonly used for error correction in data transmission and storage. Its basic principle is to encode the original data at the sending end, generating a certain amount of redundant data, which is then transmitted along with the original data. Upon receiving the data, the receiving end uses the redundant data for error decoding and correction. If a correctable error occurs, the receiving end can use the information in the redundant data to correct it without retransmitting the data.

[0043] Interleaving: Bit errors in communication often occur in bursts. Channel coding is only effective at detecting and correcting single errors and relatively short error strings. When the length of a burst error exceeds the error correction capability of FEC (Fluid Error Correction), FEC becomes ineffective in reducing the bit error rate and packet loss rate. Interleaving is a technique used to reduce the impact of burst errors on the system. It enhances data reliability by dividing the original data into four independent data streams and alternating these streams within a new data stream. This breaks long burst errors into several shorter burst errors, which are then corrected separately by several FECs, thereby improving system performance.

[0044] Bit Error Rate (BER): A metric used to evaluate the bit error rate in digital communication systems. It represents the proportion of bits received by the receiver during digital signal transmission that are erroneous.

[0045] Feed forward equalizer (FFE): It can be divided into pre-emphasis and de-emphasis. The two methods are similar, both changing the high and low frequency components at the transmit (TX) end. The difference is that pre-emphasis increases the high frequency components, while de-emphasis reduces the low frequency components. After equalization at the TX end, the signal quality can be improved.

[0046] Continuous-time linear equalizer (CTLE): An amplifier circuit with a frequency response curve that amplifies high-frequency signals and attenuates low-frequency signals to compensate for channel insertion loss.

[0047] Decision Feedback Equalizer (DFE): A digital signal processing technique used to recover digital signals affected by channel interference and distortion. In a circuit, the DFE is typically placed after the CTLE (Continuous Transmission Equalizer). The implementation of the DFE is similar to that of the FFE (Fluid Feedback Equalizer).

[0048] Packet loss rate: refers to the probability that the error exceeds the error correction capability of FEC, and the entire packet can only be lost. After the packet is lost, the receiving end will request a retransmission.

[0049] It is understood that the terms defined above are merely exemplary definitions in specific application scenarios to better understand this application, and the embodiments disclosed herein are not limited thereto.

[0050] As signal rates increase, signal quality deteriorates in two ways. Firstly, the shorter clock cycle exacerbates the effects of inherent jitter. Secondly, the increased rate leads to greater channel losses, resulting in more severe inter-symbol interference (ISI). Generally, this weakness can be mitigated through high-frequency signal compensation and equalization techniques.

[0051] The function of equalization is to process the signal at the receiving port. Based on the attenuation characteristics of the substrate through which the signal passes, the high-frequency components of the signal are appropriately enhanced. In this way, the low-frequency and high-frequency components are "equalized" to a certain level, which enhances the transmission speed and transmission distance of the signal sent to the receiving port.

[0052] Equalization can be divided into transmitter equalization and receiver equalization. Transmitter equalization is also called emphasis or FFE.

[0053] There are two types of equalization at the receiver: CTLE and DFE. DFE can assist CTLE in improving signal quality. In addition, DFE can adaptively adjust in real time according to the eye diagram. It can be used to compensate for changes in the link and chips (such as CTLE) caused by temperature or other conditions, thereby increasing the stability of the system.

[0054] Figure 1 shows a schematic diagram of an exemplary end-to-end serial link system.

[0055] Referring to Figure 1, at the data transmitting end, data can be encoded via an FEC encoder to generate encoded data. The encoded data can be converted from a digital signal to an analog signal via modulation (MOD). The analog signal can then have its high and low frequency components altered via FFE, and can subsequently be transmitted through a channel.

[0056] At the data receiving end, the received analog signal can be improved by CTLE and DFE, and then the analog signal can be converted back to a digital signal by demodulation (DeMOD) and the data signal can be decoded by FEC decoder to obtain the original data.

[0057] In practical applications, the eye diagram after CTLE and DFE equalization requires the coordinated use of FFE, CTLE, and DFE, especially under relatively complex link conditions. In such cases, FFE or CTLE and DFE alone are insufficient to open the eye diagram; a combination of FFE, CTLE, and DFE is necessary to ensure the eye diagram is fully open at the sampling points at the receiver, thereby achieving the target bit error rate.

[0058] An exemplary FEC algorithm used in high-speed protocol transmission is the RS(544, 514) algorithm, which can correct errors in any 15 10-bit symbols using 514 10-bit data symbols and 30 10-bit ECC symbols. This error correction process is extremely complex because determining the location of the 15 erroneous symbols requires iteratively solving 15 equations, thus requiring more area (e.g., the area of ​​the circuitry implementing the solution) and more delay, but it offers superior error correction capability.

[0059] Another FEC algorithm is the RS(272, 258) algorithm, which can correct errors in any 7 symbols out of 258 10-bit data symbols and 14 10-bit ECC symbols. Compared to the RS(544, 514) algorithm, the encoding and error correction involved in the RS(272, 258) algorithm are simpler. The error correction module only needs to solve a 7th-degree equation, thus requiring less computational resources. Due to its simplicity, the RS(272, 258) algorithm has a faster processing speed and is particularly suitable for processing small-scale data blocks, but its error correction capability is slightly weaker.

[0060] The market demand for high-speed information transmission is increasing, and the higher the data transmission rate, the greater the challenge to the signal integrity of serial links. To ensure the overall low cost of the link, the materials of the channel are usually not changed, but improvements and research are made to the link architecture. This poses a serious challenge to equalization technology and FEC in ultra-high-speed serial links.

[0061] The inventors of this disclosure recognized that traditional RS(544, 514) modulation has significant delays, but boasts advantages such as high bit rate and strong random error correction capabilities. However, it also places high demands on the modulation of link equalization. The link equalizer must ensure that the bit error rate (BER) is lower than the protocol's basic BER requirement; on the other hand, the equalization capability cannot be too strong, as excessive equalization capability can lead to increased retransmission rate and decreased bandwidth efficiency. This is because excessive equalization capability results in a stronger DFE coefficient, and as a non-linear equalizer, the DFE determines the current signal level based on past decisions. If the DFE coefficient is too large, meaning too much weight is given to past signals, it may lead to incorrect decisions about the current signal, which in turn can affect the next signal, potentially causing errors to propagate continuously. RS(544, 514), as a FEC specified in the Ethernet protocol, was designed from the outset to address random errors. If the errors are consecutive, then on the one hand, the upper limit of the error correction capability (i.e., 5 10-bit symbols) can easily be occupied by consecutive errors caused by a large number of DFE erroneous decisions; on the other hand, the complex algorithm of RS(544, 514) is useless because the error is highly likely to occur in the next coincidence, and therefore the ability to correct "arbitrary" (random) errors is not so necessary.

[0062] Furthermore, while RS(272, 258) doesn't handle environments with similarly poor BER well because its ability to correct random errors is weaker than RS(544, 514), the link can use stronger equalization capabilities to reduce the BER of the input FEC, thus reducing the number of random errors. However, the trade-off is a larger DFE coefficient; a single random error can lead to a DFE misjudgment, causing a series of consecutive errors caused by DFEs to follow. Nevertheless, this series of errors can be well handled by the interleaving structure of RS(272, 258), making it more suitable for high-speed links.

[0063] Furthermore, when determining the equalization capability of a link modulation, the FEC module at the end of the link is rarely considered. FEC is typically enabled only after the FFE coefficients at the TX end are determined, leading to a decrease in system performance (i.e., determining the FFE coefficients solely based on the eye diagram). This is because, for the entire system, a larger eye diagram is not always better; there exists an optimal point. If the link's equalization capability exceeds this optimal point, the retransmission rate increases, and system performance degrades. Therefore, link training must consider the overall FEC capability. To achieve the optimal performance of RS(544, 514), it is necessary to reduce the FFE coefficients at the TX end of the link. However, due to the lack of joint modeling of equalization and FEC, it is difficult to find the optimal FFE coefficients for the link, which places higher demands on modulation techniques.

[0064] As can be seen from the above, future high-speed links will need to cope with increasingly larger line losses, and the combined use of equalization technology and FEC technology will be a huge challenge.

[0065] Therefore, at least one embodiment of this disclosure proposes a low-latency interleaved error correction structure that balances random and burst errors, and is also relatively friendly to link training. For example, at least one embodiment of this disclosure proposes a low-latency RS(272, 258) multi-interleaved error correction structure, wherein RS(272, 258) is chosen because it is well compatible with the encoding and packet assembly methods of the original RS(544, 514). Of course, the embodiments of this disclosure are not limited to this, and other algorithms can be used.

[0066] At least one embodiment of this disclosure provides a data processing method, a data processing apparatus, a data transmission system, an electronic device, and a computer-readable storage medium, which can effectively reduce the complexity of encoding / decoding and error correction, reduce the time required for encoding / decoding and error correction, and reduce data transmission latency.

[0067] Figure 2 shows a flowchart of a data processing method 200 according to at least one embodiment of the present disclosure. The data processing method 200 and its additional aspects described with reference to Figure 2 can be implemented in a data processing apparatus 400, electronic device, hardware structure, software structure, or a combination of hardware and software structures as described below with reference to Figure 4. In some embodiments, the data processing method 200 can be executed at a data transmitting end (e.g., a data transmitting device).

[0068] Referring to Figure 2, the data processing method 200 includes steps S210 to S230.

[0069] In step S210, an encoding operation is performed based on the original data to generate N independent error correction codewords. Each of the N independent error correction codewords includes a data code and a check code, where N is an integer and N≥2.

[0070] The raw data can be any data that is to be sent from the sender to the receiver.

[0071] In step S220, the data codes and check codes included in the N independent error correction codewords are interleaved to obtain interleaved data.

[0072] In step S230, the interleaved data is sent.

[0073] As described above, the data processing method 200 according to at least one embodiment of the present disclosure can obtain multiple independent error correction codewords of the original data. Each independent error correction codeword can be interleaved and sent. Thus, decoding and error correction operations can be performed for each independent error correction codeword, effectively reducing the complexity of encoding, decoding and error correction, reducing the corresponding encoding, decoding and error correction time, and reducing data transmission latency.

[0074] The following describes some exemplary additional aspects of a data processing method 200 according to at least one embodiment of the present disclosure.

[0075] For example, according to at least one embodiment of the data processing method of this disclosure, N independent error correction codewords can be transmitted through multiple data lanes, and interleaving the data codes and check codes included in the N independent error correction codewords can include: alternately arranging the N independent error correction codewords in a new data stream, such that M consecutive symbols on each of the multiple data lanes belong to different error correction codewords in the N independent error correction codewords, where M is an integer and 2≤M≤N.

[0076] In some examples, M=2 and N=4, which allows two consecutive symbols on each data path to belong to different error-correcting codewords from four independent error-correcting codewords. Of course, the embodiments of this disclosure are not limited to this, and M and N can also be other values.

[0077] Thus, the data processing method according to at least one embodiment of the present disclosure can avoid the error correction codewords from a series of consecutive symbols on each data path, thereby effectively avoiding exceeding the upper limit of the error correction capability of the corresponding algorithm due to continuous errors, and can effectively deal with sudden errors on the same data path.

[0078] For example, in a data processing method according to at least one embodiment of this disclosure, M = N.

[0079] In some examples, M=4 and N=4, so that four consecutive symbols on each data path belong to different error-correcting codewords from four independent error-correcting codewords. Of course, the embodiments of this disclosure are not limited to this, and M and N can also be other values.

[0080] Thus, the data processing method according to at least one embodiment of the present disclosure can further space the symbols on each data path, thereby more effectively avoiding exceeding the upper limit of the error correction capability of the corresponding algorithm due to continuous errors, for example, it can better and more effectively deal with sudden errors on the same data path.

[0081] For example, the data processing method according to at least one embodiment of the present disclosure may further include: alternatingly arranging the N independent error correction codewords in a new data stream, such that corresponding symbols on adjacent data paths in multiple data paths belong to different error correction codewords among the N independent error correction codewords.

[0082] Thus, the data processing method according to at least one embodiment of the present disclosure can avoid crosstalk on adjacent data paths.

[0083] For example, according to at least one embodiment of the data processing method of this disclosure, generating N independent error correction codewords by encoding based on the original data may include: dividing the original data into N independent sub-data as data codes; and independently encoding the N independent sub-data to obtain the error correction code of each of the N independent sub-data as a check code.

[0084] Thus, the data processing method according to at least one embodiment of the present disclosure can independently generate multiple error correction codewords for the original data, thereby improving the efficiency of generating error correction codewords and reducing the complexity of the algorithm used to generate error correction codewords.

[0085] For example, according to at least one embodiment of the data processing method of this disclosure, dividing the original data into N independent sub-data may include: randomly dividing the original data into N independent sub-data.

[0086] Thus, the data processing method according to at least one embodiment of this disclosure can improve error correction capability from a probabilistic perspective and can be applied to more general error scenarios compared to fixedly dividing the original data into N independent sub-data.

[0087] For example, the high 128B and low 128B of the original 256B data are fixedly divided into two independent sub-data sets, and the error correction probability of correcting two errors in each of these two sub-data sets is... In contrast, randomly dividing the 256B original data into four 64B sub-data sets (instead of fixed high 128B and low 128B), and correcting two errors in each of these four sub-data sets, has a probability of [missing information]. Here, n is the number of symbols. In some examples, a symbol can be, for example, 1B (8 bits) or other numbers of bits.

[0088] For example, in practical applications, errors can occur randomly. In the example above, a fixed partition may have multiple errors occurring, for instance, in the high 128B, which cannot be corrected. In contrast, the data processing method according to at least one embodiment of this disclosure is relatively flexible and therefore applicable to more general application scenarios.

[0089] For example, according to at least one embodiment of the data processing method of this disclosure, randomly dividing the original data into N independent sub-data may include: randomly dividing the original data into N independent sub-data of equal size.

[0090] Thus, the data processing method according to at least one embodiment of this disclosure can employ the same N encoding and / or decoding and error correction methods, simplifying the design of the corresponding data transmission system.

[0091] For example, in the data processing method according to at least one embodiment of this disclosure, N = 4.

[0092] Thus, the data processing method according to at least one embodiment of this disclosure can employ four-way interleaving, thereby addressing a variety of application scenarios.

[0093] For example, in the data processing method according to at least one embodiment of the present disclosure, the encoding operation may employ the RS(272,258) algorithm.

[0094] Thus, the data processing method according to at least one embodiment of the present disclosure can reduce latency and / or increase bit rate compared to the RS(544, 514) algorithm.

[0095] For example, compared to the RS(544, 514) algorithm, the RS(272, 258) algorithm requires fewer iterations for encoding operations and / or subsequent decoding and error correction operations, which can reduce latency.

[0096] For example, compared to the RS(544, 514) algorithm, which can have 5140 bits of data in every 5440 bits, the RS(272, 258) algorithm can have 5160 bits of data in every 5440 bits, thus having a higher bit rate.

[0097] For example, according to at least one embodiment of the data processing method of this disclosure, the interleaved data can be transmitted via a high-speed link, and the high-speed link supports the transmission of the interleaved data in the form of at least one of a level signal and an optical signal.

[0098] Thus, the data processing method according to at least one embodiment of the present disclosure can be applied to sending and receiving data via level signals, sending and receiving data via optical signals, or sending and receiving data via both level signals and optical signals.

[0099] Figure 3 illustrates a flowchart of a data processing method 300 according to at least one embodiment of the present disclosure. The data processing method 300 and its additional aspects described with reference to Figure 3 can be implemented in a data processing apparatus 500, electronic device, hardware structure, software structure, or a combination of hardware and software structures as described below with reference to Figure 5. In some embodiments, the data processing method 300 can be executed at a data receiving end (e.g., a data receiving device).

[0100] Referring to Figure 3, the data processing method 300 includes steps S310 to S330.

[0101] In step S310, interleaved data is received to obtain read-back data codes and read-back error correction codes. The interleaved data is obtained by generating N independent error correction codewords based on encoding operations on the original data, and interleaving the data codes and check codes included in the N independent error correction codewords. Each of the N independent error correction codewords includes data codes and check codes, where N is an integer and N≥2.

[0102] In step S320, the read-back data code and the read-back error correction code are deinterleaved to obtain N independent read-back error correction codewords.

[0103] In step S330, decoding and error correction operations are performed on N independent readback error correction codewords.

[0104] As described above, the data processing method 300 according to at least one embodiment of the present disclosure can deinterleave, for example, the interleaved data described above with reference to FIG2, to obtain independent readback error correction codewords, and can perform decoding and error correction operations on the independent readback error correction codewords. Thus, decoding and error correction operations can be performed on each independent error correction codeword, effectively reducing the complexity of encoding, decoding and error correction, reducing the corresponding encoding, decoding and error correction time, and reducing data transmission latency.

[0105] The following describes some exemplary additional aspects of a data processing method 300 according to at least one embodiment of the present disclosure.

[0106] For example, according to at least one embodiment of the data processing method of this disclosure, decoding and error correction operations on N independent readback error correction codewords may include: independently decoding and error correction operations on each of the N independent readback error correction codewords.

[0107] Thus, the data processing method according to at least one embodiment of the present disclosure can perform decoding and error correction operations independently for each independent readback error correction codeword, thereby improving the efficiency of decoding and error correction and reducing the complexity of the algorithms used for decoding and error correction.

[0108] In other additional aspects, the data processing method 200 and its additional aspects described in FIG2 can also be applied to the data processing method 300 described in FIG3, and the corresponding technical effects can also be mapped to the additional aspects of the data processing method 300 described in FIG3, which will not be elaborated here.

[0109] Corresponding to the data processing method 200 according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure also provides a data processing apparatus. For example, the data processing apparatus may be a data transmission apparatus.

[0110] Figure 4 shows a schematic diagram of a data processing apparatus 400 according to at least one embodiment of the present disclosure.

[0111] Referring to Figure 4, the data processing device 400 includes an error correction codeword generation unit 410, an interleaving unit 420, and a transmission unit 430.

[0112] The error correction codeword generation unit 410 is configured to generate N independent error correction codewords by performing encoding operations based on the original data. Each of the N independent error correction codewords includes a data code and a check code, where N is an integer and N≥2.

[0113] The interleaving unit 420 is configured to interleave the data code and check code included in N independent error correction codewords to obtain interleaved data.

[0114] The transmitting unit 430 is configured to send the interleaved data to the data receiving end.

[0115] As described above, the data processing apparatus 400 according to at least one embodiment of the present disclosure can obtain multiple independent error correction codewords of the raw data. Each independent error correction codeword can be interleaved and transmitted, thereby enabling decoding and error correction operations to be performed for each independent error correction codeword, effectively reducing the complexity of encoding, decoding and error correction, reducing the corresponding encoding, decoding and error correction time, and reducing data transmission latency.

[0116] The additional aspects of the data processing apparatus 400 according to at least one embodiment of the present disclosure can correspond to the additional aspects of the data processing method 200 according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the data processing method 200 according to at least one embodiment of the present disclosure can also be mapped to the additional aspects of the data processing apparatus 400 according to at least one embodiment of the present disclosure, which will not be repeated here.

[0117] Corresponding to the data processing method 300 according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure also provides a data processing apparatus. For example, the data processing apparatus may be a data receiving apparatus.

[0118] Figure 5 shows a schematic diagram of a data processing apparatus 500 according to at least one embodiment of the present disclosure.

[0119] Referring to Figure 5, the data processing device 500 includes a receiving unit 510, a deinterleaving unit 520, and a decoding and error correction unit 530.

[0120] The receiving unit 510 is configured to receive interleaved data to obtain read-back data codes and read-back error correction codes. The interleaved data is obtained by encoding the original data to generate N independent error correction codewords, and then interleaving the data codes and check codes included in the N independent error correction codewords. Each of the N independent error correction codewords includes data codes and check codes, where N is an integer and N≥2.

[0121] The deinterleaving unit 520 is configured to deinterleave the read-back data code and the read-back error correction code to obtain N independent read-back error correction codewords.

[0122] The decoding and error correction unit 530 is configured to perform decoding and error correction operations on N independent readback error correction codewords.

[0123] As described above, the data processing apparatus 500 according to at least one embodiment of the present disclosure can deinterleave, for example, the interleaved data described above with reference to FIG2, to obtain independent readback error correction codewords, and can perform decoding and error correction operations on the independent readback error correction codewords. Thus, decoding and error correction operations can be performed on each independent error correction codeword, effectively reducing the complexity of encoding, decoding and error correction, reducing the corresponding encoding, decoding and error correction time, and reducing data transmission latency.

[0124] The additional aspects of the data processing apparatus 500 according to at least one embodiment of the present disclosure can correspond to the additional aspects of the data processing method 300 according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the data processing method 300 according to at least one embodiment of the present disclosure can also be mapped to the additional aspects of the data processing apparatus 500 according to at least one embodiment of the present disclosure, which will not be repeated here.

[0125] Figure 6 shows a schematic diagram of a data transmission system 600 according to at least one embodiment of the present disclosure. As shown in Figure 6, the data transmission system 600 may include the data processing apparatus 400 (and its additional aspects) as described above with reference to Figure 4 and the data processing apparatus 500 (and its additional aspects) as described with reference to Figure 5. Thus, the data processing apparatus 400 (and its additional aspects) described with reference to Figure 4 and the data processing apparatus 500 (and its additional aspects) described with reference to Figure 5 can be mapped to the data transmission system 600 described with reference to Figure 6, and will not be described again here.

[0126] The following describes one or more exemplary aspects described above in conjunction with Figures 2 to 6, using example application scenarios. It is understood that the example application scenarios described below are merely illustrative and not limiting, intended to implement one or more aspects described above in conjunction with Figures 2 to 6 in specific application scenarios, or simply to describe examples of implementing one or more aspects described above in conjunction with Figures 2 to 6. Furthermore, the aspects described below in conjunction with example application scenarios can be combined with one or more aspects described above in conjunction with Figures 2 to 6.

[0127] This example application scenario describes a low-latency RS(272, 258) multiplexed error correction structure, but the implementation is not limited to this. In other aspects, multiplexed error correction structures involving other algorithms or other multiplexed error correction structures using the same algorithm can be provided.

[0128] An error correction structure typically includes the following modules and processes: an RS encoder, a decoder, a synergistic computation module, a critical equation computation module, a Qian search module, a multi-way interleaving module and process, and a decoding and error correction process. These modules and processes will be explained in detail below.

[0129] The RS encoder is described below. For example, the RS encoder can implement one or more aspects of the encoding operations described above.

[0130] The encoding principle of RS code is to add redundancy according to certain encoding rules, making originally unrelated data correlated. For example, in this example application scenario, a division-based encoder can be used.

[0131] An exemplary process for encoding based on division consists of the following three steps:

[0132] (1) Premultiply the information polynomial m(x) by x n-k That is, shifting right by nk bits to get x n-k m(x);

[0133] (2) x n-k Dividing m(x) by the generator polynomial g(x) yields the remainder r(x), where g(x) determines a unique RS(n,k) code;

[0134] (3) From x n-k m(x)+r(x)=c(x) yields the encoded codeword polynomial.

[0135] Of course, the embodiments are not limited to this. For example, an encoder using matrix multiplication or other algorithms may be employed.

[0136] The decoding and error correction process is described below. For example, this decoding and error correction process can implement one or more aspects of the decoding and error correction operations described above.

[0137] The decoding principle is to use the data correlation generated by redundancy to correct errors that occur in the channel and recover the transmitted code sequence.

[0138] Figure 7 illustrates a schematic diagram of a decoding and error correction process according to at least one embodiment of the present disclosure.

[0139] Referring to Figure 7, the exemplary decoding and error correction process consists of the following 5 steps:

[0140] (1) In box 702, perform the syndrome calculation, for example, derive the syndrome S from the receiving polynomial. j ;

[0141] (2) In box 704, establish the key equation, for example, based on the adjoint equation S. j The key equations are solved using algorithms such as the BM algorithm, and the error polynomial and error value polynomial are obtained.

[0142] (3) In box 706, calculate the error location, for example, by substituting all possible error locations into the key equation and using, for example, the Chien search algorithm to solve for the root of the error polynomial and obtain the error location;

[0143] (4) In box 708, calculate the error value, for example, using the Forney algorithm to calculate the error value;

[0144] (5) Then, error correction can be performed based on the error location and error value to complete the error correction.

[0145] In Figure 7, the controller + frame buffer 710 can be used to control the calculation of corresponding data in each box of blocks 702-708 and to cache the data and / or calculation results required for the corresponding calculation.

[0146] Of course, the embodiments are not limited to this. For example, other algorithms or other decoding and error correction processes can be used to implement the above decoding and error correction process.

[0147] The following describes a more detailed exemplary aspect of the decoding and error correction process described with reference to Figure 7.

[0148] First, we describe the adjoint computation.

[0149] The syndrome of the RS(272,258) code can be expressed as, for example, by formula (1):

[0150] in,

[0151] In practice, Horner's algorithm can be used to calculate S. j Formula (2) is as follows:

[0152] Substituting n = 272 and b = 1 into formula (2), we get:

[0153] For example, in engineering design, pipelined hardware can be used to implement adjoint computation.

[0154] Figure 8 shows a block diagram of an adjoint calculation according to at least one embodiment of the present disclosure.

[0155] See Figure 8, where, Represents finite field multiplication. This represents addition within a finite field. During the adjoint calculation, the module first initializes, then sequentially assigns values ​​to R1, R2, ..., R... 271 The data is shifted into the shift register. The 14 syndromes are calculated after 272 clock cycles. If all syndrome coefficients are 0, it indicates that the received codeword is correct and the number of errors is 0; otherwise, the number of errors is greater than 0.

[0156] Next, the key equations will be described.

[0157] Once all 14 adjoints are solved, the error position polynomial can be solved using, for example, the improved BM algorithm. The earliest BM algorithm requires inverting elements of a finite field, which necessitates division within the finite field in each iteration. This complexity makes the algorithm unsuitable for high-speed implementation. Therefore, the exemplary improved algorithm is as follows:

[0158] (1) Initialization: Λ (0) (x)=1,T (0) (x)=1,L (0) (x)=0,γ (0) (x) = 1, k = 0;

[0159] (2) The following steps are to iteratively select from equation (4) to equation (7) until the cycle ends when k = 2t-1. Λ (k-1) (x)=γ (k) Λ (k) (x)-Δ (k-1) T (k) (x)x (5);

[0160] When Δ (k-1) =0 or 2L (k) When >k, T (k-1) (x)=xT (k) (x),L (k+1) =L (k),γ (k+1) =γ (k) (6);

[0161] Otherwise when Δ (k-1) ≠ 0 or 2L (k) When ≤k, T (k-1) (x)=Λ (k) (x),L (k-1) =k+1-L (k) ,γ (k+1) =Δ (k-1) (7); k = k + 1.

[0162] Among them Λ (k-1) (x) is the polynomial in the wrong position.

[0163] In equation (4), Δ is the convolution sum of Λ(x) and S(x). To achieve pipelined processing, techniques such as finite impulse response (FIR) filters can be used, as shown in Figure 9.

[0164] Figure 9 shows a block diagram of the key equations according to at least one embodiment of the present disclosure.

[0165] Referring to Figure 9, during initialization, all registers (D) are set to 0. Then, with each rising edge of a clock cycle, S1, S2, ..., S... are sequentially... 14 By shifting the values ​​into the shift register, we can finally obtain the coefficients of the error position polynomial Λ(x).

[0166] Next, the money search will be described.

[0167] After obtaining the error-valued polynomial from the key equation, to simplify the calculation, the Qian search method is used to find the roots of the error-valued polynomial. An example method is as follows:

[0168] Let: R(x) = r 271 x 271 +r 270 x 270 +...+r1x+r0 (8);

[0169] To test the first r n-1 Whether it is an error needs to be determined by α. n-1 Whether it is an error position number, i.e., checking α -(n-1) Is it a root of σ(x)? If α -(n-1) =If α is a root of σ(x), then: σ(α) -(n-1) )=σ(x)=1+σ1α+σ2α+...+σ t α t =0 (9);

[0170] Or: σ1α + σ2α + ... + σ t α t =-1.

[0171] Therefore, we can determine α n-1 An error occurred in the bit position. By analogy, we can deduce:

[0172] If σ1(α) + σ2(α) + … + σ t (α) t =-1, then α 271 The position is wrong;

[0173] If σ1(α) 2 )+σ2(α 2 )+…+σ t (α 2 ) t =-1, then α 270 The position is wrong;

[0174] …………………………………

[0175] If σ1(α) i )+σ2(α i )+…+σ t (α i ) t =-1, then α 271-i The position is wrong;

[0176] If σ1(α) n )+σ2(α n )+…+σ t (α n ) t =-1, then α 0 The position is wrong;

[0177] Where α n-i The position is x n-i Bit.

[0178] Therefore, for each α in turn n-i By performing a check on (i = 1, 2, ..., n), the roots of the error value polynomial are obtained. The error location δ(a) can be obtained using, for example, the Furni algorithm. i The error value when ) = 0 is:

[0179] Figure 10 shows a schematic diagram of a money search circuit according to at least one embodiment of the present disclosure. In an example application scenario, this money search circuit can be used to search for and correct error locations, and its exemplary process is as follows:

[0180] (1) t registers store σ0, σ1, σ2, ..., σt When the actual number of errors v of the data output by the register system channel is less than t, then there is σ v+1 = σ v+2 = … = σ t = 0.

[0181] (2) r n-1 Before about to read out from the cache memory, t multipliers perform multiplication operations under the control of a shift pulse, and the following values are stored in the register: σ0α, σ2a 2 , …, σ t a t , and these values are accumulated. If the value is -1, the control gate is opened, and the error value is subtracted from r n-1 output by the buffer, and C n-1 completes the error correction of r n-1 .

[0182] (3) r n-1 After the decoding is completed, perform multiplication again. At this time, σ1a 2 , σ2(a 2 ) 2 , σ t (a t ) 2 is stored in register σ, and addition operation and check are performed to perform error correction on r n-2 . The remaining code elements (symbols) are error-corrected in the same way as (2).

[0183] It can be understood that the above describes an exemplary embodiment of the decoding and error correction process. However, the embodiment is not limited thereto. For example, the decoding and error correction process can be implemented through matrix operations or other algorithms.

[0184] The following describes the interleaved error correction structure. For example, one or more exemplary aspects of the above data processing method can be implemented in this interleaved error correction structure.

[0185] This interleaved error correction structure is, for example, a coding technique for correcting data errors and solving delays. It divides the original data into several independent data streams and alternately arranges these data streams in a new data stream to enhance the reliability of the data. In this error correction structure, each data stream can use error correction coding to correct and detect errors.

[0186] FIG. 11 shows a schematic diagram of a four-way interleaved structure according to at least one embodiment of the present disclosure. For example, the four-way interleaved structure described in FIG. 11 can be used in one or more exemplary aspects of a data sending end or a data processing device 400.

[0187] Referring to FIG. 11, the input data can be divided into 4 sub-data. Here, the input data can, for example, correspond to the original data described above.

[0188] On one hand, the four sub-data items can be transmitted to the data interleaving module for interleaving. On the other hand, the four sub-data items can be independently encoded by four encoders to generate corresponding error correction codes. For example, the first sub-data item can be input to encoder 0 for encoding to generate an error correction code for the first sub-data item, the second sub-data item can be input to encoder 1 for encoding to generate an error correction code for the second sub-data item, the third sub-data item can be input to encoder 2 for encoding to generate an error correction code for the third sub-data item, and the fourth sub-data item can be input to encoder 3 for encoding to generate an error correction code for the fourth sub-data item.

[0189] After obtaining the error correction codes for each of the four sub-data, these error correction codes can be transmitted to the ECC interleaving module for interleaving.

[0190] In the above embodiments, four independent ECC words, i.e., four sub-data and their corresponding error correction codes, can be obtained, and the sub-data and error correction codes can be interleaved. Of course, the embodiments are not limited to this. In some embodiments, the encoder can directly obtain four independent ECC words and interleave the sub-data and error correction codes in the four independent ECC words.

[0191] After the interleaving operation described above, interleaved data can be obtained. Subsequently, the interleaved data can be transmitted (TX) via a channel or link.

[0192] Figure 12 illustrates a schematic diagram of a four-way deinterleaving structure according to at least one embodiment of the present disclosure. For example, the four-way deinterleaving structure described with reference to Figure 12 can be used in one or more exemplary aspects of a data receiver or data processing apparatus 500.

[0193] Referring to Figure 12, the read-back data and the read-back error correction code can be obtained by receiving interleaved data, for example, via a channel or link (RX). The interleaved data here can be the interleaved data generated by the various aspects described in Figure 11.

[0194] The read-back data and read-back error correction codes can be processed by the data deinterleaving module and the error correction code deinterleaving module respectively to obtain 4 independent read-back error correction codewords (e.g., corresponding to the 4 independent ECC words in Figure 11).

[0195] Subsequently, the four independent readback error correction codewords can be transmitted to the decoder and error correction module for decoding and error correction operations to obtain corrected data. For example, the four independent readback error correction codewords can each be decoded and corrected via their own decoder and error correction module. Exemplarily, the first readback error correction codeword can be decoded and corrected via decoder 0 and error correction module 0, the second readback error correction codeword can be decoded and corrected via decoder 1 and error correction module 1, the third readback error correction codeword can be decoded and corrected via decoder 2 and error correction module 2, and the fourth readback error correction codeword can be decoded and corrected via decoder 3 and error correction module 3.

[0196] Figure 13 illustrates a four-way interleaved data structure according to at least one embodiment of the present disclosure. The four-way interleaved data structure described with reference to Figure 13 can, for example, be a four-way interleaved data structure suitable for the RS(272, 258) algorithm. Of course, the embodiments are not limited to this. For example, this four-way interleaved data structure can also be used for other algorithms. Furthermore, for different algorithms, interleaved data structures with different numbers of paths can also be used.

[0197] Referring to Figure 13, four independent error-correcting codewords can be transmitted through 16 data paths (i.e., lanes in the figure). Of course, other numbers of data paths can be used depending on different needs and / or different data transmission protocols.

[0198] Referring to Figure 13, four consecutive symbols on each data path can belong to, for example, different FEC ECC words. In this case, it ensures that consecutive errors on the same data path can be distributed across different FECs. For example, each small block in Figure 13 can represent a 10-bit symbol, where all data belongs to 10 consecutively transmitted data on the same data path. In Figure 13, symbols of the same grayscale belong to the same FEC ECC word. For example, on data path 0, symbols 0, 16, 32, and 48, from top to bottom, come from the first, second, third, and fourth ECC words of four different ECC words, respectively; similarly, symbols 64, 80, 96, and 112 can come from the first, second, and third ECC words of four different ECC words, and so on. Other data paths can have the same or similar data structure as data path 0. In this way, symbols from different ECC words are arranged in an interleaved manner.

[0199] For example, referring to Figure 13, suppose a series of errors starts propagating from symbol 18 in Figure 13, passing through symbols 34, 50, and 66. This introduces only one symbol error for each ECC word, and therefore can be easily corrected. For example, using the RS(272, 258) algorithm, a four-way interleaving error correction structure can correct any seven such series of errors, thus greatly improving the system's bandwidth efficiency.

[0200] In addition, referring to Figure 13, corresponding symbols on adjacent data paths in multiple data paths belong to different error correction codewords among four independent error correction codewords. For example, symbol 0 on data path 0 and symbol 1 on data path 1 belong to different error correction codewords among four independent error correction codewords, and symbol 16 on data path 0 and symbol 17 on data path 1 belong to different error correction codewords among four independent error correction codewords.

[0201] Figure 13 illustrates a scenario where four consecutive symbols in each of multiple data paths belong to different ECC words, and corresponding symbols in adjacent data paths belong to different error correction codewords from four independent error correction codewords. For example, referring to Figure 13, the symbols in each data path (corresponding to each column) from top to bottom come from the first, second, and third ECC words from four different ECC words, and so on; the corresponding symbols in adjacent data paths (corresponding to each column) come from the first, second, and third ECC words from four different ECC words, respectively. Of course, this embodiment is not limited to this, and other interleaved data structures may exist.

[0202] Example application scenarios can provide multi-interleaved coding structures. For example, in a multi-interleaved coding structure, multiple FECs are interleaved to ensure the interleaved arrangement of symbols of different FECs on the same data path and adjacent data paths. This can effectively deal with burst errors on the same data path and crosstalk on adjacent data paths, spreading burst errors on the channel or link over time and transforming them into independent random errors, thus giving full play to the role of error correction codes.

[0203] The example application scenarios can provide greater flexibility for training link coefficients. For instance, error correction mechanisms using interleaving and RS coding can handle both random and sudden errors. Even if the link's equalization coefficients are not optimal, the reliability and bandwidth efficiency of system data transmission will not significantly decrease.

[0204] The example application scenario can bring the balancing strategy, system packet loss rate, latency, and area to an overall optimal state, thereby improving the overall system performance.

[0205] For the exemplary algorithm, in example application scenarios, an RS(272,258) four-way interleaved error correction structure can be provided, which has the advantages of low latency, almost no bandwidth loss, small ECC word, applicable to FEC design for joint link equalization, and high code rate.

[0206] For example, in terms of low latency, it can reduce the complexity of encoding, decoding and error correction, and the number of iterations of a single FEC is less, which is a low latency feature compared to the traditional RS(544, 514) algorithm.

[0207] For example, in the case of almost no bandwidth loss, a typical scenario for burst errors is that an ECC word contains multiple random errors, which in turn trigger DFE (Distributed Error Detection) decisions. This means that each symbol with a random error has a relatively high probability of causing the next symbol to also be faulty (the probability of the error propagating to the third symbol is much lower). This scenario of two consecutive symbols being faulty can be well handled by multi-interleaved RS (272, 258). A single RS (544, 514) and dual RS (272, 258) can correct any seven consecutive errors involving two symbols being faulty. Multi-interleaving can more effectively correct errors in transmission and improve the reliability of data transmission.

[0208] For example, in terms of ECC word size, compared to the existing RS(544, 514), by adopting RS(272, 258) encoding, the length of the error correction code is reduced, the complexity of the error correction module is reduced, and the frequency can be increased.

[0209] For example, in the design of FEC applicable to joint link equalization, interleaved FEC is designed for cases with relatively good BER but a large error propagation coefficient burst. This simultaneously improves actual error correction capability, reduces latency, optimizes area, and achieves overall optimization.

[0210] For example, in terms of high bit rate, the bit rate is higher than that of the commonly used RS(544, 514). In RS(544, 514), there can be 5140 bits of data in every 5440 bits, while in the multi-interleaved RS(272, 258), there can be 5160 bits of data in every 5440 bits.

[0211] Regarding additions or alternatives to the above example application scenarios, the illustrated error correction structure can be used in various high-speed links and also supports end-to-end integrated solutions. For example, future links may be based not only on level signals but also on optical signals. A short-distance high-speed link can first send the level signal to the optical transmission module, which then converts the signal and transmits it through optical fiber to a long-distance optical receiving module. The optical receiving module then converts the optical signal back into a level signal before sending it to the final receiving end of the link. Therefore, the error correction structure in the above example application scenarios can correct random errors and effectively handle continuous errors. It can also be applied to the aforementioned end-to-end integrated solutions, such as encoding at the level transmitter and decoding at the level receiver, providing end-to-end protection, thereby saving the encoding and decoding time of the optical module and improving the efficiency and reliability of the entire system.

[0212] Figure 14 shows a schematic diagram of an electronic device 1400 according to at least one embodiment of the present disclosure.

[0213] As shown in FIG14, the electronic device 1400 includes at least one processing unit 1420 and at least one memory 1410. The memory 1410 stores computer-readable instructions and is communicatively connected to the processing unit 1420. The processing unit 1420 executes the computer-readable instructions stored in the memory 1410 to implement a data processing method and its additional aspects according to at least one embodiment of the present disclosure.

[0214] For example, memory 1410 and processing unit 1420 can communicate with each other directly or indirectly. For example, in some examples, as shown in FIG14, the electronic device 1400 may also include a system bus 1430 through which memory 1410 and processing unit 1420 can communicate with each other; for example, processing unit 1420 can access memory 1410 through system bus 1430. For example, in other examples, components such as memory 1410 and processing unit 1420 can communicate via a network on-chip (NOC) connection.

[0215] For example, processing unit 1420 can control other components in electronic device 1400 to perform desired functions. Processing unit 1420 can be a device with data processing and / or program execution capabilities, such as a central processing unit (CPU), tensor processor (TPU), network processor (NP), or graphics processor (GPU), or it can be a digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0216] For example, memory 1410 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0217] For example, one or more computer-readable instructions may be stored on memory 1410, and processing unit 1420 may execute computer-readable instructions to perform various functions. Various application programs and various data, such as instruction processing code and various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0218] For example, when some computer instructions stored in memory 1410 are executed by processing unit 1420, they can perform one or more steps in the data processing method described above.

[0219] For example, as shown in FIG14, the electronic device 1400 may further include an input interface 1440 that allows external devices to communicate with the electronic device 1400. For example, the input interface 1440 may be used to receive instructions from external computer devices, users, etc. The electronic device 1400 may further include an output interface 1450 that enables the electronic device 1400 to connect to one or more external devices. For example, the electronic device 1400 can communicate via the output interface 1450, etc.

[0220] It should be noted that the electronic device 1400 according to at least one embodiment of the present disclosure is exemplary and not restrictive. Depending on the actual application needs, the electronic device 1400 may also include other conventional components or structures. For example, in order to realize the necessary functions of the electronic device, those skilled in the art can set other conventional components or structures according to the specific application scenario. The embodiments of the present disclosure do not limit this.

[0221] At least one embodiment of this disclosure also provides a computer-readable storage medium. FIG15 shows a schematic diagram of a computer-readable storage medium 1500 according to at least one embodiment of this disclosure.

[0222] For example, as shown in FIG15, the computer-readable storage medium 1500 stores computer-readable instructions 1510, which, when executed by a computer (including a processor), can implement a data processing method and its additional aspects according to at least one embodiment of the present disclosure.

[0223] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 1500. Some of the computer-readable instructions stored on the computer-readable storage medium 1500 may be, for example, instructions for implementing one or more steps in the data processing method described above.

[0224] For example, a computer-readable storage medium may include the storage component of a tablet computer, a hard disk of a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), optical disc read-only memory (CD-ROM), flash memory, or any combination of the above computer-readable storage media, or other suitable storage media. For example, computer-readable storage medium 1500 may include memory 1410 in the electronic device 1400 described above.

[0225] At least some embodiments of this disclosure also provide an electronic device. FIG16 shows a schematic diagram of another electronic device 1600 according to at least one embodiment of this disclosure.

[0226] The electronic device according to at least one embodiment of the present disclosure can be implemented as, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs, desktop computers, etc.

[0227] The electronic device 1600 shown in Figure 16 is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0228] For example, as shown in FIG16, in some examples, electronic device 1600 includes processor 1601, which may include the processor of any of the above embodiments (e.g., SMT processor), which performs various appropriate actions and processes according to a program stored in read-only memory (ROM) 1602 or a program loaded from storage device 1608 into random access memory (RAM) 1603. RAM 1603 also stores various programs and data required for the operation of the computer system. Processor 1601, ROM 1602, and RAM 1603 are connected via bus 1604. Input / output (I / O) interface 1605 is also connected to bus 1604.

[0229] For example, the following components can be connected to I / O interface 1605: input devices 1606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1609, such as network interface cards like LAN cards, modems, etc. Communication device 1609 allows electronic device 1600 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1610 is also connected to I / O interface 1605 as needed. Removable media 1611, such as disks, optical discs, magneto-optical discs, semiconductor memories, etc., are installed on drive 1610 as needed so that computer programs read from them can be installed into storage device 1608 as needed. Although Figure 16 shows electronic device 1600 including various devices, it should be understood that implementation or inclusion of all shown devices is not required. It can be implemented alternatively or include more or fewer devices.

[0230] For example, the electronic device 1600 may further include a peripheral interface (not shown). This peripheral interface can be of various types, such as a USB interface, a Lightning interface, etc. The communication device 1609 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0231] In addition to the exemplary descriptions above, the following points should be noted regarding this disclosure:

[0232] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0233] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0234] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A data processing method, comprising: N independent error correction codewords are generated by encoding operations based on the original data. Each of the N independent error correction codewords includes a data code and a check code, where N is an integer and N≥2. The data codes and check codes included in the N independent error correction codewords are interleaved to obtain interleaved data; as well as Send the interleaved data.

2. The data processing method according to claim 1, wherein, The N independent error correction codewords are transmitted through multiple data paths, and the data codes and check codes included in the N independent error correction codewords are interleaved, including: The N independent error correction codewords are alternately arranged in a new data stream, such that M consecutive symbols on each of the multiple data paths belong to different error correction codewords among the N independent error correction codewords, where M is an integer and 2≤M≤N.

3. The data processing method according to claim 2, wherein, M = N.

4. The data processing method according to claim 2 or 3 further includes: The N independent error correction codewords are alternately arranged in a new data stream, such that corresponding symbols on adjacent data paths in the plurality of data paths belong to different error correction codewords among the N independent error correction codewords.

5. The data processing method according to any one of claims 1-4, wherein, Based on the original data, an encoding operation is performed to generate N independent error-correcting codewords, including: The original data is divided into N independent sub-data, which are used as the data code; The encoding operation is performed independently on the N independent sub-data to obtain the error correction code for each of the N independent sub-data, which serves as the check code.

6. The data processing method according to any one of claims 1-5, wherein, The original data is divided into N independent sub-data, including: The original data is randomly divided into N independent sub-data.

7. The data processing method according to any one of claims 1-6, wherein, N＝4。 8. The data processing method according to claim 7, wherein, The encoding operation uses the RS(272,258) algorithm.

9. The data processing method according to any one of claims 1-8, wherein, The interleaved data is transmitted via a high-speed link, and the high-speed link supports the transmission of the interleaved data in the form of at least one of a level signal and an optical signal.

10. A data processing method, comprising: Receive interleaved data to obtain read-back data code and read-back error correction code, wherein the interleaved data is obtained by generating N independent error correction codewords based on encoding operations on the original data, and interleaving the data code and check code included in the N independent error correction codewords, each of the N independent error correction codewords includes a data code and a check code, where N is an integer and N≥2; The read-back data code and the read-back error correction code are deinterleaved to obtain N independent read-back error correction codewords; as well as Decode and correct the N independent readback error correction codewords.

11. The data processing method according to claim 10, wherein, Decoding and error correction operations are performed on the N independent readback error correction codewords, including: Each of the N independent readback error correction codewords is independently decoded and error corrected.

12. A data processing apparatus, comprising: The error correction codeword generation unit is configured to generate N independent error correction codewords by performing encoding operations based on the original data. Each of the N independent error correction codewords includes a data code and a check code, where N is an integer and N≥2. The interleaving unit is configured to interleave the data code and check code included in the N independent error correction codewords to obtain interleaved data; as well as The transmitting unit is configured to send the interleaved data to the data receiving end.

13. A data processing apparatus, comprising: The receiving unit is configured to receive interleaved data to obtain read-back data codes and read-back error correction codes. The interleaved data is obtained by generating N independent error correction codewords based on encoding operations on the original data, and interleaving the data codes and check codes included in the N independent error correction codewords. Each of the N independent error correction codewords includes a data code and a check code, where N is an integer and N≥2. The deinterleaving unit is configured to deinterleave the read-back data code and the read-back error correction code to obtain N independent read-back error correction codewords; as well as The decoding and error correction unit is configured to perform decoding and error correction operations on the N independent readback error correction codewords.

14. A data transmission system, comprising: The data processing apparatus according to claim 12; or The data processing apparatus according to claim 13.

15. An electronic device comprising: At least one processor; At least one memory, on which instructions are stored, When the instruction is executed by the processor, it causes the processor to perform the data processing method as described in any one of claims 1-11.

16. A computer-readable storage medium having computer-readable instructions stored thereon, in, When executed by a processor, the computer-readable instructions cause the processor to perform the data processing method as described in any one of claims 1-11.

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