Shielded gate trench device and manufacturing method therefor

Abstract

The present application relates to the technical field of semiconductors, and in particular, to a shielded gate trench device and a manufacturing method therefor. The manufacturing method comprises: providing a substrate, the substrate comprising an epitaxial layer, a first trench located in the epitaxial layer, and a first oxide layer covering at least part of a surface of the epitaxial layer and an inner wall of the first trench; forming a polysilicon structure filling the first trench, the doping concentration of the polysilicon structure gradually decreasing in a direction from the bottom to a top end of the first trench; etching back the polysilicon structure to form a second trench, a polysilicon inner wall of the second trench covering the first oxide layer on the inner wall of the first trench, and the second trench being used to form a shielded gate structure; and, on the basis of oxidation treatment, forming a second oxide layer on the polysilicon inner wall of the second trench, the thickness of the second oxide layer gradually decreasing in the direction from the bottom to the top end of the first trench. The present application enables free regulation and control of the thickness dimension and thickness variation of a field oxide layer, and is suitable for voltage withstanding devices having various voltage requirements.

Description

Shielded gate trench device and its fabrication method Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a shielded gate trench device and its fabrication method. Background Technology

[0002] Shielded gate devices are semiconductor devices with a shielded gate in the device body region, such as SGT MOSFE (Shielded Gate Trench Metal-Oxide-Semiconductor Field-Effect Transistor). The shielded gate can introduce a lateral electric field in the body region to assist in the depletion of the drift region. However, the lateral electric field exhibits a distribution characteristic of low field strength in the middle and high field strength at the bottom along the trench depth direction (refer to Figure 1), resulting in low and unstable breakdown voltage performance. Related technologies address these issues by using EPI (epitaxygen layer) with gradually varying doping concentrations, or by using a composite material layer of field oxide layer on the inner wall of the trench to utilize the difference in corrosion rate to form a stepped field plate, increasing the field strength in the middle and improving the low field strength in the middle. However, the former method has poor field strength distribution improvement and affects the etching of the shielded gate trench, leading to uncontrollable trench size issues. The latter method is only suitable for high-voltage, thick-field-plate devices and cannot be adapted to medium- and low-voltage devices with thinner field oxide requirements. Summary of the Invention

[0003] To address the aforementioned technical problems, this application discloses a method for fabricating a shielded gate trench device, comprising:

[0004] A substrate is provided, the substrate including an epitaxial layer, a first trench located in the epitaxial layer, and a first oxide layer covering at least a portion of the surface of the epitaxial layer and the inner wall of the first trench;

[0005] A polycrystalline silicon structure is formed to fill the first trench, and the doping concentration of the polycrystalline silicon structure gradually decreases along the direction from the bottom to the top of the first trench.

[0006] The polysilicon structure is etched back to form a second trench. The polysilicon inner wall of the second trench is covered with the first oxide layer of the inner wall of the first trench. The second trench is used to form a shielding gate structure.

[0007] An oxidation process is used to form a second oxide layer on the inner wall of the polycrystalline silicon of the second trench. The thickness of the second oxide layer gradually decreases along the direction from the bottom to the top of the first trench.

[0008] In one example implementation, the doping concentration of the polysilicon structure decreases in a stepwise manner along the direction from the bottom to the top of the first trench, and the thickness of the second oxide layer decreases in a stepwise manner; or,

[0009] Along the direction from the bottom to the top of the first trench, the doping concentration of the polycrystalline silicon structure gradually decreases, and the thickness of the second oxide layer gradually decreases.

[0010] In one example implementation, the polysilicon structure includes multiple polysilicon layers stacked sequentially along the depth direction of the first trench, wherein the doping concentration of each polysilicon layer varies progressively; the formation of the polysilicon structure filling the first trench includes:

[0011] In the first trench, multiple polysilicon doping deposition processes and polysilicon etch-back processes are repeatedly performed to form the multilayer polysilicon layer, and the flow rate of the dopant gas used in each polysilicon doping deposition step is gradually reduced in time.

[0012] In one example implementation, the doping concentration and thickness of each of the polysilicon layers are determined based on simulation structural design data corresponding to the shielding gate device. The simulation structural design data is generated based on a preset electric field distribution in the body region of the shielding gate device, which is used to indicate the desired intensity distribution of the transverse electric field in the body region along the depth direction of the first trench.

[0013] In one example implementation, the oxidation treatment of the polysilicon inner wall of the second trench is performed using a wet oxygen thermal oxidation process.

[0014] In one example implementation, providing the substrate includes:

[0015] An initial substrate is provided, the initial substrate comprising a base layer and an epitaxial layer located on one side of the base layer;

[0016] The epitaxial layer is etched with trenches to form the first trench;

[0017] The first oxide layer is formed by depositing an oxide film to form a conformal covering at least a portion of the surface of the epitaxial layer and the inner wall of the first trench.

[0018] In one example implementation, the etch-back process of the polysilicon structure to form the second trench includes:

[0019] The polycrystalline silicon structure is polished until the first oxide layer on the surface of the epitaxial layer is exposed;

[0020] A mask layer is formed on the first oxide layer and the polysilicon structure to block the first oxide layer and the area where the surface of the polysilicon structure is aligned with the sidewall of the polysilicon structure, and to expose the area where the surface of the polysilicon structure is aligned with the second trench.

[0021] The substrate with the mask layer is subjected to dry etching and the mask layer is removed to form the second trench.

[0022] In one example implementation, the etching process parameters are determined based on a preset etching angle corresponding to the simulation structure design data and a preset bottom thickness of the inner wall of the second trench. The preset etching angle is negatively correlated with the gradient of the change of the sidewall of the second oxide layer. The preset etching angle refers to the angle between the sidewall of the second trench and the surface of the substrate, and is the complementary angle between the sidewall of the second trench and the bottom wall of the second trench.

[0023] In one example implementation, after the oxidation process is performed to form a second oxide layer on the polycrystalline silicon inner wall of the second trench, the preparation method further includes;

[0024] A shielding grid structure conforming to the second oxide layer is formed in the second trench, and the width of the shielding grid structure gradually increases along the direction from the bottom to the top of the second trench.

[0025] In another aspect, this application also discloses a shielding trench device, which is prepared based on the above-described preparation method.

[0026] In one example implementation, the shielding trench device includes:

[0027] The substrate includes an epitaxial layer and a first trench located in the epitaxial layer;

[0028] A first oxide layer covers at least a portion of the surface of the epitaxial layer and the inner wall of the first trench;

[0029] An oxygen layer is disposed on the inner wall of the first trench, and the oxygen layer surrounds and forms a second trench. The thickness of the oxygen layer gradually decreases along the direction from the bottom to the top of the first trench.

[0030] In one example implementation, the thickness of the field oxygen layer decreases in a stepwise manner along the direction from the bottom to the top of the first trench; or, the thickness of the field oxygen layer decreases gradually along the direction from the bottom to the top of the first trench.

[0031] In another aspect, this application also discloses an integrated circuit comprising the aforementioned shielded gate trench device.

[0032] In another aspect, this application also discloses an electronic device that includes the aforementioned shielding trench device.

[0033] Based on the above technical solution, this application has the following beneficial effects:

[0034] This application forms a filled polysilicon structure in a first trench of an epitaxial layer, with the doping concentration of the polysilicon structure gradually decreasing from the bottom to the top of the first trench, forming a prestructure for forming field oxide. Then, the polysilicon structure is etched back to form a second trench, resulting in a trench inner wall with varying doping concentration. Subsequently, an oxidation process is performed to oxidize the polysilicon inner wall to form a second oxide layer. Due to the change in doping concentration, the thickness of the second oxide layer also changes, thus bonding with the first oxide layer to form a field oxide layer with a gradually varying thickness from the bottom to the top of the trench, achieving a screen in the second trench. The width of the shielding structure can be freely adjusted to significantly optimize the low field strength in the middle of the bulk region, thereby maximizing the field strength integral area of ​​the bulk region and effectively improving the breakdown voltage performance of the device. Furthermore, only one thermal oxidation process is required during the fabrication of the second oxide layer, resulting in a small thermal budget and avoiding the back diffusion problem of dopant impurities in the substrate, thus preventing a reduction in the breakdown voltage performance of the device. In addition, the thickness and variation of the field oxide layer can be freely adjusted by modulating the doping concentration of the polysilicon structure in the trench, without limiting the field oxide thickness. The high degree of freedom in structure fabrication allows it to be adapted to breakdown voltage devices with various voltage requirements. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 is a schematic diagram of the structure of a shielding trench device provided by the prior art;

[0037] Figure 2 is a schematic flowchart illustrating a method for fabricating a shielded trench device according to an example of this application;

[0038] Figure 3-11 is a device structure diagram illustrating the fabrication process of an exemplary shielded trench device according to this application;

[0039] Figure 12 is a device structure diagram of the fabrication process of a shielded gate trench device according to a reference example provided in this application;

[0040] Figure 13 is a transverse electric field distribution diagram of the device body region of an exemplary shielded trench device of this application;

[0041] The following is a supplementary explanation of the attached figures: 101-substrate layer, 102-epitaxy layer, 103-first oxide layer, 104-second oxide layer, 105-first trench, 106-bulk region, 107-field oxide layer, 201-polysilicon structure, 202-polysilicon layer, 203-polysilicon sidewall, 204-second trench, 205-shielding gate structure, 206-gate structure, 207-isolation oxide layer, 301-mask layer. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0043] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0044] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included. For example, a specified range from “1 to 10” should be considered to include any and all subranges between the minimum value 1 and the maximum value 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0045] As used in this application, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper structure, or it may extend within a localized area of ​​the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a conical surface. A single layer may comprise multiple layers. For example, field oxide layer 107 may comprise a first oxide layer 103 and a second oxide layer 104, etc., and may have the same or different materials.

[0046] It should be understood that the terms "consistent" and "perpendicular" used in this application refer to basic consistency or basic perpendicularity that meet the requirements of process tolerance, and do not refer to absolute consistency or absolute perpendicularity in a physical sense.

[0047] It should be understood that the term "plane" as used in this application, such as "first plane", "second plane", etc., refers to the XY plane of a substrate, etc., corresponding to the XY plane of a semiconductor device. "In-plane direction" refers to a direction parallel to the XY plane. "Thickness direction", "trench depth direction" or "longitudinal direction" refers to the Z direction relative to the XY plane.

[0048] The following describes the fabrication method of the shielded gate trench device provided in the embodiments of this application with reference to Figures 2-12. Figure 2 is a schematic flowchart of the fabrication method of the shielded gate trench device. This specification provides the method operation steps as shown in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operation steps may be included. The order of steps listed in the embodiments is only one of many possible execution orders and does not represent the only execution order. In actual fabrication, the method can be executed in the order shown in the embodiments or figures or in parallel. The fabrication method may include S11-S14:

[0049] S11: Provides a substrate.

[0050] Specifically, referring to FIG4, the substrate includes an epitaxial layer 102, a first trench 105 located in the epitaxial layer 102, and a first oxide layer 103 covering at least a portion of the surface of the epitaxial layer 102 and the inner wall of the first trench 105.

[0051] Specifically, the substrate further includes a base layer 101, and an epitaxial layer 102 is formed on one side of the base layer 101. The base layer 101 is a semiconductor substrate capable of being processed into a semiconductor device. Exemplarily, the constituent material of the base layer 101 may be at least one of the following: silicon, silicon-containing materials (such as gallium arsenide (GaAs) III-V compound semiconductor materials), silicon on insulator (SOI), or other types of semiconductor materials capable of forming the base layer 101.

[0052] Specifically, the epitaxial layer 102 is formed on the substrate layer 101. Optionally, the epitaxial layer 102 can be formed by an epitaxial growth process. It can be an epitaxial layer 102 that is homogeneous with the substrate layer 101, such as an epitaxial layer 102 that can continue to grow along the lattice direction of the substrate layer 101. It can also be a heterogeneous epitaxial layer 102. The specific growth temperature and other process conditions can be the same as existing processes or can be adapted. Optionally, the epitaxial layer 102 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods. Exemplarily, the material of the epitaxial layer 102 can include silicon, germanium, gallium arsenide, gallium phosphide (GaP), gallium nitride (GaN), etc., or other materials that can be epitaxially grown or deposited on the substrate layer 101 and can be used for device region processing.

[0053] Specifically, the first trench 105 is formed in the epitaxial layer 102 by trench etching. The epitaxial layer 102 may include a plurality of first trenches 105 and are spaced apart according to device performance requirements. The substrate also includes a first oxide layer 103 that conformally covers at least a portion of the surface of the epitaxial layer 102 and the inner wall of the first trench 105. Optionally, the first oxide layer 103 may be made of silicon oxide or other materials that can serve as the field oxide layer 107 for the gate.

[0054] In a possible implementation, S11 may include S111-S113:

[0055] S111: Provides the initial substrate;

[0056] S112: Trench etching is performed on the epitaxial layer 102 to form the first trench 105;

[0057] S113: A first oxide layer 103 is formed by oxide film deposition, which conformally covers at least a portion of the surface of the epitaxial layer 102 and the inner wall of the first trench 105.

[0058] Specifically, referring to Figure 3, the initial substrate includes a base layer 101 and an epitaxial layer 102 located on one side of the base layer 101. Trench etching can be performed using a mask for wet etching or dry etching. Preferably, a dry etching method is used, and more preferably, an isotropic dry etching method is used to form a first trench 105 with high dimensional accuracy and flat inner walls, thereby improving the flatness of the first oxide layer 103.

[0059] Optionally, the oxide film deposition in S113 is a deposition process of the first thin layer of the field oxide layer 107, which can be achieved by methods such as thermal oxidation, chemical vapor deposition, physical vapor deposition, and atomic layer deposition. Taking the formation of a silicon dioxide oxide layer by thermal oxidation as an example, polycrystalline silicon material is first deposited in the epitaxial layer 102 and the first trench 105, and then thermal oxidation is performed to obtain the first oxide layer 103. The thermal oxidation treatment can be dry oxygen or wet oxygen thermal treatment, preferably wet oxygen thermal treatment. Taking the deposition method as an example, oxide material can be deposited on the surface of the epitaxial layer 102 and the first trench 105 to form the first oxide layer 103, as shown in Figure 4.

[0060] By forming a first oxide layer 103 with conformal coverage, it can serve as a subsequent field oxygen structure and as an isolation layer in the preparation process of the second oxide layer 104, thus avoiding epitaxial layer ion back diffusion and structural damage during the preparation process of the second oxide layer 104.

[0061] S12: A polysilicon structure 201 is formed to fill the first trench 105. The doping concentration of the polysilicon structure 201 gradually decreases along the direction L from the bottom to the top of the first trench 105.

[0062] Specifically, referring to Figures 5-6, a polysilicon structure 201 is formed on the first oxide layer 103 in the first trench 105 and fills the first trench 105. The polysilicon structure 201 can be formed by polysilicon deposition.

[0063] Optionally, the ion doping type of the polysilicon structure 201 can be N-type doping or P-type doping, which can be selected based on the functional requirements of the device. Exemplarily, the doping element can be one or more of boron (B), aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi), or other elements capable of P-type or N-type doping. In some embodiments, P-type doping is used, and the doping element can be boron (B), aluminum (Al), gallium (Ga), and indium (In), etc. In other embodiments, the substrate isolation layer 110 is N-type doped, and the doping element can be phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), etc.

[0064] In a possible implementation, along the depth direction of the first trench 105, the doping concentration of the polysilicon structure 201 decreases stepwise or gradually from the bottom to the top of the trench. Preferably, the gradual decrease can be linear. The doping concentration refers to the concentration of dopant elements in the polysilicon structure 201. Optionally, the polysilicon structure 201 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other methods.

[0065] In some embodiments, the polysilicon structure 201 can be formed by two or more deposition processes and corresponding etch-back processes. The polysilicon structure 201 includes multiple polysilicon layers 202 stacked sequentially along the depth direction of the first trench 105. Each deposition process and etch-back process forms one polysilicon layer 202, and the doping concentration of each polysilicon layer 202 changes gradually. Accordingly, S12 may include: repeatedly performing multiple doped polysilicon deposition processes and polysilicon etch-back processes in the first trench 105 to form multiple polysilicon layers 202. The doped polysilicon deposition process refers to in-situ doping by adding dopant gas during the polysilicon deposition process.

[0066] Specifically, a first structure filling the first trench 105 is formed by polysilicon doping deposition. The first structure is then etched back until its residual thickness in the first trench 105 reaches the desired thickness, resulting in a first polysilicon layer 202. A second polysilicon doping deposition process is then performed to form a second structure filling the remaining portion of the first trench 105. This process is repeated until the residual thickness of the second structure reaches the desired thickness, resulting in a second polysilicon layer 202. This process is repeated until a polysilicon structure 201 is obtained. Thus, through multiple polysilicon doping depositions and etch-backs, polysilicon with vertically stepped or gradually varying doping concentrations within the trench can be formed.

[0067] Specifically, in the sequential steps of polysilicon deposition, the flow rate of the dopant gas gradually decreases. The dopant gas can be determined based on the type of dopant element required, and there are no specific limitations here. For example, the dopant gas used for P-doping can be PH3, etc. For example, referring to Figures 5 and 6, the polysilicon structure 201 includes 5 polysilicon layers 202, with the doping concentration increasing stepwise from top to bottom. The increasing gas flow rate from back to front will deposit polysilicon with increasing doping concentration. The thickness of the oxide layer formed after oxidation changes proportionally, and the step width also changes accordingly. The thickness of the polysilicon layer 202 can be controlled by the etching depth, specifically by adjusting the etching time.

[0068] In some cases, the flow rate of the dopant gas remains constant during the deposition of the monolayer polysilicon layer 202, while the flow rate of the dopant gas used in the subsequent polysilicon layer 202 is lower than that of the preceding polysilicon layer 202, to achieve a step-decreasing doping concentration. In other cases, in addition to the flow rate of the dopant gas used in the subsequent polysilicon layer 202 being lower than that of the preceding layer, the flow rate of the dopant gas also decreases sequentially during the deposition of the monolayer polysilicon layer 202, to achieve a gradually decreasing doping concentration.

[0069] Thus, by repeatedly performing N (N is a positive integer greater than or equal to 2) polycrystalline silicon deposition and etch-back with varying concentrations, polycrystalline silicon with N-1 level step concentrations can be formed. By adjusting the dopant gas flow rate and etch-back depth during the polycrystalline silicon deposition process, the step width and depth can be adjusted while achieving in-situ doping, so as to facilitate the control of the step thickness and depth of the subsequent second oxide layer 104.

[0070] Optionally, dry etching is used for the etching back process, preferably isotropic dry etching, to ensure that the trenches formed after the etching back are of precise size and have flat inner walls, which is beneficial for the precise control of the size and shape of the subsequent polysilicon layer 202. The etching rate and other process conditions of the etching back process can be set based on actual needs and are not limited here. The etching back method used has etching inertness to the first oxide layer 103.

[0071] In a possible implementation, the degree of variation in doping concentration of the polysilicon structure 201 is determined based on simulated structural design data. This simulated structural design data includes at least parameters such as the dimensions of the epitaxial layer 102, body region 106, second trench 204, field oxide layer 107, and shielding gate structure 205 in the shielding gate trench device. When the polysilicon comprises multiple polysilicon layers 202, the doping concentration and thickness of each polysilicon layer 202 are determined based on the simulated structural design data corresponding to the shielding gate device. The simulation structure design data is generated based on the preset electric field distribution of the body region 106 in the shielded gate device. The body region 106 includes a portion of the epitaxial layer 102, a field oxide layer 107 located in the epitaxial layer 102, and a shielding gate structure 205. The body region 106 of the device introduces a lateral electric field by setting the shielding gate structure 205 and the field oxide layer 107, which can assist in the depletion of the drift region and improve the breakdown voltage performance of the device. The lateral electric field of the body region 106 has a certain field strength distribution along the longitudinal direction. The preset electric field distribution is used to indicate the desired intensity distribution of the lateral electric field of the body region along the depth direction of the first trench 105. In the preset electric field distribution, the field strength in the middle of the body region 106 tends to be close to that at both ends. By working backward from the desired field strength distribution, the doping concentration and thickness of different polysilicon layers 202 are designed to make the lateral field strength distribution of the body region 106 of the device uniform and the field strength integral area (breakdown voltage performance) tend to be maximized, which significantly improves the problem of insufficient breakdown voltage performance caused by the low field strength in the middle of the existing structure (as shown in Figure 1).

[0072] S13: Perform a back etching process on the polysilicon structure 201 to form the second trench 204.

[0073] Specifically, deep trenches are formed by etching back the entire polysilicon structure 201, preferably using anisotropic dry etching. Referring to Figure 8, the polysilicon inner wall of the second trench 204 covers the first oxide layer 103 of the inner wall of the first trench 105, and the second trench 204 is used to form the shielding gate structure 205. Understandably, the doping concentration variation of the polysilicon inner wall is based on the doping concentration variation of the polysilicon structure 201. The higher the doping concentration, the thicker the oxide layer formed after polysilicon oxidation, and correspondingly, the smaller the width of the second trench 204 and the smaller the width of the corresponding area of ​​the shielding gate structure 205.

[0074] In a possible implementation, S13 may include S131-S133:

[0075] S131: Polish the polysilicon structure 201 until the first oxide layer 103 on the surface of the epitaxial layer 102 is exposed;

[0076] S132: A mask layer 301 is formed on the first oxide layer 103 and the polysilicon structure 201 to block the first oxide layer 103 and the area on the surface of the polysilicon structure 201 that is aligned with the polysilicon sidewall 203, and to expose the area on the surface of the polysilicon structure 201 that is aligned with the second trench 204.

[0077] S133: Dry etching is performed on the substrate with mask layer 301 to remove mask layer 301 and form second trench 204.

[0078] Specifically, after the polycrystalline silicon structure 201 is deposited, some excess polycrystalline silicon material covers the first oxide layer 103 on the epitaxial layer 102, as shown in Figure 5. The surface portion of the polycrystalline silicon structure 201 is removed by chemical mechanical polishing or other methods until the first oxide layer 103 is exposed. After polishing, the surface of the polycrystalline silicon structure 201 is preferably flush with the first oxide layer 103 on the epitaxial layer 102, as shown in Figure 6.

[0079] Further, referring to Figure 7, the mask layer 301 can be formed by photolithography patterning processes, specifically chemical vapor deposition, such as plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), sub-atmospheric chemical vapor deposition (SACVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or other types of chemical vapor deposition processes. The material of the mask layer 301 can be silicon nitride, titanium nitride, silicon dioxide, etc. Referring to Figures 7 and 8, the mask layer 301 is used to expose the polysilicon region corresponding to the second trench 204 to facilitate deep trench etching, thereby obtaining the second trench 204.

[0080] In a possible implementation, the sidewall inclination angle and bottom depth of the second trench 204 can be adjusted based on requirements to regulate the sidewall gradient change and bottom thickness of the second oxide layer 104. Accordingly, the etching process parameters are determined based on the preset etching inclination angle and the preset bottom thickness of the inner wall of the second trench corresponding to the simulation structural design data. The bottom thickness of the inner wall of the second trench refers to the distance between the bottom surface of the second trench and the surface of the first oxide layer away from the epitaxial layer. The preset etching inclination angle is negatively correlated with the gradient change of the sidewall of the second oxide layer 104. The preset etching inclination angle α is the angle between the sidewall of the second trench 204 and the surface of the substrate 101, which is the complementary angle between the sidewall of the second trench and the bottom wall of the second trench. That is, the smaller the preset etching inclination angle α, the more inclined the sidewall of the second trench 204 is, the narrower the bottom wall width is, and the greater the gradient change of the thickness of the sidewall of the second oxide layer 104, and vice versa. In one example, referring to Figure 12, a consistent doping concentration is used to fill the polysilicon structure 201. By adjusting the preset etching tilt angle α, an inclined second trench sidewall is formed. Along the direction L from the bottom to the top of the second trench 204, the thickness of the second oxide layer 104 gradually decreases, while the width of the shielding gate structure 205 gradually increases. Specifically, the etching process parameters may include, but are not limited to, the ratio of mixed etching gases, radio frequency parameters, such as the ratio of fluorocarbon gas to oxygen. By setting the etching process parameters with a preset etching tilt angle and a preset bottom thickness, a specific sidewall tilt angle can be achieved, thereby enabling free control of the thickness variation of the polysilicon sidewall 203 and the bottom thickness.

[0081] S14: Based on the oxidation process, a second oxide layer 104 is formed on the inner wall of the polysilicon of the second trench 204. The thickness of the second oxide layer 104 gradually decreases along the direction L from the bottom to the top of the first trench 105.

[0082] In this way, by taking advantage of the positive correlation between polysilicon doping concentration and oxide film thickness, polysilicon with longitudinal multi-level stepped or gradual doping concentration is formed in the trench. Then, secondary trench etching and wet oxidation are performed to form multi-level stepped field oxide with freely adjustable width and depth or to form a field oxide with gradual thickness in one step.

[0083] Optionally, the oxidation treatment of the polysilicon inner wall can be a dry oxygen thermal oxidation process or a wet oxygen thermal oxidation process. In a preferred embodiment, the oxidation treatment of the polysilicon inner wall of the second trench 204 adopts a wet oxygen thermal oxidation process, so that the difference in oxide layer thickness formed by polysilicon with different doping concentrations is more significant, thereby improving the distribution modulation effect of the transverse electric field in the bulk region. After the polysilicon inner wall oxidation is completed, a field oxide layer 107 with gradually varying or stepped thickness is formed.

[0084] Understandably, the thickness of the second oxide layer 104 varies with the doping concentration of the polysilicon sidewall 203. In some embodiments, the doping concentration of the polysilicon structure 201 decreases in a stepwise manner along the direction from the bottom to the top of the first trench 105, and the thickness of the second oxide layer 104 decreases in a stepwise manner. In other embodiments, the doping concentration of the polysilicon structure 201 decreases gradually along the direction from the bottom to the top of the first trench 105, and the thickness of the second oxide layer 104 decreases gradually.

[0085] In summary, this application forms a filled polysilicon structure 201 in the first trench 105 of the epitaxial layer 102, and the doping concentration of the polysilicon structure 201 gradually decreases from the bottom to the top of the first trench 105, forming a prestructure for forming field oxide. Then, the polysilicon structure 201 is etched back to form a second trench 204, resulting in a trench inner wall with varying doping concentration. Subsequently, the polysilicon inner wall is oxidized by an oxidation process to form a second oxide layer 104. Due to the change in doping concentration, the thickness of the second oxide layer 104 also changes, thus bonding with the first oxide layer 103 to form a field oxide layer 107 with a gradually varying thickness from the bottom to the top of the trench. The width of the shielding gate structure 205 in the second trench 204 can be freely adjusted to significantly optimize the low field strength in the middle of the body region 106, thereby maximizing the field strength integral area of ​​the body region 106 and effectively improving the breakdown voltage performance of the device. Furthermore, in the fabrication process of the second oxide layer 104, only one thermal oxidation treatment is required, resulting in a small thermal budget and avoiding the back diffusion problem of dopant impurities in the substrate, thus preventing a reduction in the breakdown voltage performance of the device. In addition, the thickness and thickness variation of the field oxide layer 107 can be freely adjusted by modulating the doping concentration of the polysilicon structure 201 in the trench, without limiting the field oxide thickness. The structure fabrication has a high degree of freedom and can be adapted to breakdown voltage devices with various voltage requirements.

[0086] Based on some or all of the above embodiments, in a possible embodiment, referring to FIG10, after S14, the preparation method further includes S15: forming a shielding grid structure 205 conforming to the second oxide layer 104 in the second trench 204, and the width of the shielding grid structure 205 gradually increases along the direction L from the bottom to the top of the second trench 204 to achieve uniform distribution of electric field strength and improve pressure resistance performance.

[0087] In some embodiments, referring to Figures 9 and 10, the thickness of the second oxide layer 104 decreases in a stepped manner along the direction L from the bottom to the top of the second trench 204, and the width of the shielding grid structure 205 increases in a stepped manner.

[0088] In a possible implementation, the shielding gate structure 205 fills a portion of the second trench 204. In the fabrication process of the shielding gate trench device, in addition to the above-mentioned process steps, it also includes gate formation, body region 106 doping, source doping, and contact hole formation. For example, the formation process of the gate structure 206 can specifically involve forming an isolation oxide layer 207 on top of the shielding gate structure 205 as shown in Figure 11. The isolation oxide layer 207 is used to isolate the gate and the shielding gate. The gate structure 206 is then further formed on the isolation oxide layer 207. A gate dielectric layer can also be covered on the surface of the epitaxial layer 102 and the surface of the first trench 105, and contact holes can be formed. The gate material and the shielding gate material can be polysilicon, etc. In other embodiments, the gate material and the shielding gate material can also be metal gate materials such as copper, aluminum, tungsten, chromium, titanium, silver, platinum, nickel, or gold. The above gate formation process is only an exemplary scheme, and this application does not limit the gate fabrication method.

[0089] In related technologies, the preparation process of the field oxide layer 107 can also involve first filling the trench with polycrystalline silicon material, and then using the mask layer 301 to perform multiple trench etchings of different widths, followed by sidewall thermal oxidation after each etching, to prepare a stepped field plate. However, this method is difficult to guarantee in terms of trench size and precision, has a high thermal budget, and the doping concentration of the substrate layer 101 is higher than that of the epitaxial layer 102. Multiple thermal oxidation processes cause ions in the substrate layer 101 to diffuse back to the epitaxial layer 102, resulting in an increase in the doping concentration of the epitaxial layer 102, highlighting the back diffusion problem and severely affecting the device's withstand voltage performance. Alternatively, a composite field oxide structure can be used to form a stepped field plate through the difference in corrosion rates. That is, a composite oxide layer made of two or more materials is formed on the inner wall of the trench. The differences in the density and material properties of the different material layers lead to different corrosion rates of the oxide layer (such as the corrosion rate of hydrofluoric acid), and the remaining parts of each material will form a stepped field oxide. However, the field oxide layer 107 prepared by this method is too thick and is only suitable for devices with high voltage and thick field plates. When a thinner field oxide layer 107 is required, it is not easy to generate steps during the corrosion process and the material selection is greatly limited.

[0090] The solution of this application forms a polycrystalline silicon structure 201 with gradually varying doping concentration in the first trench 105 and etches back to form a corresponding polycrystalline silicon inner wall. Based on the characteristic that the higher the doping concentration of polycrystalline silicon, the thicker the oxide layer, a field oxide layer 107 with gradually varying vertical thickness is formed. The process can be carried out only once with thermal oxidation, resulting in a small thermal budget. Moreover, it can achieve multi-layer field oxide steps with arbitrary depth and width by adjusting the doping concentration and etching depth according to the simulation design structure requirements. The structure fabrication has a high degree of freedom and is suitable for field oxide fabrication of various thicknesses, thereby meeting the process development requirements of low, medium and high voltage SGT. Compared to the device structure shown in Figure 1, the field strength distribution in the device body region 106 of the shielding trench device formed using the technical solution of this application is significantly improved. Referring to Figure 13, the blue curve in the figure represents the field strength distribution in the body region of the device structure in Figure 1, and the green dashed line represents the simulated field strength distribution in the body region based on the device structure in Figure 11. It can be seen that the field strength distribution in the body region is uniform and the field strength integral area tends to be maximized, which significantly improves the device withstand voltage performance defect caused by the low field strength in the middle.

[0091] The shielding trench device of this application is described below with reference to Figure 11. It should be understood that the shielding trench device in the figure is only a technical solution of one specific embodiment of this application, and the shielding trench device of this application may include fewer or more structural features, and is not limited to the device structure described in the figure.

[0092] The shielded gate trench device includes a substrate, a first oxide layer 103, and a field oxide layer 107. The substrate includes an epitaxial layer 102 and a first trench 105 located in the epitaxial layer 102. The first oxide layer 103 covers at least a portion of the surface of the epitaxial layer 102 and the inner wall of the first trench. The field oxide layer 107 is disposed on the inner wall of the first trench, and the field oxide layer 107 surrounds and forms a second trench 204. The thickness of the field oxide layer 107 gradually decreases along the direction from the bottom to the top of the first trench 105.

[0093] In a possible implementation, the thickness of the field oxide layer 107 decreases in a stepwise manner along the direction from the bottom to the top of the first trench 105; or, the thickness of the field oxide layer 107 decreases gradually along the direction from the bottom to the top of the first trench 105.

[0094] In a possible implementation, the shielding trench device further includes a shielding grid structure 205 formed in the second trench 204. The shielding grid structure 205 conformally fills a portion of the second trench 204, and the width of the shielding grid structure 205 gradually increases along the direction from the bottom to the top of the second trench 204.

[0095] In a possible implementation, the width of the shielding grid structure 205 increases in a stepped manner along the direction from the bottom to the top of the second groove 204; or, the width of the shielding grid structure 205 increases gradually along the direction from the bottom to the top of the second groove 204.

[0096] In a possible implementation, the shielded gate trench device further includes an isolation oxide layer 207 and a gate structure 206 located within the second trench 204 and stacked above the shielded gate structure 205, with the isolation oxide layer 207 located between the shielded gate structure 205 and the gate structure 206.

[0097] It should be noted that the above embodiments of the shielding trench device and the preparation method are based on the same application concept, and the shielding trench device can be prepared by the above preparation method of the shielding trench device.

[0098] This application also provides an electronic device including the aforementioned shielded trench device. Specifically, the electronic device includes the shielded trench device and electronic components connected to the shielded trench device.

[0099] The electronic device in this application embodiment can be selected from any electronic product or device such as mobile phone, PDA, tablet computer, laptop computer, game console, television, video compact disc (VCD), digital video disc (DVD), navigator, camera, camcorder, voice recorder, MP3, MP4, PlayStation Portable (PSP), etc., or it can be any intermediate product of electronic device including the above-mentioned shielding trench device.

[0100] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0101] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0102] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0103] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a shielded gate trench device, characterized in that, include: A substrate is provided, the substrate including an epitaxial layer, a first trench located in the epitaxial layer, and a first oxide layer covering at least a portion of the surface of the epitaxial layer and the inner wall of the first trench; A polycrystalline silicon structure is formed to fill the first trench, and the doping concentration of the polycrystalline silicon structure gradually decreases along the direction from the bottom to the top of the first trench. The polysilicon structure is etched back to form a second trench. The polysilicon inner wall of the second trench is covered with the first oxide layer of the inner wall of the first trench. The second trench is used to form a shielding gate structure. An oxidation process is used to form a second oxide layer on the inner wall of the polycrystalline silicon of the second trench. The thickness of the second oxide layer gradually decreases along the direction from the bottom to the top of the first trench.

2. The preparation method according to claim 1, characterized in that, Along the direction from the bottom to the top of the first trench, the doping concentration of the polycrystalline silicon structure decreases in a stepwise manner, and the thickness of the second oxide layer decreases in a stepwise manner; or, Along the direction from the bottom to the top of the first trench, the doping concentration of the polycrystalline silicon structure gradually decreases, and the thickness of the second oxide layer gradually decreases.

3. The preparation method according to claim 1, characterized in that, The polysilicon structure comprises multiple polysilicon layers stacked sequentially along the depth direction of the first trench, wherein the doping concentration of each polysilicon layer varies progressively; the polysilicon structure filling the first trench comprises: In the first trench, multiple polysilicon doping deposition processes and polysilicon etch-back processes are repeatedly performed to form the multilayer polysilicon layer, and the flow rate of the dopant gas used in each polysilicon doping deposition step is gradually reduced in time.

4. The preparation method according to claim 3, characterized in that, The doping concentration and thickness of each polysilicon layer are determined based on the simulation structure design data corresponding to the shielding gate device. The simulation structure design data is generated based on the preset electric field distribution in the body region of the shielding gate device. The preset electric field distribution is used to indicate the desired intensity distribution of the transverse electric field in the body region along the depth direction of the first trench.

5. The preparation method according to claim 1, characterized in that, The oxidation treatment of the polycrystalline silicon inner wall of the second trench adopts a wet oxygen thermal oxidation process.

6. The preparation method according to any one of claims 1-5, characterized in that, The substrate provided includes: An initial substrate is provided, the initial substrate comprising a base layer and an epitaxial layer located on one side of the base layer; The epitaxial layer is etched with trenches to form the first trench; The first oxide layer is formed by depositing an oxide film to form a conformal covering at least a portion of the surface of the epitaxial layer and the inner wall of the first trench.

7. The preparation method according to any one of claims 1-5, characterized in that, The step of etching back the polysilicon structure to form the second trench includes: The polycrystalline silicon structure is polished until the first oxide layer on the surface of the epitaxial layer is exposed; A mask layer is formed on the first oxide layer and the polysilicon structure to block the first oxide layer and the area where the surface of the polysilicon structure is aligned with the sidewall of the polysilicon structure, and to expose the area where the surface of the polysilicon structure is aligned with the second trench. The substrate with the mask layer is subjected to dry etching and the mask layer is removed to form the second trench.

8. The preparation method according to claim 7, characterized in that, The etching process parameters are determined based on the preset etching angle corresponding to the simulation structure design data and the preset bottom thickness of the inner wall of the second trench. The preset etching angle is negatively correlated with the gradient of the change of the sidewall of the second oxide layer. The preset etching angle refers to the angle between the sidewall of the second trench and the surface of the substrate, which is the complementary angle between the sidewall of the second trench and the bottom wall of the second trench.

9. The preparation method according to any one of claims 1-5, characterized in that, After the second oxide layer is formed on the inner wall of the polycrystalline silicon of the second trench based on the oxidation treatment, the preparation method further includes: A shielding grid structure conforming to the second oxide layer is formed in the second trench, and the width of the shielding grid structure gradually increases along the direction from the bottom to the top of the second trench.

10. A shielding trench device, characterized in that, The shielding trench device is prepared based on the preparation method described in any one of claims 1-9.

11. The shielding trench device according to claim 10, characterized in that, The shielding trench device includes: The substrate includes an epitaxial layer and a first trench located in the epitaxial layer; A first oxide layer covers at least a portion of the surface of the epitaxial layer and the inner wall of the first trench; An oxygen layer is disposed on the inner wall of the first trench, and the oxygen layer surrounds and forms a second trench. The thickness of the oxygen layer gradually decreases along the direction from the bottom to the top of the first trench.

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