Storage array and preparation method therefor, and memory and electronic device

Abstract

The embodiments of the present application relate to the technical field of electronic devices. Provided are a storage array and a preparation method therefor, and a memory and an electronic device. The storage array comprises a substrate, a stacking structure, a plurality of second electrodes and a ferroelectric layer. The stacking structure comprises a plurality of stacking groups; each stacking group comprises a plurality of electrode stacks arranged at intervals in a first direction; each electrode stack comprises a plurality of first electrodes stacked and arranged at intervals in a third direction; the orthographic projections, on the substrate, of electrode stacks belonging to two adjacent stacking groups are at least partially staggered relative to each other, and are alternately arranged in the first direction. Each second electrode penetrates electrode stacks in at least one stacking group, and electrode stacks in two adjacent stacking groups are penetrated by different second electrodes. At least a portion of the ferroelectric layer is arranged between the first electrodes and the second electrodes. The problem of signal interference of the memory can be alleviated without increasing additional planar design space, and the storage capacity of the memory can also be improved.

Description

Storage arrays and their fabrication methods, memory, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411844642.X, filed on December 13, 2024, entitled "Memory Array and Method of Fabrication Thereof, Memory, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic device technology, and in particular to a storage array and its fabrication method, a memory, and an electronic device. Background Technology

[0003] Memory is a device used to store information. It typically involves digitizing the information and then storing it using media such as electricity, magnetism, or optics. Ferro-electric random-access memory (FeRAM), as a new type of memory, is increasingly being used due to its advantages over traditional dynamic random-access memory (DRAM) or flash memory, including lower read / write voltage, lower power consumption, smaller device size, higher read / write speed, better cycle performance, radiation resistance, and non-volatility.

[0004] To meet the demands of high-density storage, DRAM (such as FeRAM) has evolved into a 1TnC storage structure. In a 1TnC storage structure, one transistor (T) can control the charging and discharging of multiple capacitors (C). The transistor controls the switching on and off of electrical signals, while the capacitors store electrical charge, i.e., store information.

[0005] However, the arrangement of multiple capacitors can lead to signal interference in the memory, and the value of n (i.e., the number of capacitors that a transistor can control) in the 1TnC memory structure is also limited. These problems will affect the further development of memory. Summary of the Invention

[0006] This application provides a storage array and its fabrication method, a memory, and an electronic device. The purpose is to alleviate the signal interference problem of the memory without increasing the additional planar design space, while increasing the number of capacitors in the memory, optimizing the electrical performance of the memory, and increasing the storage capacity of the memory.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] In one aspect, a memory array is provided, comprising a substrate, a stacked structure, multiple second electrodes, and a ferroelectric layer.

[0009] A stacked structure is disposed on a substrate, comprising multiple stacked groups stacked along a third direction; each stacked group includes multiple electrode stacks spaced apart along a first direction; each electrode stack includes multiple first electrodes stacked and spaced apart along a third direction; at least a portion of the orthographic projections of the electrode stacks in adjacent stacked groups onto the substrate are staggered, and in adjacent stacked groups, at least a portion of the orthographic projection of at least one electrode stack in one stacked group onto the substrate is located between the orthographic projections of two adjacent electrode stacks in the other stacked group onto the substrate; the first direction is parallel to the substrate, and the third direction is perpendicular to the substrate. Multiple second electrodes are spaced apart on the substrate along a direction parallel to the substrate and are connected to the substrate; each second electrode penetrates at least one electrode stack in a stacked group, and the electrode stacks in adjacent stacked groups are penetrated by different second electrodes. At least a portion of a ferroelectric layer is disposed between the first and second electrodes.

[0010] In the storage array provided in this application embodiment, multiple first electrodes located on the same layer are spaced apart from each other. That is, the entire electrode layer is cut into multiple first electrodes, reducing the number of ferroelectric capacitors sharing a common electrode, thereby reducing the number of read and write operations corresponding to a common electrode. This reduces or eliminates the interference experienced by each ferroelectric capacitor, lowers the probability of malfunctions in the storage array, improves the reliability of information storage in the storage array, and reduces the probability of information loss or errors.

[0011] Furthermore, in this memory array, the first electrodes in two adjacent stacked groups are staggered in the third direction so that they can be penetrated by different second electrodes. This allows for an increase in the number of stacked ferroelectric capacitors in the third direction while ensuring that the number of first electrodes penetrated by each second electrode is less than the number of all electrode layers in the stacked structure (each electrode layer includes multiple first electrodes located on the same layer). This avoids excessive ferroelectric capacitors stacked on a single second electrode, which could affect the performance of the ferroelectric capacitors. At the same time, the staggered portion of the first electrodes in two adjacent stacked groups in the third direction provides design space for the penetration of the second electrodes. At least a portion of the orthographic projection of the first electrode in one stacked group onto the substrate is located between the orthographic projections of two adjacent first electrodes in the other stacked group along the first direction onto the substrate. In other words, the design space reserved for the second electrode to pass through the first electrode in one stacked group is located between two adjacent first electrodes in the other stacked group along the first direction. This design space utilizes the space at the break point when the electrode layer is broken into multiple first electrodes (i.e., the space between two adjacent first electrodes) and does not additionally occupy the design space of the plane containing the first and second directions.

[0012] That is, by utilizing the gaps between the first electrodes, the storage array can achieve the stacking of ferroelectric capacitors in the third direction without increasing the number of ferroelectric capacitors on each second electrode or increasing the horizontal design space, thereby improving the storage capacity of the storage array.

[0013] In a possible implementation of the first aspect, in two adjacent stacked groups, the orthographic projections of multiple electrode stacks on the substrate in one stacked group and the orthographic projections of multiple electrode stacks on the substrate in the other stacked group are sequentially alternately arranged along a first direction.

[0014] That is, in two adjacent stack groups, the gap between each pair of adjacent electrode stacks in one stack group is positioned directly opposite the electrode stacks in the other stack group in the third direction. This allows each second electrode that penetrates the electrode stacks in the other stack group to be placed within the "gap," so that all gaps are utilized. This achieves a multiple increase in the number of stacked ferroelectric capacitors and ensures that each second electrode only penetrates the electrode stacks (i.e., the first electrodes) of one of the two adjacent stack groups, while also maximizing the utilization of the design space.

[0015] In one possible implementation of the first aspect, the first electrode through which the second electrode passes is disposed around the surface of the second electrode extending in a third direction, so that the first electrode can be directly opposite the entire circumferential side of the second electrode, ensuring that the ferroelectric capacitor formed by the two has a large effective capacitance area.

[0016] In a possible implementation of the first aspect, at least a portion of the second electrode includes a first sub-part and a second sub-part, which are stacked in a third direction. The first sub-part and the second sub-part respectively penetrate two adjacent stacked groups, with the first sub-part penetrating the electrode stack and the second sub-part located between two adjacent electrode stacks in the first direction.

[0017] The first sub-part allows the second electrode to have a face-to-face area with the first electrode, thereby forming a ferroelectric capacitor. The second sub-part electrically connects the ferroelectric capacitor to the substrate or to other ferroelectric capacitors in the stack. At the same time, the second sub-part is disposed between adjacent first electrodes, which realizes the utilization of the gap formed when the electrode layer is disconnected (i.e., the space between adjacent first electrodes) and avoids occupying additional design space on the plane of the first and second directions.

[0018] In one possible implementation of the first aspect, the first sub-part and the second sub-part are integrally formed. For example, they can be integrally molded. For example, a through-hole can be formed that simultaneously penetrates all stacked groups, and then a second electrode can be formed in the through-hole, so that the first sub-part and the second sub-part are integrally formed, saving fabrication steps.

[0019] In one possible implementation of the first aspect, each of the multiple second electrodes passes through multiple stacked groups, so that the lengths of the multiple second electrodes are approximately the same and their positions are relatively regular, so that the force at different positions of the storage array is more uniform and the structural stability of the storage array is improved.

[0020] In one possible implementation of the first aspect, at least one second electrode extends through all stacked groups except for the stacked group furthest from the substrate.

[0021] This structural design can reduce the difficulty of fabricating some of the second electrodes, or reduce the number of fabrication steps for some of the second electrodes. For example, some second electrodes only require the fabrication of the first sub-part, without the need to fabricate the second sub-part.

[0022] In one possible implementation of the first aspect, a portion of the ferroelectric layer is also deposited on two surfaces of the first electrode that are disposed opposite each other along a third direction; or, the ferroelectric layer is deposited on the surface of the second electrode that extends along a third direction.

[0023] Both implementations allow the ferroelectric layer to be located between the first and second electrodes, thereby forming a ferroelectric capacitor. These two implementations can correspond to different manufacturing processes, making the memory array suitable for various process scenarios and improving the fabrication flexibility of the memory array.

[0024] In one possible implementation of the first aspect, the first electrode is strip-shaped and extends along a second direction; the second direction is parallel to the substrate and intersects the first direction. A plurality of second electrodes are arranged in an array along the first and second directions; the plurality of second electrodes arranged along the second direction penetrate the same first electrode.

[0025] That is, multiple ferroelectric capacitors arranged along the second direction can share the first electrode, which makes it convenient for a single trace electrically connected to the first electrode to transmit electrical signals to multiple ferroelectric capacitors arranged along the second direction simultaneously during data read and write, thereby reducing the number of traces for transmitting electrical signals to ferroelectric capacitors and reducing the design space occupied by the storage array.

[0026] In one possible implementation of the first aspect, among the plurality of second electrodes arranged along the first direction, different second electrodes pass through different first electrodes, that is, the first electrodes in any two memories arranged along the first direction are independent of each other.

[0027] During data read / write operations, a word line selects a column of transistors, a bit line selects a row of transistors, and transistors at the intersection of word and bit lines are selected simultaneously. This selects a string of ferroelectric capacitors connected to the transistor. When the first electrodes in any two memories arranged along the first direction are independent of each other, one first electrode can select one of the ferroelectric capacitors in the string. That is, in this structure, only one ferroelectric capacitor can be selected at a time for precise data read / write.

[0028] In one possible implementation of the first aspect, at least two second electrodes arranged along the first direction penetrate the same first electrode, thereby reducing the number of break points when the electrode layer is broken into multiple first electrodes, thus reducing the fabrication difficulty.

[0029] In a possible implementation of the first aspect, the memory array further includes a plurality of transistors, word lines, and bit lines. The plurality of transistors are arranged in an array along a first direction and a second direction, and are disposed on the side of the substrate away from the stacked structure; each transistor includes a third electrode, a fourth electrode, and a gate; the third electrodes of the plurality of transistors are electrically connected to the plurality of second electrodes, respectively. One of the word lines and bit lines extends along the first direction, and the other extends along the second direction; the word lines are electrically connected to the gate, and the bit lines are electrically connected to the fourth electrode.

[0030] For example, each word line extends along a second direction, allowing one word line to simultaneously control the transmission of gate signals of multiple transistors arranged along the second direction. Each bit line extends along a first direction, allowing one bit line to simultaneously control the transmission of source (or drain) signals of multiple transistors arranged along the first direction. By transmitting electrical signals to one word line and one bit line, a transistor can be selected, causing it to turn on, and a string of ferroelectric capacitors corresponding to that transistor can be selected. Then, by transmitting an electrical signal to a first electrode, the corresponding ferroelectric capacitor can be selected, thus realizing the writing or reading of data.

[0031] In a possible implementation of the first aspect, at least two second electrodes arranged along a first direction pass through the same first electrode. Alternatively, word lines extend along a second direction, and at least two word lines connected to at least two transistors electrically connected to the at least two second electrodes are connected in parallel; or, bit lines extend along a second direction, and at least two bit lines connected to at least two transistors electrically connected to the at least two second electrodes are connected in parallel.

[0032] That is, in this embodiment, although in terms of physical structure, a first electrode is penetrated by at least two second electrodes arranged along the first direction, in terms of electrical connection, at least two ferroelectric capacitors formed by the at least two second electrodes are connected in parallel. That is, the at least two ferroelectric capacitors together form a memory cell. A word line signal and a bit line signal can simultaneously select the at least two ferroelectric capacitors (a memory cell). Therefore, there is still no interference between adjacent memory cells along the first direction.

[0033] In one possible implementation of the first aspect, a plurality of second electrodes arranged in a second direction form a conductive group; the second electrodes in at least one pair of conductive groups arranged in the first direction are staggered from each other in the first direction.

[0034] By setting the second electrodes in at least one pair of conductive groups arranged in the first direction to be staggered in the first direction, the utilization rate of the multiple second electrodes on the plane (the plane containing the first and second directions) can be improved, and the distribution density of the multiple second electrodes can be increased, that is, the distribution density of the multiple ferroelectric capacitors in the memory array can be increased, which is beneficial to reducing the design space occupied by the memory array and realizing the miniaturization design of the memory array.

[0035] In a possible implementation of the first aspect, the memory array includes transistors, word lines, and bit lines. In this implementation, a plurality of second electrodes in each conductivity group are electrically connected to the same word line, and two word lines electrically connected to at least one pair of conductivity groups are electrically connected; or, a plurality of second electrodes in each conductivity group are electrically connected to the same bit line, and two bit lines electrically connected to at least one pair of conductivity groups are electrically connected.

[0036] The second electrodes in two adjacent conductive groups are staggered in the first direction. Therefore, each second electrode in the two conductive groups is electrically connected to a bit line extending along the first direction. That is, different second electrodes can be selected by different bit lines. When the two word lines corresponding to the two conductive groups are electrically connected, although a word line signal can select all the second electrodes in the two conductive groups, the bit lines are still independent of each other. Therefore, under the combined action of the word line and the bit line, only one ferroelectric capacitor will be selected. That is, in this structure, the number of external connections of word lines can be reduced while the memory array can achieve the selection of one ferroelectric capacitor. For example, it is not necessary to connect every word line externally. For example, word lines that are electrically connected in pairs can be connected externally only once.

[0037] Secondly, a method for fabricating a storage array is provided, the method comprising:

[0038] A stacked structure is formed on a substrate; the stacked structure includes multiple stacked groups stacked along a third direction; each stacked group includes multiple electrode stacks spaced apart along a first direction; each electrode stack includes multiple first electrodes stacked and spaced apart along a third direction; at least a portion of the orthographic projections of the electrode stacks in two adjacent stacked groups onto the substrate are staggered, and in two adjacent stacked groups, at least a portion of the orthographic projection of at least one electrode stack in one stacked group onto the substrate is located between the orthographic projections of two adjacent electrode stacks in the other stacked group onto the substrate; the first direction is parallel to the substrate, and the third direction is perpendicular to the substrate.

[0039] Multiple second electrodes are formed; the multiple second electrodes are disposed at intervals on the substrate in a direction parallel to the substrate and are connected to the substrate; each second electrode penetrates at least one set of electrode stacks, and the electrode stacks in two adjacent sets of stacks are penetrated by different second electrodes.

[0040] A ferroelectric layer is formed; at least a portion of the ferroelectric layer is disposed between the first electrode and the second electrode.

[0041] In the storage array prepared by the preparation method provided in this application embodiment, the electrode layer is cut into multiple first electrodes, reducing the number of ferroelectric capacitors sharing a common electrode, thereby reducing the number of read and write operations corresponding to a common electrode. This reduces or eliminates the interference experienced by each ferroelectric capacitor, lowers the probability of malfunction in the storage array, improves the reliability of information storage in the storage array, and reduces the probability of information loss or errors.

[0042] Furthermore, the storage array obtained by this fabrication method utilizes the gaps between the first electrodes to achieve the superposition of ferroelectric capacitors in the third direction in the storage array without increasing the number of ferroelectric capacitors on each second electrode or increasing the horizontal design space, thereby improving the storage capacity of the storage array.

[0043] In a possible implementation of the second aspect, forming a stacked structure on the substrate includes:

[0044] A stacked assembly is formed on a substrate; the stacked assembly includes multiple electrode layers and multiple insulating layers alternately stacked sequentially along a third direction. Multiple slots are formed through the stacked assembly, and insulating material is filled into the slots; the multiple slots are spaced apart along a first direction, and the multiple slots break the multiple electrode layers into multiple electrode stacks. A stacked assembly is formed again in a direction away from the substrate, and slots are formed again; the slots formed on adjacent stacked assemblies are staggered relative to each other in a third direction.

[0045] That is, in the embodiments of this application, the electrode layer can be broken into multiple first electrodes by slotting, and by controlling the setting position of the slots, the slots opened on the two adjacent stack groups are staggered in the third direction, thereby achieving the purpose of staggering the first electrodes in the two adjacent stack groups, so that the second electrode prepared subsequently can penetrate only the first electrode of one of the two adjacent stack groups.

[0046] In a possible implementation of the second aspect, after forming all stacked groups and breaking the multilayer electrode layers in each stacked group into multiple electrode stacks, multiple second electrodes are formed, thereby achieving the synchronous fabrication of all second electrodes and improving the fabrication efficiency of the memory array.

[0047] Alternatively, the plurality of second electrodes includes a plurality of first preset electrodes and a plurality of second preset electrodes. In two stacked groups arranged adjacent to each other in a third direction, the plurality of first preset electrodes penetrate the electrode stack in the stacked group closer to the substrate, and the plurality of second preset electrodes penetrate the electrode stack in the stacked group farther from the substrate. The formation of the plurality of second electrodes includes: forming the plurality of first preset electrodes before the step of forming the stacked groups again in the direction away from the substrate and creating grooves again; and forming the plurality of second preset electrodes after the step of forming the stacked groups again in the direction away from the substrate and creating grooves again.

[0048] That is, after each stack group is completed and before another stack group is prepared, the second electrode corresponding to the prepared stack group is formed, thereby avoiding the need to make through holes with a large depth-to-width ratio when forming the second electrode, so as to reduce the difficulty of preparation.

[0049] In a possible implementation of the second aspect, each second electrode includes a first sub-part and a second sub-part, which are stacked in a third direction; the first sub-part extends through the electrode stack, and the second sub-part is located between two adjacent electrode stacks in the first direction.

[0050] In this method, the first and second sub-parts of the same second electrode are fabricated simultaneously, thereby reducing the number of drilling operations and improving fabrication efficiency. Alternatively, the first and second sub-parts of the same second electrode are fabricated in stages, thereby avoiding the fabrication of through-holes with large depth-to-width ratios and reducing the difficulty of drilling.

[0051] In this process, the first sub-part of one of the two second electrodes, which are respectively connected to the electrode stacks in different stacking groups, is prepared simultaneously with the second sub-part of the other second electrode. This can also reduce the number of drilling operations and improve the preparation efficiency.

[0052] In a possible implementation of the second aspect, forming a stacked group on the substrate includes: forming an initial stacked group on the substrate; the initial stacked group includes multiple layers of first functional layers and multiple layers of insulating layers alternately stacked sequentially along a third direction. The first functional layers are replaced with electrode layers to form the stacked group. A plurality of second electrodes are formed prior to replacing the first functional layers with electrode layers to form the stacked group.

[0053] In this embodiment, by setting the step of forming multiple second electrodes before the step of replacing the first functional layer with the electrode layer, the second electrodes can also play a supporting role while the second electrodes are being prepared, thus avoiding the problem of the stacked structure collapsing after the first functional layer is removed.

[0054] Thirdly, a memory is provided, comprising peripheral circuitry and a memory array provided in the embodiments of the first aspect. The memory array is electrically connected to the peripheral circuitry.

[0055] Fourthly, an electronic device is provided, comprising a bus and a memory provided in the embodiments of the third aspect. The memory is electrically connected to the bus.

[0056] The technical effects of the memory in the third aspect and the electronic devices in the fourth aspect can be seen in the technical effects of the memory array design in the first aspect, and will not be repeated here. Attached Figure Description

[0057] Figure 1 is a schematic diagram of an electronic device provided in an embodiment of this application;

[0058] Figure 2 is a schematic diagram of a memory structure provided in an embodiment of this application;

[0059] Figure 3 is a perspective view of a storage array provided in an embodiment of this application;

[0060] Figure 4 is another perspective view of the storage array provided in the embodiment of this application;

[0061] Figure 5 is a cross-sectional view of a storage array provided in an embodiment of this application;

[0062] Figure 6 is a cross-sectional view along section line A-A' in Figure 5;

[0063] Figure 7 is a cross-sectional view along section line B-B' in Figure 5;

[0064] Figure 8 is another cross-sectional view of the storage array provided in an embodiment of this application;

[0065] Figure 9 is a partial enlarged view of a storage array provided in an embodiment of this application;

[0066] Figure 10 is another partially enlarged view of the storage array provided in an embodiment of this application;

[0067] Figure 11 is a top view of a storage array provided in an embodiment of this application;

[0068] Figure 12 is a cross-sectional view along section line C-C' in Figure 11;

[0069] Figure 13 is another cross-sectional view of the storage array provided in an embodiment of this application;

[0070] Figure 14 is another cross-sectional view of the storage array provided in an embodiment of this application;

[0071] Figures 15 to 17 are some other top views of the storage array provided in the embodiments of this application;

[0072] Figures 18 to 20 are some fabrication flowcharts of the storage array provided in the embodiments of this application;

[0073] Figures 21 to 47 are structural diagrams corresponding to each fabrication step of the memory array. Detailed Implementation

[0074] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0075] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0076] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0077] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0078] Connection / linking: can refer to a mechanical or physical connection relationship, that is, A and B are connected or linked. It can mean that there are fastened components (such as screws, bolts, rivets, etc.) between A and B, or that A and B are in contact with each other and are difficult to separate. A and B can be fixed, detachable, or integrated; they can be directly connected or indirectly connected through an intermediate medium.

[0079] Coupling can be understood as direct coupling and / or indirect coupling. "Coupled connection" can be understood as a direct coupling connection and / or indirect coupling connection. Direct coupling, also known as "electrical connection," refers to components being in direct or indirect physical contact and electrically conductive. For example, in circuit construction, different components are connected through physical lines that can transmit electrical signals, such as copper foil or wires on a printed circuit board (PCB). "Indirect coupling" can be understood as two conductors conducting electricity through a gap or without contact. In one embodiment, indirect coupling can also be called capacitive coupling, for example, using the coupling between two conductive parts to form an equivalent capacitance to achieve signal transmission.

[0080] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0081] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0082] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0083] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0084] Furthermore, the scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0085] This application provides an electronic device, which can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, in-vehicle equipment, vehicles, and other different types of user equipment or terminal devices; the electronic device can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device.

[0086] Figure 1 is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of this application.

[0087] For example, as shown in FIG1, the electronic device 1000 may include a bus 205 and a system on chip (SoC) 210 connected to the bus 205.

[0088] The system-on-chip 210 can be used to process data, such as processing application data, processing image data, and caching temporary data.

[0089] For example, the system-on-chip 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and on-chip memory 213 for caching high-speed data.

[0090] For example, the on-chip memory 213 may be static random access memory (SRAM) or embedded flash (eflash), etc.

[0091] For example, the application processor 211, the image processing unit 212 and the on-chip memory 213 described above can be integrated into a single die, or they can be disposed in multiple dies respectively.

[0092] For example, as shown in FIG1, the electronic device 1000 may also include an off-chip memory 220 connected to the system-on-chip 210 via a bus 205.

[0093] For example, the off-chip memory 220 may be dynamic random access memory (DRAM). The off-chip memory 220 may be used to store volatile data, such as temporary data generated by the on-chip system 210. The storage capacity of the off-chip memory 220 is typically larger than that of the on-chip memory 213, but its read speed is typically slower than that of the on-chip memory 213.

[0094] For example, the system-on-chip 210 and the off-chip memory 220 can be packaged in a single package structure, such as 2.5D or 3D packaging, to achieve faster inter-chip data transfer rates.

[0095] For example, as shown in FIG1, the electronic device 1000 may also include a communication chip 230 and a power management chip 240 connected to the system-on-a-chip 210 via a bus 205.

[0096] The communication chip 230 can be used for protocol stack processing, or for amplifying and filtering analog radio frequency signals, or simultaneously perform the above functions. The power management chip 240 can be used to supply power to other chips.

[0097] It is understood that the structure of the electronic device 1000 shown in FIG1 does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 may include more or fewer components than those shown in FIG1, or may combine some of the components shown in FIG1, or may have a different arrangement of components than those shown in FIG1.

[0098] This application also provides a memory 100, which can be applied in the aforementioned electronic device 1000. For example, the memory 100 can be an on-chip memory 213 as shown in FIG1, or it can be an off-chip memory 220 as shown in FIG1. ​​This application does not limit the specific application scenario of the memory 100.

[0099] Figure 2 is a schematic diagram of the structure of the memory 100 provided in an embodiment of this application. As shown in Figure 2, the memory 100 includes a memory array 10 and peripheral circuitry 20.

[0100] The storage array 10 is connected to the peripheral circuit 20, which is used to control access to the storage array 10. For example, the peripheral circuit 20 can control the writing of data to the storage array 10 or control the reading of data from the storage array 10.

[0101] For example, the peripheral circuit 20 may include a word line selection circuit, a bit line selection circuit, a control circuit, and a read / write circuit, etc.

[0102] Referring to Figure 2, for example, the storage array 10 may include a plurality of array-distributed storage units G.

[0103] For example, when performing read and write operations on the memory array 10, the read and write circuit transmits control signals to the word line selection circuit and the bit line selection circuit through the control circuit. The word line selection circuit selects a column in the memory array 10, and the bit line selection circuit selects a row in the memory array 10. The word line selection circuit and the bit line selection circuit jointly determine the address of the memory cell G to be accessed.

[0104] For example, peripheral circuitry 20 may be disposed around memory array 10, for example, referring to FIG2, peripheral circuitry 20 is disposed on at least one side of memory array 10.

[0105] For example, the peripheral circuitry 20 may be stacked with the memory array 10, for instance, the memory array 10 may be stacked on top of the peripheral circuitry 20 (not shown in the figure).

[0106] This application also provides a storage array 10.

[0107] Figure 3 is a three-dimensional view of a ferroelectric capacitor in the storage array 10 provided in the embodiment of this application. Figure 4 is another three-dimensional view of the storage array 10 provided in the embodiment of this application (multiple ferroelectric capacitors are stacked). Figure 5 is a cross-sectional view of the storage array 10 provided in the embodiment of this application. Figure 6 is a cross-sectional view along section line A-A' in Figure 5. Figure 7 is a cross-sectional view along section line B-B' in Figure 5.

[0108] For example, referring to FIG4, the storage array 10 may include a plurality of ferroelectric capacitors C stacked in three dimensions (at least one ferroelectric capacitor C is used to form a storage cell G to realize signal storage). For example, the storage array 10 may be a DRAM with a 1TnC structure, or a FeRAM with a 1TnC structure. It is understood that any storage device that can be stacked in the vertical direction to increase storage density is within the protection scope of the storage array 10 referred to in the embodiments of this application. The specific type of storage array 10 in the embodiments of this application is not limited.

[0109] To avoid obscuring the view, only a portion of the structure of the memory array 10 is shown in Figure 4. For example, only the first electrode 31 and the second electrode 32 are shown, while the insulating layer 5 and the ferroelectric layer 4 are not shown. It is understood that the insulating layer 5 and the ferroelectric layer 4 are also present in the actual structure. The structure of the memory array 10 can be understood by combining Figures 5, 6, and 7 with Figure 4.

[0110] In some embodiments, as shown in FIG5, the memory array 10 includes a substrate 1, a stacked structure 2, a second electrode 32, and a ferroelectric layer 4.

[0111] Exemplarily, the material of substrate 1 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art. Alternatively, it may be made of non-conductive materials such as glass, plastic, or sapphire wafers. This application does not limit the material of substrate 1; any substrate with a load-bearing function capable of supporting the fabrication of components such as the stacked structure 2 is within the protection scope of this application.

[0112] Referring to Figure 5, the stacked structure 2 is disposed on the substrate 1. The stacked structure 2 includes multiple stacked groups N stacked along the third direction Z. Each stacked group N includes multiple electrode stacks W spaced apart along the first direction X. Each electrode stack W includes multiple first electrodes 31 stacked and spaced apart along the third direction Z.

[0113] Wherein, the first direction X is parallel to the substrate 1, and the third direction Z is perpendicular to the substrate 1, that is, the third direction Z is the thickness direction of the film layer of the substrate 1.

[0114] Referring to Figure 5, this embodiment of the application is only illustrated by taking the stacked structure 2 as an example, which includes two stacked groups N, and does not impose a limitation on the number of stacked groups N.

[0115] For example, referring to FIG5, each stack group N includes multiple electrode layers M stacked and spaced apart along the third direction Z. Referring to FIG5, each electrode layer M includes a plurality of first electrodes 31 spaced apart along the first direction X.

[0116] That is, in each stack group N, multiple first electrodes 31 arranged along the third direction Z form an electrode stack W, while multiple first electrodes 31 located in the same layer and arranged along the first direction X form an electrode layer M. "Electrode stack W" and "electrode layer M" are only a means of division adopted to facilitate the description of the arrangement of multiple first electrodes 31 in the stack group N.

[0117] For example, referring to FIG5, the stacked structure 2 further includes multiple insulating layers 5, which are disposed between two adjacent electrode layers M. For example, in each stack group N, multiple electrode layers M and multiple insulating layers 5 are stacked alternately in sequence to achieve electrical insulation between two adjacent electrode layers M, thereby facilitating the formation of different ferroelectric capacitors C that can be independently controlled for charging and discharging by the two adjacent electrode layers M.

[0118] For example, referring to Figure 5, an insulating material is also provided between two adjacent first electrodes 31 located in the same electrode layer M, thereby achieving electrical insulation between the two first electrodes 31. The insulating material can be the same as the material of the insulating layer 5.

[0119] For example, referring to Figures 4, 6 and 7, each first electrode 31 may be strip-shaped and may extend along the second direction Y.

[0120] The second direction Y is parallel to the substrate 1 and intersects the first direction X. For example, the second direction Y can be perpendicular to the first direction X.

[0121] The first electrode 31 can be used as a plate (PL) of the ferroelectric capacitor C, for example, as the common electrode of the ferroelectric capacitor C.

[0122] For example, the material of the first electrode 31 is conductive.

[0123] For example, the material of the first electrode 31 can be a metallic material, such as tungsten (W), titanium (Ti), copper (Cu), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), ruthenium (Ru), or other metals or alloys with conductive properties.

[0124] Alternatively, the material of the first electrode 31 may also be a semiconductor material, such as silicon (Si), titanium nitride (TiN), indium tin oxide (ITO), or other semiconductor materials.

[0125] For example, the first electrode 31 can be a single-layer structure or a multi-layer structure. In the case that the first electrode 31 is a multi-layer structure, the materials of the different layers can be different.

[0126] For example, referring to FIG3, the first electrode 31 may include a first sub-layer 31A and a second sub-layer 31B, wherein the material of the first sub-layer 31A may be TiN and the material of the second sub-layer 31B may be W.

[0127] Referring to Figures 4 and 5, and comparing Figures 6 and 7, the orthogonal projections of the electrode stacks W belonging to the two adjacent stack groups N on the substrate 1 are at least partially staggered.

[0128] That is, the first electrodes 31 belonging to two adjacent stack groups N are at least partially offset in the third direction Z.

[0129] That is, the orthogonal projections of the first electrode 31, which belong to two adjacent stack groups N, onto the substrate 1 are at least partially non-overlapping.

[0130] For example, the first electrodes 31 belonging to two adjacent stack groups N are completely offset in the third direction Z, that is, the orthogonal projections of the first electrodes 31 in the two adjacent stack groups N on the substrate 1 do not overlap at all.

[0131] Or, for example, referring to Figure 5, the first electrodes 31 in two adjacent stacked groups N have only their side portions (two opposite sides in the first direction X) overlapping in the third direction Z, and the middle portions of the first electrodes 31 in two adjacent stacked groups N are staggered.

[0132] In this configuration, the staggered portions of the first electrodes 31 in two adjacent stacked groups N are used to allow different second electrodes 32 to pass through.

[0133] Referring to Figures 5, 6 and 7, in two adjacent stack groups N, at least a portion of the orthogonal projection of at least one electrode stack W in one stack group N onto the substrate 1 is located between the orthogonal projections of two adjacent electrode stacks W onto the substrate 1 in the other stack group N.

[0134] That is, while the electrode stacks W belonging to two adjacent stack groups N are staggered in the third direction Z, at least one electrode stack W in one stack group N is also directly opposite the gap between two adjacent electrode stacks W in the other stack group N in the third direction Z. This allows the at least one electrode stack W to utilize the gap between two adjacent electrode stacks W in the other stack group N, making it easier for the second electrode 32 to pass through the "gap" and through the "at least one electrode stack W". In other words, it is easier for the second electrode 32 to pass through the two adjacent stack groups N to connect with the substrate 1, and only pass through the first electrode 31 in one of the two stack groups N. This achieves the stacking of two stack groups N, increases the storage capacity, and avoids the number of first electrodes 31 penetrated by the second electrode 32 from exceeding the limit value of the number of ferroelectric capacitors C that the second electrode 32 can form.

[0135] For example, in two adjacent stacked groups N, the orthographic projections of multiple electrode stacks W in one stacked group N onto the substrate 1 and the orthographic projections of multiple electrode stacks W on the substrate 1 in the other stacked group N are alternately arranged along the first direction X.

[0136] That is, the first electrodes 31 belonging to the two adjacent stack groups N are alternately arranged in the first direction X. In other words, the orthographic projections of the first electrodes 31 belonging to the two adjacent stack groups N on the substrate 1 are alternately arranged in the first direction X. That is, in the two adjacent stack groups N, at least a portion of the orthographic projection of the first electrode 31 in one stack group N on the substrate 1 is located between the orthographic projections of two adjacent first electrodes 31 on the substrate 1 in the other stack group N.

[0137] That is, in two adjacent stack groups N, the gap between each pair of adjacent electrode stacks W in one stack group N is set in the third direction Z to be directly opposite to the electrode stacks W in the other stack group N. This is so that each second electrode 32 used to penetrate the electrode stacks W in the other stack group N can be set in the "gap". This ensures that all gaps are utilized, thereby achieving a multiple increase in the number of stacked ferroelectric capacitors C and ensuring that each second electrode 32 only penetrates the electrode stacks W (i.e., the first electrode 31) of one stack group N in the two adjacent stack groups N, while also maximizing the utilization of the design space.

[0138] In other embodiments, the orthographic projections of multiple electrode stacks W in one stack group N onto the substrate 1 and the orthographic projections of multiple electrode stacks W in the other stack group N onto the substrate 1 can also be alternated along the first direction X in other ways (i.e., other rules besides "in sequence").

[0139] For example, in two adjacent stack groups N, only one electrode stack W in one stack group N is positioned directly opposite the gap between adjacent electrode stacks W in the other stack group N. That is, only one gap (the space between adjacent electrode stacks W) of the design space can be utilized to achieve the stacking of a smaller number of ferroelectric capacitors C (compared to the aforementioned sequential alternation).

[0140] Alternatively, for example, in two adjacent stacked groups N, the orthographic projections of multiple electrode stacks W in one stacked group N onto the substrate 1 and the orthographic projections of multiple electrode stacks W in the other stacked group N onto the substrate 1 can be alternately arranged in pairs along the first direction X, that is, alternating once every two (for example, in the upper and lower stacked groups N, in the lower stacked group N, only one electrode stack W is arranged directly above the gap of the odd or even columns). Similarly, they can be alternated once every three or more. This will not be elaborated here. The alternation method can be flexibly adjusted according to the storage capacity requirements. This application embodiment does not limit this.

[0141] Referring to Figure 5, a plurality of second electrodes 32 are disposed at intervals on the substrate 1 along a direction parallel to the substrate 1 and are connected to the substrate 1.

[0142] For example, referring to Figures 6 and 7, the plurality of second electrodes 32 can be arranged in an array along the first direction X and the second direction Y, with two adjacent second electrodes 32 in the first direction X spaced apart, and two adjacent second electrodes 32 in the second direction Y also spaced apart.

[0143] The second electrode 32 is used as another plate in the ferroelectric capacitor C of the storage array 10. For example, when the first electrode 31 is used as the common electrode of the ferroelectric capacitor C, the second electrode 32 can be used as the storage electrode (also known as the storage node SN) of the ferroelectric capacitor C to store charge, thereby realizing data storage.

[0144] Each second electrode 32 is connected to the substrate 1, thereby facilitating the transmission of electrical signals from circuits located in the substrate 1 or on the side of the substrate 1 away from the stacked structure 2 to the second electrode 32, thereby enabling the charging and discharging of the multiple ferroelectric capacitors C formed by the second electrode 32.

[0145] For example, referring to Figures 5 and 6, the second electrode 32 is columnar, and the center line of the second electrode 32 can extend along a third direction Z.

[0146] For example, the second electrode 32 can be cylindrical, prismatic, or other irregular cylindrical shapes.

[0147] For example, the second electrode 32 can also be a single-layer structure or a multi-layer structure. In the case that the second electrode 32 is a multi-layer structure, the materials of the different layers can be different.

[0148] For example, referring to Figure 3, the second electrode 32 may include a support post 32A and a conductive layer 32B. The conductive layer 32B surrounds the side of the support post 32A. Both the support post 32A and the conductive layer 32B can be conductive materials. For example, the material of the conductive layer 32B can be TiN, and the material of the support post 32A can be W.

[0149] The second electrode 32 has good conductivity. The material of the second electrode 32 can be found in the previous description of the first electrode 31, and will not be repeated here.

[0150] For example, the second electrode 32 and the first electrode 31 may be made of the same material or different materials.

[0151] For example, when both the second electrode 32 and the first electrode 31 are made of metal, the ferroelectric capacitor C in the storage array 10 has a metal-insulator-metal (MIM) structure.

[0152] Alternatively, for example, if one of the materials of the second electrode 32 and the first electrode 31 is a semiconductor material, the ferroelectric capacitor C in the storage array 10 is a metal-insulator-semiconductor (MIS) structure.

[0153] Referring to Figure 5, each second electrode 32 penetrates the electrode stack W.

[0154] That is, the second electrode 32 will penetrate the multiple first electrodes 31 stacked along the third direction Z.

[0155] The second electrode 32 penetrates the first electrode 31 so that the second electrode 32 and the first electrode 31 have a facing area (i.e., effective capacitance area), thereby facilitating the formation of a ferroelectric capacitor C.

[0156] For example, referring to FIG5, in two adjacent stack groups N, the portion of the gap between the first electrode 31 in one stack group N and the two adjacent first electrodes 31 in another stack group N that is directly opposite each other in the third direction Z (i.e., the portion of the first electrode 31 that is offset from the first electrode 31 in the other stack group N) is used to be penetrated by the second electrode 32. Thus, while ensuring that the second electrode 32 can be connected to the substrate 1 (i.e., the second electrode 32 penetrates the stack group W through the gap between two adjacent electrode stacks W in a certain stack group W and extends smoothly to the substrate 1), the second electrode 32 can also penetrate only the electrode stack W of one of the two adjacent stack groups N.

[0157] For example, referring to FIG5, at least one second electrode 32 penetrates the electrode stack W of one of two adjacent stack groups N and is located between two adjacent electrode stacks W in another stack group N. For example, the second electrode 32 used to penetrate the electrode stack W in the stack group N that is far away from the substrate 1 in the two adjacent stack groups N also penetrates the gap between two adjacent electrode stacks W in the stack group N that is close to the substrate 1, so that the second electrode 32 can also extend smoothly to the substrate 1 and connect to the substrate 1 even when the number of ferroelectric capacitors formed (i.e. the number of first electrodes 31 it penetrates) is small.

[0158] For example, referring to FIG5, the second electrodes 32 for penetrating the first electrodes 31 (or electrode stacks W) in two adjacent stack groups N are alternately arranged in the first direction X. For example, a plurality of second electrodes 32 for penetrating the electrode stacks W in one of the two adjacent stack groups N are alternately arranged in the first direction X with a plurality of second electrodes 32 for penetrating the electrode stacks W in the other stack group N, thereby forming a structure in which the electrode stacks W belonging to the two adjacent stack groups N are alternately staggered.

[0159] For example, referring to Figures 3, 5, 6 and 7, all sides of the second electrode 32 (the surface perpendicular to the substrate 1) penetrate the first electrode 31, so that the first electrode 31 can be arranged around (along the circumference of the second electrode 32) the side surface of the second electrode 32 (i.e. the surface extending along the third direction X), so that the first electrode 31 can be directly opposite the entire circumferential side surface of the second electrode 32, ensuring that the ferroelectric capacitor C formed by the two has a large effective capacitance area.

[0160] Referring to Figure 5, each second electrode 32 penetrates at least one stack group N of first electrodes 31 (or electrode stack W). In Figure 5, the second electrode 32 is used to illustrate the example of the second electrode 32 penetrating the first electrode 31 in one stack group N. It does not limit the number of stack groups N in which the second electrode 32 can penetrate the first electrode 31.

[0161] For example, in some other embodiments, the stacked structure 2 may include four stacked groups N, and among the plurality of second electrodes 32, each of the second electrodes 32 in some of the second electrodes 32 may penetrate the first electrode 31 in the first and third groups (arranged in a direction away from the substrate 1) of the stacked groups N, while each of the remaining second electrodes 32 may penetrate the first electrode 31 in the second and fourth groups of the stacked groups N.

[0162] Referring to Figure 5, the first electrode 31 in two adjacent stack groups N is penetrated by different second electrodes 32, that is, a second electrode 32 is only used to form a ferroelectric capacitor C with the first electrode 31 of one stack group N in two adjacent stack groups N.

[0163] For example, referring to Figure 5, the second electrodes 32 arranged adjacent to each other in the first direction X pass through the first electrodes 31 in different stacking groups N.

[0164] For example, in Figure 5, the first second electrode 32 from left to right penetrates the first electrode 31 in the upper layer (the layer away from the substrate 1) of the stacked group N, while the second second electrode 32 disposed adjacent to it penetrates the first electrode 31 in the lower layer (the layer close to the substrate 1) of the stacked group N.

[0165] For example, when the stacked structure 2 includes four or more stacked groups N, the stacked groups N in which the first electrode 31 penetrates by two adjacent second electrodes 32 are arranged alternately along the third direction Z.

[0166] Referring to Figures 3, 5, 6 and 7, at least a portion of the ferroelectric layer 4 is disposed between the first electrode 31 and the second electrode 32.

[0167] The ferroelectric layer 4 is electrically insulating so that the first electrode 31 and the second electrode 32 are electrically insulated from each other, thereby facilitating the formation of a ferroelectric capacitor C by the ferroelectric layer 4, the first electrode 31 and the second electrode 32. The ferroelectric capacitor C can reverse the polarization direction of the ferroelectric electrode, thereby realizing the data storage function.

[0168] For example, the material of the ferroelectric layer 4 may include one or more insulating materials such as aluminum oxide (Al2O3), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), titanium dioxide (TiO2), yttrium oxide (Y2O3), and silicon nitride (Si3N4).

[0169] For example, the ferroelectric layer 4 can be ferroelectric, that is, the material of the ferroelectric layer 4 can spontaneously polarize within a certain temperature range, and its spontaneous polarization direction can be reversed due to the reversal of the direction of the electric field, so that the capacitor formed by the third electrode layer 13, the ferroelectric layer 4 and the second electrode post 12 is a ferroelectric capacitor C, thereby improving the capacity of the ferroelectric capacitor C and the electrical performance of the storage array 10.

[0170] For example, the material of the ferroelectric layer 4 can be a ferroelectric material based on the hafnium oxide (HfO) material system. For instance, the material of the ferroelectric layer 4 can be zirconium (Zr)-doped hafnium dioxide (HfO2), silicon (Si)-doped HfO2, aluminum (Al)-doped HfO2, lanthanum (La)-doped HfO2, yttrium (Y)-doped HfO2, gadolinium (Gd)-doped HfO2, strontium (Sr)-doped HfO2, etc.

[0171] Alternatively, the material of ferroelectric layer 4 can also be a ferroelectric material in the hafnium zirconium oxide (HZO) system. For example, the material of ferroelectric layer 4 can be lanthanum (La)-doped HZO, yttrium (Y)-doped HZO, strontium (Sr)-doped HZO, gadolinium (Gd)-doped HZO, gadolinium-lanthanum (Gd / La) co-doped HZO, etc. The doping element can also be one or more of nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, neodymium, magnesium, barium, indium, gallium, calcium, and carbon.

[0172] Alternatively, the material of the ferroelectric layer 4 can also be a ferroelectric material system such as hafnium silicon oxide, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium zirconium lanthanum oxide, hafnium zirconium cerium oxide, hafnium zirconium yttrium oxide, or hafnium zirconium gadolinium oxide.

[0173] For example, the ferroelectric layer 4 can be a single-layer structure or a multi-layer structure. In the case that the ferroelectric layer 4 is a multi-layer structure, the materials of the different layers can be the same or different.

[0174] In some other embodiments, the electrode layer is a single layer (i.e., not disconnected into multiple first electrodes). Multiple ferroelectric capacitors located on the same layer share this electrode layer as a common electrode. When a ferroelectric capacitor is selected, the common electrode (electrode layer) corresponding to that ferroelectric capacitor is biased to a high potential. This causes a voltage difference to also be generated between the common electrode (electrode layer) of some ferroelectric capacitors that share the electrode layer with the selected ferroelectric capacitor and the storage electrode. This makes it possible for these ferroelectric capacitors that do not need to be selected to be mistakenly selected. Even if the voltage difference in these ferroelectric capacitors that do not need to be selected does not cause the ferroelectric capacitor to be selected, its ferroelectric material polarization direction (i.e., the stored information) will be interfered with by the voltage difference. During multiple read and write processes (i.e., the process of selecting a certain ferroelectric capacitor), ferroelectric capacitors that are interfered with multiple times are prone to problems such as charge degradation, information loss, or errors.

[0175] In the storage array 10 provided in this application embodiment, by cutting the electrode layer M into multiple first electrodes 31, the number of ferroelectric capacitors C sharing a common electrode is reduced. For example, the structure in which the entire layer of ferroelectric capacitors C shares a common electrode (the entire layer of electrode layers) can be adjusted to the structure in Figure 6 where only a column of ferroelectric capacitors C arranged along the second direction Y shares a common electrode (first electrode 31). This reduces the number of read and write operations corresponding to a common electrode, reduces the number of times each ferroelectric capacitor C is interfered with, or even eliminates interference altogether, reduces the probability of malfunction in the storage array 10, improves the reliability of information storage in the storage array 10, and reduces the probability of lost or incorrect stored information.

[0176] Furthermore, due to the dielectric capacitance between the two plates of a ferro-electric capacitor (FeCap), a self-loading effect occurs, limiting the number of ferro-electric capacitors C corresponding to a single second electrode 32 (i.e., the number of memory capacitors C stacked in the third direction Z). For example, when the uppermost ferro-electric capacitor C among the multiple ferro-electric capacitors formed by a single second electrode 32 in Figure 5 is selected, the potentials of the first electrode 31 and the second electrode 32 connected to that ferro-electric capacitor C change, generating a sufficient electric field between the two electrodes of the ferro-electric capacitor C to reverse the ferroelectric polarization direction and store information. During the process, all capacitors sharing the second electrode 32 will be charged and discharged, which will affect the performance of the topmost ferroelectric capacitor C (for example, it will cause signal delay and other problems). The more ferroelectric capacitors C formed by the second electrode 32, the greater the impact on the topmost ferroelectric capacitor C. In order to ensure the electrical performance of the storage array 10, the number of memory C stacked on the third direction Z cannot be increased arbitrarily. For example, only 8 layers of memory C can be stacked, or only 16 layers can be stacked, or at most 32 layers of memory C can be stacked, which limits the further improvement of the storage capacity of the storage array 10 on the third direction Z.

[0177] In the storage array 10 provided in this application embodiment, by setting the first electrode 31 in two adjacent stack groups N to be penetrated by different second electrodes 32, the number of stacked ferroelectric capacitors C (i.e., the number of stack groups N) in the third direction Z can be increased, while the number of first electrodes 31 penetrated by each second electrode 32 is less than the number of all electrode layers M in the stack structure 2, thus avoiding affecting the performance of the ferroelectric capacitors C. At the same time, by setting the first electrodes 31 (or electrode stacks W) in two adjacent stack groups N to be staggered in the third direction Z and alternately arranged in the first direction X, design space can be reserved for the penetration of the second electrode 32 (i.e., the staggered part of the first electrodes 31), and this design space utilizes the space at the break position when the electrode layer M is broken into multiple first electrodes 31 (i.e., the space between two adjacent first electrodes 31), without additionally occupying the design space of the plane in the first direction X and the second direction Y.

[0178] That is, the storage array 10 provided in this application embodiment can increase the number of ferroelectric capacitors C along the third direction Z without occupying additional design space in the plane where the first direction X and the second direction Y are located. At the same time, it can also ensure that the number of ferroelectric capacitors C formed by each second electrode 32 does not exceed the limit (i.e., the maximum value of n in the 1TnC storage structure), thereby increasing the storage capacity of the storage array 10 while ensuring the performance of the ferroelectric capacitors C.

[0179] For example, in the case where a second electrode 32 in the memory array 10 can only form 8 ferroelectric capacitors C with 8 layers of first electrodes 31 (i.e., 1T8C structure), referring to FIG5, the memory array 10 provided in this application embodiment may include two stack groups N, each stack group N forming 8 ferroelectric capacitors C, thereby forming 16 layers of ferroelectric capacitors C in the entire memory array 10 (i.e., doubling the storage capacity). At the same time, each second electrode 32 in each stack group N still only forms 8 ferroelectric capacitors C with 8 layers of first electrodes 31, which will not exceed the limit of the number of ferroelectric capacitors C that each second electrode 32 can form. Furthermore, the second electrode 32 penetrating the first electrode 31 in the upper stack group N is connected to the substrate 1 through the gap between two adjacent first electrodes 31 in the lower stack group N (in order to disconnect the gap formed by the electrode layer M), thereby realizing the external connection of the ferroelectric capacitors C in the upper stack group N.

[0180] In some embodiments, referring to FIG5, each second electrode 32 is connected to the substrate 1 to facilitate external connection of the second electrode 32. For example, transistors or some circuits may be disposed in the substrate 1 or on the side of the substrate 1 away from the stacked structure 2. The second electrode 32 connected to the substrate 1 may be electrically connected to these electronic devices or circuits to realize signal input and output.

[0181] For example, referring to FIG5, a portion of the second electrode 32 may be disposed between two adjacent first electrodes 31 in at least one stack group N. For example, referring to FIG5, the second electrode 32 for penetrating the first electrode 31 in the upper stack group N also penetrates the insulating material of the lower stack group N located between two adjacent first electrodes 31, so that the second electrode 32 can be connected to the substrate 1 while also bypassing the first electrode 31 in the lower stack group N and penetrating the first electrode 31 in the upper stack group N.

[0182] For example, referring to FIG5, the second electrode 32 may include a first sub-part 321 and a second sub-part 322, the first sub-part 321 and the second sub-part 322 are stacked in the third direction Z, the first sub-part 321 and the second sub-part 322 respectively penetrate two adjacent stacked groups N, and the first sub-part 321 penetrates the first electrode 31 (or electrode stack W), and the second sub-part 322 is located between two adjacent first electrodes 31 (or electrode stack W) in the first direction X.

[0183] The first sub-part 321 enables the second electrode 32 and the first electrode 31 to have a facing area, thereby forming a ferroelectric capacitor C. The second sub-part 322 electrically connects the ferroelectric capacitor C to the substrate 1, or to other ferroelectric capacitors C in other stacked groups N (e.g., arranged in a direction away from the substrate 1, the ferroelectric capacitors C in the first stacked group N and the ferroelectric capacitors C in the third stacked group N are electrically connected through the second sub-part 322 of the second electrode 32). At the same time, the second sub-part 322 is disposed between adjacent first electrodes 31, realizing the utilization of the gap formed when the electrode layer M is disconnected (i.e., the space between adjacent first electrodes 31), avoiding additional occupation of design space on the plane of the first direction X and the second direction Y.

[0184] For example, some first sub-parts 321 of the second electrode 32 may be closer to the substrate 1 than the second sub-parts 322, or some second sub-parts 322 of the second electrode 32 may be closer to the substrate 1 than the first sub-parts 321, or some second electrodes 32 may include a plurality of first sub-parts 321 and a plurality of second sub-parts 322, and the plurality of first sub-parts 321 and the plurality of second sub-parts 322 are alternately arranged in sequence along the third direction Z.

[0185] For example, the first sub-part 321 and the second sub-part 322 can be integrally formed. For instance, they can be integrally molded. For example, a through-hole that penetrates all stacked groups N can be formed first, and then the second electrode 32 can be formed in the through-hole, so that the first sub-part 321 and the second sub-part 322 are integrally formed, saving manufacturing steps.

[0186] Alternatively, by way of example, the first sub-part 321 and the second sub-part 322 may also be two structures, and the two structures are electrically connected. For example, the two can be prepared in steps. For example, the second sub-part 322 that penetrates one stack group N can be prepared first, and then the first sub-part 321 that penetrates another stack group N can be prepared.

[0187] In some embodiments, referring to FIG5, each of the plurality of second electrodes 32 passes through a plurality of stacked groups N.

[0188] For example, in Figure 5, the memory array 10 includes two stacked groups N. The second electrode 32, which penetrates the first electrode 31 in the upper stacked group N, also penetrates the lower stacked group N (penetrating the insulating material between adjacent first electrodes 31 in the lower stacked group N), so that the ferroelectric capacitor C in the upper stacked group N can be electrically connected to the substrate 1. Similarly, the second electrode 32, which penetrates the first electrode 31 in the lower stacked group N, also penetrates the upper stacked group N (penetrating the insulating material between adjacent first electrodes 31 in the upper stacked group N). This makes the lengths of the multiple second electrodes 32 approximately the same and their positions relatively regular, so that the force at different positions of the memory array 10 is more uniform, thereby improving the structural stability of the memory array 10.

[0189] Figure 8 is another cross-sectional view of the storage array 10 provided in an embodiment of this application.

[0190] In some embodiments, referring to FIG8, at least one second electrode 32 penetrates through the other stacked groups N of the plurality of stacked groups N except for the stacked group N furthest from the substrate 1.

[0191] That is, among the plurality of second electrodes 32, at least a portion of the second electrodes 32 (e.g., at least half of the second electrodes 32) do not extend to the stack group N furthest from the substrate 1.

[0192] For example, in Figure 8, the memory array 10 includes two stacked groups N. The second electrode 32, which is used to penetrate the first electrode 31 in the upper stacked group N, needs to penetrate all stacked groups N in order to connect to the substrate 1. However, the second electrode 32, which is used to penetrate the first electrode 31 in the lower stacked group N, only needs to penetrate the lower stacked group N and does not need to penetrate all stacked groups N.

[0193] This structural design can reduce the difficulty of fabricating some of the second electrodes 32, or reduce the number of fabrication steps for some of the second electrodes 32. For example, in Figure 8, some of the second electrodes 32 only require the fabrication of the first sub-part 321, without the need to fabricate the second sub-part 322.

[0194] Figure 9 is a partial enlarged view of the storage array 10 provided in an embodiment of this application, and Figure 10 is another partial enlarged view of the storage array 10 provided in an embodiment of this application.

[0195] In some embodiments, referring to FIG9, a portion of the ferroelectric layer 4 may be deposited on the surface of the first electrode 31, for example, on two opposing surfaces of the first electrode 31 in the third direction Z (i.e., the upper and lower surfaces).

[0196] Referring to Figure 9, another part of the ferroelectric layer 4 is disposed on the side wall of the through hole of the first electrode 31 through which the second electrode 32 penetrates, that is, disposed between the first electrode 31 and the second electrode 32.

[0197] In some embodiments, referring to FIG10, the ferroelectric layer 4 is laid on the side of the second electrode 32 (i.e., the surface extending in the third direction Z), so that when the second electrode 32 penetrates the first electrode 31, a portion of the ferroelectric layer 4 can be located between the first electrode 31 and the second electrode 32.

[0198] Both of the aforementioned embodiments allow the ferroelectric layer 4 to be located between the first electrode 31 and the second electrode 32, thereby forming a ferroelectric capacitor C. These two embodiments can correspond to different methods of preparing the ferroelectric layer 4, thus making the storage array 10 suitable for various process scenarios and improving the fabrication flexibility of the storage array 10.

[0199] Figure 11 is another top view of the storage array 10 provided in the embodiment of this application, and Figure 12 is a cross-sectional view along the section line C-C' in Figure 11.

[0200] In some embodiments, referring to FIG12, the memory array 10 further includes a plurality of transistors T, word lines WL and bit lines BL.

[0201] The plurality of transistors T can be arranged in an array in the first direction X and the second direction Y. For example, referring to Figure 11, a transistor T is arranged at the intersection of each word line WL and bit line BL.

[0202] For example, each string of ferroelectric capacitors C stacked along the third direction Z corresponds to a transistor T.

[0203] Referring to Figure 12, the plurality of transistors T are disposed on the side of the substrate 1 away from the stacked structure 2 so that the transistors T can be electrically connected to the ferroelectric capacitor C.

[0204] Referring to Figure 12, the transistor T includes a third electrode T1, a fourth electrode T2, and a gate T3, wherein the third electrode T1 is one of the source and drain of the transistor T, and the fourth electrode T2 is the other of the source and drain of the transistor T.

[0205] Referring to Figure 12, the third electrode T1 of multiple transistors T is electrically connected to multiple second electrodes 32 respectively, so as to transmit electrical signals to the second electrodes 32, and each transistor T is electrically connected to one second electrode 32, so as to realize the charging and discharging of multiple ferroelectric capacitors C formed by the second electrode 32 stacked along the third direction Z.

[0206] Applying a voltage to the gate T3 of transistor T turns transistor T on, thus making the third electrode T1 and the fourth electrode T2 conduct. The current transmitted in the fourth electrode T2 can be transmitted to the third electrode T1 and then through the third electrode T to one plate (second electrode 32) of the ferroelectric capacitor C, so that a voltage difference is formed between the two plates (first electrode 31 and second electrode 32) of the selected ferroelectric capacitor C for charging and discharging.

[0207] The word line WL is used to transmit electrical signals to the gate T3 of transistor T (i.e., word line WL is electrically connected to gate T3). Gate T3 can be a part of word line WL, and in some cases, the two can be indistinguishable. The bit line BL is used to transmit electrical signals to the fourth electrode T2 of transistor T (i.e., bit line BL is electrically connected to the fourth electrode T2). Similarly, the fourth electrode T2 can also be a part of bit line BL, and in some cases, the two can be indistinguishable. The first electrode 31 can be electrically connected to an external conductive structure so that electrical signals can be transmitted to the first electrode 31. Data read and write operations can be achieved by setting the magnitude of word line WL, bit line BL, and the voltage applied to the first electrode 31.

[0208] Referring to Figure 11, one of the word line WL and the bit line BL extends along the first direction X, and the other extends along the second direction Y. That is, the length extension direction of either the word line WL or the bit line BL is the same as the length extension direction of the first electrode 31.

[0209] For example, referring to Figure 11, each word line WL extends along the second direction Y, so that one word line WL can simultaneously control the transmission of gate signals of multiple transistors T arranged along the second direction Y. Each bit line BL extends along the first direction X, so that one bit line BL can simultaneously control the transmission of source (or drain) signals of multiple transistors T arranged along the first direction X. By transmitting electrical signals to one word line WL and one bit line BL, a transistor T can be selected, causing the transistor T to turn on, and a string of ferroelectric capacitors C (stacked along the third direction Z) corresponding to the transistor T can be selected. Then, by transmitting an electrical signal to a first electrode 31, the corresponding ferroelectric capacitor C can be selected, realizing the writing or reading of data.

[0210] In some embodiments, referring to Figures 6 and 7, the first electrode 31 is strip-shaped and extends along the second direction Y.

[0211] Referring to Figures 6 and 7, a plurality of second electrodes 32 can be arranged in an array along the first direction X and the second direction Y, and the plurality of second electrodes 32 arranged along the second direction Y can penetrate the same first electrode 31.

[0212] That is, multiple ferroelectric capacitors C arranged along the second direction Y can share the first electrode 31, which makes it convenient for a single trace electrically connected to the first electrode 31 to transmit electrical signals to multiple ferroelectric capacitors C arranged along the second direction Y during data reading and writing, thereby reducing the number of traces for transmitting electrical signals to the ferroelectric capacitors C and reducing the design space occupied by the storage array 10.

[0213] In some embodiments, referring to FIG12, among the plurality of second electrodes 32 arranged along the first direction X, different second electrodes 32 pass through different first electrodes 31, that is, the first electrodes 31 in any two memories C arranged along the first direction X are independent of each other.

[0214] During data read / write, word line WL selects a column of transistors T, bit line BL selects a row of transistors T, and word line WL and bit line BL together select a string of ferroelectric capacitors C. When the first electrodes 31 in any two memory cells C arranged along the first direction X are independent of each other, one first electrode 31 can select one ferroelectric capacitor C in the string of ferroelectric capacitors C. That is, in this structure, only one ferroelectric capacitor C can be selected each time for precise data read / write.

[0215] Here, "a row" refers to multiple items arranged along the first direction X, "a column" refers to multiple items arranged along the second direction Z, and "a string" refers to multiple items arranged along the third direction Z.

[0216] The storage array 10 provided in this embodiment can reduce signal interference. For example, after a string of ferroelectric capacitors C is selected by word line WL and bit line BL, although multiple ferroelectric capacitors C arranged along the first direction X share the same bit line BL, their word line WL and first electrode 31 are independent of each other. They can still independently control the potential of the two electrodes in the remaining ferroelectric capacitors C, so that the stored data is not disturbed, effectively improving the reliability of storage array 10 and reducing the probability of data errors or data loss.

[0217] Figure 13 is another cross-sectional view of the storage array 10 provided in the embodiment of this application, and Figure 14 is another cross-sectional view of the storage array 10 provided in the embodiment of this application.

[0218] In some other embodiments, referring to Figures 13 and 14, at least two (two are used as an example in Figures 13 and 14) second electrodes 32 arranged along the first direction X penetrate the same first electrode 31. That is, the number of disconnection points when the electrode layer M is broken into multiple first electrodes 31 can be reduced, thereby reducing the difficulty of fabrication.

[0219] Figure 14 illustrates the structure of the storage array 10 by way of two second electrodes 32 arranged along the first direction X passing through the same first electrode 31. In some other embodiments, three or more adjacent second electrodes 32 may pass through the same first electrode 31.

[0220] For example, referring to FIG13, in this embodiment, different word lines WL are set independently of each other, that is, during each read and write process, a word line WL selects only one column of transistors T, so as to select a ferroelectric capacitor C together with the bit line BL and the first electrode 31.

[0221] For example, referring to FIG14, when the word line WL extends along the second direction Y, the at least two word lines WL connected to the at least two transistors T that are electrically connected to the at least two second electrodes 32 that pass through the same first electrode 31 and are arranged along the first direction X are connected in parallel. That is, during each read and write process, a word line signal can be transmitted to the at least two WL at the same time, so that at least two columns of transistors T can be selected at one time, so as to select at least two ferroelectric capacitors C together with the bit line BL and the first electrode 31, so that a memory cell G contains at least two ferroelectric capacitors C.

[0222] That is, in this embodiment, although in terms of physical structure, a first electrode 31 is penetrated by at least two second electrodes 32 arranged along the first direction X, in terms of electrical connection, at least two ferroelectric capacitors C formed by the at least two second electrodes 32 are connected in parallel. That is, the at least two ferroelectric capacitors C together form a memory cell G. A word line signal and a bit line signal can simultaneously select the at least two ferroelectric capacitors C (a memory cell G). Therefore, there is still no interference between adjacent memory cells G.

[0223] Similarly, when the bit line BL extends along the second direction Y, the at least two bit lines BL connected to the at least two transistors T that are electrically connected to the at least two second electrodes 32 that pass through the same first electrode 31 and are arranged along the first direction X are connected in parallel, which is similar to the case where the bit line WL extends along the second direction Y, and will not be described again here.

[0224] Figure 15 is a top view of a storage array 10 in which each of the plurality of second electrodes 32 arranged in the first direction X penetrates a first electrode 31. Figure 16 is a top view of a storage array 10 in which every two of the plurality of second electrodes 32 arranged in the first direction X penetrate the same first electrode 31. Figure 17 is a top view of a storage array 10 in which every four of the plurality of second electrodes 32 arranged in the first direction X penetrate the same first electrode 31.

[0225] In the storage array 10 provided in this application embodiment, referring to Figures 15 to 17, the arrangement of the plurality of second electrodes 32 can be varied.

[0226] For example, referring to Figure 15(a), Figure 16(a) and Figure 17(a), a plurality of second electrodes 32 may be arranged along the first direction X.

[0227] Alternatively, in some embodiments, a plurality of second electrodes 32 arranged in the second direction Y form a conductive group 32L, that is, a row of second electrodes 32 constitutes a conductive group 32L, and a plurality of conductive groups 32L are arranged along the first direction X.

[0228] Referring to Figures 15, 16 and 17, the second electrodes 32 in at least one pair of conductive groups 32L arranged in the first direction X are staggered from each other in the first direction X.

[0229] For example, referring to Figure 16(b) and Figure 17(b), the second electrodes 32 used to penetrate the first electrodes 31 in different stacked groups N are staggered in the first direction X, while the second electrodes 32 used to penetrate the first electrodes 31 in the same stacked group N are still arranged in the first direction X.

[0230] Or, for example, referring to Figure 15(b), Figure 16(c) and Figure 17(c), the second electrodes 32 in any pair of adjacent conductive groups 32L are staggered from each other in the first direction X.

[0231] For example, referring to Figures 15, 16 and 17, the second electrodes 32 in at least one pair of conductive groups 32L arranged in the first direction X may be offset by a second electrode 32 diameter in the first direction X.

[0232] By setting the second electrodes 32 in at least one pair of conductive groups 32L arranged in the first direction X to be staggered in the first direction X, the utilization rate of the multiple second electrodes 32 on the plane (the plane containing the first direction X and the second direction Y) can be improved, and the distribution density of the multiple second electrodes 32 can be increased, that is, the distribution density of the multiple ferroelectric capacitors C in the storage array 10 can be increased, which is beneficial to reducing the design space occupied by the storage array 10 and realizing the miniaturization design of the storage array 10.

[0233] Any arrangement of the second electrode 32 in Figures 15 to 17 can correspond to various connection methods of word line WL or bit line BL. The following embodiments only take the structure in which word line WL and first electrode 31 extend in the same direction (both extend along the second direction Y) as an example for illustration. The connection method of the structure in which bit line BL extends along the second direction Y can be referred to the following description of the connection method of word line WL, and will not be repeated.

[0234] In some embodiments, at least two adjacent word lines WL are independently configured or connected in parallel, or at least two word lines WL that are not adjacent are connected in parallel (i.e., differentially connected).

[0235] For example, referring to Figure 15(a), Figure 16(a) and Figure 16(b), each word line WL is set independently relative to the other word lines WL so that a ferroelectric capacitor C can be selected.

[0236] Alternatively, for example, referring to (c) in Figure 16 and (c) in Figure 17, two adjacent word lines WL can be connected in parallel, wherein the two word lines WL are used to control the ferroelectric capacitors C in the same stack group N, so that a word line signal can select two ferroelectric capacitors C, that is, a memory cell G may include two ferroelectric capacitors C.

[0237] Alternatively, for example, referring to Figures 17(a) and 17(b), four adjacent word lines WL can be connected in parallel, wherein the four word lines WL are used to control the ferroelectric capacitors C in the same stack group N, so that a word line signal can select four ferroelectric capacitors C, that is, a memory cell G may include four ferroelectric capacitors C.

[0238] Alternatively, as shown in Figure 15(b), two word lines WL (or more) located in odd-numbered columns can be electrically connected, and multiple ferroelectric capacitors C can be selected using a single word line signal. It is understood that word lines WL can also be electrically connected under other patterns, such as multiple word lines WL located in even-numbered columns, or word lines WL separated by two or more word lines WL. This application does not limit this to specific arrangements.

[0239] For example, referring to (c) in Figure 16 and (c) in Figure 17, a plurality of second electrodes 32 in each conductive group 32L are electrically connected to the same word line WL, that is, the word line WL extends along the second direction Y. In this structure, the second electrodes 32 in at least a pair of conductive groups 32L arranged in the first direction X are staggered from each other in the first direction X, and the two word lines WL that are electrically connected to the at least a pair of conductive groups 32L are electrically connected to each other.

[0240] Referring to Figures 16(c) and 17(c), the second electrodes 32 in two adjacent conductive groups 32L are staggered in the first direction X. Therefore, each second electrode 32 in the two conductive groups 32L is electrically connected to a bit line BL extending along the first direction X. That is, different second electrodes 32 can be selected by different bit lines BL. When the two word lines WL corresponding to the two conductive groups 32L are electrically connected, although a word line signal WL can select all the second electrodes 32 in the two conductive groups 32L, the bit lines BL are still independent of each other. Therefore, under the combined action of word line WL and bit line BL, only one ferroelectric capacitor C will be selected. That is, in this structure, the number of external connections of word lines WL can be reduced while the memory array 10 can achieve the selection of one ferroelectric capacitor C. For example, it is not necessary for each word line WL to be externally connected. For example, the word lines WL that are electrically connected in pairs can be externally connected only once.

[0241] For example, when the bit line BL extends along the second direction, a plurality of second electrodes 32 in each conductive group 32L are electrically connected to the same bit line BL. The two bit lines BL that are electrically connected to the aforementioned at least one pair of conductive groups 32L are electrically connected, which is the same as in the previous embodiment and will not be repeated here.

[0242] This application embodiment also provides a method for fabricating a storage array 10. Figures 18, 19 and 20 are some fabrication flowcharts of the storage array 10 provided in this application embodiment, and Figures 21 to 47 are structural diagrams corresponding to each fabrication step of the storage array 10.

[0243] Some of the figures in Figures 21 to 47 only include cross-sectional views (views in the XZ direction) corresponding to the preparation steps. Other figures in Figures 21 to 47 may include top views (views in the XY direction) and cross-sectional views (views in the XZ direction) corresponding to the preparation steps.

[0244] As shown in Figure 18, the preparation method includes the following steps S1 to S3.

[0245] S1: A stacked structure 2 is formed on substrate 1.

[0246] Referring to Figures 30, 39, or 45, the stacked structure 2 formed in step S1 includes multiple stacked groups N stacked along the third direction Z. Each stacked group N includes multiple electrode stacks W spaced apart along the first direction X. Each electrode stack W includes multiple first electrodes 31 stacked and spaced apart along the third direction Z. At least a portion of the orthographic projections of the electrode stacks W in two adjacent stacked groups N onto the substrate 1 are staggered. In two adjacent stacked groups N, at least a portion of the orthographic projection of at least one electrode stack W in one stacked group N onto the substrate 1 is located between the orthographic projections of two adjacent electrode stacks W onto the substrate 1 in the other stacked group N.

[0247] Referring to Figures 30, 39, or 45, the first electrode 31 in each stack group N can also be divided into multiple electrode layers M stacked and spaced apart along the third direction Z, each electrode layer M including multiple first electrodes 31 spaced apart in the first direction X of the eye.

[0248] S2: Form multiple second electrodes 32.

[0249] Referring to Figures 30, 39 or 45, the plurality of second electrodes 32 formed in step S2 are disposed at intervals on the substrate 1 along a direction parallel to the substrate 1 and are connected to the substrate 1. Each second electrode 32 penetrates at least one set of electrode stacks W in a stack group N, and the electrode stacks W in two adjacent stack groups N are penetrated by different second electrodes 32.

[0250] S3: Formation of ferroelectric layer 4.

[0251] Referring to Figures 30, 39 or 45, at least a portion of the ferroelectric layer 4 is disposed between the first electrode 31 and the second electrode 32.

[0252] In the storage array 10 prepared by the preparation method provided in this application embodiment, the electrode layer M is cut into multiple first electrodes 31, which reduces the number of ferroelectric capacitors C sharing a common electrode, thereby reducing the number of read and write operations corresponding to a common electrode. This reduces the number of times each ferroelectric capacitor C is interfered with or even no longer interfered with, thereby reducing the probability of malfunction in the storage array 10, improving the reliability of information storage in the storage array 10, and reducing the probability of information loss or information errors.

[0253] Furthermore, in the storage array 10 obtained by this preparation method, the first electrodes 31 in two adjacent stack groups N are staggered so that they can be penetrated by different second electrodes 32. This allows the number of stacked ferroelectric capacitors C in the third direction Z to be increased, while ensuring that the number of first electrodes 31 penetrated by each second electrode 32 is less than the number of all electrode layers M in the stacked structure 2. This avoids excessive ferroelectric capacitors C stacked on a single second electrode 32, which could affect the performance of the ferroelectric capacitors C. At the same time, the staggered arrangement of the first electrodes 31 in two adjacent stack groups N in the third direction Z and their alternating arrangement in the first direction X provides design space for the penetration of the second electrodes 32. This design space utilizes the space at the break point when the electrode layer M is broken into multiple first electrodes 31 (i.e., the space between two adjacent first electrodes 31), and does not additionally occupy the design space of the planes in the first direction X and the second direction Y.

[0254] That is, by utilizing the gap between the first electrodes 31, the storage array 10 can achieve the superposition of ferroelectric capacitors C in the third direction Z in the storage array without increasing the number of ferroelectric capacitors C on each second electrode 32, and without increasing the horizontal design space, thereby improving the storage capacity of the storage array 10.

[0255] In some embodiments, referring to FIG19, the aforementioned step S1 may include the following steps S11 to S13:

[0256] S11: Form a stack group N on substrate 1.

[0257] Referring to Figure 28 or Figure 42, the stack group N includes multiple electrode layers M and multiple insulating layers 5 that are alternately stacked along the third direction Z.

[0258] S12: Form multiple slots H2 that run through the stack group N, and fill the slots H2 with insulating material.

[0259] Referring to Figure 27 or Figure 41, multiple slots H2 are spaced apart along the first direction X, and the multiple slots H2 break the multilayer electrode layer M into multiple first electrodes 31 (or multiple electrode stacks W).

[0260] S13: Stack group N is formed again in the direction away from substrate 1 in the stack group N, and slot H2 is opened again.

[0261] Referring to Figure 29 or Figure 43, the slots H2 opened on the two adjacent stack groups N are staggered in the third direction Z.

[0262] That is, in this embodiment of the application, the electrode layer M can be broken into multiple first electrodes 31 by slotting H2, and by controlling the setting position of slot H2, the slots H2 opened on the two adjacent stack groups N are staggered in the third direction Z, thereby achieving the purpose of staggering the first electrodes 31 in the two adjacent stack groups N, so that the second electrode 32 prepared subsequently can penetrate only the first electrode 31 of one of the two adjacent stack groups N.

[0263] The embodiments of this application do not impose restrictions on the order of the aforementioned steps S1, S2 and S3. The following will provide some embodiments to illustrate different preparation sequences of steps S1 to S3, as well as different preparation steps.

[0264] Example 1:

[0265] As shown in Figure 20, in this embodiment, the aforementioned step S11 includes step S111 and step 112, and in this embodiment, step S2 is located between step S111 and step 112.

[0266] S111: Referring to Figure 21, an initial stack group 2' is formed on the substrate 1.

[0267] Referring to Figure 21, the initial stack group 2' includes multiple layers of first functional layer A1 and multiple layers of insulating layer 5 that are alternately stacked along the third direction Z.

[0268] For example, substrate 1 can be a bare wafer for bonding the memory array 10 with other structures, such as logic circuits, or substrate 1 can be a wafer containing complete logic circuits.

[0269] For example, the first functional layer A1 can be an insulating material or a semiconductor material, such as an oxide, nitride or polysilicon. The first functional layer A1 and the insulating layer 5 are made of different materials so that the first functional layer A1 can be removed later.

[0270] For example, the thickness of the first functional layer A1 and / or the insulating layer 5 can be 10nm to 200nm, and the number of layers of the first functional layer A1 can be 1 to 32.

[0271] S2: Referring to Figure 23, multiple second electrodes 32 are formed.

[0272] Referring to Figure 22, a through hole H1 is first formed through the initial stack group 2' so that the second electrode 32 can be installed later.

[0273] For example, the via H1 can be formed using photolithography and dry etching.

[0274] Referring to Figure 23, the second electrode 32 penetrates the initial stack 2' and is in contact with the substrate 1.

[0275] For example, the second electrode 32 can be formed using an ALD or CVD process.

[0276] For example, a CMP process can be used to remove other excess materials formed during the fabrication of the second electrode 32, such as removing the material of the second electrode 32 located on the upper surface of the initial stack group 2'.

[0277] For example, a protective layer can also be formed on the inner wall of the via H1 before forming the second electrode 32 to prevent damage to the second electrode 32 by subsequent etching steps. In this case, the portion of the protective layer located at the bottom of the via H1 needs to be etched open to expose the substrate 1, so that the second electrode 32 can contact the substrate 1.

[0278] For example, referring to FIG23, before forming the second electrode 32, the ferroelectric layer 4 is also formed, that is, step S3 can be located before step S2. For example, after forming the through hole H1, the ferroelectric layer 4 and the second electrode 32 are formed in sequence, thereby obtaining the structure shown in FIG10.

[0279] S112: Referring to Figure 25, the first functional layer A1 is replaced with the electrode layer M to form a stack group N.

[0280] Referring to Figure 24, the first functional layer A1 is first removed to form a trench U1, which will then be used to set the electrode layer M.

[0281] In this embodiment, by performing step S2 before step S112, the second electrode 32 can be fabricated while also serving as a support, thus preventing the stacked structure from collapsing after the first functional layer A1 is removed.

[0282] For example, referring to FIG24, before removing the first functional layer A1, the side of the initial stack group 2' can be removed by photolithography and dry etching so that an insulating material can be formed at the side location to protect the replaced electrode layer M.

[0283] For example, the first functional layer A1 can be removed by wet etching.

[0284] For example, in the case where a protective layer is also formed when the second electrode 32 is formed, after removing the first functional layer A1, it is also necessary to remove the protective layer exposed by the trench U1 in order to expose the second electrode 32.

[0285] For example, referring to FIG25, the ferroelectric layer 4 can be formed before the electrode layer M is formed, that is, step S3 can also be located here. For example, after the trench U1 is formed, the ferroelectric layer 4 and the electrode layer M are formed in sequence to prepare the structure shown in FIG9.

[0286] For example, the ferroelectric layer 4 and the electrode layer M can be formed using the ALD process.

[0287] For example, referring to FIG26, after the electrode layer M is formed, an insulating material is formed on the side of the stack group N to protect the electrode layer M.

[0288] S12: Referring to Figure 27, multiple slots H2 are formed through the stack N. Referring to Figure 28, insulating material is filled into the slots H2 to break the electrode layer M into multiple first electrodes 31, that is, to break the multilayer electrode layer M into multiple electrode stacks W.

[0289] Referring to Figure 27, in this embodiment, a slot H2 is formed between each pair of adjacent second electrodes 32 so that in the first direction X, one second electrode 32 passes through one first electrode 31 (or one electrode stack W).

[0290] S13: Referring to Figure 29, stack group N is formed again in the direction away from substrate 1, and slot H2 is opened again.

[0291] That is, step S13 is used to form a stack group N that is relatively far away from the substrate 1. The fabrication process used in step S13 can refer to the aforementioned steps S111, S112, S2 and S12, which will not be repeated here. The same applies to the fabrication of three or more stack groups N, as long as the condition that the slots H2 opened on the two adjacent stack groups N in the third direction Z are staggered in the third direction Z is met.

[0292] For example, referring to FIG29, during the formation of the upper stack group N, the second electrode 32 for penetrating the first electrode 31 (or electrode stack W) in the upper stack group N also penetrates the insulating material between adjacent first electrodes 31 (or electrode stack W) in the lower stack group N, so that the second electrode 32 corresponding to the upper stack group N can be connected to the substrate 1.

[0293] For example, referring to FIG30, a portion of a second electrode 32 (i.e., a second sub-part 322) can be formed between two adjacent first electrodes 31 (or electrode stacks W) in the upper stack group N. This portion is connected to the second electrode 32 that penetrates the first electrode 31 (or electrode stacks W) in the lower stack group N, so as to obtain a storage array 10 with more uniform force on the upper and lower stack groups N.

[0294] For example, each second electrode 32 includes a first sub-part 321 and a second sub-part 322, wherein the first sub-part 321 and the second sub-part 322 of a portion of the second electrode 32 can be fabricated simultaneously. For example, referring to FIG29, a through hole H1 that completely penetrates the two stacked groups N can be formed, such that the first sub-part 321 and the second sub-part 322 are integrally formed in the second electrode 32 used to penetrate the first electrode 31 (or electrode stack W) in the upper stacked group N.

[0295] Alternatively, by way of example, the first sub-part 321 and the second sub-part 322 can be fabricated separately. For example, referring to FIG31, a second sub-part 322 for connecting the second electrode 32 corresponding to the upper stack group N to the substrate 1 can be formed between two adjacent first electrodes 31 (or electrode stack W) in the lower stack group N before the upper stack group N is fabricated. The first sub-part 321 of the second electrode 32 corresponding to the upper stack group N is formed after the upper stack group N is fabricated (thus obtaining FIG30). That is, in the second electrode 32 corresponding to the upper stack group N, the first sub-part 321 and the second sub-part 322 are formed in different fabrication steps.

[0296] Example 2:

[0297] Referring to Figures 32 to 39, the preparation steps of this second embodiment are the same as those of the first embodiment. The difference is that in this second embodiment, a slot H2 is opened every two second electrodes 32 along the first direction X, so that every two second electrodes 32 pass through the same first electrode 31 (or electrode stack W) in the first direction X.

[0298] For example, in other embodiments, a slot H2 may be formed every four or other numbers of second electrodes 32, and this application embodiment does not limit this.

[0299] For example, the preparation steps in this second embodiment can be referred to the foregoing description of the first embodiment, and will not be repeated here.

[0300] For example, referring to FIG34, which differs from FIG24 corresponding to Embodiment 1, in this embodiment, while removing the first functional layer A1, the insulating layer 5 is disconnected so that the subsequently formed electrode layer M can be correspondingly disconnected into multiple first electrodes 31. For example, referring to FIG35, when forming the electrode layer M, the electrode layer M not only fills between two adjacent insulating layers 5, but also fills between two insulating layers 5 that are disconnected from each other in the first direction X. Then, referring to FIG36, the portion of the electrode layer M except for the portion located between two adjacent insulating layers 5 is removed and replaced with insulating material, so that the electrode layer M can be disconnected into multiple first electrodes 31.

[0301] Example 3:

[0302] In this embodiment, a stacked group N consisting of an insulating layer 5 and an electrode layer M can be directly formed, and steps S2 and S3 are performed after the stacked group N is formed.

[0303] S11: Referring to Figure 40, a stack group N is formed on substrate 1.

[0304] In this embodiment, an alternating electrode layer M and an insulating layer 5 can be directly formed on the substrate 1. The thickness of the electrode layer M and / or the insulating layer 5 can be 10 nm to 300 nm, and the deposition process can be one or more of PECVD, ALD and PVD.

[0305] S12: Referring to Figure 41, multiple slots H2 are formed that penetrate the stack group N. Referring to Figure 42, insulating material is filled into the slots H2.

[0306] S13: Referring to Figure 43, stack group N is formed again in the direction away from substrate 1, and slot H2 is opened again.

[0307] In this embodiment of the application, only the stacking structure 2 including two stacking groups N is used as an example for illustrative purposes. It can be understood that in the stacking structure 2 including three or more stacking groups N, steps S11 and S12 can be repeatedly executed to stack and form multiple stacking groups N.

[0308] S3: Refer to Figure 45 to form the ferroelectric layer 4.

[0309] S2: Referring to Figure 45, multiple second electrodes 32 are formed.

[0310] Referring to Figure 44, a through-hole H1 penetrating multiple stacked groups N can be formed first, and then referring to Figure 45, a ferroelectric layer 4 and a second electrode 32 can be formed sequentially in the through-hole.

[0311] For example, referring to Figures 44 and 45, multiple second electrodes 32 can be formed after all stacked groups N are formed and the electrode layers M in each stacked group N are broken into multiple first electrodes 31, thereby achieving the synchronous fabrication of all second electrodes 32 and improving the fabrication efficiency of the memory array 10.

[0312] Alternatively, as exemplarily, referring to Figures 46 and 47, the plurality of second electrodes 32 include a plurality of first preset electrodes 323 and a plurality of second preset electrodes 324. In two stacked groups N arranged adjacent to each other along the third direction Z, the plurality of first preset electrodes 323 penetrate the first electrode 31 (or electrode stack W) in the stacked group N closer to the substrate 1, and the plurality of second preset electrodes 324 penetrate the first electrode 31 (or electrode stack W) in the stacked group N further away from the substrate 1, wherein:

[0313] Step S2 can be prepared in steps. For example, before step S13, multiple first preset electrodes 323 are formed, and after step S13, multiple second preset electrodes 324 are formed.

[0314] That is, after each stack group N is completed and before another stack group N is prepared, the second electrode 32 corresponding to the prepared stack group N is formed, thereby avoiding the need to make a through hole H1 with a large depth-to-width ratio when forming the second electrode 32, so as to reduce the difficulty of preparation.

[0315] Here, "corresponding" is understood to mean that a certain stack group N corresponds to the second electrode 32 that passes through the first electrode 31 (or electrode stack W) in the stack group N.

[0316] It is understandable that by repeating steps S11, S12, S13, S3 and S2 after Figure 47, the structure shown in Figure 45 can be obtained.

[0317] For example, the same second electrode 32 in this third embodiment can also be integrally formed or prepared in steps.

[0318] For example, referring to Figure 45, the first sub-part 321 and the second sub-part 322 of the same second electrode 32 are prepared simultaneously and integrally formed.

[0319] Alternatively, referring to Figure 47, the first sub-part 321 and the second sub-part 322 of the same second electrode 32 are prepared in steps.

[0320] In this embodiment, referring to FIG47, the first sub-part 32 in one second electrode 32 and the second sub-part 322 in the other second electrode 32 can be prepared simultaneously, thereby reducing the number of repeated drillings when preparing the through hole H1 and simplifying the preparation process of the storage array 10.

[0321] The above embodiment three uses the structure in which only one first electrode 31 (or electrode stack W) is penetrated by only one of the multiple second electrodes 32 arranged in the first direction X as an example to illustrate the preparation method of the storage array 10. It can be understood that, similar to embodiment two, the preparation steps provided in embodiment three can also prepare a storage array 10 in which two or more of the multiple second electrodes 32 arranged in the first direction X penetrate the same first electrode 31.

[0322] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage array, characterized in that, include: Substrate; A stacked structure is disposed on the substrate, the stacked structure comprising multiple stacked groups stacked along a third direction; each stacked group comprising multiple electrode stacks spaced apart along a first direction; each electrode stack comprising multiple first electrodes stacked and spaced apart along the third direction; in two adjacent stacked groups, at least a portion of the orthographic projection of the electrode stacks belonging to the two adjacent stacked groups on the substrate is staggered, and in two adjacent stacked groups, at least a portion of the orthographic projection of at least one electrode stack in one stacked group on the substrate is located between the orthographic projections of two adjacent electrode stacks in the other stacked group on the substrate; The first direction is parallel to the substrate, and the third direction is perpendicular to the substrate; Multiple second electrodes are disposed at intervals on the substrate along a direction parallel to the substrate and are connected to the substrate; each second electrode penetrates at least one set of electrode stacks, and the electrode stacks in two adjacent sets of stacks are penetrated by different second electrodes; A ferroelectric layer is at least partially disposed between the first electrode and the second electrode.

2. The storage array according to claim 1, characterized in that, In two adjacent stack groups, the orthographic projections of multiple electrode stacks in one stack group onto the substrate and the orthographic projections of multiple electrode stacks in the other stack group onto the substrate are alternately arranged along the first direction.

3. The storage array according to claim 1 or 2, characterized in that, The first electrode, through which the second electrode passes, is disposed around the surface of the second electrode extending in the third direction.

4. The storage array according to any one of claims 1 to 3, characterized in that, At least a portion of the second electrode includes a first sub-part and a second sub-part, the first sub-part and the second sub-part being stacked upwards in the third party; The first sub-part and the second sub-part each penetrate two adjacent stacked groups, with the first sub-part penetrating the electrode stack and the second sub-part located between two adjacent electrode stacks in the first direction.

5. The storage array according to claim 4, characterized in that, The first sub-part and the second sub-part are integrally formed.

6. The storage array according to any one of claims 1 to 5, characterized in that, In the plurality of second electrodes, each second electrode penetrates through the plurality of stacked groups.

7. The storage array according to any one of claims 1 to 5, characterized in that, At least one of the second electrodes extends through all of the multiple stacked groups except for the stacked group furthest from the substrate.

8. The storage array according to any one of claims 1 to 7, characterized in that, A portion of the ferroelectric layer is also deposited on two surfaces of the first electrode that are directly opposite each other along the third direction; or, the ferroelectric layer is deposited on the surface of the second electrode that extends along the third direction.

9. The storage array according to any one of claims 1 to 8, characterized in that, The first electrode is strip-shaped and extends along a second direction; the second direction is parallel to the substrate and intersects the first direction. The plurality of second electrodes are arranged in an array along the first direction and the second direction; Multiple second electrodes arranged along the second direction pass through the same first electrode.

10. The storage array according to any one of claims 1 to 9, characterized in that, In a plurality of second electrodes arranged along the first direction, different second electrodes penetrate different first electrodes; or, At least two second electrodes arranged along the first direction penetrate the same first electrode.

11. The storage array according to any one of claims 1 to 10, characterized in that, Also includes: A plurality of transistors are arranged in an array in the first direction and the second direction, and are disposed on the side of the substrate away from the stacked structure; each transistor includes a third electrode, a fourth electrode and a gate; the third electrode of the plurality of transistors is electrically connected to the plurality of second electrodes respectively; The word line and the bit line, one of which extends along the first direction and the other extends along the second direction; the word line is electrically connected to the gate and the bit line is electrically connected to the fourth electrode.

12. The storage array according to claim 11, characterized in that, At least two second electrodes arranged along the first direction penetrate the same first electrode; Wherein, the word lines extend along the second direction, and at least two word lines connected to at least two transistors electrically connected to the at least two second electrodes are connected in parallel; or, the bit lines extend along the second direction, and at least two bit lines connected to at least two transistors electrically connected to the at least two second electrodes are connected in parallel.

13. The storage array according to any one of claims 1 to 12, characterized in that, A plurality of second electrodes arranged in a second direction form a conductive group; the second electrodes in at least one pair of conductive groups arranged in the first direction are staggered from each other in the first direction.

14. The storage array according to claim 13, characterized in that, The memory array includes transistors, word lines, and bit lines; In each conductive group, multiple second electrodes are electrically connected to the same word line, and the two word lines electrically connected to each of the at least one pair of conductive groups are electrically connected to each other; or... Multiple second electrodes in each conductive group are electrically connected to the same bit line, and the two bit lines that are electrically connected to the at least one pair of conductive groups are electrically connected to each other.

15. A method for fabricating a memory array, characterized in that, include: A stacked structure is formed on a substrate; the stacked structure includes multiple stack groups stacked along a third direction. Each stack group includes a plurality of electrode stacks spaced apart along a first direction; each electrode stack includes a plurality of first electrodes stacked and spaced apart along a third direction; the orthographic projections of electrode stacks belonging to two adjacent stack groups on the substrate are at least partially staggered, and in two adjacent stack groups, at least a portion of the orthographic projection of at least one electrode stack in one stack group on the substrate is located between the orthographic projections of two adjacent electrode stacks in the other stack group on the substrate. The first direction is parallel to the substrate, and the third direction is perpendicular to the substrate; A plurality of second electrodes are formed; the plurality of second electrodes are disposed at intervals on the substrate along a direction parallel to the substrate and are connected to the substrate; each second electrode penetrates at least one set of electrode stacks, and the electrode stacks in two adjacent sets of stacks are penetrated by different second electrodes; Formation of a ferroelectric layer; At least a portion of the ferroelectric layer is disposed between the first electrode and the second electrode.

16. The preparation method according to claim 15, characterized in that, The formation of the stacked structure on the substrate includes: A stacked group is formed on the substrate; the stacked group includes multiple electrode layers and multiple insulating layers that are alternately stacked sequentially along the third direction; Multiple slots are formed through the stacked group, and insulating material is filled in the slots; the multiple slots are spaced apart along the first direction, and the multiple slots break the multilayer electrode layer into the multiple electrode stacks; The stack group is re-formed in the direction away from the substrate, and the slot is opened again; the slots opened on the two adjacent stack groups are staggered from each other in the direction of the third.

17. The preparation method according to claim 16, characterized in that, After forming all the stacked groups and breaking the multilayer electrode layers in each stacked group into multiple electrode stacks, multiple second electrodes are formed; or, The plurality of second electrodes includes a plurality of first preset electrodes and a plurality of second preset electrodes. In two stacked groups arranged adjacent to each other along the third direction, the plurality of first preset electrodes penetrate the electrode stack in the stacked group closer to the substrate, and the plurality of second preset electrodes penetrate the electrode stack in the stacked group farther from the substrate, wherein: The formation of a plurality of second electrodes includes: Before the steps of re-forming the stacked group in a direction away from the substrate and re-opening the slot, the plurality of first preset electrodes are formed; After the stacking group is re-formed in a direction away from the substrate and the slot is opened again, the plurality of second preset electrodes are formed.

18. The preparation method according to claim 16 or 17, characterized in that, Each second electrode includes a first sub-part and a second sub-part, which are stacked in the third direction; the first sub-part extends through the electrode stack, and the second sub-part is located between two adjacent electrode stacks disposed in the first direction. In this case, the first sub-part and the second sub-part of the same second electrode are fabricated simultaneously; or... The first sub-part and the second sub-part of the same second electrode are prepared step by step, and are respectively through two second electrodes in different stacked groups of electrode stacks. The first sub-part in one second electrode is prepared synchronously with the second sub-part in the other second electrode.

19. The preparation method according to claim 16, characterized in that, The formation of the stack group on the substrate includes: An initial stack group is formed on the substrate; the initial stack group includes multiple first functional layers and multiple insulating layers that are alternately stacked sequentially along the third direction; The first functional layer is replaced with an electrode layer to form the stack group; The formation of multiple second electrodes occurs before the replacement of the first functional layer with an electrode layer to form the stack group.

20. A memory, characterized in that, include: Storage array as described in any one of claims 1 to 14; The peripheral circuitry is electrically connected to the storage array.

21. An electronic device, characterized in that, include: The memory as described in claim 20; The bus is electrically connected to the memory.

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