Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of memory cells distributed in different layers and stacked in a direction perpendicular to a substrate (1); a plurality of bit lines (30), which penetrate the memory cells in different layers, extend in the direction perpendicular to the substrate (1) and are distributed at intervals in a second direction; and a plurality of word lines distributed in different layers, the word lines and the bit lines (30) being distributed in a first direction parallel to the substrate (1). The word lines comprise first sub-word lines (40a) and second sub-word lines (40b) distributed at intervals in the direction perpendicular to the substrate (1), wherein the first sub-word lines (40a) and the second sub-word lines (40b) extend in the second direction parallel to the substrate (1). Each memory cell comprises a transistor, wherein each transistor comprises a semiconductor layer (23) connected to each bit line (30), and the semiconductor layer (23) is arranged between each first sub-word line (40a) and each second sub-word line (40b).

Description

A semiconductor device and its manufacturing method, and an electronic device.

[0001] This application claims priority to Chinese Patent Application No. 202411823698.7, filed on December 11, 2024, entitled "A Semiconductor Device and a Method for Manufacturing the Same Thereof, and an Electronic Device", the contents of which shall be construed as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0004] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] This application provides a semiconductor device, including:

[0007] Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers;

[0008] Multiple bit lines, penetrating different layers of the memory cells, extend along a direction perpendicular to the substrate and are spaced apart in a second direction;

[0009] Multiple word lines are distributed in different layers, and the word lines and bit lines are distributed along a first direction parallel to the substrate; the word lines include first sub-word lines and second sub-word lines that are spaced apart along a direction perpendicular to the substrate; the first sub-word lines and the second sub-word lines extend along a second direction parallel to the substrate; the first direction and the second direction intersect.

[0010] The memory cell includes a transistor, the transistor including a semiconductor layer connecting the bit line; the semiconductor layer is disposed between the first sub-word line and the second sub-word line; the first sub-word line is distributed on the side of the semiconductor layer away from the substrate, and the second sub-word line is distributed on the side of the semiconductor layer facing the substrate.

[0011] In some embodiments, the semiconductor device further includes: a first isolation layer disposed between the first sub-word line and the second sub-word line and extending along the second direction, the semiconductor layer surrounding the first isolation layer.

[0012] In some embodiments, the semiconductor device includes: a multilayer memory cell array, each layer of the memory cell array including a plurality of memory cells arrayed along a first direction and a second direction; and multiple semiconductor layers of a plurality of transistors distributed in the same column along the second direction in the same layer surrounding different regions of a sidewall of the same first isolation layer, wherein the first isolation layer includes a recessed region disposed between adjacent semiconductor layers along the second direction on the side facing the bit line.

[0013] In some embodiments, the transistor further includes: a first gate insulator layer disposed between the first sub-word line and the semiconductor layer, and a second gate insulator layer disposed between the second sub-word line and the semiconductor layer; the first gate insulator layers of transistors in the same column distributed along the second direction in the same layer are connected to form an integral structure extending along the second direction; the second gate insulator layers of transistors in the same column distributed along the second direction in the same layer are connected to form an integral structure extending along the second direction.

[0014] In some embodiments, the semiconductor device further includes: a second isolation layer disposed between adjacent bit lines along a second direction and extending through multiple layers, the second isolation layer including a vertical portion extending through multiple layers in a direction perpendicular to the substrate and a plurality of horizontal portions extending between the first gate insulator layer and the second gate insulator layer respectively and connected to the recessed region of the first isolation layer, the first gate insulator layer, and the second gate insulator layer.

[0015] In some embodiments, the dimension of the first sub-word line along the first direction is smaller than the dimension of the first gate insulator layer along the first direction, and a first isolation sub-layer connected to the first sub-word line, the first gate insulator layer, and the bit line is disposed on the side of the first sub-word line facing the bit line; the dimension of the second sub-word line along the first direction is smaller than the dimension of the second gate insulator layer along the first direction, and a second isolation sub-layer connected to the second sub-word line, the second gate insulator layer, and the bit line is disposed on the side of the second sub-word line facing the bit line.

[0016] In some embodiments, the transistor further includes a first electrode connected to the semiconductor layer, the first electrode, the word line, and the bit line being distributed along the first direction, the semiconductor layer being disposed between the first electrode and the bit line, and the first electrode forming an annular groove with an opening direction parallel to the substrate.

[0017] In some embodiments, the semiconductor layer has protrusions parallel to the substrate and disposed opposite each other along a second direction on the side facing away from the substrate or the side facing the substrate. The size of the semiconductor layer along the second direction decreases sequentially from the location of the protrusion toward the bit line; the size of the semiconductor layer along the second direction decreases sequentially from the location of the protrusion toward the first electrode.

[0018] In some embodiments, a third isolation sub-layer is provided on the side of the first sub-word line away from the bit line, and is connected to the first sub-word line, the first gate insulator layer, and the first electrode; a fourth isolation sub-layer is provided on the side of the second sub-word line away from the bit line, and is connected to the second sub-word line, the second gate insulator layer, and the first electrode.

[0019] In some embodiments, the memory cell further includes: a capacitor, the capacitor including a first sub-electrode, the first electrode surrounding the first sub-electrode, a first dielectric layer disposed between the first electrode and the first sub-electrode, the first sub-electrode being distributed on the inner wall of the annular groove formed by the first electrode; or, the first sub-electrode being distributed on the inner wall of the annular groove formed by the first electrode and on the outer wall parallel to the substrate; the first sub-electrodes of memory cells at the same position in different layers are connected to form an integral structure.

[0020] In some embodiments, the capacitor further includes a second sub-electrode and a second dielectric layer, the second sub-electrode being distributed on the outer sidewall of the first electrode perpendicular to the substrate, the second dielectric layer being disposed between the second sub-electrode and the first electrode, and extending to a region between the first isolation layer and the first gate insulator layer located between adjacent semiconductor layers along a second direction, and a region between the first isolation layer and the second gate insulator layer located between adjacent semiconductor layers along a second direction.

[0021] This disclosure provides a method for manufacturing a semiconductor device, including:

[0022] A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate;

[0023] A first trench is formed that penetrates the stacked structure in a direction perpendicular to the substrate and extends in a second direction. Based on the trench, the first sacrificial layer is etched in a direction parallel to the substrate to form a first lateral trench extending in the second direction.

[0024] Multiple bit lines are formed in the first trench, extending perpendicular to the substrate direction and spaced apart along the second direction;

[0025] A first sub-word line and a second sub-word line extending along a second direction and spaced apart along a direction perpendicular to the substrate are formed in the first transverse trench, as well as a plurality of semiconductor layers spaced apart along the second direction. The first sub-word line and the second sub-word line respectively contact two first insulating layers that serve as sidewalls of the first transverse trench. The first sub-word line is disposed on the side of the second sub-word line away from the substrate. The semiconductor layers are disposed between the first sub-word line and the second sub-word line. The plurality of semiconductor layers correspond one-to-one with the plurality of bit lines, and the semiconductor layers are connected to the corresponding bit lines.

[0026] In some embodiments, forming a plurality of bit lines extending perpendicular to the substrate direction and spaced apart in the second direction in the first trench, and forming a first sub-word line and a second sub-word line extending in the second direction within the first lateral trench, includes:

[0027] A first conductive layer and a gate insulating structure layer are formed to sequentially cover the inner wall of the first transverse trench, and a second sacrificial layer is formed to fill the first transverse trench, wherein the end of the first conductive layer is at a predetermined distance from the opening of the first transverse trench.

[0028] A second insulating layer is formed to fill the first trench and the first transverse trench;

[0029] A plurality of first holes are formed that penetrate the second insulating layer along a direction perpendicular to the substrate and are spaced apart along the second direction. The sidewalls of the first holes expose the second sacrificial layer, and a plurality of bit lines are formed that respectively fill the plurality of first holes.

[0030] A plurality of second holes are formed on the side of the first transverse trench away from the first trench, and the first sacrificial layer is etched along the second direction to expose the first conductive layer based on the second holes in a direction parallel to the substrate to form a first groove.

[0031] Based on the second hole and the first groove, the first conductive layer and the gate insulating structure layer are etched to expose the second sacrificial layer, and the distance between the first conductive layer and the second hole after etching is greater than the distance between the gate insulating structure layer and the second hole; a fourth insulating layer is formed covering the end of the first conductive layer facing the second hole, and a first dummy layer is formed to fill the second hole and the first groove;

[0032] A second trench is formed on the side of the second hole away from the first trench, penetrating the stacked structure in a direction perpendicular to the substrate and extending in the second direction. The first sacrificial layer is etched based on the second trench to expose the first conductive layer, forming a second lateral trench. The first conductive layer and the gate insulating structure layer are etched based on the second lateral trench to expose the second sacrificial layer, such that the first conductive layer forms the first sub-word line and the second sub-word line, and the gate insulating structure layer forms a first gate insulator layer and a second gate insulator layer spaced apart in a direction perpendicular to the substrate.

[0033] In some embodiments, forming a plurality of semiconductor layers spaced apart along a second direction within the first lateral trench includes:

[0034] The first dummy layer is etched away to form the first capacitor electrode distributed on the inner wall of the first groove;

[0035] A plurality of third holes are formed that penetrate the second insulating layer along a direction perpendicular to the substrate and are spaced apart along the second direction, and the third holes are disposed between adjacent bit lines along the second direction;

[0036] Based on the third hole, the second sacrificial layer is etched away in a direction parallel to the substrate to form a channel;

[0037] A semiconductor thin film and an eighth insulating thin film are deposited sequentially. The eighth insulating thin film fills the channel. The eighth insulating thin film and the semiconductor thin film in the third hole are etched away. The eighth insulating thin film and the semiconductor thin film in the channel are etched to form a semiconductor structure layer and a first isolation layer. The semiconductor structure layer is connected to a plurality of bit lines spaced apart along the second direction and to a plurality of first capacitor electrodes spaced apart along the second direction. There are recessed regions disposed between adjacent bit lines along the second direction on the side away from the substrate and the side facing the substrate.

[0038] The semiconductor structure layer is etched based on the second trench and the second lateral trench, such that the semiconductor structure layer is broken into a plurality of semiconductor layers spaced apart along the second direction.

[0039] This application provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of any of the semiconductor devices described above.

[0040] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings.

[0041] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0042] Overview of the attached figures

[0043] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0044] Figures 1A to 1G are cross-sectional views of the semiconductor device provided in the embodiments of this disclosure along the AA', A1A1', BB' directions parallel to the substrate, and the CC', DD', EE', and FF' directions perpendicular to the substrate; Figure 1H is an enlarged view of region 100 in Figure 1E;

[0045] Figures 2A, 2B, and 2C are cross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments after the formation of the first conductive layer and the gate insulating structure layer.

[0046] Figures 3A, 3B, and 3C are cross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments after the formation of the second insulating layer;

[0047] Figures 4A, 4B, and 4C are cross-sectional views along the AA', BB', and DD' directions after the bit lines are formed, respectively, according to some embodiments.

[0048] Figures 5A to 5E are cross-sectional views along the AA', BB', CC', DD', and EE' directions respectively, provided in some embodiments after the formation of the second hole and the first groove.

[0049] Figures 6A to 6E are cross-sectional views along the AA', BB', CC', DD' and EE' directions respectively, provided in some embodiments after the formation of the second trench and the second transverse trench;

[0050] Figures 7A to 7E are cross-sectional views along the AA', BB', CC', DD', and EE' directions after the word line structure is formed according to some embodiments.

[0051] Figures 8A to 8E are cross-sectional views along the AA', BB', CC', DD', and FF' directions respectively, provided in some embodiments after forming the first capacitor electrode, the first sub-electrode, and the first dielectric layer.

[0052] Figures 9A to 9E are cross-sectional views along the AA', BB', DD', EE', and FF' directions after the third hole is formed, according to some embodiments.

[0053] Figures 10A to 10E are cross-sectional views along the A1A1', BB', DD', EE', and FF' directions respectively, provided in some embodiments after the formation of a semiconductor structure layer;

[0054] Figures 11A to 11F are cross-sectional views along the A1A1', BB', CC', DD', EE', and FF' directions, respectively, provided in some embodiments after disconnecting multiple semiconductor layers in the same column.

[0055] Detailed Explanation

[0056] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0057] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0058] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0059] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0060] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0061] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0062] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0063] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0064] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0065] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0066] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0067] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0068] Figures 1A to 1G are cross-sectional views of the semiconductor device provided in this disclosure along the directions parallel to substrate 1 (AA', A1A1', BB', CC', DD', EE', and FF'), and perpendicular to substrate 1 (CC', DD', EE', and FF'). The AA' direction passes through the film layer containing the first isolation layer 18; the A1A1' direction passes through the semiconductor layer 23 but not through the film layer containing the first isolation layer 18; the BB' direction passes through the film layer between adjacent first capacitor electrodes 41 along a direction perpendicular to substrate 1; the CC' and FF' directions are parallel, and the CC' direction passes through the region containing the capacitor; the FF' direction passes through the region containing the transistor; the DD' and EE' directions are parallel and intersect with the CC' and FF' directions; the DD' direction passes through the region containing the capacitor; and the EE' direction passes through the region between adjacent capacitors along the second direction Y. As shown in Figures 1A to 1G, this disclosure provides a semiconductor device that may include:

[0069] Multiple memory cells are stacked along the direction perpendicular to substrate 1, distributed across different layers;

[0070] Multiple bit lines 30 extend through the memory cells in different layers along a direction perpendicular to the substrate 1 and are spaced apart in the second direction Y.

[0071] Multiple word lines are distributed on different layers. The word lines and bit lines 30 are distributed along a first direction X parallel to the substrate 1. The word lines may include first sub-word lines 40a and second sub-word lines 40b spaced apart along a direction perpendicular to the substrate 1. The first sub-word lines 40a and second sub-word lines 40b extend along a second direction Y parallel to the substrate 1. The first sub-word line 40a may be configured such that the second sub-word line 40b is located away from the substrate 1. The first direction X and the second direction Y intersect. The first sub-word line 40a and the second sub-word line 40b belong to the same word line, that is, the first sub-word line 40a and the second sub-word line 40b are connected to the same signal terminal and loaded with the same control signal.

[0072] The memory cell includes a transistor, and the transistor may include a semiconductor layer 23 connected to the bit line 30; the semiconductor layer 23 is disposed between the first sub-word line 40a and the second sub-word line 40b; the first sub-word line 40a is distributed on the side of the semiconductor layer 23 away from the substrate 1, and the second sub-word line 40b is distributed on the side of the semiconductor layer 23 facing the substrate 1.

[0073] The solution provided in this embodiment, by setting the word lines as double-layered sub-word lines and disposing the semiconductor layer between the double-layered sub-word lines, can shield the word lines of adjacent memory cells along the direction perpendicular to the substrate, avoid interference between memory cells and adjacent word lines, and improve the control effect of word lines on the channel.

[0074] In some embodiments, the orthographic projections of the first sub-word line 40a and the second sub-word line 40b onto the substrate 1 overlap. The orthographic projections of the first sub-word line 40a and the semiconductor layer 23 onto the substrate 1 overlap, as do the orthographic projections of the second sub-word line 40b and the semiconductor layer 23 onto the substrate 1.

[0075] In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0076] In some embodiments, as shown in Figures 1E, 1F, and 1G, the semiconductor device may further include: a first isolation layer 18 extending along the second direction Y between the first sub-word line 40a and the second sub-word line 40b, wherein the semiconductor layer 23 surrounds the first isolation layer 18. In the solution provided in this embodiment, the semiconductor layer 23 has a ring-shaped structure, which facilitates manufacturing, and the ring-shaped semiconductor layer is easily controlled by the double-layered sub-word lines. The first isolation layer 18 may be a solid structure.

[0077] In some embodiments, the semiconductor device may include: a multilayer memory cell array, each layer of the memory cell array including a plurality of memory cells arrayed along the first direction X and the second direction Y; and multiple semiconductor layers 23 of multiple transistors arranged in the same column along the second direction Y of the same layer surrounding different regions of the sidewall of the same first isolation layer 18. The side of the first isolation layer 18 facing the bit line 30 may include recessed regions disposed between adjacent semiconductor layers 23 along the second direction Y, as shown in Figures 1A and 1B. The multiple semiconductor layers 23 in the same column are spaced apart along the second direction Y. The side of the first isolation layer 18 facing away from the bit line 30 may be a plane substantially parallel to the second direction Y. The recessed regions may be located between adjacent bit lines 30 along the second direction Y.

[0078] In some embodiments, as shown in FIG1G, the transistor may further include: a first gate insulator layer 24a disposed between the first sub-word line 40a and the semiconductor layer 23, and a second gate insulator layer 24b disposed between the second sub-word line 40b and the semiconductor layer 23. Multiple first gate insulator layers 24a of multiple transistors distributed in the same column along the second direction Y in the same layer can be connected to form an integral structure extending along the second direction Y, and multiple second gate insulator layers 24b of multiple transistors distributed in the same column along the second direction Y in the same layer can be connected to form an integral structure extending along the second direction Y. The solution provided in this embodiment can form a column of first gate insulator layers 24a and second gate insulator layers 24b of transistors in one step, simplifying the process and reducing costs. However, the embodiments of this disclosure are not limited to this; the multiple first gate insulator layers 24a of multiple transistors in the same column can be disconnected, and the multiple second gate insulator layers 24b of multiple transistors in the same column can be disconnected.

[0079] Figure 1H is an enlarged view of region 100 in Figure 1E. In some embodiments, as shown in Figure 1H, the dimension of the first sub-word line 40a along the first direction X is smaller than the dimension of the first gate insulator layer 24a along the first direction X. A first isolation sub-layer 121 connected to the first sub-word line 40a, the first gate insulator layer 24a, and the bit line 30 is provided on the side of the first sub-word line 40a facing the bit line 30. The dimension of the second sub-word line 40b along the first direction X is smaller than the dimension of the second gate insulator layer 24b along the first direction X. A second isolation sub-layer 122 connected to the second sub-word line 40b, the second gate insulator layer 24b, and the bit line 30 is provided on the side of the second sub-word line 40b facing the bit line 30. The first isolation sub-layer 121 can isolate the bit line 30 and the first sub-word line 40a, and the second isolation sub-layer 122 can isolate the bit line 30 and the second sub-word line 40b.

[0080] In some embodiments, as shown in Figures 1A, 1B, 1C, and 1F, the semiconductor device may further include a second isolation layer 19 disposed between adjacent bit lines 30 along the second direction Y, penetrating multiple layers. The second isolation layer 19 may include a vertical portion extending through multiple layers along a direction perpendicular to the substrate 1 and a plurality of horizontal portions. The plurality of horizontal portions extend respectively between the first gate insulator layer 24a and the second gate insulator layer 24b in different layers and are connected to the recessed region of the first isolation layer 18, the first gate insulator layer 24a, and the second gate insulator layer 24b. The second isolation layer 19 may be connected to the side of the first gate insulator layer 24a opposite to the first sub-word line 40a, and to the side of the second gate insulator layer 24b opposite to the second sub-word line 40b.

[0081] In some embodiments, the transistor may further include a first electrode connected to the semiconductor layer 23, namely a first capacitor electrode 41. The first electrode, the word line and the bit line 30 are distributed along the first direction X. The semiconductor layer 23 is disposed between the first electrode and the bit line 30. The first electrode may form an annular groove with an opening direction parallel to the substrate 1, as shown in FIG1E.

[0082] In some embodiments, a third isolation sublayer 141 is provided on the side of the first sub-word line 40a away from the bit line 30, and is connected to the first sub-word line 40a, the first gate insulator layer 24a, and the first electrode (i.e., the first capacitor electrode 41). A fourth isolation sublayer 142 is provided on the side of the second sub-word line 40b away from the bit line 30, and is connected to the second sub-word line 40b, the second gate insulator layer 24b, and the first electrode. The third isolation sublayer 141 isolates the first sub-word line 40a and the first capacitor electrode 41; the fourth isolation sublayer 142 isolates the second sub-word line 40b and the first capacitor electrode 41.

[0083] In some embodiments, the memory cell may further include: a capacitor, the capacitor including a first capacitor electrode 41 (i.e., a first electrode) and a second capacitor electrode, the second capacitor electrode including a first sub-electrode 421, the first electrode surrounding the first sub-electrode 421, a first dielectric layer 431 disposed between the first electrode and the first sub-electrode 421, the first sub-electrode 421 being distributed on the inner wall of the annular groove formed by the first electrode; or, the first sub-electrode 421 being distributed on the inner wall of the annular groove formed by the first electrode and the outer wall parallel to the substrate 1 (i.e., the outer wall facing the substrate 1 and the outer wall away from the substrate 1); the first sub-electrodes 421 of memory cells at the same position in different layers may be connected to form an integral structure extending in a direction perpendicular to the substrate 1. The third isolation sub-layer 141 and the fourth isolation sub-layer 142 are also connected to the first dielectric layer 431.

[0084] In some embodiments, the first dielectric layer 431 of memory cells at the same location on different layers can be connected to form an integral structure.

[0085] In some embodiments, the memory cell may include a capacitor aperture penetrating multiple layers along a direction perpendicular to the substrate 1. A first capacitor electrode 41, a first dielectric layer 431, and a first sub-electrode 421 are sequentially distributed from the outside to the inside of the capacitor aperture. The first sub-electrode 421 fills the capacitor aperture. The solution provided in this embodiment can form multiple first capacitor electrodes 41, multiple first dielectric layers 431, and multiple first sub-electrodes 421 of capacitors simultaneously, simplifying the process.

[0086] In some embodiments, the capacitor may further include a second sub-electrode 422 and a second dielectric layer 432. The second sub-electrode 422 is distributed on the outer sidewall of the first electrode perpendicular to the substrate 1. The second dielectric layer 432 is disposed between the second sub-electrode 422 and the first electrode, and extends to the region between the first isolation layer 18 and the first gate insulator layer 24a located between adjacent semiconductor layers 23 along the second direction Y, and the region between the first isolation layer 18 and the second gate insulator layer 24b located between adjacent semiconductor layers 23 along the second direction Y, as shown in Figures 1B, 1F, and 1G. The second dielectric layer 432 is also connected to the second isolation layer 19. In the region defined by the first gate insulator layer 24a and the second gate insulator layer 24b, the region between adjacent semiconductor layers 23 along the second direction Y is divided into two parts along the first direction X, referred to as the first region and the second region. The first region, which is far away from the bit line 30, is filled by the first isolation layer 18 and the second dielectric layer 432 distributed on the side of the first isolation layer 18 away from the substrate 1 and the side of the first isolation layer 18 facing the substrate 1. The second region, which is close to the bit line 30, is filled by the second isolation layer 19, as shown in FIG1F.

[0087] In some embodiments, as shown in Figures 1A and 1B, the second sub-electrode 422 may also fill the region between adjacent first capacitor electrodes 41 along the second direction Y. The second sub-electrodes 422 of a plurality of capacitors arranged in the same column along the second direction Y may be connected to form an integral structure.

[0088] In some embodiments, the second sub-electrodes 422 of multiple memory cells in the same column of different layers can be connected to form an integral structure. The second sub-electrodes 422 of multiple memory cells in multiple layers can be connected by a planar film layer extending through multiple layers in a direction perpendicular to the substrate 1.

[0089] In some embodiments, as shown in FIG1B, the semiconductor layer 23 has protrusions parallel to the substrate 1 and disposed opposite each other along the second direction Y on the side facing away from the substrate 1 or the side facing the substrate 1. From the location of the protrusions toward the bit line 30, the size of the semiconductor layer 23 along the second direction Y decreases sequentially; from the location of the protrusions toward the first electrode, the size of the semiconductor layer 23 along the second direction Y decreases sequentially. The solution provided in this embodiment facilitates the disconnection of multiple semiconductor layers 23 by etching from both sides. Compared with the single-sided etching solution, it allows for a larger contact surface between the semiconductor layer 23 and the bit line 30 and the first capacitor electrode 41. In some embodiments, the position where the size of the semiconductor layer 23 along the second direction Y is the largest can be approximately the same as the distance between the bit line 30 and the first capacitor electrode 41 along the first direction X, that is, the protrusion is located at the middle position of the semiconductor layer 23.

[0090] In some embodiments, as shown in FIG1E, the maximum dimension of the first capacitor electrode 41 along the direction perpendicular to the substrate 1 can be the same as the distance between the side of the first sub-line 40a away from the substrate 1 and the side of the second sub-line 40b facing the substrate 1. That is, when manufacturing the first capacitor electrode 41 and the first sub-line 40a and the second sub-line 40b, the height of the film layer where the first capacitor electrode 41 is located is the same as the height of the film layer where the first sub-line 40a and the second sub-line 40b are located.

[0091] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. In this embodiment, a film pattern is formed through a "patterning process" or a "photolithography process." The "patterning process" includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning or photolithography process contains at least one "pattern".

[0092] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0093] 1) Forming a first conductive layer 27 and a gate insulating structure layer 24';

[0094] A substrate 1 is provided, and a first insulating film and a first sacrificial layer film are alternately deposited on the substrate 1 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and first sacrificial layers 10;

[0095] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a plurality of first trenches T1 that penetrate the stacked structure (only one first trench T1 is shown in Figures 2A, 2B and 2C), and the first trenches T1 extend along the second direction Y;

[0096] Based on the first trench T1, the first sacrificial layer 10 is etched laterally (along the direction parallel to the substrate 1) to form the first lateral trench L1;

[0097] A first conductive film, a gate insulating film, and a second sacrificial layer are sequentially deposited to form a first conductive layer 27, a gate insulating structure layer 24', and a second sacrificial layer 9. The first conductive layer 27 and the gate insulating structure layer 24' sequentially cover the bottom wall and sidewall of the first trench T1 and the inner wall of the first transverse trench L1. The second sacrificial layer 9 fills the first transverse trench L1 and covers the bottom wall and bottom wall of the first trench T1, as shown in Figures 2A, 2B, and 2C. Figures 2A, 2B, and 2C are cross-sectional views along the AA', BB', and DD' directions after the formation of the first conductive layer 27 and the gate insulating structure layer 24', respectively, provided in some embodiments.

[0098] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0099] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent second to ninth insulating films are similar and will not be described in detail.

[0100] In some embodiments, the first sacrificial layer film and the second sacrificial layer film may be films with an etching selectivity ratio to the first insulating film, such as silicon nitride (SiN).

[0101] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0102] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0103] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0104] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0105] The materials of the subsequent second to fifth conductive films are similar to those of the first conductive film, and will not be described in detail again.

[0106] In some embodiments, the material of the gate insulating structure layer 24' may comprise one or more high-K dielectric materials. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0107] 2) Forming a second insulating layer 12;

[0108] The second sacrificial layer film, gate insulating film, and first conductive film in the first trench T1 are removed by etching, while the second sacrificial layer film, gate insulating film, and first conductive film in the first transverse trench L1 are retained, such that the first conductive layer 27, the gate insulating structure layer 24', and the second sacrificial layer 9 are distributed only in the first transverse trench L1; and the first conductive layer 27 in the first transverse trench L1 is etched to a first predetermined length, such that the length of the first conductive layer 27 along the first direction X is less than the length of the gate insulating structure layer 24' along the first direction X, and there is a predetermined distance between the end of the first conductive layer 27 and the opening of the first transverse trench L1;

[0109] A second insulating film is deposited, filling the first trench T1 and the first lateral trench L1 to form a second insulating layer 12, as shown in Figures 3A, 3B, and 3C. Figures 3A, 3B, and 3C are cross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments, after the formation of the second insulating layer 12. The second insulating layer 12 is distributed at the end of the first conductive layer 27 in the first lateral trench L1 (i.e., the cavity formed after the first conductive layer 27 in the first lateral trench L1 is etched), facilitating the isolation of the subsequently formed bit line 30 from the first conductive layer 27. The first isolation sublayer 121 and the second isolation sublayer 122 are part of the second insulating layer 12.

[0110] 3) Form bit line 30;

[0111] The second insulating layer 12 is etched along a direction perpendicular to the substrate 1 to form a plurality of first holes K1 penetrating the second insulating layer 12. The plurality of first holes K1 are spaced apart along the second direction Y. The sidewalls of the first holes K1 expose the second sacrificial layer 9, that is, along the first direction X, the first holes K1 penetrate the second insulating layer 12.

[0112] A second conductive film is deposited to form a bit line 30 that fills the first hole K1, as shown in Figures 4A, 4B and 4C. Figures 4A, 4B and 4C are cross-sectional views along the AA' direction, BB' direction and DD' direction after the bit line 30 is formed according to some embodiments.

[0113] In some embodiments, the bit line 30 may include a first sub-layer 31 and a second sub-layer 32. The first sub-layer 31 may be a conductive material with good adhesion to other film layers, such as TiN, and the second sub-layer 32 may be a conductive material with low resistivity, such as tungsten. The first sub-layer 31 covers the bottom wall and sidewalls of the first hole K1, and the second sub-layer 32 fills the first hole K1.

[0114] 4) Form the second hole K2 and the first groove A1;

[0115] A third insulating film is deposited to form a third insulating layer 13 covering the aforementioned structure;

[0116] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a plurality of second holes K2 penetrating the stacked structure. The plurality of second holes K2 are spaced apart along the second direction Y. The second holes K2 are disposed on the side of the first conductive layer 27 away from the bit line 30. The second holes K2 can be elongated holes extending along the first direction X. The size of the second holes K2 can be set according to the size requirements of the capacitor.

[0117] Based on the second hole K2, the first sacrificial layer 10 is etched laterally to expose the first conductive layer 27, forming the first groove A1; and at this time, different second holes K2 remain unconnected, that is, the first sacrificial layer 10 is retained between adjacent second holes K2 along the second direction Y.

[0118] The first conductive layer 27 is etched to expose the gate insulating structure layer 24';

[0119] The gate insulating structure layer 24' is etched to expose the second sacrificial layer 9, as shown in Figures 5A, 5B, 5C, 5D, and 5E. Figures 5A to 5E are cross-sectional views along the AA', BB', CC', DD', and EE' directions respectively, provided in some embodiments, after the formation of the second hole K2 and the first groove A1. The length of the first conductive layer 27 etched along the first direction X can be slightly greater than the length of the gate insulating structure layer 24' etched, so that after etching, the gate insulating structure layer 24' protrudes slightly relative to the first conductive layer 27 towards the second hole K2, making the distance between the first conductive layer 27 and the second hole K2 after etching greater than the distance between the gate insulating structure layer 24' and the second hole K2. At this time, there are multiple openings (at the first groove A1) on the side of the first conductive layer 27 away from the bit line 30.

[0120] 5) Form the second trench T2 and the second transverse trench L2;

[0121] A fourth insulating film is deposited, which covers the bottom and sidewalls of the second hole K2 and the first groove A1. The fourth insulating film in the second hole K2 is etched away, and the fourth insulating film in the first groove A1 is etched away until the gate insulating structure layer 24' and the second sacrificial layer 9 are exposed. The fourth insulating film covering the side of the first conductive layer 27 facing the second hole K2 is retained, forming a fourth insulating layer 14. The fourth insulating layer 14 includes a third isolation sublayer 141 and a fourth isolation sublayer 142.

[0122] After depositing the first dummy layer film, it is ground flat to form the first dummy layer 71; the first dummy layer 71 fills the second hole K2 and the first groove A1; after grinding, the third insulating layer 13 is removed, so that the side of the first dummy layer 71 facing away from the substrate 1 is flush with the side of the bit line 30 facing away from the substrate 1; a fifth insulating film is deposited to form a fifth insulating layer 15 covering the structure formed above.

[0123] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a plurality of second trenches T2 penetrating the stacked structure; the second trenches T2 extend along a second direction Y, and adjacent second trenches T2 define a group of memory cells, each group of memory cells including two columns of memory cells; the second trenches T2 are disposed on the side of the second hole K2 opposite to the bit line 30.

[0124] The first sacrificial layer 10 is removed by lateral etching (etching along the direction parallel to the substrate 1) based on the second trench T2, exposing the first conductive layer 27 and forming the second lateral trench L2; as shown in Figures 6A, 6B, 6C, 6D and 6E, Figures 6A to 6E are cross-sectional views along the AA' direction, BB' direction, CC' direction, DD' direction and EE' direction after the formation of the second trench T2 and the second lateral trench L2 provided in some embodiments.

[0125] In some embodiments, the first dummy layer film may be a film layer with an etching selectivity ratio to the fourth insulating film, such as polycrystalline silicon. The materials of the subsequent second and third dummy layer films are similar to those of the first dummy layer film and will not be described further.

[0126] 6) Forming a character line structure;

[0127] Based on the second lateral trench L2, the first conductive layer 27 is etched to expose the gate insulating structure layer 24'. At this time, the first conductive layer 27 forms a disconnected first sub-word line 40a and a second sub-word line 40b. The first sub-word line 40a and the second sub-word line 40b are respectively distributed on two sidewalls of the first lateral trench L1 parallel to the substrate 1. At this time, a word line structure including two sub-word lines stacked along the direction perpendicular to the substrate 1 is formed.

[0128] The gate insulating structure layer 24' is etched to expose the second sacrificial layer 9; at this time, the gate insulating structure layer 24' forms a disconnected first gate insulator layer 24a and second gate insulator layer 24b; the first gate insulator layer 24a is connected to the first sub-word line 40a, and is separated from the first sub-word line 40a and the subsequently formed semiconductor layer 23; the second gate insulator layer 24b is connected to the second sub-word line 40b, and is separated from the second sub-word line 40b and the subsequently formed semiconductor layer 23.

[0129] After sequentially depositing the sixth insulating film and the second dummy layer film, the layers are ground smooth to form the sixth insulating layer 16 and the second dummy layer 72. The sixth insulating layer 16 covers the inner walls of the second trench T2 and the second transverse trench L2, and the second dummy layer 72 fills the second trench T2 and the second transverse trench L2, as shown in Figures 7A, 7B, 7C, 7D and 7E. Figures 7A to 7E are cross-sectional views along the AA' direction, BB' direction, CC' direction, DD' direction and EE' direction after forming the word line structure according to some embodiments.

[0130] 7) Form the first capacitor electrode 41, the first sub-electrode 421, and the first dielectric layer 431;

[0131] Etching removes the first dummy layer 71 from the second hole K2 and the first groove A1;

[0132] The third conductive film and the third dummy layer film are deposited sequentially, and the third dummy layer film and the third conductive film in the second hole K2 are etched away, while the third dummy layer film and the third conductive film in the first groove A1 are retained to form the third dummy layer and the first capacitor electrode 41.

[0133] The third dummy layer in the first groove A1 is removed by lateral etching based on the second hole K2;

[0134] Based on the second hole K2, the first insulating layer 11 is laterally etched to expose the outer wall of the first capacitor electrode 41 facing the substrate 1 and away from the substrate 1, forming the second groove A2;

[0135] After sequentially depositing a first dielectric film and a fourth conductive film, the layers are smoothed to form a first dielectric layer 431 and a first sub-electrode 421. The first dielectric layer 431 covers the inner walls of the second hole K2, the first groove A1, and the second groove A2, and the first sub-electrode 421 fills the second hole K2, the first groove A1, and the second groove A2, as shown in Figures 8A, 8B, 8C, 8D, and 8E. Figures 8A to 8E are cross-sectional views along the AA', BB', CC', DD', and FF' directions, respectively, provided in some embodiments after forming the first capacitor electrode 41, the first sub-electrode 421, and the first dielectric layer 431. The side of the first sub-electrode 421 facing away from the substrate 1 is flush with the side of the bit line 30 facing away from the substrate 1. The fifth insulating layer 15 is removed after smoothing.

[0136] In some embodiments, the first sub-electrode 421 may include a third sub-layer 33 and a fourth sub-layer 34. The third sub-layer 33 may be a film with good adhesion, such as TiN, and the fourth sub-layer 34 may be a conductive material with low resistivity, such as tungsten. The third sub-layer 33 is distributed on the bottom wall and inner sidewall of the first capacitor electrode 41, as well as on the outer sidewall facing the substrate 1 and the outer sidewall facing away from the substrate 1. The fourth sub-layer 34 fills the second hole K2, the first groove A1, and the second groove A2.

[0137] In some embodiments, the first dielectric film may be a high-K dielectric material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. The materials of the subsequent second dielectric film are similar to those of the first dielectric film and will not be described further.

[0138] 8) Formation of the third hole K3;

[0139] A seventh insulating film is deposited to form a seventh insulating layer 17 covering the aforementioned structure; the seventh insulating layer 17 covers the bit line 30 and the first sub-electrode 421, so as to protect the bit line 30 and the first sub-electrode 421 in subsequent manufacturing processes.

[0140] The seventh insulating layer 17 and the second insulating layer 12 are etched along a direction perpendicular to the substrate 1 to form a plurality of third holes K3 penetrating the seventh insulating layer 17 and the second insulating layer 12. The plurality of third holes K3 are spaced apart along the second direction Y. The sidewalls of the third holes K3 expose the second sacrificial layer 9. That is, along the first direction X, the third holes K3 penetrate the second insulating layer 12. The third holes K3 are disposed between adjacent bit lines 30 along the second direction Y. Only one third hole K3 is disposed between every two adjacent bit lines 30 along the second direction Y. The sidewalls of the third holes K3 expose the two adjacent bit lines 30.

[0141] Based on the third hole K3, the second sacrificial layer 9 is removed by lateral etching to form channel B1, as shown in Figures 9A, 9B, 9C, 9D, and 9E. Figures 9A to 9E are cross-sectional views along the AA', BB', DD', EE', and FF' directions after the formation of the third hole K3, provided in some embodiments. The first capacitor electrode 41 is exposed in channel B1.

[0142] 9) Forming a semiconductor structure layer 23';

[0143] A semiconductor thin film and an eighth insulating thin film are sequentially deposited on the substrate 1 on which the aforementioned structure is formed;

[0144] The eighth insulating film in the third hole K3 is etched away, and the eighth insulating film in the channel B1 is etched laterally while retaining a predetermined length of the eighth insulating film. The exposed semiconductor film (including the semiconductor film in the third hole K3 and a portion of the semiconductor film in the channel B1 near the third hole K3) is etched away, forming a semiconductor structure layer 23' and a first isolation layer 18. The semiconductor structure layer 23' can be divided into a first part and a second part distributed along the first direction X, wherein the first part is close to the bit line 30 and the second part is close to the first capacitor electrode 41. In the current step, the first part includes multiple segments that are disconnected from each other (all of which are connected to the second part). The second part can be divided in a subsequent step, so that the semiconductor structure layer 23' forms multiple semiconductor layers 23 that are disconnected from each other. The semiconductor structure layer 23' surrounds the first isolation layer 18. The side of the first isolation layer 18 facing the bit line 30 may include a recessed region disposed between adjacent semiconductor layers 23 along the second direction Y.

[0145] After depositing the ninth insulating film, it is ground flat. The ninth insulating film fills the third hole K3 and channel B1 to form the second isolation layer 19, as shown in Figures 10A, 10B, 10C, 10D, and 10E. Figures 10A to 10E are cross-sectional views along the A1A1' direction, BB' direction, DD' direction, EE' direction, and FF' direction after forming the semiconductor structure layer 23' according to some embodiments.

[0146] The side of the second insulating layer 19 facing away from the substrate 1 is flush with the side of the first sub-electrode 421 facing away from the substrate 1. The seventh insulating layer 17 was removed during the grinding process.

[0147] In some embodiments, the material of the semiconductor thin film may be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0148] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0149] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0150] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0151] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0152] 10) Disconnect multiple semiconductor layers 23 in the same column;

[0153] The second dummy layer 72 is etched away to expose the sixth insulating layer 16.

[0154] The sixth insulating layer 16 is etched to expose the second trench T2 and the second lateral trench L2, thus exposing the semiconductor structure layer 23'.

[0155] The semiconductor structure layer 23' is etched to form a third groove A3 and a plurality of semiconductor layers 23 disconnected from each other. The semiconductor layers 23 are connected to the bit line 30 and the first capacitor electrode 41. The third groove A3 includes two sub-grooves. The bottom wall of the sub-grooves is the second isolation layer 19. The upper and lower sidewalls of the sub-grooves parallel to the substrate 1 expose the first gate insulator layer 24a and the first isolation layer 18, respectively. Alternatively, the first isolation layer 18 and the second gate insulator layer 24b are exposed. The two sidewalls of the sub-grooves that intersect with the substrate 1 expose the semiconductor layers 23, as shown in Figures 11A, 11B, 11C, 11D, 11E and 11F. Figures 11A to 11F are cross-sectional views along the A1A1' direction, BB' direction, CC' direction, DD' direction, EE' direction and FF' direction after disconnecting the plurality of semiconductor layers 23 in the same row according to some embodiments. In this embodiment, the semiconductor structure layer 23' is cut off by etching from both sides. Compared with etching from one side, this allows for a larger contact area between the semiconductor layer 23 and the bit line 30.

[0156] 11) Forming a second dielectric layer 432 and a second sub-electrode 422;

[0157] A second dielectric film and a fifth conductive film are deposited sequentially to form a second dielectric layer 432 and a second sub-electrode 422. The second dielectric layer 432 fills the third groove A3 and covers the inner walls of the second trench T2 and the second lateral trench L2. The second sub-electrode 422 fills the second trench T2 and the second lateral trench L2, as shown in Figures 1A to 1G.

[0158] In some embodiments, the second sub-electrode 422 may include a fifth sub-layer 35 and a sixth sub-layer 36. The fifth sub-layer 35 may be a film layer with good adhesion, such as TiN, and the sixth sub-layer 36 may be a conductive material with low resistivity, such as tungsten.

[0159] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0160] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, comprising: Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers; Multiple bit lines, penetrating different layers of the memory cells, extend along a direction perpendicular to the substrate and are spaced apart in a second direction; Multiple word lines are distributed in different layers, and the word lines and bit lines are distributed along a first direction parallel to the substrate; the word lines include first sub-word lines and second sub-word lines that are spaced apart along a direction perpendicular to the substrate; the first sub-word lines and the second sub-word lines extend along a second direction parallel to the substrate; the first direction and the second direction intersect. The memory cell includes a transistor, the transistor including a semiconductor layer connecting the bit line; the semiconductor layer is disposed between the first sub-word line and the second sub-word line; the first sub-word line is distributed on the side of the semiconductor layer away from the substrate, and the second sub-word line is distributed on the side of the semiconductor layer facing the substrate.

2. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: a first isolation layer disposed between the first sub-word line and the second sub-word line and extending along the second direction, the semiconductor layer surrounding the first isolation layer.

3. The semiconductor device according to claim 2, wherein, The semiconductor device includes: a multilayer memory cell array, each layer of the memory cell array including a plurality of memory cells distributed along the first direction and the second direction; and multiple semiconductor layers of a plurality of transistors distributed in the same column along the second direction in the same layer surrounding different regions of the sidewall of the same first isolation layer, wherein the first isolation layer includes a recessed region disposed between adjacent semiconductor layers along the second direction on the side facing the bit line.

4. The semiconductor device according to claim 3, wherein, The transistor further includes: a first gate insulator layer disposed between the first sub-word line and the semiconductor layer, and a second gate insulator layer disposed between the second sub-word line and the semiconductor layer; the first gate insulator layers of transistors in the same column distributed along the second direction in the same layer are connected to form an integral structure extending along the second direction; the second gate insulator layers of transistors in the same column distributed along the second direction in the same layer are connected to form an integral structure extending along the second direction.

5. The semiconductor device according to claim 4, wherein, The semiconductor device further includes: a second isolation layer disposed between adjacent bit lines along a second direction, penetrating multiple layers, the second isolation layer including a vertical portion extending through multiple layers along a direction perpendicular to the substrate and a plurality of horizontal portions extending between the first gate insulator layer and the second gate insulator layer respectively and connected to the recessed region of the first isolation layer, the first gate insulator layer and the second gate insulator layer.

6. The semiconductor device according to claim 5, wherein, The dimension of the first sub-word line along the first direction is smaller than the dimension of the first gate insulator layer along the first direction. A first isolation sub-layer is provided on the side of the first sub-word line facing the bit line, which is connected to the first sub-word line, the first gate insulator layer, and the bit line. The dimension of the second sub-word line along the first direction is smaller than the dimension of the second gate insulator layer along the first direction. A second isolation sub-layer is provided on the side of the second sub-word line facing the bit line, which is connected to the second sub-word line, the second gate insulator layer, and the bit line.

7. The semiconductor device according to claim 6, wherein, The transistor further includes a first electrode connected to the semiconductor layer. The first electrode, the word line, and the bit line are distributed along the first direction. The semiconductor layer is disposed between the first electrode and the bit line. The first electrode forms an annular groove with an opening direction parallel to the substrate.

8. The semiconductor device according to claim 7, wherein, The semiconductor layer has protrusions that are parallel to the substrate and arranged opposite each other along a second direction on the side facing away from the substrate or the side facing the substrate. The size of the semiconductor layer along the second direction decreases sequentially from the location of the protrusion toward the bit line. The size of the semiconductor layer along the second direction also decreases sequentially from the location of the protrusion toward the first electrode.

9. The semiconductor device according to claim 7, wherein, The first sub-word line has a third isolation sub-layer disposed on the side away from the bit line, which is connected to the first sub-word line, the first gate insulator layer, and the first electrode. The second sub-word line has a fourth isolation sub-layer disposed on the side away from the bit line, which is connected to the second sub-word line, the second gate insulator layer, and the first electrode.

10. The semiconductor device according to claim 7, wherein, The storage cell further includes a capacitor, the capacitor including a first sub-electrode, the first electrode surrounding the first sub-electrode, a first dielectric layer disposed between the first electrode and the first sub-electrode, the first sub-electrode being distributed on the inner wall of the annular groove formed by the first electrode; or, the first sub-electrode being distributed on the inner wall of the annular groove formed by the first electrode and on the outer wall parallel to the substrate; the first sub-electrodes of storage cells at the same position in different layers are connected to form an integral structure.

11. The semiconductor device according to claim 10, wherein, The capacitor further includes a second sub-electrode and a second dielectric layer. The second sub-electrode is distributed on the outer sidewall of the first electrode perpendicular to the substrate. The second dielectric layer is disposed between the second sub-electrode and the first electrode and extends to the region between the first isolation layer and the first gate insulator layer located between adjacent semiconductor layers along the second direction, and the region between the first isolation layer and the second gate insulator layer located between adjacent semiconductor layers along the second direction.

12. A method for manufacturing a semiconductor device, comprising: A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate; A first trench is formed that penetrates the stacked structure in a direction perpendicular to the substrate and extends in a second direction. Based on the trench, the first sacrificial layer is etched in a direction parallel to the substrate to form a first lateral trench extending in the second direction. Multiple bit lines are formed in the first trench, extending perpendicular to the substrate direction and spaced apart along the second direction; A first sub-word line and a second sub-word line extending along a second direction and spaced apart along a direction perpendicular to the substrate are formed in the first transverse trench, as well as a plurality of semiconductor layers spaced apart along the second direction. The first sub-word line and the second sub-word line respectively contact two first insulating layers that serve as sidewalls of the first transverse trench. The first sub-word line is disposed on the side of the second sub-word line away from the substrate. The semiconductor layers are disposed between the first sub-word line and the second sub-word line. The plurality of semiconductor layers correspond one-to-one with the plurality of bit lines, and the semiconductor layers are connected to the corresponding bit lines.

13. The method for manufacturing a semiconductor device according to claim 12, wherein, The step of forming multiple bit lines extending perpendicular to the substrate direction and spaced apart along the second direction in the first trench, and forming a first sub-word line and a second sub-word line extending along the second direction in the first transverse trench, includes: A first conductive layer and a gate insulating structure layer are formed to sequentially cover the inner wall of the first transverse trench, and a second sacrificial layer is formed to fill the first transverse trench, wherein the end of the first conductive layer is at a predetermined distance from the opening of the first transverse trench. A second insulating layer is formed to fill the first trench and the first transverse trench; A plurality of first holes are formed that penetrate the second insulating layer along a direction perpendicular to the substrate and are spaced apart along the second direction. The sidewalls of the first holes expose the second sacrificial layer, and a plurality of bit lines are formed that respectively fill the plurality of first holes. A plurality of second holes are formed on the side of the first transverse trench away from the first trench, and the first sacrificial layer is etched along the second direction to expose the first conductive layer based on the second holes in a direction parallel to the substrate to form a first groove. Based on the second hole and the first groove, the first conductive layer and the gate insulating structure layer are etched to expose the second sacrificial layer, and the distance between the first conductive layer and the second hole after etching is greater than the distance between the gate insulating structure layer and the second hole; a fourth insulating layer is formed covering the end of the first conductive layer facing the second hole, and a first dummy layer is formed to fill the second hole and the first groove; A second trench is formed on the side of the second hole away from the first trench, penetrating the stacked structure in a direction perpendicular to the substrate and extending in the second direction. The first sacrificial layer is etched based on the second trench to expose the first conductive layer, forming a second lateral trench. The first conductive layer and the gate insulating structure layer are etched based on the second lateral trench to expose the second sacrificial layer, such that the first conductive layer forms the first sub-word line and the second sub-word line, and the gate insulating structure layer forms a first gate insulator layer and a second gate insulator layer spaced apart in a direction perpendicular to the substrate.

14. The method for manufacturing a semiconductor device according to claim 13, wherein, Forming a plurality of semiconductor layers spaced apart along a second direction within the first lateral trench includes: The first dummy layer is etched away to form the first capacitor electrode distributed on the inner wall of the first groove; A plurality of third holes are formed that penetrate the second insulating layer along a direction perpendicular to the substrate and are spaced apart along the second direction, and the third holes are disposed between adjacent bit lines along the second direction; Based on the third hole, the second sacrificial layer is etched away in a direction parallel to the substrate to form a channel; A semiconductor thin film and an eighth insulating thin film are deposited sequentially. The eighth insulating thin film fills the channel. The eighth insulating thin film and the semiconductor thin film in the third hole are etched away. The eighth insulating thin film and the semiconductor thin film in the channel are etched to form a semiconductor structure layer and a first isolation layer. The semiconductor structure layer is connected to a plurality of bit lines spaced apart along the second direction and to a plurality of first capacitor electrodes spaced apart along the second direction. There are recessed regions disposed between adjacent bit lines along the second direction on the side away from the substrate and the side facing the substrate. The semiconductor structure layer is etched based on the second trench and the second lateral trench, such that the semiconductor structure layer is broken into a plurality of semiconductor layers spaced apart along the second direction.

15. An electronic device comprising a semiconductor device as claimed in any one of claims 1 to 11, or a semiconductor device formed by a method of manufacturing a semiconductor device according to any one of claims 12 to 14.

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