Display panel and display device
By increasing the overlap area between the isolation structure and the first power line, the burn-in problem caused by the high current density at the overlap of the isolation structure in the OLED display panel was solved, thus improving the yield and voltage distribution uniformity of the display panel.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HEFEI VISIONOX TECH CO LTD
- Filing Date
- 2025-10-29
- Publication Date
- 2026-06-18
AI Technical Summary
In existing OLED display panels, the current density at the junction of the isolation structure and the common voltage trace is high, which can easily lead to screen burn-in and affect the yield of the display panel.
By increasing the total overlap area between the isolation structure and the first power line, making it larger than the total overlap area between the first power line and the bonding area, the overlap area between the isolation structure and the first power line is increased, thereby reducing the risk of screen burn-in caused by current density.
This reduces the current density at the junction of the isolation structure and the first power line, thereby reducing the risk of screen burn-in and improving the yield rate and voltage distribution uniformity of the display panel.
Smart Images
Figure CN2025130981_18062026_PF_FP_ABST
Abstract
Description
Display panel and display device Technical Field
[0001] This application relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology
[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide application range, becoming the mainstream display devices. In the traditional display panel manufacturing process, a fine metal mask (FMM) is typically used to pattern the light-emitting pixels. FMM technology is mature and has extensive mass production experience. However, FMM technology also has problems such as limited precision, high development costs, and long development cycles. Fine metal mask-less technology eliminates the limitations of traditional OLED processes on display size, resolution, and other screen performance aspects, offering advantages such as high performance, full-size display, and agile delivery. Patents CN118251982A, CN116648095A, CN117062489A, CN118742138A, CN118678783A, CN118660598A, CN118675450A, CN118824188A, and CN118781966A describe relevant content on the technology of not using fine metal masks, and are provided for reference.
[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention
[0004] To overcome the above deficiencies, the present application aims to provide a display panel, the display panel including a display area and a bonding area located on one side of the display area; the display panel includes: a substrate; a wiring layer located on one side of the substrate, the wiring layer including a first power line, a first end of the first power line overlapping with the bonding area; an isolation structure located on the side of the wiring layer away from the substrate, the isolation structure being at least partially located in the display area; the isolation structure being electrically connected to the bonding area through at least one first power line; wherein, the isolation structure includes at least one overlap area, the orthographic projection of the overlap area on the substrate is located within the orthographic projection of the first power line on the substrate, the overlap area including a plurality of first overlap holes, the isolation structure being electrically connected to the second end of the first power line through the first overlap holes, and the total area of the first overlap holes being greater than the total overlap area between the first power line and the bonding area.
[0005] Another objective of this application is to provide a display panel, the display panel including a display area and a bonding area located on one side of the display area; the display panel includes: a substrate; a wiring layer located on one side of the substrate, the wiring layer including a first power line, a first end of the first power line overlapping with the bonding area; an isolation structure located on the side of the wiring layer away from the substrate, the isolation structure being at least partially located in the display area, the isolation structure being electrically connected to the bonding area through at least one first power line; wherein, the isolation structure includes at least one overlap area, the orthographic projection of the overlap area onto the substrate is located within the orthographic projection of the first power line onto the substrate, the isolation structure is connected to the first power line in the overlap area, and the total area of the overlap area is greater than or equal to 0.1% of the area of the display area.
[0006] Another objective of this application is to provide a display panel, the display panel including a display area and a bonding area located on one side of the display area; the display panel includes: a substrate; a wiring layer located on one side of the substrate, the wiring layer including a first power line, a first end of the first power line overlapping with the bonding area; an isolation structure located on the side of the wiring layer away from the substrate, the isolation structure being at least partially located in the display area; the isolation structure being electrically connected to the bonding area through at least one first power line; wherein, the isolation structure includes at least one overlap area, the orthographic projection of the overlap area onto the substrate is located within the orthographic projection of the first power line onto the substrate, the overlap area including a plurality of first overlap holes, the isolation structure being electrically connected to a second end of the first power line through the first overlap holes, and the total area of the first overlap holes connected to the second end of at least one first power line being greater than the total overlap area between the first end of the same first power line and the bonding area.
[0007] Another object of this application is to provide a display device, which includes the display panel provided in this application, or the display device includes a display panel made by the manufacturing method of the display panel provided in this application.
[0008] This application has the following beneficial effects:
[0009] This application provides a display panel and a display device. By setting the total overlap area of the overlap hole between the isolation structure and the first power line to be greater than the total overlap area between the first power line and the bonding area, the overlap area between the isolation structure and the first power line is increased, thereby reducing the risk of screen burn-in due to high current density at the overlap point between the isolation structure and the first power line. Attached Figure Description
[0010] Figure 1 is one of the schematic diagrams showing the connection between the isolation structure and the first power supply provided in this embodiment.
[0011] Figure 2 is one of the cross-sectional schematic diagrams of the display panel provided in this embodiment.
[0012] Figure 3 is a second schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0013] Figure 4 is the third schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0014] Figure 5 is the fourth schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0015] Figure 6 is the fifth schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0016] Figure 7a is a schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0017] Figure 7b is the seventh schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0018] Figure 8a is the eighth schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0019] Figure 8b is a schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0020] Figure 9 is a schematic diagram of the isolation opening and the first overlapping hole provided in this embodiment.
[0021] Figure 10a is the tenth schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0022] Figure 10b is an eleventh schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0023] Figure 11 is a third cross-sectional schematic diagram of the display panel provided in this embodiment.
[0024] Figure 12 is a schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0025] Figure 13 is a schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0026] Figure 14 is one of the schematic diagrams of the first lap hole provided in this embodiment.
[0027] Figure 15 is a second schematic diagram of the first overlapping hole provided in this embodiment.
[0028] Figure 16 is a third schematic diagram of the first overlapping hole provided in this embodiment.
[0029] Figure 17 is a fourth cross-sectional schematic diagram of the display panel provided in this embodiment.
[0030] Figure 18 is one of the schematic diagrams of the isolation structure provided in this embodiment.
[0031] Figure 19 is a second schematic diagram of the isolation structure provided in this embodiment.
[0032] Figure 20 is the fourteenth schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment.
[0033] Figure 21 is a schematic diagram of the connection between the isolation structure and the first power supply provided in this embodiment, number fifteen.
[0034] Icons: 111-Substrate; 130-Insulating layer; 131-First insulating layer; 132-Second insulating layer; 120-First electrode; 120-First connection trace; 140-Isolation structure; 141-Support portion; 142-Shielding portion; 143-Receiving portion; 150-Light-emitting functional layer; 160-Second electrode; 170-Packaging unit; 180-First encapsulation layer; 190-Second encapsulation layer; 200-Tracking layer; 210-First power line; 211-Branch; 220-Second power line; 600-Overlap area; 1401-First overlap area; 1404-Sub-overlap area; 1403-Second overlap area; 1201-Second overlap hole ; 801 - Light-emitting device; 910 - Isolation opening; 920 - Recess; 310 - Bonding contact; 320 - Sub-bonding area; 410 - First overlapping hole; 401 - First through hole; 402 - Second through hole; 403 - Third through hole; 501 - Third insulating layer; 502 - Second connection trace; 503 - Touch trace layer; 701 - First sub-isolation structure; 702 - Second sub-isolation structure; 810 - Pixel unit; AA - Display area; NA10 - Bonding area; NA21 - First border area; NA22 - Second border area; D1 - First direction; D2 - Second direction; AA11 - First sub-display area; AA12 - Second sub-display area. Detailed Implementation
[0035] In some related display panels, by setting an isolation structure in the display panel, the organic light-emitting material layer between adjacent pixel openings is broken during the whole-layer evaporation of the organic light-emitting material layer. Thus, organic light-emitting material layers with different emission colors can be formed in different pixel openings by patterned etching after the whole-layer evaporation.
[0036] The inventors discovered that in the aforementioned display panel, the isolation structure is conductive. The cathode of the light-emitting device, located within the isolation opening, overlaps with the isolation structure and is then connected to the common voltage trace (Vss) through the isolation structure. The common voltage trace and the isolation structure are not on the same layer and are interconnected through overlap holes. The current density at these overlap holes is relatively high, which can easily lead to screen burn-in and affect the yield rate of the display panel.
[0037] In view of this, this embodiment provides a solution that can reduce the risk of screen burn-in on display panels. The solution provided in this embodiment will be described in detail below.
[0038] Please refer to Figure 1, which is a schematic diagram of a display panel provided in this embodiment. The display panel may include a display area AA and a bonding area NA10 located on one side of the display area AA.
[0039] Optionally, in this embodiment, the display area AA includes a light-emitting side and a backlight side. The bonding area NA10 is used to mount integrated circuit chips or connect to other circuit boards, and the bonding area NA10 can be folded to the backlight side of the display panel.
[0040] Please refer to Figure 2. The display panel provided in this embodiment may include a substrate 111, a wiring layer 200, and an isolation structure 140.
[0041] In this embodiment, the material of the substrate 111 may include a rigid material, such as glass. Alternatively, the material of the substrate 111 may include a flexible material, such as polyimide (PI).
[0042] Optionally, an array functional layer may also be provided on one side of the substrate 111. The array functional layer may include multiple film layer structures, such as a buffer layer, an active layer, multiple conductive layers, multiple insulating layers 130, and a planarization layer. The multiple film layer structures of the array functional layer can form multiple thin film transistors (TFTs) and wiring structures at different locations. The thin film transistors can cooperate with each other to form multiple pixel driving units or driving circuits, and the wiring structures provide signals or voltages to the circuits.
[0043] The wiring layer 200 is located on one side of the substrate 111, and the wiring layer 200 can be a conductive layer in the array of functional layers. The wiring layer 200 includes a first power line 210. Optionally, in this embodiment, the first power line 210 can be used to transmit a common voltage (Vss), and a first end of the first power line 210 can be connected to the bonding region NA10. For example, the bonding region NA10 is provided with a plurality of bonding contacts 310, and the first end of the first power line 210 can be connected to the bonding contacts 310.
[0044] The isolation structure 140 is located on the side of the wiring layer 200 away from the substrate 111, and the isolation structure 140 is at least partially located in the display area AA. For example, the isolation structure 140 encloses a plurality of isolation openings 910 located in the display area AA. The isolation structure 140 is electrically connected to the bonding area NA10 via at least one first power line 210.
[0045] Optionally, in the display area AA, the display panel also includes a light-emitting device 801 located at least partially within the isolation opening 910. The light-emitting device 801 includes a first electrode 120, a light-emitting functional layer 150, and a second electrode 160 stacked in a direction away from the substrate 111.
[0046] Optionally, the first electrode 120 can be connected to the pixel driving circuit in the array functional layer, and the second electrode 160 can be connected to the first power line 210 that transmits the common voltage (Vss) through the isolation structure 140. When there is a potential difference between the first electrode 120 and the second electrode 160, the light-emitting functional layer 150 located between the first electrode 120 and the second electrode 160 is driven to emit light.
[0047] Referring to Figure 3, the isolation structure 140 includes at least one overlap region 600. The orthographic projection of the overlap region 600 on the substrate 111 lies within the orthographic projection of the first power line 210 on the substrate 111. The overlap region 600 includes a plurality of first overlap holes 410. The isolation structure 140 is electrically connected to the second end of the first power line 210 through the first overlap holes 410. Thus, the isolation structure 140 achieves electrical connection with the bonding region NA10 through the first power line 210.
[0048] The total area of the first lap hole 410 is greater than the total lap area of the first power line 210 and the bonding area NA10.
[0049] The total area of the first overlapping hole 410 can be the total area of the orthographic projection of the first overlapping hole 410 on the substrate 111, and the total overlapping area of the first power line 210 and the bonding area NA10 can be the total area of the overlapping portion of the orthographic projection of the first power line 210 on the substrate 111 and the orthographic projection of the bonding contact 310 in the bonding area NA10 on the substrate 111.
[0050] Based on the above design, by setting the total overlap area of the overlap hole between the isolation structure 140 and the first power line 210 to be greater than the total overlap area between the first power line 210 and the bonding area NA10, the overlap area between the isolation structure 140 and the first power line 210 is increased, thereby reducing the risk of screen burn-in due to high current density at the overlap point between the isolation structure 140 and the first power line 210.
[0051] In some possible implementations, see Figures 4 and 5, the display panel also includes a first bezel area NA21 located between the display area AA and the bonding area NA10. At least three overlap areas 600 are located in the first bezel area NA21, and the isolation structure 140 overlaps with at least three first power lines 210 respectively through the at least three overlap areas 600.
[0052] That is, in this embodiment, the isolation structure 140 can be connected to at least three first power lines 210 in the first frame area NA21. This increases the number of connection points between the isolation structure 140 and the first power lines 210, making the voltage distribution on the side of the isolation structure 140 closer to the first frame more uniform and reducing the risk of large differences in voltage drop uniformity at different locations of the isolation structure 140.
[0053] Optionally, the bonding area NA10 includes at least two sub-bonding areas 320, and the number of overlapping areas 600 is greater than or equal to the number of sub-bonding areas 320.
[0054] In some possible implementations, the display area AA, the first border area NA21, and the bonding area NA10 are arranged sequentially along the first direction D1, and at least two sub-bonding areas 320 are arranged along the second direction D2, with the first direction D1 intersecting the second direction D2.
[0055] Optionally, the bonding contact 310 may be located on the side of the sub-bonding area 320 away from the display area AA. In the second direction D2, two overlapping areas 600 are located on both sides of the first bezel area NA21, and at least one first power line 210 is located between two adjacent sub-bonding areas 320.
[0056] That is, in this embodiment, at least a portion of the first power line 210 can extend from the bonding area NA10 along the first direction D1 through the gap between two adjacent sub-bonding areas 320 to the first border area NA21 and connect with the isolation structure 140. In this way, the position between the sub-bonding areas 320 can be fully utilized to arrange the first power line 210, increasing the number of overlap areas between the isolation structure 140 and the first power line 210.
[0057] Optionally, the subbonded area 320 may be equipped with a driver chip.
[0058] In this embodiment, when the bonding area NA10 is folded to the back of the display area AA, the first power line 210 located in the bonding area NA10 also bends accordingly. In this case, the extension direction of the first power line 210 is consistent with the bending and folding direction of the bonding area NA10.
[0059] In some possible implementations, see Figure 5, in the second direction D2, the width W1 of the overlap area 600 located between two adjacent sub-bonding areas 320 is greater than the width W2 of the overlap area 600 located on both sides of the first border area NA21.
[0060] For example, in the second direction D2, the width W1 of the overlap area 600 located between two adjacent sub-bonding areas 320 is twice the width W2 of the overlap area 600 located on both sides of the first border area NA21.
[0061] This increases the overlap area between the first power line 210 and the isolation structure 140, reduces the overlap resistance, and lowers the risk of screen burn-in.
[0062] In some possible implementations, see Figure 6, in the second direction D2, the overlap area 600 located between two adjacent sub-bonding areas 320 includes two sub-overlap areas 1404 spaced apart along the second direction D2.
[0063] In the second direction D2, the width of the sub-overlapping area 1404 is equal to the width of the bonding area NA10 located on both sides of the first border area NA21.
[0064] Optionally, the two sub-overlap areas 1404 of the same overlap area 600 are respectively connected to different bonding contacts 310 of the bonding area NA10. For example, the two sub-overlap areas 1404 of the same overlap area 600 are respectively connected to bonding contacts 310 belonging to different circuit boards.
[0065] In some possible implementations, see Figures 7a and 7b, the display panel also includes a first border area NA21 and a second border area NA22 that are set opposite to each other. The first border area NA21 is located between the display area AA and the bonding area NA10, and the second border area NA22 is located on the side of the display area AA away from the first border area NA21.
[0066] The overlap area 600 includes at least one first overlap area 1401 located in the first border area NA21 and at least one second overlap area 1403 located in the second border area NA22.
[0067] That is, in this embodiment, the isolation structure 140 can be connected to different first power lines 210 in the first frame area NA21 and the second frame area NA22 respectively. In this way, the number of overlapping areas can be further increased, the overlapping resistance can be reduced, and the distribution of overlapping areas can be made more uniform. This improves the voltage uniformity of the side of the isolation structure 140 near the first frame area NA21 and the side near the second frame area NA22, thus ensuring the display uniformity of the display panel.
[0068] Optionally, the display area AA, the first border area NA21, and the bonding area NA10 are arranged sequentially along the first direction D1. In the second direction D2, two first overlapping areas 1401 are located on either side of the first border area NA21. The first direction D1 intersects with the second direction D2.
[0069] Optionally, the isolation structure 140 is connected to different first power lines 210 via a first overlap area 1401 and a second overlap area 1403. This avoids overloading a single first power line 210.
[0070] In some possible implementations, a first overlapping area 1401 and a second overlapping area 1403 are located on the same straight line in the first direction D1.
[0071] Optionally, the number of first overlapping areas 1401 and the number of second overlapping areas 1403 are equal.
[0072] In this way, the uniformity of the overlap area distribution on the side of the isolation structure 140 near the first frame region NA21 and the side near the second frame region NA22 can be improved, thereby improving the overall voltage distribution uniformity of the isolation structure 140.
[0073] In some possible implementations, see Figures 8a and 8b, the display panel also includes a first border area NA21 located between the display area AA and the bonding area NA10. The display area AA, the first border area NA21 and the bonding area NA10 are arranged sequentially along a first direction D1. A first power line 210 extends from the first border area NA21 to the display area AA along the first direction D1. At least a portion of the first overlap hole 410 is located in the display area AA.
[0074] That is, in this embodiment, the first power line 210 can extend to the display area AA and overlap with the isolation structure 140. In this way, the number of overlap areas between the isolation structure 140 and the first power line 210 can be further increased, and the voltage uniformity of each position of the isolation structure 140 in the display area AA can be improved.
[0075] Optionally, the display panel also includes a second border area NA22 located on the side of the display area AA away from the first border area NA21, and the first power line 210 extends from the first border area NA21 through the display area AA to the second border area NA22 along the first direction D1.
[0076] Optionally, the first overlapping holes 410 are all located in the display area AA.
[0077] Optionally, please refer to Figure 9, which is an enlarged schematic diagram of the SA1 position shown in Figure 8b. The orthographic projection of the first overlapping hole 410 on the substrate 111 is located between the orthographic projections of two or more adjacent isolation openings 910 on the substrate 111. In this way, the first overlapping hole 410 can be prevented from affecting the isolation openings 910, thereby improving the pixel density of the display panel.
[0078] Optionally, the orthographic projection of the first overlapping hole 410 on the substrate 111 is located between the orthographic projections of two adjacent repeating pixel units on the substrate 111. For example, in this embodiment, a red, a green, and a blue light-emitting device 801 can form a pixel unit, and multiple pixel units are repeatedly arranged. In this case, the first overlapping hole 410 can be disposed between the repeating pixel units.
[0079] Optionally, referring to Figures 10a and 10b, the first power line 210 further includes a branch 211 located in the display area AA and extending in a direction different from the first direction D1. The isolation structure 140 overlaps with at least a portion of the branch 211 through the first overlap hole 410. This further increases the number of overlap areas between the isolation structure 140 and the first power supply, and improves the voltage uniformity at various locations of the isolation structure 140 within the display area AA.
[0080] In some possible implementations, see Figure 11, the first electrode 120 is electrically connected to at least a portion of the traces in the trace layer 200 through the second lap hole 1201.
[0081] In this case, the area of the first lap hole 410 projected onto the substrate 111 is greater than the area of the second lap hole 1201 projected onto the substrate 111.
[0082] For example, the area of a single first lap hole 410 projected onto the substrate 111 is greater than or equal to 9 square micrometers.
[0083] In some possible implementations, see Figure 12, the display area AA and the bonding area NA10 are arranged along the first direction D1, and the orthographic projection of the first lap hole 410 on the substrate 111 is rectangular, with the long side of the rectangle extending along the second direction D2, which is different from the first direction D1.
[0084] In some possible implementations, referring to Figure 13, the display area AA and the bonding area NA10 are arranged along a first direction D1. The isolation structure 140 includes a first sub-isolation structure 701 and a second sub-isolation structure 702 arranged and spaced apart along a second direction D2. The first sub-isolation structure 701 and the second sub-isolation structure 702 are electrically connected to different first power lines 210. The first direction D1 intersects the second direction D2.
[0085] Optionally, the display area AA includes a first sub-display area AA11 and a second display area AA12 arranged along the second direction D2, with a first sub-isolation structure 701 located in the first sub-display area AA11 and a second sub-isolation structure 702 located in the second sub-display area AA12.
[0086] For example, the display panel provided in this embodiment can be a foldable display panel, and the gap between the sub-isolation structures is the folding area of the display panel. Different sub-isolation structures are electrically connected to different first power lines 210, so that power can be supplied to the two sub-isolation structures relatively independently. That is, when the first sub-display area AA11 does not need to display, but the second sub-display area AA12 needs to display, power can be supplied to the first sub-isolation structure 701 located in the first sub-display area AA11 without the first power line 210, but power can be supplied to the second sub-isolation structure 702 located in the second sub-display area AA12 through another first power line 210, thereby reducing the overall power consumption of the display panel.
[0087] In some possible implementations, see Figure 14, the display panel also includes a first insulating layer 131 and a second insulating layer 132 located between the isolation structure 140 and the wiring layer 200.
[0088] The first insulating layer 131 includes a first through-hole 401, and the second insulating layer 132 includes a second through-hole 402. The orthographic projection of the second through-hole 402 on the substrate 111 is located within the orthographic projection of the first through-hole 401 on the substrate 111. The first through-hole 401 and the second through-hole 402 communicate to form a first overlap hole 410. The first overlap hole 410 exposes at least a portion of the first power line 210.
[0089] At least a portion of the isolation structure 140 extends into the first lap hole 410 and is electrically connected to the first power line 210.
[0090] Optionally, in this embodiment, the first insulating layer 131 can be a planarization layer formed of organic material, and the second insulating layer 132 can be a pixel defining layer formed of inorganic material. The second insulating layer 132 can cover the sidewall of the first insulating layer 131 facing the first through hole 401, thereby avoiding exposure of the sidewall of the first insulating layer 131 and reducing the risk of moisture intrusion into the first insulating layer 131.
[0091] Optionally, the isolation structure 140 includes a recessed portion 920 recessed in a direction toward the substrate 111, wherein the orthographic projection of the recessed portion 920 on the substrate 111 and the orthographic projection of the first lap hole 410 on the substrate 111 at least partially overlap.
[0092] For example, a first insulating layer 131 and a second insulating layer 132 may be provided between the isolation structure 140 and the wiring layer 200. The isolation structure 140 is connected to the first power line 210 in the wiring layer 200 through a first overlapping hole 410 that penetrates the first insulating layer 131 and the second insulating layer 132. In this case, the isolation structure 140 at the position corresponding to the first overlapping hole 410 will form a recess 920 due to being embedded in the first overlapping hole 410.
[0093] In some possible implementations, referring to Figure 15, the display panel also includes a first insulating layer 131 and a second insulating layer 132 located between the isolation structure 140 and the wiring layer 200, and a first through-hole 401 penetrating the first insulating layer 131. A first lap hole 410 penetrates the second insulating layer 132.
[0094] The display panel also includes a first connection trace 121 located between the first insulating layer 131 and the second insulating layer 132.
[0095] A first through-hole 401 exposes at least a portion of the first power line 210, and at least a portion of the first connection trace 121 extends into the first through-hole 401 and is electrically connected to the first power line 210. A first overlap hole 410 exposes at least a portion of the first connection trace 121, and at least a portion of the isolation structure 140 extends into the first overlap hole 410 and is electrically connected to the first connection trace 121.
[0096] Optionally, the orthographic projection of the first through hole 401 on the substrate 111 and the orthographic projection of the first lap hole 410 on the substrate 111 are staggered.
[0097] That is, in this embodiment, the isolation structure 140 can be connected to the first power line 210 via the first connecting trace 121, wherein the first connecting trace 121 can be disposed on the same layer as the first electrode 120 of the light-emitting device 801. In this way, the flexibility of the first connecting hole 410 can be improved.
[0098] Optionally, the isolation structure 140 includes a recessed portion 920 recessed in a direction close to the substrate 111, the orthographic projection of the recessed portion 920 on the substrate 111 and the orthographic projection of the first overlapping hole 410 on the substrate 111 at least partially overlapping. Optionally, the recessed portion 920 is formed in the isolation structure 140 at locations corresponding to the positions of the first through hole 401 and the first overlapping hole 410.
[0099] In some possible implementations, please refer to FIG16, the display panel further includes a first insulating layer 131 and a second insulating layer 132 located between the isolation structure 140 and the wiring layer 200. The display panel also includes a third insulating layer 501 located on the side of the isolation structure 140 away from the substrate 111 and a touch wiring layer 503 located on the side of the third insulating layer 501 away from the substrate 111.
[0100] The first insulating layer 131 includes a first through hole 401, the second insulating layer 132 includes a second through hole 402, and the third insulating layer 501 includes a third through hole.
[0101] The orthographic projection of the second via 402 on the substrate 111 lies within the orthographic projection of the first via 401 on the substrate 111. The first via 401, the second via 402, and the third via 403 are connected and expose at least a portion of the first power line 210. The orthographic projection of the isolation structure 140 on the substrate 111 is offset from the orthographic projections of the first via 401, the second via 402, and the third via 403 on the substrate 111.
[0102] The first lap hole 410 penetrates the third insulating layer 501. For example, the third insulating layer 501 covers the isolation structure 140, and the first lap hole 410 exposes the isolation structure 140.
[0103] The touch wiring layer 503 includes touch wiring and a second connection wiring 502 disposed on the same layer. At least a portion of the second connection wiring 502 extends into the connected first through hole 401, second through hole 402 and third through hole 403 and is electrically connected to the first power line 210. At least another portion of the second connection wiring 502 is electrically connected to the isolation structure 140 through the first overlap hole 410.
[0104] That is, in this embodiment, the second connection trace 502 in the touch trace layer 503 can be connected to the first power line 210 and the isolation structure 140 respectively, thereby realizing the electrical connection between the first power line 210 and the isolation structure 140.
[0105] In some possible implementations, see Figure 17, the display panel also includes a plurality of encapsulation units 170, each encapsulation unit 170 including a side of the corresponding light-emitting device 801 away from the substrate 111.
[0106] Optionally, the display panel further includes a first encapsulation layer 180 and a second encapsulation layer 190 located sequentially on the side of the encapsulation unit 170 and the isolation structure 140 away from the substrate 111.
[0107] Optionally, the materials of the encapsulation unit 170 and the second encapsulation layer 190 include inorganic materials. The material of the first encapsulation layer 180 includes organic materials.
[0108] In some possible implementations, please refer to FIG18. The isolation structure 140 includes a support portion 141 and a shielding portion 142 located on the side of the support portion 141 away from the substrate 111. The orthographic projection of the end of the support portion 141 near the isolation opening 910 on the substrate 111 is located within the orthographic projection of the shielding portion 142 on the substrate 111.
[0109] Alternatively, under the same etching conditions, the corrosion resistance of the support portion 141 is weaker than that of the shielding portion 142.
[0110] Optionally, the material of the support portion 141 may include aluminum, and / or the material of the shielding portion 142 may include titanium.
[0111] Optionally, referring to FIG19, the isolation structure 140 also includes a receiving portion 143 located between the support portion 141 and the substrate 111.
[0112] Optionally, the orthographic projection of the receiving portion 143 on the substrate 111 is located within the orthographic projection of the end of the shielding portion 142 near the isolation opening 910 on the substrate 111.
[0113] Optionally, the material of the receiving part 143 includes molybdenum.
[0114] In some possible implementations, please refer to Figure 20. The wiring layer 200 may also include a second power trace 220 extending from the bonding area NA10 to the first border area NA21. The second power trace 220 may be used to transmit driving power (Vdd). The second power trace 220 may be electrically connected to the pixel driving circuit in the display area AA. Figure 20 does not show the connection path between the second power trace 220 and the pixel driving circuit in the display area AA, and it will not be described in detail in this embodiment.
[0115] Referring to Figure 21, this application also provides a display panel, which includes a display area AA and a bonding area NA10 located on one side of the display area AA. The display panel includes a substrate 111, a wiring layer 200, and an isolation structure 140.
[0116] The wiring layer 200 is located on one side of the substrate 111. The wiring layer 200 includes a first power line 210, and the first end of the first power line 210 can overlap with the bonding area NA10. For example, the bonding area NA10 is provided with a plurality of bonding contacts 310, and the first end of the first power line 210 can overlap with the bonding contacts 310.
[0117] The isolation structure 140 is located on the side of the wiring layer 200 away from the substrate 111, and the isolation structure 140 is at least partially located in the display area AA. For example, the isolation structure 140 encloses a plurality of isolation openings 910 located in the display area AA. The isolation structure 140 is electrically connected to the bonding area NA10 via at least one first power line 210.
[0118] The isolation structure 140 includes at least one overlap area 600, which is connected to the first power line 210. The total area of the overlap area 600 is greater than or equal to 0.1% of the area of the display area AA.
[0119] For example, the orthographic projection of the overlap region 600 on the substrate 111 lies within the orthographic projection of the first power line 210 on the substrate 111. The overlap region 600 includes a plurality of first overlap holes 410, and the isolation structure 140 is electrically connected to the first power line 210 through the first overlap holes 410. The total area of the overlap region 600 is the total area covered by the arrangement of the plurality of first overlap holes 410.
[0120] Based on the above design, by increasing the area of the overlap region 600, the overlap resistance between the isolation structure 140 and the first power supply is reduced, thereby reducing the risk of screen burn-in of the display panel.
[0121] In some possible implementations, the display area AA and the bonding area NA10 are arranged along a first direction D1, and the first power line 210 extends from the bonding area NA10 along the first direction D1 to connect with the isolation structure 140.
[0122] The sum of the widths W11 of the multiple overlapping areas 600 in the second direction D2 is greater than or equal to 1 / 20 of the length W21 of the display area AA in the second direction D2, and the first direction D1 intersects the second direction D2.
[0123] Optionally, the first direction D1 is perpendicular to the second direction D2.
[0124] In some possible implementations, the display panel also includes a first bezel area NA21 located between the display area AA and the bonding area NA10. The overlap area 600 includes at least three overlap areas 600 located in the first bezel area NA21, and the isolation structure 140 overlaps with at least three first power lines 210 respectively through the at least three overlap areas 600.
[0125] Optionally, the bonding area NA10 includes at least two sub-bonding areas 320, and the number of overlapping areas 600 is greater than or equal to the number of sub-bonding areas 320.
[0126] Optionally, the display area AA, the first border area NA21, and the bonding area NA10 are arranged sequentially along the first direction D1, and at least two sub-bonding areas 320 are arranged along the second direction D2, with the first direction D1 intersecting the second direction D2.
[0127] Optionally, the bonding contact 310 may be located on the side of the sub-bonding area 320 away from the display area AA. In the second direction D2, two bonding areas NA10 are located on both sides of the first bezel area NA21, and at least one first power line 210 is located between two adjacent sub-bonding areas 320.
[0128] This application also provides a display panel, which includes a display area AA and a bonding area NA10 located on one side of the display area AA. The display panel includes a substrate 111, a wiring layer 200, and an isolation structure 140.
[0129] The wiring layer 200 is located on one side of the substrate 111. The wiring layer 200 includes a first power line 210, and the first end of the first power line 210 can be connected to the bonding area NA10.
[0130] The isolation structure 140 is located on the side of the wiring layer 200 away from the substrate 111, and the isolation structure 140 is at least partially located in the display area AA. For example, the isolation structure 140 encloses a plurality of isolation openings 910 located in the display area AA. The isolation structure 140 is electrically connected to the bonding area NA10 via at least one first power line 210.
[0131] The isolation structure 140 includes at least one overlap region 600. The orthographic projection of the overlap region 600 on the substrate 111 lies within the orthographic projection of the first power line 210 on the substrate 111. The overlap region 600 includes a plurality of first overlap holes 410. The isolation structure 140 is electrically connected to the first power line 210 through the first overlap holes 410. The total area of the first overlap holes 410 connected to the second end of at least one first power line 210 is greater than the total overlap area between the first end of the same first power line 210 and the bonding region NA10. This ensures that the total area of all first overlap holes 410 is greater than the total overlap area between all first power lines 210 and the bonding region NA10.
[0132] This application also provides a display device, which includes the display panel provided in this application. The display device may include devices with display functions such as mobile phones, tablets, smart wearable devices, televisions, laptops, and monitors.
[0133] In summary, this application provides a display panel and a display device. By setting the total overlap area of the overlap hole between the isolation structure and the first power line to be greater than the total overlap area between the first power line and the bonding area, the overlap area between the isolation structure and the first power line is increased, thereby reducing the risk of screen burn-in due to high current density at the overlap point between the isolation structure and the first power line.
[0134] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
Claims
1. A display panel, comprising a display area and a bonding area located on one side of the display area; the display panel comprising: Substrate; A wiring layer located on one side of the substrate, the wiring layer including a first power line, the first end of the first power line overlapping with the bonding region; An isolation structure located on the side of the wiring layer away from the substrate, the isolation structure being at least partially located in the display area; The isolation structure is electrically connected to the bonding area via at least one of the first power lines; The isolation structure includes at least one overlap area, the orthographic projection of the overlap area onto the substrate is located within the orthographic projection of the first power line onto the substrate, the overlap area includes a plurality of first overlap holes, the isolation structure is electrically connected to the second end of the first power line through the first overlap holes, and the total area of the first overlap holes is greater than the total overlap area between the first power line and the bonding area.
2. The display panel according to claim 1, wherein, The display panel further includes a first border area located between the display area and the bonding area; at least three overlapping areas are located in the first border area, and at least three overlapping areas are respectively connected to at least three first power lines; The bonding region includes at least two sub-bonding regions, and the number of overlapping regions is greater than or equal to the number of sub-bonding regions; The sub-bonding area is equipped with a driver chip.
3. The display panel according to claim 2, wherein, The display area, the first border area, and the bonding area are arranged sequentially along a first direction, and at least two of the sub-bonding areas are arranged along a second direction, wherein the first direction intersects with the second direction; In the second direction, the two overlapping areas are located on both sides of the first frame area, and at least one of the first power lines is located between two adjacent sub-bonding areas.
4. The display panel according to claim 3, wherein, In the second direction, the width of the overlap area located between two adjacent sub-bonding areas is greater than the width of the overlap area located on both sides of the first border area; In the second direction, the width of the overlap area located between two adjacent sub-bonding areas is twice the width of the overlap area located on both sides of the first border area.
5. The display panel according to claim 4, wherein, In the second direction, the overlap area located between two adjacent sub-bonding areas includes two sub-overlap areas spaced apart along the second direction; In the second direction, the width of the sub-overlapping area is equal to the width of the overlapping area located on both sides of the first border area; The two sub-overlap areas of the same overlap area are respectively connected to different bonding contacts of the bonding area.
6. The display panel according to any one of claims 1 to 5, wherein, The display panel further includes a first border area and a second border area disposed opposite to each other, the first border area being located between the display area and the bonding area, and the second border area being located on the side of the display area away from the first border area; The overlapping area includes at least one first overlapping area and at least one second overlapping area, wherein the first overlapping area is located in the first border area and the second overlapping area is located in the second border area; The display area, the first border area, and the bonding area are arranged along a first direction; in a second direction, the two first overlapping areas are located on both sides of the first border area; the first direction intersects with the second direction; The first overlap area and the second overlap area are connected to different first power lines; In the first direction, a first overlapping area and a second overlapping area are located on the same straight line; The number of the first overlapping area is equal to the number of the second overlapping area.
7. The display panel according to any one of claims 1 to 6, wherein, The display panel further includes a first border area located between the display area and the bonding area, the display area, the first border area and the bonding area are arranged sequentially along a first direction, the first power line extends from the first border area to the display area along the first direction, and at least a portion of the first overlap hole is located in the display area; The display panel further includes a second frame area located on the side of the display area away from the first frame area, and the first power line extends from the first frame area through the display area to the second frame area along the first direction; The first overlapping holes are all located in the display area; The orthographic projection of the first overlapping hole on the substrate is located between the orthographic projections of two or more adjacent isolation openings on the substrate; The orthographic projection of the first overlapping hole on the substrate is located between the orthographic projections of two adjacent repeating pixel units on the substrate; The first power line also includes a branch located in the display area and extending in a direction other than the first direction, and the isolation structure overlaps with at least a portion of the branch through the first overlap hole.
8. The display panel according to any one of claims 1 to 7, wherein, The display panel further includes a light-emitting device located at least partially within the isolation opening. The light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the substrate. The first electrode is electrically connected to at least a portion of the wiring in the wiring layer through a second overlap hole. The second electrode is electrically connected to the isolation structure; The area of the first overlapping hole projected onto the substrate is larger than the area of the second overlapping hole projected onto the substrate. The area of the orthographic projection of a single first lap hole onto the substrate is greater than or equal to 9 square micrometers; The display panel also includes multiple packaging units, which are located on the side of the corresponding light-emitting device away from the substrate; The display panel further includes a first encapsulation layer and a second encapsulation layer located sequentially on the side of the encapsulation unit and the isolation structure away from the substrate; The materials of the packaging unit and the second packaging layer include inorganic materials; the material of the first packaging layer includes organic materials.
9. The display panel according to any one of claims 1 to 8, wherein, The display area and the bonding area are arranged along a first direction, and the orthographic projection of the first bonding hole on the substrate is rectangular, with the long side of the rectangle extending along a second direction, which is different from the first direction.
10. The display panel according to any one of claims 1 to 9, wherein, The display area and the bonding area are arranged along a first direction, and the isolation structure includes a first sub-isolation structure and a second sub-isolation structure arranged and spaced apart along a second direction. The first sub-isolation structure and the second sub-isolation structure are electrically connected to different first power lines. The first direction intersects the second direction. The display area includes a first sub-display area and a second sub-display area arranged along a second direction, with the first sub-isolation structure located in the first sub-display area and the second sub-isolation structure located in the second sub-display area.
11. The display panel according to any one of claims 1 to 10, wherein, The display panel further includes a first insulating layer and a second insulating layer located between the isolation structure and the wiring layer; The first insulating layer includes a first through-hole, and the second insulating layer includes a second through-hole. The orthographic projection of the second through-hole on the substrate is located within the orthographic projection of the first through-hole on the substrate. The first through-hole and the second through-hole communicate to form the first overlap hole, and the first overlap hole exposes at least a portion of the first power line. At least a portion of the isolation structure extends into the first overlapping hole and is electrically connected to the first power line. The isolation structure includes a recessed portion that is recessed toward the substrate, the orthographic projection of the recessed portion onto the substrate and the orthographic projection of the first overlapping hole onto the substrate at least partially overlap.
12. The display panel according to any one of claims 1 to 10, wherein, The display panel further includes a first insulating layer and a second insulating layer located between the isolation structure and the wiring layer, and a first through hole penetrating the first insulating layer; the first overlapping hole penetrates the second insulating layer; The display panel also includes a first connection trace located between the first insulating layer and the second insulating layer; The first through hole exposes at least a portion of the first power line, and at least a portion of the first connection trace extends into the first through hole and is electrically connected to the first power line; the first overlap hole exposes at least a portion of the first connection trace, and at least a portion of the isolation structure extends into the first overlap hole and is electrically connected to the first connection trace. The orthographic projection of the first through hole on the substrate and the orthographic projection of the first overlapping hole on the substrate are offset; The isolation structure includes a recessed portion that is recessed toward the substrate, wherein the orthographic projection of the recessed portion onto the substrate and the orthographic projection of the first via onto the substrate at least partially overlap.
13. The display panel according to any one of claims 1 to 10, wherein, The display panel further includes a first insulating layer and a second insulating layer located between the isolation structure and the wiring layer; the display panel further includes a third insulating layer located on the side of the isolation structure away from the substrate and a touch wiring layer located on the side of the third insulating layer away from the substrate; The first insulating layer includes a first through-hole, the second insulating layer includes a second through-hole, and the third insulating layer includes a third through-hole. The orthographic projection of the second through-hole on the substrate is located within the orthographic projection of the first through-hole on the substrate. The first through-hole, the second through-hole, and the third through-hole are connected and expose at least a portion of the first power line. The orthographic projection of the isolation structure on the substrate is offset from the orthographic projections of the first through-hole, the second through-hole, and the third through-hole on the substrate. The first overlapping hole penetrates the third insulating layer. The touch trace layer includes touch traces and second connection traces disposed on the same layer. A portion of the second connection trace extends into the connected first through hole, second through hole and third through hole and is electrically connected to the first power line. A portion of the second connection trace is electrically connected to the isolation structure through the first overlapping hole.
14. The display panel according to any one of claims 1 to 13, wherein, The isolation structure includes a support portion and a shielding portion located on the side of the support portion away from the substrate, wherein the orthographic projection of the support portion on the substrate is located within the orthographic projection of the shielding portion on the substrate; Under the same etching conditions, the corrosion resistance of the support portion is weaker than that of the shielding portion; The material of the support portion includes aluminum, and / or the material of the shielding portion includes titanium; The isolation structure also includes a receiving portion located between the support portion and the substrate; The orthographic projection of the receiving part on the substrate is located within the orthographic projection of the blocking part on the substrate; The material of the receiving part includes molybdenum.
15. A display panel, comprising a display area and a bonding area located on one side of the display area; the display panel comprising: Substrate; A wiring layer located on one side of the substrate, the wiring layer including a first power line, the first end of the first power line overlapping with the bonding region; An isolation structure located on the side of the wiring layer away from the substrate, the isolation structure being at least partially located in the display area, and the isolation structure being electrically connected to the bonding area via at least one first power line; The isolation structure includes at least one overlapping area, the orthographic projection of the overlapping area onto the substrate is located within the orthographic projection of the first power line onto the substrate, the isolation structure is connected to the first power line in the overlapping area, and the total area of the overlapping area is greater than or equal to 0.1% of the display area.
16. The display panel according to claim 15, wherein, The display area and the bonding area are arranged along a first direction, and the first power line extends from the bonding area along the first direction to connect with the isolation structure; The sum of the widths of the overlapping areas in the second direction is greater than or equal to 1 / 20 of the length of the display area in the second direction, and the first direction intersects the second direction; The first direction is perpendicular to the second direction.
17. The display panel according to claim 16, wherein, The overlapping area includes a plurality of first overlapping holes, and the isolation structure is electrically connected to the first power line through the first overlapping holes.
18. The display panel according to claim 16 or 17, wherein, The display panel further includes a first border area located between the display area and the bonding area; at least three overlapping areas are located in the first border area, and at least three overlapping areas are respectively overlapping with at least three first power lines; The bonding region includes at least two sub-bonding regions, and the number of overlapping regions is greater than or equal to the number of sub-bonding regions; The sub-bonding area is equipped with a driver chip.
19. The display panel according to claim 18, wherein, The display area, the first border area, and the bonding area are arranged sequentially along a first direction, and at least two of the sub-bonding areas are arranged along a second direction, wherein the first direction intersects with the second direction; In the second direction, the two overlapping areas are located on both sides of the first frame area, and at least one of the first power lines is located between two adjacent sub-bonding areas.
20. A display device comprising the display panel according to any one of claims 1-19.