Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises: a base; a driving circuit layer arranged on the base and comprising a pixel driving circuit, the pixel driving circuit comprising a driving transistor; and a light-emitting structure layer arranged on the side of the driving circuit layer away from the base and comprising a plurality of light-emitting elements, each light-emitting element comprising an anode, an organic light-emitting layer, and a cathode sequentially arranged in a direction away from the base, and the cathodes of adjacent light-emitting elements being isolated from one another. The light-emitting structure layer further comprises a plurality of connection electrodes, the connection electrodes and the anodes being arranged in a same layer, the connection electrodes being connected to the driving transistor, and the connection electrodes being connected to the cathodes.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202411804135.3, filed on December 09, 2024, entitled “Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, display technology, and in particular to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. With the continuous development of display technology, display devices using OLEDs as light-emitting elements and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0004] However, display substrates are prone to image retention during display. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] This disclosure provides a display substrate and a display device to improve the problem of image retention that easily occurs on display substrates.

[0007] On one hand, embodiments of this disclosure provide a display substrate, comprising: a substrate; a driving circuit layer disposed on the substrate, including a pixel driving circuit, the pixel driving circuit including a driving transistor; and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, including a plurality of light-emitting elements, the light-emitting elements including an anode, an organic light-emitting layer and a cathode arranged sequentially along a direction away from the substrate; the cathodes of adjacent light-emitting elements are isolated from each other; wherein, the light-emitting structure layer further includes a plurality of connecting electrodes, the connecting electrodes being disposed in the same layer as the anode; the connecting electrodes being connected to the driving transistor and the connecting electrodes being connected to the cathode.

[0008] In one exemplary embodiment, the light-emitting structure layer further includes a pixel definition layer, the pixel definition layer at least partially covering the connection electrode; the pixel definition layer includes a first opening parallel to the substrate direction, the first opening exposing the surface of the connection electrode; the connection electrode is connected to the cathode, including: the cathode is connected to the connection electrode through the first opening; the connection electrode is connected to the driving transistor, including: the connection electrode is connected to the drain electrode of the driving transistor.

[0009] In one exemplary embodiment, the surface of the connecting electrode includes a bottom surface located near the substrate, a top surface located away from the substrate, and a side surface connecting the bottom surface and the top surface. The first opening exposes the surface of the connecting electrode, including: the first opening exposes at least one side surface of the connecting electrode.

[0010] In one exemplary embodiment, on the side of the first opening away from the substrate, the pixel definition layer has a triangular or trapezoidal cross-section in a plane perpendicular to the substrate.

[0011] In one exemplary embodiment, within one of the light-emitting elements, the orthographic projection of the connecting electrode on the substrate does not overlap with the orthographic projection of the cathode on the substrate, and the first opening is located on the side of the connecting electrode closer to the anode.

[0012] In one exemplary embodiment, within a single light-emitting element, the orthographic projection of the connecting electrode onto the substrate is within the range of the orthographic projection of the cathode onto the substrate, and the first opening is located on the side of the connecting electrode away from the anode.

[0013] In one exemplary embodiment, in the extending direction of the connecting electrode, the ratio of the length of the adjacent side of the connecting electrode to that of the cathode is greater than or equal to 0.8 and less than or equal to 1.

[0014] In one exemplary embodiment, the anodes of the plurality of light-emitting elements are interconnected.

[0015] In one exemplary embodiment, the orthographic projection of the connecting electrode on the substrate surrounds the orthographic projection of the anode on the substrate.

[0016] In one exemplary embodiment, the driving circuit layer further includes a first power line, and the anode is connected to the first power line through a via.

[0017] In one exemplary embodiment, the light-emitting structure layer further includes a first power line located on the side of the pixel definition layer away from the substrate, and the orthographic projection of the first power line on the substrate is within the range of the orthographic projection of the pixel definition layer on the substrate, and the anode is connected to the first power line through a via.

[0018] In one exemplary embodiment, the pixel definition layer further includes a second opening located between adjacent light-emitting elements; the cathodes of the adjacent light-emitting elements are isolated from each other, including: the cathodes of the adjacent light-emitting elements are disconnected at the second opening.

[0019] In one exemplary embodiment, the distance between the pixel definition layers located on both sides of the second opening gradually increases in a plane parallel to the substrate along a direction away from the substrate.

[0020] In one exemplary embodiment, the light-emitting structure layer further includes an isolation portion located on the side of the pixel definition layer away from the substrate, and the orthographic projection of the isolation portion on the substrate is within the range of the orthographic projection of the pixel definition layer on the substrate; the cathodes of adjacent light-emitting elements are isolated from each other, including: the cathodes of adjacent light-emitting elements are disconnected at the isolation portion.

[0021] In one exemplary embodiment, the light-emitting structure layer further includes a first power line located on the side of the pixel definition layer away from the substrate, and the isolation portion is connected to the first power line.

[0022] In one exemplary embodiment, the light-emitting structure layer further includes an overlapping portion located on the side of the cathode away from the substrate; the cathode is connected to the connecting electrode through the first opening, including: the overlapping portion at least fills the first opening, so that the cathode and the connecting electrode are interconnected.

[0023] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0024] The display substrate provided in this embodiment isolates the cathodes of multiple sub-pixels from each other and sets a connecting electrode in the same layer as the anode in a single sub-pixel. The connecting electrode is connected to the driving transistor of the sub-pixel, and the cathode in a single sub-pixel is connected to the connecting electrode. This realizes the connection between the cathode of the light-emitting element and the pixel driving circuit, which helps to improve the image retention of the display panel, improve the display quality, and requires less structural modification to the display substrate. The manufacturing process is simple and can improve the image retention of the display substrate during display.

[0025] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0027] Overview of the attached figures

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0029] Figure 1 is a schematic diagram of a display substrate;

[0030] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0031] Figure 3 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0032] Figure 4 is a schematic cross-sectional view of a display substrate;

[0033] Figure 5 is an equivalent circuit diagram of a pixel driving circuit in an exemplary embodiment.

[0034] Figure 6 is a top view of the light-emitting structure layer of a display substrate in an exemplary embodiment;

[0035] Figure 7 is a cross-sectional view of the substrate along direction AA in Figure 6 in an exemplary embodiment;

[0036] Figure 8 is an enlarged schematic diagram of the dashed area E in Figure 7 in an exemplary embodiment;

[0037] Figure 9 is a top view of the light-emitting structure layer of the display substrate in another exemplary embodiment;

[0038] Figure 10 is a cross-sectional view of the substrate along direction AA in Figure 9 in an exemplary embodiment;

[0039] Figure 11 is a top view of the light-emitting structure layer of the display substrate in another exemplary embodiment;

[0040] Figure 12 is a top view of the light-emitting structure layer of the display substrate in another exemplary embodiment;

[0041] Figure 13 is a cross-sectional view of the substrate along direction AA in Figure 12 in an exemplary embodiment;

[0042] Figure 14 is a cross-sectional view of the substrate along direction AA in Figure 12 in another exemplary embodiment.

[0043] Detailed Explanation

[0044] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0045] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0046] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0047] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0048] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0049] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0050] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0051] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0052] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0053] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a schematic diagram of a display substrate structure. As shown in Figure 1, the display substrate may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting element connected to the circuit unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the data signal lines, and the light-emitting signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0055] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting element. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting element under the control of the scan signal line and the light-emitting signal line. The light-emitting element in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel. The light-emitting element is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0056] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a green sub-pixel (G) emitting green light, and the third sub-pixel P3 can be a blue sub-pixel (B) emitting blue light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular pattern, etc., which is not limited in this disclosure.

[0057] In an exemplary embodiment, a pixel unit may include four sub-pixels. For example, the four sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel that emits white (W) light. Alternatively, the four sub-pixels may include a red sub-pixel, a blue sub-pixel, and two green sub-pixels. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontally parallel, vertically parallel, square, or diamond shape, etc., and this disclosure does not limit the arrangement.

[0058] Figure 3 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 2T1C, 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 3, the pixel driving circuit may include two transistors (first transistor T1 and second transistor T2) and one storage capacitor C1. The pixel driving circuit is connected to the data signal line D, the scan signal line S, and the first power supply line VDD, respectively.

[0059] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the gate electrode of the first transistor T1, the second electrode of the second transistor T2, and the first terminal of the storage capacitor C1. The second node N2 is connected to the second electrode of the first transistor, the second terminal of the storage capacitor C1, and the first electrode of the light-emitting element EL. The third node N3 is connected to the first electrode of the first transistor T1 and the first power line VDD. The gate electrode of the second transistor T2 is connected to the scan signal line S, and the first electrode of the second transistor T2 is connected to the data signal line D. The second electrode of the light-emitting element EL is connected to the second power line VSS, where the signal of the second power line VSS is a continuously supplied low-level signal, and the signal of the first power line VDD is a continuously supplied high-level signal. The first transistor T1 can be referred to as the driving transistor. The first transistor T1 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its gate electrode and its first electrode. After the first transistor T1 is turned on, a driving current path is formed between the first power line VDD and the second power line VSS, causing the light-emitting element EL to emit light.

[0060] In an exemplary embodiment, the light-emitting element EL can be an OLED, including a stacked first electrode, an organic light-emitting layer and a second electrode, or it can be a QLED, including a stacked first electrode, a quantum dot light-emitting layer and a second electrode. In this embodiment, the first electrode can be an anode and the second electrode can be a cathode. This disclosure does not limit this.

[0061] In an exemplary embodiment, the first transistor T1 and the second transistor T2 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve product yield. In some possible implementations, the transistors in the pixel driving circuit may include both P-type and N-type transistors.

[0062] In an exemplary embodiment, the transistors in the pixel driving circuit can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OPT TFT is made of oxide semiconductor. LTPS TFTs have advantages such as high mobility and fast charging, while OPT TFTs have advantages such as low leakage current. Integrating LTPS TFTs and OPTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0063] Figure 4 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels on the display substrate. As shown in Figure 4, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in this disclosure.

[0064] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include multiple transistors and storage capacitors constituting the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, an organic light-emitting layer 302, and a cathode 303. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 emits light of a corresponding color under the driving of the anode 301 and the cathode 303. The anodes 301 of multiple sub-pixels are isolated from each other, and the cathodes 303 may cover the entire surface of the substrate 101, that is, the cathodes 303 of multiple sub-pixels may be interconnected. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external moisture cannot enter the light-emitting structure layer 103. In an exemplary embodiment, the display substrate may also include a touch layer or other film layer located on the side of the encapsulation layer 104 away from the substrate 101, which is not a limitation of this disclosure.

[0065] In an exemplary embodiment, the organic light-emitting layer 302 may include an emitting layer (EML) and one or more of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). For example, the organic light-emitting layer 302 may include a hole injection layer, a hole transport layer, an electron block layer, an emitting layer, a hole block layer, an electron transport layer, and an electron injection layer sequentially stacked along a direction away from the substrate 101. In an exemplary embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole blocking layer of all sub-pixels can be a common layer connected together, the light emission layer of adjacent sub-pixels can have a small overlap or can be isolated, and the electron blocking layer of adjacent sub-pixels can have a small overlap or can be isolated.

[0066] In the structure shown in Figure 4, the anode of the light-emitting element (EL) is connected to the drain electrode of the driving transistor. The EL is prone to degradation after a period of operation, causing changes in its operating voltage. Environmental factors such as temperature can also lead to these changes, resulting in a decrease in the display quality of the display substrate. Referring to Figure 3, since the anode of the EL is connected to the first node N1 via the storage capacitor C1, voltage changes in the EL cause potential changes at the first node N1, leading to changes in the gate electrode potential of the driving transistor. When the driving transistor in the pixel driving circuit is an N-type transistor, the voltage difference between the gate and source electrodes of the driving transistor alters the driving current flowing through the EL. This not only causes image retention on the display substrate but also makes the brightness of the displayed image decrease more noticeably, accelerating the degradation of display quality.

[0067] Figure 5 is an equivalent circuit diagram of a pixel driving circuit in an exemplary embodiment. The difference between Figure 5 and Figure 3 is that the connection method between the light-emitting element EL and the pixel driving circuit is different. In Figure 5, the second electrode of the light-emitting element EL is connected to the pixel driving circuit. The rest can be referred to the description of Figure 3 above, and will not be repeated here.

[0068] In an exemplary embodiment, the first electrode of the light-emitting element EL can be connected to the first power line VDD, the second electrode of the light-emitting element EL can be connected to the third node N3, the second node N2 can be directly connected to the second power line VSS, the first electrode is the anode, and the second electrode is the cathode.

[0069] In this embodiment, by connecting the cathode of the light-emitting element EL to the pixel driving circuit, even if the driving transistor in the pixel driving circuit is an N-type transistor, the voltage change of the light-emitting element EL will not affect the driving transistor. This helps to ensure the stable operation of the sub-pixel, improve the afterimage of the display panel, and enhance the display quality.

[0070] However, the connection between the light-emitting element (EL) and the pixel driving circuit shown in Figure 5 cannot be realized in the display substrate shown in Figure 4. Therefore, in order to improve the image retention of the display substrate and enhance the display quality, it is necessary to change the structure of the display substrate.

[0071] This disclosure provides a display substrate, including a base;

[0072] A driving circuit layer is disposed on the substrate and includes a pixel driving circuit, wherein the pixel driving circuit includes a driving transistor;

[0073] A light-emitting structure layer is disposed on the side of the driving circuit layer away from the substrate, and includes a plurality of light-emitting elements. Each light-emitting element includes an anode, an organic light-emitting layer, and a cathode arranged sequentially in a direction away from the substrate; the cathodes of different light-emitting elements are isolated from each other.

[0074] The light-emitting structure layer further includes multiple connecting electrodes, which are disposed in the same layer as the anode; the connecting electrodes are connected to the driving transistor and the cathode.

[0075] The display substrate provided in this embodiment isolates the cathodes of multiple sub-pixels from each other and sets a connection electrode in the same layer as the anode in a single sub-pixel. The connection electrode is connected to the driving transistor of the sub-pixel, and the cathode in a single sub-pixel is connected to the connection electrode. This realizes the connection between the cathode of the light-emitting element and the pixel driving circuit, which helps to improve the image retention of the display panel, enhance the display quality, and requires less structural modification to the display substrate and has a simple manufacturing process.

[0076] Figure 6 is a top view of the light-emitting structure layer of a display substrate in an exemplary embodiment, showing the orthographic projection of the pixel opening, the second electrode of the light-emitting element, and the connecting electrode on the substrate, while omitting the rest of the structure of the light-emitting structure layer.

[0077] As shown in Figure 6, the display substrate may include a plurality of pixel units P arranged in a matrix, including rows of pixel units arranged along a first direction X and columns of pixel units arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y may be perpendicular to each other. A single pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. In an exemplary embodiment, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 within a single pixel unit P may be arranged in a triangular pattern. The first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a green sub-pixel (G) emitting green light, and the third sub-pixel P3 may be a blue sub-pixel (B) emitting blue light. This disclosure does not limit this.

[0078] In an exemplary embodiment, the orthographic projection of the pixel opening K1 of the first sub-pixel P1 onto the substrate 101 lies within the range of the orthographic projection of the second electrode 303-1 of the first sub-pixel P1 onto the substrate 101; the orthographic projection of the pixel opening K2 of the second sub-pixel P2 onto the substrate 101 lies within the range of the orthographic projection of the second electrode 303-2 of the second sub-pixel P2 onto the substrate 101; and the orthographic projection of the pixel opening K3 of the third sub-pixel P3 onto the substrate 101 lies within the range of the orthographic projection of the second electrode 303-3 of the third sub-pixel P3 onto the substrate 101. Furthermore, the second electrodes 303-1 of the first sub-pixel P1, 303-2 of the second sub-pixel P2, and 303-3 of the third sub-pixel P3 are mutually isolated. The second electrode is the cathode of the light-emitting element. The second electrode 303-1 of the first sub-pixel P1 can be connected to the drain electrode (not shown) of the driving transistor of the corresponding pixel driving circuit through the connecting electrode 311-1. The orthographic projection of the connecting electrode 311-1 on the substrate 101 does not overlap with the orthographic projection of the pixel opening K1 of the first sub-pixel P1 on the substrate 101. The second electrode 303-2 of the second sub-pixel P2 can be connected to the drain electrode of the driving transistor of the corresponding pixel driving circuit through the connecting electrode 311-2. The orthographic projection of the connecting electrode 311-2 on the substrate 101 does not overlap with the orthographic projection of the pixel opening K2 of the second sub-pixel P2 on the substrate 101. The second electrode 303-3 of the third sub-pixel P3 can be connected to the drain electrode of the driving transistor of the corresponding pixel driving circuit through the connecting electrode 311-3. The orthographic projection of the connecting electrode 311-3 on the substrate 101 does not overlap with the orthographic projection of the pixel opening K3 of the third sub-pixel P3 on the substrate 101. By ensuring that the connecting electrodes and pixel openings do not overlap, the aperture ratio of the display substrate will not be affected, which helps to guarantee the display effect of the display substrate.

[0079] In an exemplary embodiment, within a single pixel unit P, the connection electrode 311-1 of the first sub-pixel P1 can be located on one side of the pixel opening K1 of the first sub-pixel P1 and the first electrode of the first sub-pixel P1 in the first direction X; the connection electrode 311-2 of the second sub-pixel P2 can be located on the other side of the pixel opening K2 of the second sub-pixel P2 and the first electrode of the second sub-pixel P2 in the first direction X; and the connection electrode 311-3 of the third sub-pixel P3 can be located on one side of the pixel opening K3 of the third sub-pixel P3 and the first electrode of the third sub-pixel P3 in the second direction Y. This design allows the multiple connection electrodes within a single pixel unit P to be dispersed from each other, without affecting the arrangement of the first electrode and other structures of the light-emitting element, thus facilitating the layout design of the display substrate. The positional distribution of the multiple connection electrodes within a single pixel unit P can be set as needed, and this disclosure does not impose any limitations on this.

[0080] In an exemplary embodiment, the shape of the connecting electrode can be rectangular. In a set of interconnected connecting electrodes and second electrodes, as shown in FIG6, the ratio of the lengths of adjacent sides of the connecting electrode and the second electrode can be greater than or equal to 0.1 and less than or equal to 0.4. For example, the ratio of the lengths of adjacent sides of the connecting electrode and the second electrode can be greater than or equal to 0.1 and less than or equal to 0.3. This disclosure does not limit this. In the first sub-pixel P1, the adjacent sides of the connecting electrode 311-1 and the second electrode 303-1 extend along the second direction Y and overlap each other. The length of the side of the connecting electrode 311-1 near the second electrode 303-1 is S1, and the length of the side of the second electrode 303-1 near the connecting electrode 311-1 is S2. The ratio of S1 to S2 can be greater than or equal to 0.1 and less than or equal to 0.4. In the third sub-pixel P3, the adjacent sides of the connecting electrode 311-3 and the second electrode 303-3 extend along the first direction X and overlap each other. The length of the side of the connecting electrode 311-3 near the second electrode 303-3 is S3, and the length of the side of the second electrode 303-3 near the connecting electrode 311-3 is S4. The ratio of S3 to S4 can be greater than or equal to 0.1 and less than or equal to 0.4. The lengths of the adjacent sides of the connecting electrode 311-2 and the second electrode 303-2 in the second sub-pixel P2 can be referred to the description of the first sub-pixel P1, and will not be repeated here. By setting the ratio of the lengths of the adjacent sides of the connecting electrode and the second electrode to be greater than or equal to 0.1 and less than or equal to 0.4, the area occupied by the connecting electrode near the sub-pixel is smaller, which helps to arrange the circuit and light-emitting elements of the display substrate in an overall manner. In other embodiments, the connecting electrode can take other shapes, such as trapezoidal, triangular, circular, elliptical, other polygonal shapes, and irregular shapes, etc., and this disclosure does not limit them.

[0081] Figure 7 is a cross-sectional view of the display substrate along direction AA in Figure 6 in an exemplary embodiment, illustrating two adjacent third sub-pixels P3. The remaining structure of the display substrate is omitted. The structures of the first sub-pixel P1 and the second sub-pixel P2 can be referred to the description of the structure of the third sub-pixel P3, and will not be repeated here. The following description uses the sub-pixel located on the left side of Figure 7 as an example. The structure of the sub-pixel located on the right side of Figure 7 is similar to that of the sub-pixel located on the left side, and will not be repeated here.

[0082] In an exemplary embodiment, as shown in Figures 6 and 7, the light-emitting structure layer 103 may include a first electrode 301-3, a pixel definition layer 304, an organic light-emitting layer 302-3, and a second electrode 303-3 sequentially disposed along a direction away from the substrate 101. The pixel definition layer 304 includes a pixel opening K3, which exposes the surface of the first electrode 301-3. The orthographic projection of the pixel opening K3 onto the substrate 101 is within the range of the orthographic projection of the organic light-emitting layer 302-3 of the third sub-pixel P3 onto the substrate 101. The orthographic projection of the organic light-emitting layer 302-3 of the third sub-pixel P3 onto the substrate 101 is within the range of the orthographic projection of the second electrode 303-3 of the third sub-pixel P3 onto the substrate 101. As shown in Figure 7, the connection electrode 311-3 of the third sub-pixel P3 is disposed in the same layer as the first electrode 301-3, and the connection electrode 311-3 of the third sub-pixel P3 is connected to the drain electrode 25 of the driving transistor 210 through a via. The connection electrode 311-3 of the third sub-pixel P3 is located on one side of the second electrode 303-3 of the third sub-pixel P3. The surface of the connection electrode 311-3 of the third sub-pixel P3 may include a bottom surface located near the substrate 101, a top surface located away from the substrate 101, and a side surface connecting the bottom surface and the top surface. The bottom surface of the connection electrode 311-3 is connected to the drain electrode 25 of the driving transistor 210 through a via. The pixel definition layer 304 also includes a first opening Km, which is located on the side of the connection electrode 311-3 near the first electrode 301-3. The first opening Km faces the first electrode 301-3 of the third sub-pixel P3 and exposes at least one side surface of the connection electrode 311-3 of the third sub-pixel P3. The second electrode 303-3 of the third sub-pixel P3 can be connected through the first opening Km and the exposed surface of the connection electrode 311-3 of the third sub-pixel P3, thereby achieving connection with the drain electrode 25 of the driving transistor 210.

[0083] Figure 8 is an enlarged schematic diagram of the dashed area E in Figure 7 in an exemplary embodiment. As shown in Figure 8, the first opening Km extends in a direction parallel to the substrate 101 and faces the first electrode 301-3 of the third sub-pixel P3. The pixel definition layer 304 in the first opening Km is removed, exposing the side of the connection electrode 311-3 of the third sub-pixel P3 near the first electrode 301-3 of the third sub-pixel P3. The orthographic projection of the connection electrode 311-3 of the third sub-pixel P3 on the substrate 101 is within the range of the orthographic projection of the pixel definition layer 304 on the substrate 101. The orthographic projection of the first opening Km on the substrate 101 is within the range of the orthographic projection of the pixel definition layer 304 on the substrate 101. The second electrode 303-3 of the third sub-pixel P3 can extend into the first opening Km and connect with the connection electrode 311-3 of the third sub-pixel P3. The edge of the pixel definition layer 304 at the first opening Km can protrude a distance beyond the connecting electrode 311-3 of the third sub-pixel P3, as shown by the dashed box U in Figure 8. On the side of the first opening Km away from the substrate 101, the cross-section of the pixel definition layer 304 in the plane perpendicular to the substrate 101 can be trapezoidal or triangular (not shown in the figure), forming an "eaves" structure above the connecting electrode 311-3. When the organic light-emitting layer 302-3 is subsequently formed by chemical vapor deposition (CVD), this "eaves" structure blocks the particles of the vapor deposition, preventing the organic light-emitting layer 302-3 from entering the first opening Km. The organic light-emitting layer 302-3 is isolated at the first opening Km. Subsequently, the second electrode 303-3 can be formed by atomic layer deposition (ALD). This method allows the second electrode 303-3 to extend smoothly into the first opening Km, achieving connection with the connecting electrode 311-3. In other embodiments, the organic light-emitting layer 302-3 and the second electrode 303-3 may be separated at the first opening Km. Subsequently, the second electrode 303-3 and the connecting electrode 311-3 can be connected by an overlapping portion (not shown) on the side inside the first opening Km, thereby achieving the connection between the second electrode 303-3 and the connecting electrode 311-3. This disclosure does not limit this. Appropriate preparation methods can be selected as needed to form the organic light-emitting layer 302-3 and the second electrode 303-3, and this disclosure does not limit this.

[0084] In an exemplary embodiment, continuing to refer to FIG7, the pixel definition layer 304 further includes a second opening Kn located between adjacent sub-pixels. The organic light-emitting layer 302-3 and the second electrode 303-3 are disconnected at the second opening Kn, isolating adjacent sub-pixels from each other. As shown in FIG7, in a plane parallel to the substrate 101, the first distance D1 between the pixel definition layers 304 located on both sides of the second opening Kn can gradually increase in the direction away from the substrate 101, making the cross-sectional shape of the pixel definition layer 304 at the second opening Kn an inverted trapezoid. This structure allows the organic light-emitting layer 302-3 and the second electrode 303-3 to be disconnected at the second opening Kn during the formation process, which helps to reduce the process steps in forming the display substrate. In other embodiments, the pixel definition layer 304 may not have a second opening Kn. Instead, a partition portion (not shown) may be formed on the side of the pixel definition layer 304 away from the substrate 101, using the partition portion to disconnect the organic light-emitting layer 302-3 and the second electrode 303-3 at the second opening Kn. This disclosure does not limit this.

[0085] In an exemplary embodiment, the first electrodes of a plurality of sub-pixels may be interconnected and connected to a first power line (not shown), which is not a limitation herein.

[0086] In an exemplary embodiment, the display substrate may include a substrate 101 and a driving circuit layer 102 disposed on the substrate 101. The driving circuit layer 102 includes a light-shielding layer, a plurality of transistors disposed on the light-shielding layer, and a capacitor. The light-shielding layer may include a plurality of light-shielding electrodes 21, which are located on the side of the transistors closer to the substrate 101. These electrodes can block light incident from the side of the substrate 101 away from the light-shielding layer from affecting the transistors in the display substrate, thus preventing changes in the electrical characteristics of the transistors due to external light exposure and improving the stability of the transistors. For example, the semiconductor material used in the active layer of the transistor has a photoconductive effect, and its electrical characteristics, such as on-state current and off-state current, change significantly in the presence of light and the absence of light. That is, drift and other problems are prone to occur in the presence of light, resulting in unstable electrical characteristics.

[0087] In an exemplary embodiment, a driving transistor 210 is disposed on the side of the light-shielding electrode 21 away from the substrate 101. The driving transistor 210 includes an active layer 22, a gate electrode 23, a source electrode 24, and a drain electrode 25. The source electrode 24 and the drain electrode 25 are respectively connected to the active layer 22 through vias. In an exemplary embodiment, the source electrode 24 can be connected to the light-shielding electrode 21 through a via. The light-shielding electrode 21 has a certain voltage after being energized, which can form an auxiliary electric field with the corresponding gate electrode 23 to turn on the channel region of the transistor. A first insulating layer 11 is disposed between the light-shielding layer 21 and the active layer 22, and a second insulating layer 12 is disposed between the active layer 22 and the gate electrode 23. A third insulating layer 13 and a fourth insulating layer 14 can be disposed sequentially on the side of the gate electrode 23 away from the substrate 101. The source electrode 24 and the drain electrode 25 can be located on the side of the fourth insulating layer 14 away from the substrate 101. The first insulating layer 11 can be called a buffer layer, the second insulating layer 12 can be called a gate insulating layer (GI), the third insulating layer 13 can be called a first interlayer insulating layer (ILD), and the fourth insulating layer 14 can be called a second interlayer insulating layer.

[0088] In an exemplary embodiment, the storage capacitor of the pixel driving circuit may include a first electrode plate 41, a second electrode plate 42, and a third electrode plate 43 arranged sequentially opposite to each other in a direction perpendicular to the substrate 101. The first electrode plate 41 may be arranged in the same layer as the light-shielding layer 21, the second electrode plate 42 may be arranged in the same layer as the gate electrode 23, and the third electrode plate 43 may be arranged in the same layer as the source electrode 24 and the drain electrode 25. By setting the storage capacitor to include multiple electrodes, the area occupied by the storage capacitor can be reduced while maintaining the storage capacitor capacity, which is beneficial to the spatial layout of the display substrate. The structure of the storage capacitor can be set as needed, and this disclosure does not limit it.

[0089] In an exemplary embodiment, a planarization layer 15 may be provided on the side of the source electrode 24 and drain electrode 25 away from the substrate 101, and the light-emitting structure layer 103 is located above the planarization layer 15. In an exemplary embodiment, a passivation layer (not shown) may also be provided between the source electrode 24 and drain electrode 25 and the planarization layer 15, and this disclosure does not limit this.

[0090] In this embodiment, by isolating the second electrodes of multiple sub-pixels from each other and setting a connection electrode in the same layer as the first electrode in a single sub-pixel, the connection electrode is connected to the drain electrode of the driving transistor of the sub-pixel. The second electrode in a single sub-pixel is connected to the connection electrode, thereby connecting the cathode of the light-emitting element to the pixel driving circuit. This helps to improve the image retention of the display panel, enhance the display quality, and requires minimal structural modification to the display substrate. The second electrode can be directly connected to the connection electrode, and the fabrication process is simple.

[0091] Figure 9 is a top view of the light-emitting structure layer of the display substrate in another exemplary embodiment. The difference between Figure 9 and Figure 6 is that the second electrode and the connecting electrode in a single sub-pixel are connected by an overlap portion, and the orthographic projection relationship between the second electrode and the connecting electrode in a single sub-pixel is different. The rest can be referred to the description of Figure 6 above, and will not be repeated here.

[0092] In an exemplary embodiment, as shown in FIG9, the orthographic projection of the connection electrode 311-1 of the first sub-pixel P1 onto the substrate 101 can be located within the range of the orthographic projection of the second electrode 303-1 of the first sub-pixel P1 onto the substrate 101, and the orthographic projection of the connection electrode 311-1 of the first sub-pixel P1 onto the substrate 101 does not overlap with the orthographic projection of the pixel opening K1 of the first sub-pixel P1 onto the substrate 101. The connection electrode 311-1 and the second electrode 303-1 of the first sub-pixel P1 are connected through the overlap portion 312-1 of the first sub-pixel P1. The orthographic projection of the overlap portion 312-1 of the first sub-pixel P1 onto the substrate 101 overlaps with the orthographic projection of the connection electrode 311-1 onto the substrate 101, and the orthographic projection of the overlap portion 312-1 of the first sub-pixel P1 onto the substrate 101 overlaps with the orthographic projection of the second electrode 303-1 onto the substrate 101. The positional relationship between the connecting electrode 311-2, the second electrode 303-2, the overlapping portion 312-2 and the pixel opening K2 of the second sub-pixel P2, and the positional relationship between the connecting electrode 311-3, the second electrode 303-3, the overlapping portion 312-3 and the pixel opening K3 of the third sub-pixel P3 can be referred to the description of the first sub-pixel P1, and will not be repeated here.

[0093] Figure 10 is a cross-sectional view of the display substrate along direction AA in Figure 9 in an exemplary embodiment. The difference between Figure 10 and Figure 7 is the light-emitting structure layer. The rest can be referred to the description of Figure 7 above, and will not be repeated here.

[0094] In an exemplary embodiment, as shown in Figures 9 and 10, the first opening Km is located on the side of the connecting electrode 311-3 away from the first electrode 301-3. The first opening Km extends in a direction parallel to the substrate 101 and faces away from the first electrode 301-3 of the third sub-pixel P3. The pixel definition layer 304 within the first opening Km is removed, exposing the side of the connecting electrode 311-3 of the third sub-pixel P3. The orthographic projection of the connecting electrode 311-3 of the third sub-pixel P3 onto the substrate 101 is within the range of the orthographic projection of the pixel definition layer 304 onto the substrate 101. The orthographic projection of the first opening Km onto the substrate 101 is also within the range of the orthographic projection of the pixel definition layer 304 onto the substrate 101. The organic light-emitting layer 302-3 and the second electrode 303-3 are both isolated at the first opening Km. The overlapping portion 312-3 of the third sub-pixel P3 is located on the side of the second electrode 303-3 away from the substrate 101. One end of the overlapping portion 312-3 of the third sub-pixel P3 is connected to the second electrode 303-3, and the other end extends into the first opening Km and connects to the connecting electrode 311-3, thereby realizing the connection between the second electrode 303-3 and the connecting electrode 311-3 of the third sub-pixel P3. In other embodiments, the overlapping portion 312-3 may not be provided. By controlling the preparation method of the organic light-emitting layer 302-3 and the second electrode 303-3, the second electrode 303-3 can directly extend into the first opening Km and connect to the connecting electrode 311-3. This disclosure does not limit this.

[0095] In an exemplary embodiment, the overlapping portion 312-3 may be located on both sides of the second opening Kn of the pixel definition layer 304, and this disclosure does not limit this.

[0096] In this embodiment, by isolating the second electrodes of multiple sub-pixels from each other and setting a connection electrode in the same layer as the first electrode in a single sub-pixel, the connection electrode is connected to the drain electrode of the driving transistor of the sub-pixel. The second electrode in a single sub-pixel is connected to the connection electrode through the overlap portion, thereby connecting the cathode of the light-emitting element to the pixel driving circuit. This helps to improve the image retention of the display panel, enhance the display quality, and requires less structural modification to the display substrate, making the manufacturing process simple.

[0097] Figure 11 is a top view of the light-emitting structure layer of the display substrate in another exemplary embodiment. The difference between Figure 11 and Figure 9 is the connection of electrodes. The rest can be referred to the description of Figure 9 above. The cross-sectional view of Figure 11 along the AA direction can be referred to Figure 10, which will not be repeated here.

[0098] In an exemplary embodiment, as shown in FIG11, within a single pixel unit P, the connection electrode 311-1 of the first sub-pixel P1 can be located on one side of the pixel opening K1 of the first sub-pixel P1 and the second direction Y of the first electrode of the first sub-pixel P1; the connection electrode 311-2 of the second sub-pixel P2 can be located on the other side of the pixel opening K2 of the second sub-pixel P2 and the second direction Y of the first electrode of the second sub-pixel P2; and the connection electrode 311-3 of the third sub-pixel P3 can be located on one side of the pixel opening K3 of the third sub-pixel P3 and the second direction Y of the first electrode of the third sub-pixel P3. This design allows the multiple connection electrodes within a single pixel unit P to be dispersed from each other, without affecting the arrangement of the first electrode and other structures of the light-emitting element, thus facilitating the layout design of the display substrate. The positional distribution of the multiple connection electrodes within a single pixel unit P can be set as needed, and this disclosure does not impose any limitations on this.

[0099] In an exemplary embodiment, the connecting electrode 311-3 of the third sub-pixel P3 can extend along the first direction X. The adjacent sides of the connecting electrode 311-3 and the second electrode 303-3 extend along the first direction X and overlap each other through the overlapping portion 312-3. For example, the connecting electrode 311-3 can be a rectangle with its long side located in the first direction X. The length of the connecting electrode 311-3 along the first direction X is S3. The length of the adjacent sides of the second electrode 303-3 and the connecting electrode 311-3 along the first direction X is S4. The ratio of S3 to S4 can be greater than or equal to 0.8 and less than or equal to 1. The first opening Km can expose the entire side of the connecting electrode 311-3 in the second direction Y. The overlapping portion 312-3 can extend along the first direction X and can contact the entire side of the connecting electrode 311-3. The length of the connecting electrode 311-3 along the first direction X can be the maximum size of the connecting electrode 311-3 along the first direction X. The length of the second electrode 303-3 along the first direction X can also be the maximum size of the second electrode 303-3 along the first direction X. The extension direction of the connecting electrode 311-3 and the length ratio of the connecting electrode 311-3 and the second electrode 303-3 along the extension direction can be set as needed. This disclosure does not limit this. The connecting electrode 311-1 of the first sub-pixel P1 can extend along the first direction X. The adjacent sides of the connecting electrode 311-1 and the second electrode 303-1 extend along the first direction X and overlap each other through the overlapping portion 312-1. For example, the connecting electrode 311-1 can be a rectangle with its long side located in the first direction X. The length of the connecting electrode 311-1 along the first direction X is S5, and the length of the adjacent sides of the second electrode 303-1 and the connecting electrode 311-1 along the first direction X is S6. The ratio of S5 to S6 can be greater than or equal to 0.8 and less than or equal to 1. The lengths of the adjacent sides of the connecting electrode 311-2 and the second electrode 303-2 of the second sub-pixel P2 can be referred to the description of the first sub-pixel P1, and will not be repeated here.

[0100] In this embodiment, the connecting electrode 311-3 is larger in size, and the contact area between the overlapping portion 312-3 and the connecting electrode 311-3 is larger, which helps to reduce the voltage drop of the signal passing through the overlapping portion 312-3 and the connecting electrode 311-3, thereby improving the display quality of the display substrate.

[0101] Figure 12 is a top view of the light-emitting structure layer of the display substrate in another exemplary embodiment. The difference between Figure 12 and Figure 9 is the connection of electrodes. The rest can be referred to the description of Figure 9 above, and will not be repeated here.

[0102] In an exemplary embodiment, as shown in FIG12, within a single pixel unit P, the orthographic projection of the connection electrode 311-1 of the first sub-pixel P1 onto the substrate 101 surrounds the pixel opening K1 of the first sub-pixel P1 and the orthographic projection of the first electrode of the first sub-pixel P1 onto the substrate 101. The orthographic projection of the connection electrode 311-1 onto the substrate 101 is located within the range of the orthographic projection of the second electrode 303-1 onto the substrate 101. Similarly, the orthographic projection of the connection electrode 311-2 of the second sub-pixel P2 onto the substrate 101 surrounds the pixel opening K2 of the second sub-pixel P2 and the orthographic projection of the first electrode of the second sub-pixel P2 onto the substrate 101. The orthographic projection of the connection electrode 311-2 onto the substrate 101 is located within the range of the orthographic projection of the second electrode 303-2 onto the substrate 101. The orthographic projection of the connecting electrode 311-3 of the third sub-pixel P3 on the substrate 101 surrounds the pixel opening K3 of the third sub-pixel P3 and the orthographic projection of the first electrode of the third sub-pixel P3 on the substrate 101. The orthographic projection of the connecting electrode 311-3 on the substrate 101 is located within the range of the orthographic projection of the second electrode 303-3 on the substrate 101.

[0103] In an exemplary embodiment, within a single sub-pixel, the first opening Km is located on the side of the connecting electrode away from the first electrode and exposes at least one side of the connecting electrode. An overlap portion can be connected to the connecting electrode through the first opening Km. In Figure 12, the first opening Km exposes one side of the connecting electrode along the second direction Y. The overlap portion is a strip extending along the first direction X and contacts the exposed side of the overlap portion. The length relationship of the adjacent sides of the connecting electrode and the second electrode can be referred to the description of Figure 11. In other embodiments, the first opening Km can expose two sides of the connecting electrode along the second direction Y. Two overlap portions can be provided within a single sub-pixel, and each overlap portion can overlap one exposed side of the connecting electrode with the second electrode. Alternatively, the first opening Km can expose all sides of the connecting electrode. The overlap portion can be annular and contacts the exposed side of the first opening Km. The length relationship of the adjacent sides of the connecting electrode and the second electrode in the first direction X and the second direction Y can be referred to the description of the foregoing embodiments, and this disclosure does not limit this. In other embodiments, an overlap portion may not be provided, and the second electrode can be directly connected to the connecting electrode. This disclosure does not limit this.

[0104] Figure 13 is a cross-sectional view of the display substrate along direction AA in Figure 12 in an exemplary embodiment. The difference between Figure 13 and Figure 10 is that the connecting electrodes are added and a first power line is added. The rest of the structure can be referred to the description of Figure 10, and will not be repeated here.

[0105] In an exemplary embodiment, as shown in FIG13, the first power line 61 may be disposed on the same layer as the source electrode 24 and the drain electrode 25 of the driving transistor 210, and the first electrode 301-3 of the third sub-pixel P3 may be connected to the first power line 61 through a via. This disclosure does not limit this.

[0106] In this embodiment, by setting the connecting electrode around the first electrode, the area of ​​the connecting electrode is larger without affecting the aperture ratio of the sub-pixels, which further reduces the voltage drop of the signal transmitted by the connecting electrode and helps to improve the display quality of the display substrate.

[0107] Figure 14 is a cross-sectional view of the display substrate along direction AA in Figure 12 in another exemplary embodiment. The difference between Figure 14 and Figure 7 is that the position of the connecting electrode is added, as well as the addition of the overlapping part, the first power line and the partition part. The rest of the structure can be referred to the description of Figure 7, and will not be repeated here.

[0108] In an exemplary embodiment, as shown in FIG14, an isolation portion 62 is provided on the side of the pixel definition layer 304 away from the substrate 101. The organic light-emitting layer and the second electrode on both sides of the isolation portion 62 are disconnected, thereby isolating adjacent sub-pixels from each other. By providing the isolation portion 62, a second opening Kn does not need to be provided on the pixel definition layer 304, reducing the number of openings on the pixel definition layer. In the exemplary embodiment, the isolation portion 62 can act as a spacer pillar, eliminating the need to fabricate spacer pillars on the display substrate and helping to reduce fabrication steps.

[0109] In an exemplary embodiment, a first power line 61 is provided on the side of the pixel definition layer 304 away from the substrate 101. The orthographic projection of the first power line 61 onto the substrate 101 can be within the range of the orthographic projection of the pixel definition layer 304 onto the substrate 101. The first power line 61 can be connected to the first electrode 301-3 of the third sub-pixel P3 through a via. The first power line 61 is disposed on the same layer as the isolation portion 62. The isolation portion 62 can be connected to the first power line 61, so that the isolation portion 62 can also be used to transmit the first power signal, which helps to reduce the voltage drop of the first power signal. This disclosure does not limit this.

[0110] In an exemplary embodiment, the second electrode 303-3 and the connecting portion 311-3 of the third sub-pixel P3 can be connected by the overlapping portion 312-3. After the second electrode is formed, the overlapping portion 312-3 can be formed at the first opening Km, and the overlapping portion 312-3 extends into the first opening Km and connects with the connecting portion 311-3.

[0111] In the exemplary embodiments, the embodiments in Figures 6 to 14 can be combined arbitrarily with each other, and this disclosure does not limit them.

[0112] This disclosure also provides a display device, including the display substrate described in any of the above embodiments. The display device can be any product or component with display functionality, such as an OLED display, QLED display, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this disclosure is not limited thereto.

[0113] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising: Base; A driving circuit layer is disposed on the substrate and includes a pixel driving circuit, wherein the pixel driving circuit includes a driving transistor; A light-emitting structure layer is disposed on the side of the driving circuit layer away from the substrate, and includes a plurality of light-emitting elements. Each light-emitting element includes an anode, an organic light-emitting layer, and a cathode arranged sequentially in a direction away from the substrate; the cathodes of adjacent light-emitting elements are isolated from each other. The light-emitting structure layer further includes multiple connecting electrodes, which are disposed in the same layer as the anode; the connecting electrodes are connected to the driving transistor and the cathode.

2. The display substrate according to claim 1, wherein, The light-emitting structure layer further includes a pixel definition layer, which at least partially covers the connection electrode; the pixel definition layer includes a first opening parallel to the substrate direction, the first opening exposing the surface of the connection electrode; The connecting electrode is connected to the cathode, including: The cathode is connected to the connecting electrode through the first opening; The connection electrode is connected to the driving transistor, including: the connection electrode is connected to the drain electrode of the driving transistor.

3. The display substrate according to claim 2, wherein, The surface of the connecting electrode includes a bottom surface located near the substrate, a top surface located away from the substrate, and a side surface connecting the bottom surface and the top surface. The first opening exposes the surface of the connecting electrode, including: The first opening exposes at least one side of the connecting electrode.

4. The display substrate according to claim 3, wherein, On the side of the first opening away from the substrate, the pixel definition layer has a triangular or trapezoidal cross-section in a plane perpendicular to the substrate.

5. The display substrate according to claim 4, wherein, Within one of the light-emitting elements, the orthographic projection of the connecting electrode on the substrate does not overlap with the orthographic projection of the cathode on the substrate, and the first opening is located on the side of the connecting electrode closer to the anode.

6. The display substrate according to claim 4, wherein, Within a single light-emitting element, the orthogonal projection of the connecting electrode onto the substrate lies within the range of the orthogonal projection of the cathode onto the substrate, and the first opening is located on the side of the connecting electrode away from the anode.

7. The display substrate according to claim 5 or 6, wherein, In the extending direction of the connecting electrode, the ratio of the length of the connecting electrode to the length of the adjacent side of the cathode is greater than or equal to 0.8 and less than or equal to 1.

8. The display substrate according to claim 5 or 6, wherein, The anodes of the multiple light-emitting elements are interconnected.

9. The display substrate according to claim 6, wherein, The orthographic projection of the connecting electrode on the substrate surrounds the orthographic projection of the anode on the substrate.

10. The display substrate according to claim 9, wherein, The drive circuit layer also includes a first power line, and the anode is connected to the first power line through a via.

11. The display substrate according to claim 9, wherein, The light-emitting structure layer further includes a first power line, which is located on the side of the pixel definition layer away from the substrate, and the orthographic projection of the first power line on the substrate is within the range of the orthographic projection of the pixel definition layer on the substrate. The anode is connected to the first power line through a via.

12. The display substrate according to claim 4, wherein, The pixel definition layer further includes a second opening located between adjacent light-emitting elements; the cathodes of the adjacent light-emitting elements are isolated from each other, including: The cathode of the adjacent light-emitting element is disconnected at the second opening.

13. The display substrate according to claim 12, wherein, Along a direction away from the substrate, the distance between the pixel definition layers located on both sides of the second opening gradually increases in a plane parallel to the substrate.

14. The display substrate according to claim 4 or 11, wherein, The light-emitting structure layer further includes an isolation portion, which is located on the side of the pixel definition layer away from the substrate, and the orthographic projection of the isolation portion on the substrate is within the range of the orthographic projection of the pixel definition layer on the substrate; The cathodes of the adjacent light-emitting elements are isolated from each other, including: The cathode of the adjacent light-emitting element is disconnected at the isolation section.

15. The display substrate according to claim 14, wherein, The light-emitting structure layer further includes a first power line, which is located on the side of the pixel definition layer away from the substrate, and the isolation portion is connected to the first power line.

16. The display substrate according to claim 4, wherein, The light-emitting structure layer further includes an overlapping portion, which is located on the side of the cathode away from the substrate; The cathode is connected to the connecting electrode through the first opening, including: The overlapping portion at least fills the first opening, so that the cathode and the connecting electrode are interconnected.

17. A display device comprising a display substrate as claimed in any one of claims 1-16.

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