Interconnect structure and design method therefor

Abstract

The present application provides an interconnect structure and a design method therefor. The interconnect structure comprises: a recess arranged in a first dielectric layer; a plurality of pillars arranged in the recess at intervals, the pillars being formed of the first dielectric layer, and the top walls of the pillars being flush with the surface of the first dielectric layer; and a conductive material filled between the recess and the pillars. The present application can be used for mitigating recess defects of an interconnect structure.

Description

Interconnection Structure and Design Methods

[0001] This application claims priority to Chinese Patent Application No. 202411830643.9, filed on December 12, 2024, entitled “Interconnection Structure and Design Method Thereof”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to an interconnect structure and its design method. Background Technology

[0003] In semiconductor manufacturing, damascus-based metal (e.g., copper) interconnects are widely used for electrical connections in back-end metal wiring processes. These metal interconnects are significantly affected by their filling processes (e.g., electroplating) and chemical mechanical polishing (CMP) pattern loading. Large metal pad areas are prone to severe dishing defects. For wiring layers such as top metal (TM) and ultra-thick metal (UTM), dishing defects can adversely affect subsequent electrical connections and device packaging.

[0004] Furthermore, the aforementioned dents can only be confirmed through optical inspection when their degree of dentation is relatively severe. If the degree of dentation is not sufficiently severe, it is difficult to detect through optical inspection, and optical inspection cannot quantify the degree of dentation. While preparing samples of the dents and using methods such as atomic force microscopy (AFM) can provide relatively accurate quantification of the degree of dentation, these methods still depend on accurately detecting the dents, and the time and cost of sample preparation and testing significantly impact production. Summary of the Invention

[0005] The purpose of this application is to provide an interconnect structure and its design method to mitigate the dent defects of the interconnect structure.

[0006] To address the aforementioned technical problems, the interconnection structure provided in this application includes:

[0007] A groove is provided in the first dielectric layer;

[0008] Several columns are spaced apart in the groove, the columns are composed of the first medium layer and the top wall of the columns is flush with the surface of the first medium layer;

[0009] A conductive material is filled between the groove and the column.

[0010] Optionally, the groove is provided with at least four spaced columns, and the sum of the cross-sectional areas of all the columns in the groove is less than or equal to 30% of the cross-sectional area of ​​the groove.

[0011] Optionally, all the columns within the groove have the same size, and adjacent columns arranged in the same direction have the same distance between them.

[0012] Optionally, the groove is provided with a first column located at the center of the groove and a plurality of second columns surrounding the first column, wherein the size of the first column is larger than the size of the second columns.

[0013] Optionally, the cross-sectional shape of the column is rectangular.

[0014] Based on another aspect of this application, a design method for an interconnect structure is also provided, comprising:

[0015] Provide the interconnection structure as described above;

[0016] A second dielectric layer is formed covering the interconnect structure;

[0017] A test resistor with a preset resistance range is formed on the second dielectric layer above the interconnect structure. The test resistor is formed by connecting several linear resistance units to each other.

[0018] Obtain the actual resistance value of the test resistor, and adjust the size and / or number and / or arrangement of the pillars in the interconnect structure according to the actual resistance value, so that the actual resistance value of the adjusted test resistor conforms to the preset resistance value range.

[0019] Optionally, the test resistor is formed by connecting a plurality of linear resistor units extending along a first direction and a second direction. Each linear resistor unit in the test resistor has the same linewidth, and the linear resistor units extending along the first direction and / or the second direction are evenly spaced. The first direction and the second direction are orthogonal.

[0020] Optionally, the test resistor is in the shape of a mosquito coil or a snake.

[0021] Optionally, three bridge arm resistors are formed on the second dielectric layer and connected to the interconnect structure, and the actual resistance value of the test resistor is obtained by using the bridge method.

[0022] Optionally, the actual resistance value of the test resistor can be obtained using a single-bridge method, with the test resistor as a single variable.

[0023] Optionally, the actual resistance value of the test resistor can be obtained by using the test resistor and the reference resistor as two variables and employing a double-bridge method. The reference resistor is a resistor structure with the same design as the test resistor, formed on the flat surface of the second dielectric layer.

[0024] In summary, this application provides an interconnect structure and a design method for the interconnect structure. The interconnect structure includes a groove disposed in a first dielectric layer; a plurality of pillars disposed in the groove, wherein the pillars are formed of the first dielectric layer and the top wall of the pillars is flush with the surface of the first dielectric layer; and conductive material filling the space between the groove and the pillars. In this application, when the conductive material is filled in the groove, the groove is further provided with a plurality of pillars flush with the first dielectric layer as supports. This reduces the degree of indentation of the conductive material filling the groove (before the grinding process) compared to the degree of indentation after filling the groove with conductive material without the pillars, which helps to reduce the degree of indentation after the grinding process. Moreover, more importantly, when the conductive material is ground to near the surface of the first dielectric layer during the grinding process, the pillars in the groove can act as a grinding stop, reducing or preventing the grinding pad from continuously grinding the conductive material around the pillars, thereby reducing the indentation defects of the formed interconnect structure. Attached Figure Description

[0025] Those skilled in the art will understand that the accompanying drawings are provided to better understand this application and do not constitute any limitation on the scope of this application.

[0026] Figure 1a is a top view of an interconnection structure provided in an embodiment of this application;

[0027] Figure 1b is a cross-sectional schematic diagram of an interconnection structure provided in an embodiment of this application;

[0028] Figure 2a is a top view of an interconnection structure provided in an embodiment of this application;

[0029] Figure 2b is a top view of another interconnection structure provided in an embodiment of this application;

[0030] Figure 3 is a flowchart of a design method for an interconnect structure provided in an embodiment of this application;

[0031] Figures 4a to 4e are schematic diagrams of the corresponding steps of the interconnection structure design method provided in this embodiment.

[0032] In the attached figures: 10-First dielectric layer; 10a-Barrier dielectric layer; 10b-First silicon oxide layer; 10c-First silicon nitride layer; 10d-Second silicon oxide layer; 11-Groove; 12-Conductive material; 13-Pillar; 13a-First pillar; 13b-Second pillar; 14-Interconnect structure; X-First direction; Y-Second direction; 31-Second dielectric layer; 31a-Second silicon nitride layer; 31b-Third silicon oxide layer; 32-Test resistor; 321-Resistor unit; 322-Test terminal. Detailed Implementation

[0033] To make the objectives, advantages, and features of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, used only to facilitate and clarify the illustration of the embodiments of this application. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0034] As used herein, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0035] One embodiment of this application provides an interconnection structure.

[0036] Figure 1a is a top view of an interconnection structure provided in an embodiment of this application, and Figure 1b is a cross-sectional view of an interconnection structure provided in an embodiment of this application.

[0037] As shown in Figures 1a and 1b, the interconnect structure 14 provided in this embodiment includes a groove 11, a plurality of pillars 13, and a conductive material 12. The groove 11 is disposed in the first dielectric layer 10. The plurality of pillars 13 are spaced apart in the groove 11, and the pillars 13 are formed by the first dielectric layer 10, with the top wall of the pillars 13 flush with the surface of the first dielectric layer 10. The conductive material 12 fills the space between the groove 11 and the pillars 13.

[0038] A first dielectric layer 10 is disposed on a substrate, in which integrated circuit devices and various doped components, such as n-type doped wells, p-type doped wells, source and drain electrodes, other doped components, or combinations thereof, are formed for forming various devices or components of devices. Integrated circuit devices include various IC devices formed on a semiconductor substrate, including field-effect transistors, diodes, bipolar transistors, imaging sensors, resistors, capacitors, inductors, memory cells, or combinations thereof. The first dielectric layer 10 and the interconnect structure 14 are both part of an interconnect structure layer (having multiple interconnect layers) on the substrate. The interconnect structure 14 is disposed in an upper interconnect layer, which may also contain other linear interconnect structures.

[0039] In this embodiment, the upper interconnect layer can be the top interconnect layer or the second-to-top interconnect layer in the interconnect structure layer. The first dielectric layer 10 may include multiple dielectric layers. Specifically, the first dielectric layer 10 includes a barrier dielectric layer 10a, a first silicon oxide layer 10b, a first silicon nitride layer 10c, and a second silicon oxide layer 10d, which are stacked sequentially from bottom to top. The groove 11 penetrates the second silicon oxide layer 10d and the first silicon nitride layer 10c and extends to a certain depth of the first silicon oxide layer 10b. The bottom of the groove 11 is connected to the lower interconnect layer through a through-hole (not shown). The shape of the groove 11 matches the shape (external shape) of the interconnect structure 14. It should be noted that in the examples of this application, the interconnect structure 14 may be a block structure (e.g., a metal pad), and both the groove 11 and the interconnect structure 14 are rectangular. However, in other examples of this application, the interconnect structure 14 may also be other structures formed by filling the groove with conductive material and having a larger size (relative to the interconnect line). The cross-sectional shape of the interconnect structure 14 and the groove 11 may also be any other suitable shape, such as a circle or a composite pattern composed of multiple patterns.

[0040] Referring to Figures 1a and 1b, a plurality of pillars 13 (e.g., at least four pillars) are also provided within the groove 11. The pillars 13 are composed of a first dielectric layer 10 (or a portion thereof), and the top walls of the pillars 13 are flush with or substantially flush with the surface of the first dielectric layer 10. Conductive material 12 fills the space between the groove 11 and the pillars 13, and between each pillar 13. The top walls of the conductive material 12 are flush with or substantially flush with the top walls of the surrounding pillars 13 or the first dielectric layer 10. In other words, the pillars 13 can be considered as being embedded between the conductive material 12 within the groove 11. The conductive material 12 can be, for example, any suitable metallic material. In this embodiment, the conductive material 12 may include metallic copper and may be formed using a chemical electroplating process. In this embodiment, the pillars 13 may include a second silicon oxide layer 10d, a first silicon nitride layer 10c, and a partial thickness of a first silicon oxide layer 10b in the first dielectric layer 10.

[0041] Of course, the advantages of the interconnect structure 14 provided in this embodiment are more easily understood from the process of forming the aforementioned groove 11, pillar 13, and conductive material 12. Specifically, firstly, a patterned mask layer is formed on the first dielectric layer 10. The patterned mask layer has openings to expose the area where the groove 11 is to be formed, and the patterned mask layer also has at least four spaced coverage areas within the openings corresponding to the areas where the pillar 13 is to be formed. Next, a dry etching process is performed to form the groove 11 and the pillar 13 located in the groove 11 in the first dielectric layer 10. The pillar 13 is flush with the top wall of the first dielectric layer 10 surrounding the groove 11. Next, a conductive material 12 is formed to cover the surface of the first dielectric layer 10 and fill the groove 11 to its top. Next, a polishing process is performed to remove the conductive material 12 on the first dielectric layer 10, and the conductive material 12 retained in the groove 11 is used to form the interconnect structure 14. As can be seen from the above process, when the conductive material 12 is filled into the groove 11, at least four pillars 13 flush with the first dielectric layer 10 are also provided in the groove 11 as supports. This makes the degree of depression of the conductive material 12 filled above the groove 11 before the grinding process less (compared to the degree of depression after filling the groove with conductive material 12 without the pillars 13), which helps to reduce the degree of depression after the grinding process. Moreover, more importantly, when the conductive material 12 is ground to near the surface of the first dielectric layer 10 during the grinding process, the pillars 13 in the groove 11 can also play the role of grinding stop (similar to a grinding stop layer), reducing or preventing the grinding pad from continuously grinding the conductive material 12 around the pillars 13, thereby reducing the depression defects of the formed interconnect structure. The size, number, shape, and arrangement of the pillars 13 can be determined by the degree of indentation of the conductive material 12 in the groove 11 after grinding when the pillars 13 are not provided, and the requirements for the indentation defects of the interconnect structure 14. The degree of indentation of the conductive material 12 in the groove 11 after grinding when the pillars 13 are not provided can be related to the size of the groove 11, the filling performance of the conductive material 12, and the grinding difference between the first dielectric layer 10 and the conductive material 12. It is understood that the proportion of the sum of the cross-sectional areas of all the pillars 13 in the groove 11 to the cross-sectional area of ​​the groove 11 should not be too large (e.g., less than or equal to 30%), so as to avoid affecting the resistance of the interconnect structure 14 and the contact resistance with other interconnect structures.

[0042] In one example, as shown in the top view of Figure 2a, the groove 11 may be rectangular (its size may be, for example, 50 micrometers * 50 micrometers), and it includes an edge parallel to the first direction X and the second direction Y. The first direction X and the second direction Y are orthogonal. At least four pillars 13 (nine pillars 13 in this example) are spaced apart in the groove 11 along the first direction X and the second direction Y. Each pillar 13 has the same size, and adjacent pillars 13 arranged in the same direction have the same distance between them. In other words, at least four pillars 13 are arrayed in the groove 11.

[0043] In another example, as shown in the top view of Figure 2b, the groove 11 may be rectangular, including an edge parallel to the first direction X and the second direction Y, the first direction X and the second direction Y being orthogonal, and the groove 11 having a first column 13a located at the center of the groove 11 and a plurality of second columns 13b (e.g., 4) surrounding the first column 13a, the size of the first column 13a being larger than the size of the second column 13b.

[0044] In addition, in the examples shown in Figures 1a, 2a and 2b, the cross-sectional shape of the column 13 is rectangular. In other examples of this embodiment, the cross-sectional shape of the column 13 may be other suitable shapes other than rectangular (e.g., circular, sheet-like, L-shaped, T-shaped, etc.). Moreover, the spacing between the columns 13 along the first direction X may be different from the spacing between the columns 13 along the second direction Y.

[0045] An embodiment of this application also provides a design method for an interconnect structure, used to design and verify the above-described interconnect structure.

[0046] Figure 3 is a flowchart of a design method for an interconnect structure provided in an embodiment of this application.

[0047] As shown in Figure 3, the design method of the interconnect structure provided in this embodiment includes:

[0048] S01: Provides the interconnection structure as described above;

[0049] S02: Form a second dielectric layer covering the interconnect structure;

[0050] S03: A test resistor with a preset resistance value range is formed on the second dielectric layer above the interconnect structure. The test resistor is formed by connecting several linear resistance units to each other.

[0051] S04: Obtain the actual resistance value of the test resistor, and adjust the size and / or number and / or arrangement of the pillars in the interconnection structure according to the actual resistance value, so that the actual resistance value of the adjusted test resistor conforms to the preset resistance value range.

[0052] Figures 4a to 4e are schematic diagrams of the corresponding steps of the interconnect structure design method provided in this embodiment. Next, the design method of the interconnect structure will be described in detail with reference to Figures 4a to 4e.

[0053] First, step S01 is executed, providing the interconnect structure 14 as described above. The specific configuration of the interconnect structure 14 can be found in the above embodiments and will not be repeated here. Taking the design and verification of the rationality of the arrangement of each pillar 13 in the groove 11 as an example (applied to experimental specimens), the DOE experiment method can also be used. Multiple grooves 11 are set in the first dielectric layer 10, and pillars 13 of various shapes, sizes, quantities, and arrangements are set within these multiple grooves 11 to facilitate quickly obtaining a better design. In the example shown in 2a, the spacing distance L between pillars 13 along the first direction X and the spacing distance W between pillars 13 along the second direction Y can be used as parameter variables for design.

[0054] Next, step S02 is performed, as shown in FIG4a, to form a second dielectric layer 31 covering the interconnect structure 14. The degree of recess in the second dielectric layer 31 on the interconnect structure 14 can be close to the degree of recess in the interconnect structure 14. In one example, the interconnect structure 14 is an interconnect layer (e.g., the second-to-top interconnect layer) below the top interconnect layer. The second dielectric layer 31 can have the same or similar film structure and film thickness as the dielectric material layer between the second-to-top interconnect layer and the top interconnect layer in the actual product. In other words, the dielectric material layer between the second-to-top interconnect layer and the top interconnect layer in the actual product is used as the second dielectric layer 31. In another example, the interconnect structure 14 is the top interconnect layer, and the second dielectric layer 31 can be prepared with reference to the dielectric layer under the top interconnect layer. For example, the second dielectric layer 31 has the same film structure and film thickness as the dielectric material layer between the second-to-top interconnect layer and the top interconnect layer in the actual product. Of course, the thinner the second dielectric layer 31, the higher the sensitivity of the interconnect structure 14. In practice, a second dielectric layer 31 that is thinner than the dielectric material layer between the second-to-top interconnect layer and the top interconnect layer in an actual product can also be formed. In this embodiment, the second dielectric layer 31 may include a second silicon nitride layer 31a and a third silicon oxide layer 31b formed sequentially.

[0055] Next, as shown in the cross-sectional view of FIG4b, step S03 is performed to form a test resistor 32 with a preset resistance value range on the second dielectric layer 31 above the interconnect structure 14. The test resistor 32 is formed by connecting several linear resistor units 321 to each other.

[0056] In this design, identical test resistors 32 can be formed on the second dielectric layer 31 above multiple interconnect structures 14. The test resistor 32 is formed by sequentially connecting multiple linear resistor units 321 extending along the first direction X and the second direction Y, and extending out two ends as test terminals 322. The first direction X and the second direction Y are orthogonal. The preset resistance value range can be the resistance value of the test resistor 32 formed on a flat surface. However, since the surface of the second dielectric layer 31 carrying the test resistor 32 has different degrees of depression (depression defects), the length of each linear resistor unit 321 in the test resistor 32 increases with the increase of the degree of depression. Therefore, the greater the degree of depression (depression defect) of the interconnect structure 14, the greater the resistance value of the test resistor 32. In other words, the degree of depression of the interconnect structure 14 can be measured by the size of the actual resistance value of the test resistor 32 relative to the preset resistance value range.

[0057] As shown in the top view of Figure 4c, in one example, the test resistor 32 can be in the shape of a mosquito coil, such as a rectangular spiral, and the outermost linear resistor unit 321 of the test resistor 32 can correspond to or substantially correspond to the edge of the interconnect structure 14.

[0058] As shown in the top view of Figure 4d, in another example, the test resistor 32 can be snake-shaped, that is, meandering and extending. The outermost linear resistor unit 321 of the test resistor 32 can correspond to or substantially correspond to the edge of the interconnect structure 14.

[0059] Furthermore, in the examples shown in Figures 4c and 4d, each linear resistor unit 321 in the test resistor 32 has the same linewidth, and the linear resistor units 321 extending along the first direction X and the second direction Y are evenly spaced. However, in other examples of this embodiment, some linear resistor units 321 may have different linewidths, and the linear resistor units 321 along the same direction may have different spacing distances, depending on actual needs. Additionally, in the examples shown in Figures 4c and 4d, the test terminals 322 of the test resistor 32 are led out from opposite directions (diagonal directions). However, in other examples of this embodiment, the two test terminals 322 may also be led out from the same direction, or even from the same angle.

[0060] Next, step S04 is executed to obtain the actual resistance value of the test resistor 32. The size and / or quantity and / or arrangement of the pillars 13 in the interconnect structure 14 are adjusted according to the actual resistance value so that the actual resistance value of the adjusted test resistor 32 conforms to the preset resistance value range.

[0061] In this embodiment, three bridge arm resistors are formed on the second dielectric layer 31 to match an interconnect structure 14. The actual resistance value of the test resistor 32 is obtained using the bridge method. Based on the difference between the actual resistance value and the preset resistance value range, the size and / or number and / or arrangement of the pillars 13 in the interconnect structure 14 are appropriately adjusted. When designing multiple sets of pillars 13 (pillar 13 combinations) with different sizes and / or numbers and / or arrangements using the DOE experimental method, the best-designed interconnect structure 14 (pillar 13 combination) can be directly selected. The actual resistance value of the test resistor 32 corresponding to the best-designed interconnect structure 14 is within the preset resistance value range and preferably in the middle position. Of course, if the actual resistance values ​​of the test resistor 32 corresponding to the above multiple sets of main body combinations (interconnect structures 14) with different sizes and / or numbers and / or arrangements do not conform to the preset resistance value range, the corresponding size, number, and arrangement of pillars 13 can be redesigned according to the variation pattern of the above multiple sets of data, and the above operations are repeated.

[0062] Figure 4e is a circuit diagram of the bridge method for testing resistance. R1, R3 and R4 are the three bridge arm resistors, and R2 is the test resistor 32 to be tested. The test resistor 32 is used as a single variable, and the actual resistance value of the test resistor 32 is obtained by the single bridge method.

[0063] In a preferred embodiment, a resistor structure with the same design as the test resistor 32 can also be formed on the flat surface of the second dielectric layer 31 as a reference resistor to replace the bridge arm resistor R3 in the same group as the test resistor 32. The actual resistance value of the test resistor 32 is obtained by using the double bridge method. Moreover, the change in resistance of the test resistor 32 under the same process conditions relative to the resistance formed on the flat surface can be quantified very intuitively by the ratio of R2 / R3.

[0064] In another preferred example, two test resistors 32 to be tested can also be used as one of the bridge arm resistors, such as R2 and R3, to compare the resistance values ​​of different test resistors 32 in pairs, that is, to compare the degree of indentation of different interconnect structures 14 in pairs.

[0065] Furthermore, it should be noted that the aforementioned test resistor 32 can also be applied to mass-produced products, that is, an interconnect structure 14 is formed in the test area, a test resistor 32 is formed on the second dielectric layer 31 above it, and the actual resistance value of the test resistor 32 is obtained using the above method to evaluate the degree of depression (depression defect) of the interconnect structure 14.

[0066] In summary, this application provides an interconnect structure and a design method for the interconnect structure. The interconnect structure includes a groove disposed in a first dielectric layer; a plurality of pillars spaced apart within the groove, the pillars being formed of the first dielectric layer and their top walls flush with the surface of the first dielectric layer; and a conductive material filling the space between the groove and the pillars. In this application, when the conductive material is filled in the groove, the groove is further provided with a plurality of pillars flush with the first dielectric layer as supports. This reduces the degree of indentation of the conductive material filled above the groove before the grinding process (compared to the degree of indentation after filling the groove with conductive material without the pillars), which helps to reduce the degree of indentation after the grinding process. Moreover, more importantly, when the conductive material is ground to near the surface of the first dielectric layer during the grinding process, the pillars in the groove can act as a grinding stop, reducing or preventing the grinding pad from continuously grinding the conductive material around the pillars, thereby reducing the indentation defects of the formed interconnect structure.

[0067] The above description is merely a description of preferred embodiments of this application and is not intended to limit the scope of this application in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An interconnection structure, characterized in that, include: A groove is provided in the first dielectric layer; Several columns are spaced apart in the groove, the columns are composed of the first medium layer and the top wall of the columns is flush with the surface of the first medium layer; A conductive material is filled between the groove and the column.

2. The interconnection structure according to claim 1, characterized in that, The groove contains at least four spaced columns, and the sum of the cross-sectional areas of all the columns in the groove is less than or equal to 30% of the cross-sectional area of ​​the groove.

3. The interconnection structure according to claim 2, characterized in that, All the columns within the groove have the same size, and adjacent columns arranged in the same direction have the same distance between them.

4. The interconnection structure according to claim 2, characterized in that, The groove contains a first column located at the center of the groove and several second columns surrounding the first column, wherein the size of the first column is larger than the size of the second columns.

5. The interconnection structure according to any one of claims 1 to 4, characterized in that, The cross-sectional shape of the column is rectangular.

6. A design method for an interconnect structure, characterized in that, include: Provide an interconnection structure as described in any one of claims 1 to 5; A second dielectric layer is formed covering the interconnect structure; A test resistor with a preset resistance range is formed on the second dielectric layer above the interconnect structure. The test resistor is formed by connecting several linear resistance units to each other. Obtain the actual resistance value of the test resistor, and adjust the size and / or number and / or arrangement of the pillars in the interconnect structure according to the actual resistance value, so that the actual resistance value of the adjusted test resistor conforms to the preset resistance value range.

7. The design method of the interconnect structure according to claim 6, characterized in that, The test resistor is formed by connecting a plurality of linear resistor units extending along a first direction and a second direction. Each of the linear resistor units in the test resistor has the same linewidth, and the linear resistor units extending along the first direction and / or the second direction are evenly spaced. The first direction and the second direction are orthogonal.

8. The design method of the interconnect structure according to claim 6 or 7, characterized in that, The test resistor is shaped like a mosquito coil or a snake.

9. The design method of the interconnect structure according to any one of claims 6 to 8, characterized in that, Three bridge arm resistors are also formed on the second dielectric layer and connected to the interconnect structure, and the actual resistance value of the test resistor is obtained by the bridge method.

10. The design method of the interconnect structure according to any one of claims 6 to 9, characterized in that, Using the test resistor as a single variable, the actual resistance value of the test resistor is obtained using a single-bridge method.

11. The design method of the interconnect structure according to any one of claims 6 to 9, characterized in that, Using the test resistor and reference resistor as two variables, the actual resistance value of the test resistor is obtained by a double-bridge method, wherein the reference resistor is a resistor structure with the same design as the test resistor formed on the flat surface of the second dielectric layer.

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