Method for separating chips
The method addresses GaN chip separation challenges by using a capping layer and high-temperature decomposition to create channels and trenches, reducing damage and thermal budget, thus enhancing the efficiency and economy of the chip singulation process.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- ROBERT BOSCH GMBH
- Filing Date
- 2025-12-08
- Publication Date
- 2026-06-18
AI Technical Summary
Vertical power semiconductor devices based on GaN face issues during chip separation, such as deformation, rupture, and alteration of device parameters due to sawing or laser cutting, leading to damage and destruction.
A method involving the application of a capping layer followed by selective decomposition of the epitaxial layer using high-temperature processes and etching techniques to create channels and trenches, allowing for gentle and efficient chip separation.
The method reduces chip damage and deformation, enhances detachment from the substrate, and minimizes thermal budget requirements, resulting in a more economical and effective chip singulation process.
Smart Images
Figure EP2025085904_18062026_PF_FP_ABST
Abstract
Description
[0001] R. 416555
[0002] - 1 -
[0003] Description
[0004] title
[0005] Method for singulating chips
[0006] The invention relates to a method for singulating chips.
[0007] State of the art
[0008] Vertical power semiconductor devices based on GaN typically comprise an impurity substrate, a buffer layer, and an epitaxial layer during the fabrication process. The buffer layer acts as a mediator for lattice matching between the impurity substrate and the epitaxial layer. At the end of the fabrication process, the impurity substrate and buffer layer are removed, and the vertical power semiconductor devices are separated into chips. Because the processed semiconductor wafer is thin, the chips can be deformed during the separation process, for example, by sawing or laser cutting, which can alter device parameters such as the threshold voltage. Furthermore, the membranes can rupture, resulting in the destruction or damage of the device.
[0009] The purpose of the invention is to overcome these disadvantages.
[0010] Disclosure of the invention
[0011] The inventive method for singulating chips with doped first regions on a substrate, wherein the substrate comprises a first semiconductor material, wherein a buffer layer is arranged on the substrate and at least one epitaxial layer is arranged on the buffer layer, which comprises a second semiconductor material, wherein the first semiconductor material and the second R. 416555
[0012] - 2 -
[0013] The process, in which the semiconductor material differs, comprises the application of a capping layer to the at least one epitaxial layer by means of CVD, in particular by means of LPCVD, and the exposure of second regions of the capping layer by means of lithography, wherein the second regions define the output regions of chip singulation lines. Furthermore, the process comprises the removal of the second regions of the capping layer by means of an etching process, whereby the output regions of the chip singulation lines are exposed, and the activation of the doped first regions by means of a high-temperature process above 1000 °C, wherein the epitaxial layer is degraded from the output regions of the chip singulation lines essentially perpendicularly to the buffer layer in the form of channels.In other words, the decomposition of GaN at high temperatures into metallic gallium and nitrogen is used to selectively create topography in a wafer, with individual chips being quasi-completely or completely separated from the substrate.
[0014] The advantage here is that a manufacturing step is eliminated. The process is therefore more economical and gentler on the chips.
[0015] In a further training course, the epitaxial layer is decomposed laterally from the shafts in the area of an interface with the buffer layer.
[0016] The advantage here is that the chips can be easily detached from the buffer layer.
[0017] In a further embodiment, the epitaxial layer is further degraded laterally from the shafts using wet etching or gas phase etching.
[0018] The advantage here is that the chips detach completely from the buffer layer.
[0019] In a further development process, first and second trenches are created from a surface of the epitaxial layer using dry etching, wherein the first trenches are wider than the second trenches, and wherein both the first and second trenches extend into the epitaxial layer, with the second trenches being arranged on top of the first trenches. R. 416555
[0020] - 3 -
[0021] The advantage here is that the necessary slit depth for chip removal is less, which reduces the necessary thermal budget for dopant activation during the annealing process.
[0022] In a further embodiment, the side walls of the shafts are treated using wet casting, in particular using TMAH.
[0023] The advantage here is that this smooths the side walls of the created shafts.
[0024] In a further training course, the second semiconductor material covered is GaN.
[0025] In a further embodiment, the first semiconductor material comprises sapphire or silicon.
[0026] In a further training course, the capping layer comprises SiN or SiCh.
[0027] An advantage here is that the capping layer is inert to TMAH.
[0028] In another embodiment, the process pressure of the high-temperature process is a maximum of 1 bar.
[0029] Further advantages arise from the following description of exemplary embodiments or the dependent patent claims.
[0030] Brief description of the drawings
[0031] The present invention is explained below with reference to preferred embodiments and the accompanying drawings. These show:
[0032] Figure 1 shows a method for singulating chips,
[0033] Figure 2a shows an intermediate product after step 140 of the process according to the invention, R. 416555
[0034] - 4 -
[0035] Figure 2b shows an intermediate product after step 150 of the process according to the invention,
[0036] Figure 3a shows an intermediate product with optional trench after step 140 of the process according to the invention.
[0037] Figure 3b shows an intermediate product with optional trenching after step 150 of the process according to the invention.
[0038] Figure 4a shows an intermediate product of lateral decomposition during the high-temperature process, and
[0039] Figure 4b shows an intermediate product of lateral decomposition by wet or gas phase etching.
[0040] Figure 1 shows a method 100 for singulating chips. The chips comprise doped first regions on a substrate, the substrate having a first semiconductor material, for example Si. A buffer layer is arranged on the substrate, and on the buffer layer is at least one epitaxial layer, which has a second semiconductor material. The epitaxial layer comprises GaN. This means that the first semiconductor material and the second semiconductor material are different. The method 100 starts with the deposition 120 of a capping layer onto the at least one epitaxial layer by CVD, preferably by LPCVD. The capping layer comprises, for example, SiN or SiCh. In a subsequent step 130, second regions of the capping layer are exposed by lithography, the second regions defining output regions of chip singulation lines.In a subsequent step 140, the second regions of the capping layer are removed by an etching process, exposing the output regions of the chip singulation lines. This etching process can be wet or dry chemical. In a subsequent step 150, the doped first regions are activated by a high-temperature process above 1000 °C, whereby the epitaxial layer is degraded essentially perpendicularly from the output regions of the chip singulation lines to the buffer layer in the form of channels. That is, due to the lack of capping, the R. 416555 degrades.
[0041] - 5 -
[0042] GaN decomposes along the chip singulation lines to or within the buffer layer at a suitably chosen temperature budget and process pressure. At typical activation temperatures above 1000°C, atmospheric pressure is sufficient for GaN decomposition. If decomposition extends down to the buffer layer, complete chip singulation is achieved after the back-side buffer removal process.
[0043] During the high-temperature process, in addition to the vertical decomposition of GaN, the epitaxial layer also decomposes laterally. This occurs starting from the created channel at the interface with the substrate. Lateral decomposition can be influenced by a specific epitaxial design. This includes growth defects and changes in the chemical composition of the epitaxial layer. To further enhance lateral decomposition at the interface between the substrate and the epitaxial layer, wet etching or gas-phase etching can be performed.
[0044] To smooth the sidewalls of the created shafts, wet etching with TMAH is performed. TMAH preferentially attacks vertical and oblique crystal facets of the GaN crystal. The capping layer is inert to TMAH, thus protecting the rest of the wafer surface.
[0045] To reduce the temperature budget, in an optional step 110, performed before step 120, first and second trenches can be created from a surface of the epitaxial layer using dry etching. The first trenches are wider than the second trenches, with both extending into the epitaxial layer. The second regions are positioned on top of or encompass the first trenches. This means that trench formation occurs within the first trenches. The trench depth required for chip detachment is also reduced. Therefore, the thermal budget required for dopant activation of the doped first regions during annealing can be reduced.
[0046] As an alternative to the capping layer, the process pressure can be varied. This allows for targeted control of the decomposition of GaN and the evaporation of Ga. If a Ga droplet is located on the surface of the epitaxial layer, the process slows down. 416555
[0047] - 6 -
[0048] Decomposition of the underlying gallium nitride. The gallium acts as a kind of intrinsic capping, protecting the GaN decomposition by covering the epitaxial layer.
[0049] Figure 2a shows an intermediate product 200 after carrying out step 140 of the inventive method 100. The intermediate product 200 comprises a substrate 201. A buffer layer 202 is arranged on the substrate 201. An epitaxial layer 203 is arranged on the buffer layer 202. A capping layer 204 is arranged on the epitaxial layer 203, the capping layer having second regions 205 that define the output regions of the chip singulation lines.
[0050] Figure 2b shows an intermediate product 200 after carrying out step 150 of the process 100 according to the invention. Identical reference numerals in Figure 2b denote the same features as in Figure 2a. The intermediate product 200 has channels 206 along which the GaN has decomposed. The channels extend to the buffer layer 202.
[0051] Figure 3a shows an intermediate product 300 after carrying out step 140 of the inventive method 100, wherein the optional step 110, the creation of first grooves 307 and second grooves 308 by dry etching starting from a surface of the epitaxial layer 303, has been carried out. Identical reference numerals in Figure 3a correspond to the features of Figure 2a. The first grooves 307 and the second grooves 308 extend into the epitaxial layer 303. The first grooves 307 are wider than the second grooves 308. The second regions 305 are arranged on the first grooves 307.
[0052] Figure 3b shows an intermediate product 300 after carrying out step 140 of the inventive method 100, wherein the optional step 110, the production of first trenches 307 and second trenches 308 by dry etching starting from a surface of the epitaxial layer 303, has been carried out. Identical reference numerals in Figure 3b correspond to the features in Figure 3a. The shafts 309 extend from the first trenches 307 to the buffer layer 302. R. 416555
[0053] - 7 -
[0054] Figure 4a shows an intermediate product 400 of a lateral decomposition 410 during the high-temperature process. Identical posterior reference numerals in Figure 4a correspond to the features of Figure 2a.
[0055] Figure 4b shows an intermediate product 400 of a lateral decomposition 411 during wet or gas-phase etching, wherein the chip 412 is completely detached. Identical posterior reference numerals of Figure 4a correspond to the features of Figure 2a.
[0056] The invention is used, for example, in the manufacture of vertical GaN power transistors exhibiting a high reverse voltage, particularly MOSFETs, which are used in the electric drive systems of electric or hybrid vehicles, for example in DC / DC converters and inverters, as well as in vehicle chargers. The power transistors can also be used in inverters for household appliances such as washing machines.
Claims
R. 416555 - 8 - Claims 1. Method (100) for singulating chips with doped first regions on a substrate, wherein the substrate comprises a first semiconductor material, wherein a buffer layer is arranged on the substrate and at least one epitaxial layer is arranged on the buffer layer, which comprises a second semiconductor material, wherein the first semiconductor material and the second semiconductor material are different, comprising the steps: • Application (120) of a capping layer to the at least one epitaxial layer by means of CVD, in particular by means of LPCVD, • Exposure (130) of second areas of the capping layer by means of lithography, wherein the second areas define output areas of chip singulation lines, • Removal (140) of the second areas of the capping layer by means of an etching process, exposing the output areas of the chip singulation lines, • Activation (150) of the doped first regions by means of a high temperature process above 1000 °C, wherein the epitaxial layer is degraded from the output regions of the chip singulation lines essentially perpendicularly to the buffer layer in the form of shafts.
2. Method (100) according to claim 1, characterized in that the epitaxial layer is decomposed laterally in the area of an interface to the buffer layer starting from the shafts.
3. Method (100) according to one of claims 1 or 2, characterized in that the epitaxial layer is further degraded laterally starting from the shafts by means of wet etching or gas phase etching. R. 416555 - 9 - 4. Method (100) according to one of the preceding claims, characterized in that in a step (110) starting from a surface of the epitaxial layer, first trenches and second trenches are produced by dry etching, wherein the first trenches are wider than the second trenches, wherein the first trenches and the second trenches extend into the epitaxial layer, and wherein the second regions are arranged on the first trenches.
5. Method (100) according to one of the preceding claims, characterized in that side walls of the shafts are treated by means of wet etching, in particular by means of TMAH.
6. Method (100) according to one of the preceding claims, characterized in that the second semiconductor material comprises GaN.
7. Method (100) according to one of the preceding claims, characterized in that the first semiconductor material comprises sapphire or Si.
8. Method (100) according to one of the preceding claims, characterized in that the capping layer comprises SiN or SiÜ2.
9. Method (100) according to one of the preceding claims, characterized in that the process pressure of the high-temperature process is a maximum of 1 bar.