Semiconductor package
The introduction of recesses or slits on the heat sink pad surface in semiconductor packages addresses the trade-off between TIM thickness and insulation, improving thermal conductivity and structural integrity for effective heat dissipation.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- NEXPERIA BV
- Filing Date
- 2025-12-11
- Publication Date
- 2026-06-18
AI Technical Summary
Existing top-side cooled semiconductor packages face a trade-off between desired thermal interface material (TIM) thickness and electrical insulation, leading to reduced isolation and potential breakdown, which hampers effective heat dissipation.
Incorporating recesses or slits on the heat sink pad surface to increase contact area with air or TIM, allowing for improved thermal conductivity without compromising structural integrity.
Enhances thermal performance by reducing thermal resistance and potentially eliminating the need for external heat sinks, while maintaining structural strength and enabling efficient heat dissipation.
Smart Images
Figure EP2025086661_18062026_PF_FP_ABST
Abstract
Description
[0001] Title
[0002] Semiconductor package.
[0003] Technical Field
[0004] The present disclosure relates to semiconductor packages, more specifically using a topcool package or double-side-cool package to dissipate heat produced by semiconductor structure to outside the package.
[0005] Background
[0006] Semiconductor devices generate heat during operation, necessitating effective cooling solutions to maintain performance and reliability. Traditionally, bottom-side cooling has been widely employed, wherein a heat sink is mounted beneath the semiconductor package. However, top-side cooling has emerged as a viable alternative, involving the placement of a heat sink on the top side of the package. The use of both bottom and top heat sinks is also known as a way to dissipate the heat generated by semiconductor chips, transferring it out of the enclosure and increasing the overall performance of electronic devices.
[0007] By using topcool devices the thermal path from the junction to the heat sink bypasses the printed circuit board (PCB), thereby significantly reducing the thermal resistance between the junction and the heat sink. This reduction enables more efficient heat extraction, a critical factor for achieving high-performance and long-lifetime devices. Consequently, Topcool technology is becoming an increasingly preferred solution for applications requiring robust thermal management.
[0008] In the prior art top-side cooled semiconductor packages have been introduced, where the heat flows through the top of the semiconductor package via a layer of thermal interface material (TIM) directly to the heat sink. The topside metal has been flat. Usually the TIM is applied as a layer between the top-side of the semiconductor package and the heat sink. The load on top of the semiconductor package coming from the mounted heat sink may compress the TIM layer, resulting to thin the TIM layer. A decreasing thickness of the TIM layer between the top-side of the semiconductor package and the heat sink may result in a reduced isolation, which could eventually lead to a breakdown of the semiconductor package. Accordingly, designing top-side cooled semiconductor packages is hampered by the trade-off between a desired TIM thickness and a required electrical insulation.
[0009] Accordingly, it is a goal of the present disclosure to provide an improved semiconductor package that enables increase the contact area between top-side and air or TIM. Accordingly, the thermal resistance from junction to air or external heat sink can be reduced.
[0010] Summary
[0011] According to an aspect of the present disclosure, a semiconductor package is proposed which at least comprises a lead frame made from an electrically conductive metal material, at least two terminals, namely a first terminal and a second terminal, are made from an electrically conductive metal material; at least one semiconductor die structure having a first die side and a second die side opposite to the first die side; a plurality of connections electrically and mechanically connecting the at least one semiconductor die structure with the at least one terminals via the lead frame; at least one heat sink pad having a first pad surface side and a second pad surface side opposite to the first pad surface side and mounted with its second pad surface side to the first die side of the semiconductor die structure; as well as a moulding resin is used for encapsulating the lead frame, the at least one semiconductor die structure, the plurality of connections, the at least one heat sink pad and the at least two terminals in such a way, that at least a portion of the heat sink pad and at least a portion of the at least two terminals exposed. The exposed first pad surface side comprises at least one recess extending from the first pad surface side towards the second pad surface side.
[0012] The inventors have found that it may be beneficial to provide the topside heat sink pad surface (first pad surface side) with at least one recess. This can increase the contact area between topside metal and air / TIM. Accordingly, the thermal resistance from junction to air / TIM can be reduced. This solution offers at least two key advantages: First eliminating the need for an external heat sink in certain applications. The topcool device can operate without an external heat sink because the topside metal is directly exposed to air. With sufficient contact area between the topside metal and the air system designers can rely solely on air cooling to dissipate heat. This simplifies the cooling system and reduces overall costs.
[0013] Second enhancing thermal performance with an external heat sink when an external heat sink is required designers can use a thermal interface material TIM with higher thermal conductivity than the topcool metal. The proposed design lowers the thermal resistance between the semiconductor junction and the heat sink improving heat transfer efficiency.
[0014] In an example of the disclosure a depth dimension of the at least one recess is smaller than a thickness of the heat sink pad. The thickness of the heat sink pad should be measured between the first pad surface side and the second pad surface side. Accordingly, he recesses are not holes, making it possible to design an even larger heat transfer surface while maintaining higher strength parameters.
[0015] In a particular example, a depth of the recess is up to 50% of the thickness of the heat sink pad. This depth of indentation makes it possible to maintain the high strength parameters of the structure as well as increase the heat transfer surface.
[0016] It should be noted, that the recess may have a width ranges between from 50 pm to 500 pm, whereas an intermediate space between adjacent recesses may be from 50 pm to 500 pm. This means that both the depth of recesses and the spacing of subsequent recesses can be fixed and set within the indicated range, as well as variable within the above range within a single embodiment.
[0017] In the latter example, the at least one recess is configured as a slit.
[0018] In a further detail similarly improving the above advantage the recesses are configured as slits extend along a width dimension of the first pad surface side.
[0019] In a further example, the recesses are configured as parallel slits.
[0020] In a further example, the recesses are configured as intersecting slits. It may also beneficial to provide the recesses configured as bores located in a regular or irregular pattern.
[0021] Brief description of the figures
[0022] Fig. 1 details of a first example of a semiconductor package with recesses configured as parallel, transverse slits according to the disclosure.
[0023] Fig. 2A details of a first example of a semiconductor package with recesses configured as parallel, transverse slits according to the disclosure.
[0024] Fig. 2B details of a first example of a semiconductor package with recesses configured as parallel, transverse slits according to the disclosure.
[0025] Fig. 3 depicts a third example of a semiconductor package with recesses configured as longitudinal slits.
[0026] Fig. 4 depicts a fourth example of a semiconductor package with recesses configured as intersecting slits.
[0027] Fig. 5 depicts a fifth example of a semiconductor package with recesses configured as slits angled at 45 degrees to the direction of the semiconductor package
[0028] Fig. 6 depicts a fourth example of a semiconductor package with recesses configured as geometrical shapes slits and a bore.
[0029] Fig. 7 depicts a second example of a semiconductor package with recesses configured as bores are arranged in an irregular pattern according to the disclosure
[0030] Detailed description
[0031] It is noted that in the description of the figures, same reference numerals refer to the same of similar components performing a same of essentially similar function.
[0032] A more detailed description is made with reference to particular examples, some of which are illustrated in the appended drawings, such that the features of the present disclosure may be understood in more detail. It is noted that the drawings only illustrate typical examples and are therefore not to be considered to limit the scope of the subject matter of the claims. The drawings are incorporated for facilitating an understanding of the disclosure and are thus not necessarily drawn to scale. Advantages of the subject matter as claimed will become apparent to those skilled in the art upon reading the description in conjunction with the accompanying drawings.
[0033] The ensuing description above provides preferred exemplary embodiment(s) only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the preferred exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing a preferred exemplary embodiment of the disclosure, it being understood that various changes may be made in the function and arrangement of elements, including combinations of features from different embodiments, without departing from the scope of the disclosure.
[0034] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to." As used herein, the terms "connected", “coupled” or any variant thereof means any connection, either direct or indirect, between two or more elements; the connection between the elements can be physical, logical, electromagnetic, or a combination thereof. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word "or" in reference to a list of two or more items, covers all the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
[0035] Figures 1 , 2A, 2B depicts the details of a first example of a semiconductor package according to the disclosure that reduces a thermal resistance from junction to air (or TIM) by recesses 14 on a heat sink pad 13 which increase the contact area of a first pad surface side 13a.
[0036] The first example of a top-side cooled semiconductor package according to the disclosure is denoted with reference numeral 10. As shown in the drawings, such semiconductor package at least comprises terminals 12a, 12b made from an electrically conductive metal material, one heat sink pad, and a moulding resin 11 encapsulating the at least one semiconductor die structure 15, the plurality of connections, the at least one heat sink pad 13 and the terminals 12 leaving at least a portion of the first pad side of the heat sink pad 13 and at least a portion of eleven first terminals 12a and eleven second terminals 12b exposed, and they are formed in an array of multiple terminals arranged side-by-side.
[0037] Usually, the at least one semiconductor die structure 15 has a first die side 15a and a second die side 15b opposite to the first die side 15a. The semiconductor die structure is mounted on the lead frame 12 (not shown) or it is electrically coupled with the lead frame 12 or directly with terminal 12avia a plurality of internal connections, such as bond clips 12c (depict on Fig. 2A) or bond wires 12w (depict on Fig. 2B).
[0038] Moreover, in top-side cooled semiconductor packages at least one heat sink pad 13 is mounted to the first die side 15a of the semiconductor die structure 15.
[0039] The semiconductor package 10 is formed by means of a moulding resin 11 , which encapsulates the lead frame 12, the at least one semiconductor die structure 15, the bond wires 12w (Fig.2B) and / or the bond clips 12c (Fig.2A), the at least one heat sink pad 13 and the various terminals 12a-12b in such a way, that at least an outer portion of the heat sink pad 13 and at least an extended portion of the terminals 12a-12b remain exposed.
[0040] In the example of Figures 1 , 2A and 2B the exposed first pad surface side 13a comprises recesses 14 configured as parallel slits extending from the first pad surface side 13a towards the second pad surface side 13b. The recesses 14 are transverse slits, where two of them extend along a width dimension of the first pad surface side.
[0041] Figures 2A depict a depth 14a of the recesses 14, which is 20% of the thickness 13c of the heat sink pad in this example. A width 14b of the recess 14 is 50 pm, and an intermediate space 14c between adjacent recesses 14 is from 50 pm to 500 pm. The second pad surface side 13b of the heat sink pad 13 is connected and electrically coupled with the first die surface side 15a of the semiconductor die structure 15 and the first terminals 12a. The second die side 15b of the die structure 15 is connected and electrically coupled with the bond clip 12c. The bond clip 12c is connected and electrically coupled with the lead frame 12. The lead frame 12 is connected and electrically coupled with the second terminals 12b. In other implementation examples, lead frame 12 and second terminals 12b may be a monolithic part.
[0042] Figures 2B depict a depth 14a of the recesses 14, which is 50% of the thickness 13c of the heat sink pad in this example. A width 14b of the recess 14 is 50 pm, and an intermediate space 14c between adjacent recesses 14 is from 50 pm to 500 pm. The second pad surface side 13b of the heat sink pad 13 is connected and electrically coupled with the first die surface side 15a of the semiconductor die structure 15 and the first terminals 12a. The second die side 15b of the die structure 15 is connected and electrically coupled with the wire bond 12c. The wire bond 12w is connected and electrically coupled with the lead frame 12. The lead frame 12 is connected and electrically coupled with the second terminals 12b. In other implementation examples, lead frame 12 and second terminals 12b may be a monolithic part.
[0043] Fig. 3 depicts a semiconductor package 10i comprising a heat sink pad 13 with recesses 14i configured as parallel, longitudinal slits extending from the first pad surface side 13a towards the second pad surface side 13b.
[0044] Fig. 4 depicts a semiconductor package IO2 comprising a heat sink pad 13 with recesses 142 are configured as intersecting slits extending from the first pad surface side 13a towards the second pad surface side 13b.
[0045] Fig. 5 depicts a semiconductor package IO3 comprising a heat sink pad 13 with recesses 14a configured as slits angled at 45 degrees to the direction of the semiconductor package IO3.
[0046] Fig. 6 depicts a semiconductor package IO4 comprising a heat sink pad 13 with recesses 144 configured as geometrically shaped (circular) slits 144a and a bore 144b extending from the first pad surface side 13a towards the second pad surface side 13b. Fig. 7 depicts a semiconductor package 10s comprising a heat sink pad 13 with recesses 14s are configured as bores extending from the first pad surface side 13a towards the second pad surface side 13b. The recesses 14s are arranged in an irregular pattern A width of the recesses - bores diameter 14bs is 500 pm.
[0047] LIST OF REFERENCE NUMERALS USED
[0048] 10nsemiconductor package (1st-2nd-3rd-4thexample)
[0049] 11 moulding resin encapsulant
[0050] 12 lead frame
[0051] 12a-12b terminals
[0052] 12c bond clip
[0053] 12w bond wires
[0054] 13 heat sink pad (first example)
[0055] 13a first pad surface side
[0056] 13b second pad surface side
[0057] 14 recess (ist-2nd-3rd-4thexample)
[0058] 15 semiconductor die structure
[0059] 15a first die side
[0060] 15b second die side
Claims
9CLAIMS1. A semiconductor package at least comprising: a lead frame made from an electrically conductive metal material; at least two terminals, namely a first terminal and a second terminal, are made from an electrically conductive metal material; at least one semiconductor die structure having a first die side and a second die side opposite to the first die side; a plurality of connections electrically and mechanically connecting the at least one semiconductor die structure with the at least one terminal via the lead frame; at least one heat sink pad having a first pad surface side and a second pad surface side opposite to the first pad surface side and mounted with its second pad surface side to the first die side of the semiconductor die structure; and a moulding resin encapsulating the lead frame, the at least one semiconductor die structure, the plurality of connections, the at least one heat sink pad and the at least two terminals leaving at least a portion of the first pad side of the heat sink pad and at least a portion of the at least two terminals exposed, wherein the exposed first pad surface side comprises at least one recess extending from the first pad surface side towards the second pad surface side.
2. A semiconductor package in accordance with claim 1 , wherein a depth dimension of the at least one recess is smaller than a thickness of the heat sink pad.
3. A semiconductor package in accordance with claims 1 or 2, wherein a depth of the recess is up to 50% of the thickness of the heat sink pad.
4. A semiconductor package in accordance with claims 1 or 2 or 3, wherein a width of the recess ranges between is from 50 pm to 500 pm.
5. A semiconductor package in accordance with any of the claims 1-4, wherein an intermediate space between adjacent recesses is from 50 pm to 500 pm.
6. A semiconductor package in accordance with any of the claims 1-5, wherein the at least one recess is configured as a slit.
7. A semiconductor package in accordance with claim 6, wherein the recesses are configured as slits extend along a width dimension of the first pad surface side.
8. A semiconductor package in accordance with any of the claims 5-7, wherein the recesses are configured as parallel slits.
9. A semiconductor package in accordance with any of the claims 5-8, wherein the recesses are configured as intersecting slits.
10. A semiconductor package in accordance with any of the claims 1-9, wherein the at least one recess is configured as a bore.
11. A semiconductor package in accordance with claim 10, wherein the recesses are configured as bores are arranged in a regular or irregular pattern.