Semiconductor device and leadframe suitable for a manufacturing process of the semiconductor device

Abstract

A semiconductor device comprising: at least one semiconductor die, at least two contacts, made of a conductive material, electrically coupled with the at least one semiconductor die where a first contact (1) is adjacent to a second contact (2), and at least two connectors where a first connector (3) comprises a first part (3a) and a second part (3b), and a second connector (4) comprises a first part (4a) and a second part (4b), wherein the second parts (3b, 4b) of the first connector (3) and the second connector (4) are wider than the first parts (3a, 4a) of the first connector (3) and the second connector (4), a dielectric encapsulation which encapsulates the at least one semiconductor die, the plurality of contacts, and the plurality of connectors such that at most the first part (3a) of the first connector (3) and the first part (4a) of the second connector (4) are encapsulated partially and are extending from the dielectric encapsulation, wherein, the first contact (1) is connected to a first edge (6) of the second part (3b) of the first connector (3), and the second contact (2) is connected to the second connector (4) with a second edge (7) of the second part (4b).

Description

[0001] TITLE

[0002] Semiconductor device and leadframe suitable for a manufacturing process of the semiconductor device

[0003] TECHNICAL FIELD

[0004] The present disclosure relates to a semiconductor device and a leadframe for a manufacturing process of the semiconductor device, and more precisely the present disclosure relates to packages with a reduced parasitic inductance.

[0005] BACKGROUND OF THE DISCLOSURE

[0006] Document AN5384, rev. 2, March 2023 titled “ACEPACK SMIT module package guidelines for mounting and thermal management” published by STMicroelectronics and available on site https: / / www.st.com / resource / en / application_note / an5384-acepack-smit- module-package-guidelines-for-mounting-and-thermal-management- stmicroelectronics.pdf discloses an ACEPACK SMIT product The terminals have a uniform width both outside and inside the encapsulation volume brown / red translucent shading down to the terminal foot which widens for mechanical robustness. Terminal spacing outside the encapsulation is defined by creepage and clearance standards in air and may be in the order of a few millimetres to prevent electrical short circuit / arcing between terminals of different electric potentials. The conventional lead frame approach with uniform terminal width both inside and outside encapsulation has a shortcoming in that it creates high inductance due to large lead spacing creating a large current loop area, which degrades product performance during hard switching.

[0007] Document CN214152889U discloses a power module terminal and power module, power module terminal include DC terminal and AC terminal, and the DC terminal includes: the first assembly comprises a first contact area, a first transition area, a first lamination area and a first pin, wherein the first lamination area is connected to the first contact area through the first transition area, and the first pin is arranged on one side, far away from the first transition area, of the first lamination area; the second assembly comprises a second contact area, a second transition area, a second lamination area and a second pin, the second lamination area is connected to the second contact area through the second transition area, and the second pin is arranged on one side, far away from the second transition area, of the second lamination area. The utility model has the advantages that the transition area is arranged between the contact area and the lamination area, so that the current loss is reduced; on the other hand, stray inductance of the power module terminal is reduced, and reliability and service life of the power module are improved. The utility model discloses but wide application in semiconductor package technical field.

[0008] Accordingly, it is a goal of the present disclosure to provide a reduction of a parasitic inductance in packages manufactured using a single lead frame, which will provide a better electrical property of the semiconductor device while using a standard manufacturing process.

[0009] SUMMARY OF THE DISCLOSURE

[0010] According to a first example of the disclosure, a semiconductor device is disclosed. The semiconductor device comprising at least one semiconductor die, at least two contacts, made of a conductive material, electrically coupled with the at least one semiconductor die where a first contact is adjacent to a second contact, and at least two connectors where a first connector comprises a first part and a second part, and a second connector comprises a first part and a second part. The second parts of the first connector and the second connector are wider than the first parts of the first connector and the second connector. The semiconductor device further comprising a dielectric encapsulation which encapsulates the at least one semiconductor die, the plurality of contacts, and the plurality of connectors such that at most the first part of the first connector and the first part of the second connector are encapsulated partially and are extending from the dielectric encapsulation. The first contact is connected to a first edge of the second part of the first connector, and the second contact is connected to the second connector with a second edge of the second part.

[0011] Preferably the second part of the first connector, and the second part of the second connector are separated with the same distance from each other as the first contact and the second contact.

[0012] Preferably the first connector and / or the first contact further comprises a first surface capacitively coupled with a second surface of the second connector.

[0013] Preferably the second surface is made of a third part of the second connector connected to the second part of the second connector with a second coupler 4d and preferably a fourth edge of the third part of the second connector is connected to the second contact. Preferably the first surface is made of a third part of the first connector connected with a first coupler to the second part of the first connector. The third part of the first connector and the third part of the second connector are adjacent and parallel to each other, and preferably a third edge of the third part of the first connector is connected to the first contact.

[0014] Preferably the third part of the first connector and the third part of the second connector are perpendicular to the first contact and the second contact.

[0015] Preferably the third part of the second connector is parallel to the first contact and one side of the third part of the second connector is adjacent to the first contact.

[0016] Preferably the first part of the first connector and the second part of the first connector forms a single edge, namely a fifth edge, and / or one the first part of the second connector and the second part of the second connector forms a single edge, namely a sixth edge, preferably the fifth edge is the farthest away from the second connector and the sixth edge is the farthest away from the first connector.

[0017] According to a second example of the disclosure, a leadframe suitable for a manufacturing process of the semiconductor device is disclosed. The leadframe comprising a frame with a plurality of connectors where a first connector comprises a first part and a second part, and a second connector comprises a first part and a second part. The second part of the first connector and the second connector is wider than the first part of the first connector and the second connector.

[0018] Preferably the first part of the first connector and the second part of the first connector forms a single edge, namely a fifth edge, and / or one the first part of the second connector and the second part of the second connector forms a single edge, namely a sixth edge, preferably the fifth edge is the farthest away from the second connector and the sixth edge is the farthest away from the first connector.

[0019] Preferably the second connector comprises a third part which is connected by means of a second coupler to the second part of the second connector. The second coupler is adjacent to the first connector.

[0020] Preferably the first connector comprises a third part which is connected by means of a first coupler to the second part of the first connector. The first coupler is adjacent to the second connector.

[0021] Preferably the third part of the second connector is wider than the second part of the second connector.

[0022] Preferably the first part of the first connector and the second part of the first connector forms a single edge, namely a fifth edge, and / or one the first part of the second connector and the second part of the second connector forms a single edge, namely a sixth edge, preferably the fifth edge is the farthest away from the second connector and the sixth edge is the farthest away from the first connector.

[0023] BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The disclosure will now be discussed with reference to the drawings, in which:

[0025] Figure 1 shows a semiconductor device known in the prior art,

[0026] Figure 2 shows a semiconductor device according to the invention,

[0027] Figure 3 shows a semiconductor device with improved electrical parameters,

[0028] Figure 4 shows yet another semiconductor device with improved electrical parameters,

[0029] Figure 5 shows a sideview of the semiconductor device shown in Figure 4,

[0030] Figure 6-9 show leadframes used for manufacturing semiconductor devices shown in Figures 1-5.

[0031] DETAILED DESCRIPTION OF THE DISCLOSURE

[0032] For a proper understanding of the disclosure, in the detailed description below corresponding elements or parts of the disclosure will be denoted with identical reference numerals in the drawings.

[0033] Throughout this disclosure it should be noted that an encapsulation is not shown for the sake of clarity of the internal structure of the semiconductor device. The person skilled in the art will know that the final product must have encapsulation.

[0034] Figure 1 shows a semiconductor device with a known structure as an aid for comparison with the invention embodiments. In this case both first connector 3 and second connector 4 comprises a first part 3a, 4a with the same width as a second part 4b, 4c - the width of both connector 3 and 4 is the same inside and outside the encapsulated region. For simplicity therefore, consider the vertical portion hereinafter, namely second parts 3b, 4b, of the connectors 3, 4 to be fully within the encapsulation and the horizontal free end, namely the first parts 3a, 4a, of the connectors 3, 4 to be outside the encapsulation. The power loop inductance of the conventionally designed structure from DC+ to DC- through the high-side and low-side switches was simulated and found to be 11.1nH.

[0035] Figure 2 shows a first embodiment of the invention where connectors 3, 4 which do not have uniform width inside and outside encapsulation. In this example the semiconductor device comprising at least one semiconductor die, at least two contacts, made of a conductive material, electrically coupled with the at least one semiconductor die where a first contact 1 is adjacent to a second contact 2, and at least two connectors where a first connector 3 comprises a first part 3a and a second part 3b, and a second connector 4 comprises a first part 4a and a second part 4b. The second parts 3b, 4b of the first connector 3 and the second connector 4 are wider than the first parts 3a, 4a of the first connector 3 and the second connector 4. The semiconductor device further comprises a dielectric encapsulation which encapsulates the at least one semiconductor die, the plurality of contacts, and the plurality of connectors such that at most the first part 3a of the first connector 3 and the first part 4a of the second connector 4 are encapsulated partially and are extending from the dielectric encapsulation. The first contact 1 is connected to a first edge 6 of the second part 3b of the first connector 3, and the second contact 2 is connected to the second connector 4 with a second edge 7 of the second part 4b.

[0036] It should be noted that, when discussing connections of edges, it is a bended piece of the first connector 3 or the second connector 4, which acts as the edge. This is done to provide surface sufficient to attached the first connector 3 or the second connector 4 to other element. This is a standard procedure and it is mentioned here in order to clarify what the term “edge” mean in this application.

[0037] It is to be understood that the semiconductor die is important to the overall working performance of the semiconductor device, however the present invention relates to the connectors 3, 4. Due to this fact the semiconductor die and detailed connections to the contacts, in particular the first contact 1 and / or the second contact 2 are not further discussed since this is a typical knowledge of the person skilled in the art.

[0038] In the preferred embodiment the spacing between them is closed to a distance similar to that of the spacing between substrate copper traces since this provides the best results - the second part 3b of the first connector 3, and the second part 4b of the second connector 4 are separated essentially with the same distance from each other as the first contact 1 and the second contact 2.

[0039] In the first embodiment the power loop inductance is reduced by 14% to 9.6nH. Following the prior art documents would not lead to this solution since structures with such tight spacing are typically easier to form from two or more components. Creating such structures from a single leadframe requires co-design of leadframe and substrate layout, which requires careful consideration, since it is an additional complicating factor.

[0040] To further improve the performance of the semiconductor the first connector 3 and / or the first contact 1 further comprises a first surface capacitively coupled with a second surface of the second connector 4. In a preferred embodiment the second surface is made of a third part 4c of the second connector 4 connected to the second part 4b of the second connector 4 with a second coupler 4d and preferably a fourth edge 9 of the third part 4c of the second connector 4 is connected to the second contact 2. Example of this can be seen in figures 3 and 4.

[0041] It should be noted that that both the first coupler 3d and the second coupler 4d are not shown in figures 3 and 4 to improve clarity. The first coupler 3d and the second coupler 4d are presented in figures 8 and 9 where those are clearly visible. Since the person skilled in the art will know how the leadframe is used it should be clear that after the bending of the first connector 3 and the second connector 4, as shown in the figures 8 and 9, the person skilled in the art will get structures the same as on figures 3 and 4.

[0042] Figure 3 shows one of the possible improvements of the semiconductor device as shown in figure 2. In this embodiment the first surface is made of a third part 3c of the first connector 3 connected with the first coupler 3d to the second part 3b of the first connector 3. The third part 3c of the first connector 3 and the third part 4c of the second connector 4 are adjacent and parallel to each other, and preferably a third edge 8 of the third part 4b of the first connector 4 is connected to the first contact 2. Preferably the third part 3c of the first connector 3 and the third part 4c of the second connector 4 are perpendicular to the first contact 1 and the second contact 2.

[0043] The connectors 3, 4 are extended further in this embodiment into the module and are forming these extensions, namely the third parts 4c, 4d, into two upright structures with close spacing. The power loop inductance is reduced further to 9.4nH. The additional reduction is dependent on the spacing. The example diagram shows a relatively wide spacing, but if a smaller spacing can be used, further reduction is possible.

[0044] Figure 4 shows another improvement of the invention shown in figure 2. In this embodiment the third part 4c of the second connector 4 is parallel to the first contact 1 and one side of the third part 4c of the second connector 4 is adjacent to the first contact 3. In this embodiment the connectors 3, 4 structures extend into the module and form the extension, namely the third part 4c, of the DC+ terminal into a plane that overlaps the DC- substrate pad, namely the first contact 1. The power loop inductance is reduced further to 9.3nH. The additional reduction is dependent on the spacing. As is it visible in figure 5 a relatively wide spacing between the first contact 1 and the third part 4c of the second connector 4 is shown, but if a smaller spacing can be used in particular solution, further reduction is possible. The person skilled in the art will know what are both limits of the manufacturing process as well as minimal spacing required due to electrical properties of the semiconductor device.

[0045] Figure 6 shows a leadframe used for the manufacturing of the semiconductor device, know in the prior art, as shown in figure 1.

[0046] Figure 7 show a leadframe used for the manufacturing of the semiconductor device as shown in figure 2. The leadframe comprises a frame with a plurality of connectors where a first connector 3 comprises a first part 3a and a second part 3b, and a second connector 4 comprises a first part 4a and a second part 4b, wherein the second part 3b, 4b of the first connector 3 and the second connector 4 is wider than the first part 3a, 4a of the first connector 3 and the second connector 4.

[0047] Figure 8 show a leadframe used for the manufacturing of the semiconductor device as shown in figure 3. The leadframe, compared to one in figure 7, where the second connector 4 comprises a third part 4c which is connected by means of a second coupler 4d to the second part 4b of the second connector 4, wherein the second coupler 4d is adjacent to the first connector 3. Additionally, the first connector 3 comprises a third part 3c which is connected by means of a first coupler 3d to the second part 3b of the first connector 3, wherein the first coupler 3d is adjacent to the second connector 4.

[0048] Figure 9 show a leadframe used for the manufacturing of the semiconductor device as shown in figure 4 and 5. The leadframe in this embodiment, compared to one in figure 7, comprises the second connector 4 comprises a third part 4c which is connected by means of a second coupler 4d to the second part 4b of the second connector 4, wherein the second coupler 4d is adjacent to the first connector 3. It should be noted that in this embodiment there is the third part 3c is not present. Preferably the third part 4c of the second connector 4 is wider than the second part 4b of the second connector 4.

[0049] In yet another embodiment of the leadframe the first part 3a of the first connector 3 and the second part 3b of the first connector 3 forms a single edge, namely a fifth edge 10, and / or one the first part 4a of the second connector 4 and the second part 4b of the second connector 4 forms a single edge, namely a sixth edge 11, preferably the fifth edge 10 is the farthest away from the second connector 4 and the sixth edge 11 is the farthest away from the first connector 2.

[0050] It should be noted that that manufacturing of the semiconductor device according to the invention with a use of the leadframes as shown in figures 7-9 will require bending steps. However, since this is known in the prior art, this aspect will not be discussed further.

[0051] The invention can be applied to any suitably designed power module with terminals manufactured from a single lead frame. Co-design of substrate and lead frame is required to maximise the benefit of the invention, so it is most applicable to new module designs.

[0052] However, the invention can assist the incorporation of wide bandgap chips into industry standard packaging developed for silicon power devices. WBG chips typically have smaller area than their silicon counterparts, meaning these standard packages are often oversized for the WBG chips, creating additional area that can be used as shown in this disclosure.

[0053] The invention offers a benefit to all applications using such a module, since parasitic inductance increases system losses in any hard-switching application.

[0054] LIST OF REFERENCE NUMERALS USED

[0055] 1 first contact

[0056] 2 second contact

[0057] 3 first connector

[0058] 3a first part of the first connector

[0059] 3b second part of the first connector

[0060] 3c third part of the first connector

[0061] 3d first coupler

[0062] 4 second connector

[0063] 4a first part of the second connector 4b second part of the second connector

[0064] 4c third part of the second connector

[0065] 4d second coupler

[0066] 5 leadframe 6 first edge

[0067] 7 second edge

[0068] 8 third edge

[0069] 9 fourth edge

[0070] 10 fifth edge 11 sixth edge

Claims

CLAIMS1. A semiconductor device comprising: at least one semiconductor die, at least two contacts, made of a conductive material, electrically coupled with the at least one semiconductor die where a first contact (1) is adjacent to a second contact (2), and at least two connectors where a first connector (3) comprises a first part (3a) and a second part (3b), and a second connector (4) comprises a first part (4a) and a second part (4b), wherein the second parts (3b, 4b) of the first connector (3) and the second connector (4) are wider than the first parts (3a, 4a) of the first connector (3) and the second connector (4), a dielectric encapsulation which encapsulates the at least one semiconductor die, the plurality of contacts, and the plurality of connectors such that at most the first part (3a) of the first connector (3) and the first part (4a) of the second connector (4) are encapsulated partially and are extending from the dielectric encapsulation, wherein, the first contact (1) is connected to a first edge (6) of the second part (3b) of the first connector (3), and the second contact (2) is connected to the second connector (4) with a second edge (7) of the second part (4b).

2. The semiconductor device according to claim 1, wherein the second part (3b) of the first connector (3), and the second part (4b) of the second connector (4) are separated with the same distance from each other as the first contact (1) and the second contact (2).

3. The semiconductor device according to claim 1 or 2, wherein the first connector (3) and / or the first contact (1) further comprises a first surface capacitively coupled with a second surface of the second connector (4).

4. The semiconductor device according to claim 3, wherein the second surface is made of a third part (4c) of the second connector (4) connected to the second part (4b) of the second connector (4) with a second coupler (4d) and preferably a fourth edge (9) of the third part (4c) of the second connector (4) is connected to the second contact (2).

5. The semiconductor device according to claim 4, wherein the first surface is made of a third part (3c) of the first connector (3) connected with a first coupler (3d) to the second part (3b) of the first connector (3), and wherein the third part (3c) of thefirst connector (3) and the third part (4c) of the second connector (4) are adjacent and parallel to each other, and preferably a third edge (8) of the third part (4b) of the first connector (4) is connected to the first contact (2).

6. The semiconductor device according to claim 5, wherein the third part (3c) of the first connector (3) and the third part (4c) of the second connector (4) are perpendicular to the first contact (1) and the second contact (2).

7. The semiconductor device according to claim 4, wherein the third part (4c) of the second connector (4) is parallel to the first contact (1) and one side of the third part (4c) of the second connector (4) is adjacent to the first contact (3).

8. The semiconductor device according to anyone of previous claims, wherein the first part (3a) of the first connector (3) and the second part (3b) of the first connector (3) forms a single edge, namely a fifth edge (10), and / or one the first part (4a) of the second connector (4) and the second part (4b) of the second connector (4) forms a single edge, namely a sixth edge (11), preferably the fifth edge (10) is the farthest away from the second connector (4) and the sixth edge (11) is the farthest away from the first connector (2).

9. A leadframe suitable for a manufacturing process of the semiconductor device as described in claims 1-9, comprising: a frame with a plurality of connectors where a first connector (3) comprises a first part (3a) and a second part (3b), and a second connector (4) comprises a first part (4a) and a second part (4b), wherein the second part (3b, 4b) of the first connector (3) and the second connector (4) is wider than the first part (3a, 4a) of the first connector (3) and the second connector (4).

10. The leadframe according to claim 10, wherein the first part (3a) of the first connector (3) and the second part (3b) of the first connector (3) forms a single edge, namely a fifth edge (10), and / or one the first part (4a) of the second connector (4) and the second part (4b) of the second connector (4) forms a single edge, namely a sixth edge (11), preferably the fifth edge (10) is the farthest away from the second connector (4) and the sixth edge (11) is the farthest away from the first connector (2).

11. The leadframe according to claim 10 or 11, wherein the second connector (4) comprises a third part (4c) which is connected by means of a second coupler (4d) to the second part (4b) of the second connector (4), wherein the second coupler (4d) is adjacent to the first connector (3).

12. The leadframe according to claim 11 , wherein the first connector (3) comprises a third part (3c) which is connected by means of a first coupler (3d) to the second part (3b) of the first connector (3), wherein the first coupler (3d) is adjacent to the second connector (4).

13. The leadframe according to claim 11 , wherein the third part (4c) of the second connector (4) is wider than the second part (4b) of the second connector (4).

14. The leadframe according to anyone of claims 9-13, wherein the first part (3a) of the first connector (3) and the second part (3b) of the first connector (3) forms a single edge, namely a fifth edge (10), and / or one the first part (4a) of the second connector (4) and the second part (4b) of the second connector (4) forms a single edge, namely a sixth edge (11), preferably the fifth edge (10) is the farthest away from the second connector (4) and the sixth edge (11) is the farthest away from the first connector (2).

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