A semiconductor device
The semiconductor device with p-type shielding regions and optimized trench configurations addresses elevated electric fields in SiC MOSFETs, enhancing gate oxide protection and maintaining low resistance for high-voltage operation.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- NEXPERIA BV
- Filing Date
- 2025-12-12
- Publication Date
- 2026-06-18
AI Technical Summary
Existing silicon carbide (SiC) MOSFETs face issues with elevated electric fields at the gate oxide, leading to potential deterioration or destruction due to high potential differences between the gate and drain terminals, especially when imperfections are present in the oxide or interface material.
A semiconductor device with a shielding structure comprising p-type shielding regions at the bottom of trenches and varying trench configurations to reduce electric fields near the gate oxide, including isolating layers with specific thickness distributions and electrical connections to maintain device performance.
The proposed design effectively reduces electric fields at the gate oxide, minimizing deterioration while maintaining low on-state resistance and ensuring proper device operation at high voltages.
Smart Images
Figure EP2025086901_18062026_PF_FP_ABST
Abstract
Description
[0001] TITLE
[0002] A semiconductor device.
[0003] TECHNICAL FIELD
[0004] The present disclosure relates to a semiconductor device more precisely to a SiC Trench MOSFETs having shielding structures to control the electric fields in the cell structure, especially in gate oxide.
[0005] BACKGROUND OF THE DISCLOSURE
[0006] Accordingly, it is a goal of the present disclosure to provide an improved transistors in particularly SiC MOSFET with a gate oxide, such as the metal-oxide- semiconductor field-effect transistor (MOSFET) to face the issue of elevated electric fields at the oxide. Based on silicon carbide, the commonly used power MOSFET is N-channel MOSFET with n-type drift layer. Under normal operating conditions a high potential difference is created between the gate and drain terminal, resulting in a much higher electric field compared to Si devices. If the electric field at the gate interface is too large, a deterioration or destruction of the oxide layer can occur, especially if imperfections in the oxide or interface material are present.
[0007] In document US10784349 B2 a MOSFET cell structure with gate trench protected by the shielding region in two neighboring source trenches is disclosed.
[0008] In document US20230197712A1 a shielding structures set in a relative wide region where two trenches are created and contribute two conducting channels is disclosed. Between two such regions, one trench is created that can be protected by the wide regions.
[0009] In document US10217858B2 a cell structure with the gate trench protected by the trench-bottom shielding structure and the deeply implanted shielding structure between two trenches is disclosed.
[0010] SUMMARY OF THE DISCLOSURE
[0011] According to the first example of the disclosure, a semiconductor device has a top surface and a bottom surface opposite to the top surface. The semiconductor device comprises a first layer having a first conductivity type located at the top surface and a second layer having a second conductivity type located under the first layer. The semiconductor device further comprises a drift layer under the second layer which further extends to the bottom surface and a conductive element having a third conductivity type. In the semiconductor device according to the first example of the disclosure there is at least one pair of first trenches, wherein each first trench extends from the top surface through the first layer further through the second layer and partially into the drift layer, each of the trenches comprises an isolating layer and a conductive element having a third conductivity type, wherein the isolating layer is arranged between the conductive element and the first layer and the second layer . The semiconductor device according to the first example of the disclosure further comprise one second trench that extends from the top surface through the first layer further through the second layer and partially into the drift layer, each of the trenches comprises an isolating layer and a conductive element having a third conductivity type, wherein the isolating layer is arranged between the conductive element and the first layer and the second layer wherein second trench is located between the first trenches . The semiconductor device according to the first example of the disclosure also comprises a shielding region located under the first trenches at the bottom of the first trenches, wherein the shielding region extends partially into the drift layer from the bottom of the first trenches towards the bottom surface covering at least partially the bottom of the first trenches.
[0012] The semiconductor device, according to the second example of the disclosure has the isolating layer that has substantially uniform thickness on the trench walls and on the trench bottom.
[0013] The semiconductor device, according to the third example of the disclosure has the isolating layer that has substantially smaller thickness on the trench walls and bigger thickness on the trench bottom.
[0014] The semiconductor device, according to another example of the disclosure, has the shielding region that has substantially the same width as the first trench and covers the whole width of the first trench.
[0015] The semiconductor device, according to another example of the disclosure further comprising at least one additional shielding trench in the form of a trench located between the first trench and the second trench extending from the top surface through the first layer and partially into the second layer.
[0016] The semiconductor device, according to another example of the disclosure have the first trench that extends deeper into the drift layer than the second trench.
[0017] The semiconductor device, according to another example of the disclosure has, between the drift layer and the second layer, an additional current spreading layer which extends to the at least shielding region.
[0018] The semiconductor device, according to another example of the disclosure, has at least one first trench that is wider than the second trench.
[0019] The semiconductor device, according to another example of the disclosure, has the first trenches and the second trenches that are electrically interconnected using an additional runner layer located on the top surface.
[0020] The semiconductor device, according to another example of the disclosure have, under the drift layer, a substrate layer.
[0021] The semiconductor device, according to another example of the disclosure, has the shielding region that is electrically connected with a surface contact in the semiconductor device layout.
[0022] The semiconductor device, according to another example of the disclosure have the shielding region and shielding trench that are electrically connected with a surface contact in the semiconductor device layout.
[0023] Disclosure also relates to an example of a MOSFET device configured to operate at high voltages made from silicon carbide having a N-channel MOSFET with an n-type drift layer. In N-channel MOSFET, introducing a p-type shielding region below or near the gate trench region significantly reduces the electric field close to the gate oxide. In device structure, different ways can be designed to lay out the shielding. In different designs, the shielding structure can provide direct or indirect protection to the oxide in gate trenches. Besides, these shielding structures must be properly contacted to not disturb the device switching. The existence of a p-type shielding structure can introduce JFET resistance in the drift layer or deactivate some conducting channels, therefore, degrades the on-state performance.
[0024] The disclosed example provides improvement of reduced overall channel resistance maintaining the required gate oxide shielding effect.
[0025] BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The disclosure will now be discussed with reference to the drawings which show in:
[0027] Figure 1 . A cross section of a semiconductor device according to the disclosure.
[0028] Figure 2. A cross section of a semiconductor device according to the disclosure.
[0029] Figure 3. A cross section of a semiconductor device according to the disclosure.
[0030] Figure 4. A cross section of a semiconductor device according to the disclosure. Figure 5. A cross section of a semiconductor device according to the disclosure.
[0031] Figure 6. A cross section of a semiconductor device according to the disclosure.
[0032] Figure 7. An isometric view of a semiconductor device according to the disclosure. Figure 8. A top view of a semiconductor device according to the disclosure.
[0033] Figure 9. A top view of a semiconductor device according to the disclosure.
[0034] Figure 10. A top view of a semiconductor device according to the disclosure.
[0035] Figure 11. A top view of a semiconductor device according to the disclosure.
[0036] Figure 12. A top view of a semiconductor device according to the disclosure.
[0037] Figure 13. A cross section according to the dashed line from Figure 12 view of a semiconductor device according to the disclosure.
[0038] Figure 14. A top view of a semiconductor device according to the disclosure.
[0039] Figure 15. A cross section according to the dashed line from Figure 14 view of a semiconductor device according to the disclosure.
[0040] Figure 16. A top view of a semiconductor device according to the disclosure.
[0041] Figure 17. A cross section according to the dashed line from Figure 16 view of a semiconductor device according to the disclosure.
[0042] Figure 18. A top view of a semiconductor device according to the disclosure.
[0043] Figure 19. A cross section according to the dashed line from Figure 18 view of a semiconductor device according to the disclosure.
[0044] Figure 20. A top view of a semiconductor device according to the disclosure.
[0045] Figure 21. A Cross section according to the dashed line from Figure 20 view of a semiconductor device according to the disclosure.
[0046] Figure 22. An isometric view of a semiconductor device according to the disclosure.
[0047] Figure 23. An isometric view of a semiconductor device according to the disclosure.
[0048] DETAILED DESCRIPTION OF THE DISCLOSURE
[0049] For a proper understanding of the disclosure, in the detailed description below corresponding elements or parts of the disclosure will be denoted with identical reference numerals in the drawings.
[0050] The disclosed example has two sets of trenches: first trench A and second trench B. First trench A has p-type shielding region 6 at the trench bottom. The semiconductor device, according to the example of the disclosure, have a top surface and a bottom surface opposite to the top surface and comprises a first layer 1 having a first conductivity type (n+) located at the top surface and a second layer 2 having a second conductivity type (p-) located under the first layer 1 and a drift layer 4 having n- conductivity type, under the second layer 2 which further extends to the bottom surface. According to this example the semiconductor device further comprises a conductive element 3 having a third conductivity type (Poli Silicon material, the conductivity type of the first or second layer refers to p-doping and / or n-doping. In some examples of the disclosure the gate electrode 3 can be first or second conductivity type) and at least one pair of first trenches A, wherein each first trench A extends from the top surface through the first layer 1 further through the second layer 2 and partially into the drift layer 4, each of the first and second trenches A, B comprises an isolating layer 5 and a conductive element 3 having a third conductivity type, wherein the isolating layer 5 is arranged between the conductive element 3 and the first layer 1 and the second layer 2. The conductive element 3 is then electrically isolated from the first layer 1 and the second layer 2 (and any other functional layer as they act as gate electrodes in MOS semiconductor device, they may be connected to runners or terminals standard elements of MOS semiconductor device). Furthermore, the semiconductor device comprises at least one second trench B that extends from the top surface through the first layer 1 further through the second layer 2 and partially into the drift layer 4. Each of the trenches B comprises an isolating layer 5 and a conductive element 3 having a third conductivity type, wherein the isolating layer 5 (and drift layer 4) is arranged between the conductive element 3 and the first layer 1 and the second layer 2 wherein second trench B is located between the first trenches A. Under the trenches A there is located a shielding region 6 (at the bottom of the first trenches A), wherein the shielding region 6 extends partially into the drift layer 4 from the bottom of the first trenches A towards the bottom surface covering at least partially the bottom the first trenches A. Complete (covering whole first trench A bottom) (Fig. 1) or partial (covering a part of first trench A bottom) (Fig. 2) p+ shielding region 6 can provide direct protect to the gate oxide-isolating layer 5 in first trench A. While second trench B lies between two first trenches A and is indirectly protected by the shielding region 6, as shown in Fig.1-2. Both first trench A and second trench B participate in the current conduction in the on-state. The trench width / depth can vary between the two trench sets. In the example of the invention, first trench A is wider than second trench B, depending on the second trench B bottom ion-implantation requirements. In another example of the invention the second trench B has narrower width for no ionimplantation. To achieve a good shielding effect, first trench A is deeper than second trench B (Fig. 3). Both trenches A and B are acting as gate electrodes, creating an inversion channel which contributes to current conduction in the semiconductor device. Conversely, the source electrodes are only situated on the top of the n+ region but are not connected to any of the conductive elements 3, as these are gate electrodes.
[0051] In another example of the inventiWon, to further alleviate the electric field in the gate oxide, the second trench B bottom has introduced thicker isolating layer 5 made of oxide (Si oxide) than along the side walls, as shown in Fig.4. The shielding region 6 made of p+ material is connected with the surface p+ contact region in the device layout design (top view). The advantage of the disclosed examples (Fig. 1- 4) is that no conduction channel has been deactivated. The proposed examples greatly reduce the JFET resistance.
[0052] In another example of the disclosure a current spreading layer CSL is added to optimize the current flowing in JFET region. The current spreading layer CSL is located between the drift layer 4 (made of n- material) and the second layer 2. The CSL extends to at least shielding region 6, as seen in Fig 5. In another example of the disclosure the first layer 1 (n+) and the shielding region 6 (p+) and the shielding trench 8 are connected through the metallic layer 10 via ohmic contact 12 (ohmic contact between n+ first conductivity type the first layer 1 and second layer of second conductivity type p+ ) in the mesa region. The metallic layer 10 is isolated form the conductive element 3 (gate) via the oxide layer 11 shown in Fig 6. An isometric view of this example of the semiconductor device is presented in Fig. 7 wherein the p+ layer 13 is exposed on the edges of the semiconductor device having the ohmic contact 12 on top of the p+ layer 13.
[0053] To provide improved protection of the isolating layer 5 (gate oxide) in the second trench B, the semiconductor device pitch (pitch is the spacing between objects without regard to their size in a circuit. The pitch of parallel conducting lines is the distance between them, center to center. The width of the lines can be anything less than the pitch and there will still be space between the lines.) should be minimized. In this case, the room to leave for ohmic contact 12 in the Mesa region can be very limited for processing (Mesa regio is an area on a semiconductor wafer where the semiconductor has not been etched away.). Taking this into consideration, three basic examples of the disclosure can be proposed to solve this problem.
[0054] The first example is a short first trench Array, no continuous trench. In this example of the disclosure, first trench A and second the trench B set both are in the form of array, length in the range 10 - 50pm. The top view of different layers is shown in Fig 8- 11. The length of first trench A and second trench B are not equal, but in another example, they are equal, this is to vary for purpose of good ohmic contact (in general) and device performances. The shielding region 6 is connected to the p+ layer 13 (Fig. 9). In another example on top of the p+ layer 13 an ohmic contact 12 is formed (Fig. 10-12). The first trench A is connected with the second trench B via runner 7 (formed with the same conductivity type material the conductive element 6). The ohmic contact 12 and poly-Si are perpendicular to the trench orientation. To better illustrate the device structure, crosssection views are shown in Figures 13, 15, 17, 19, and 21. The first cross section shown in Fig. 13 is made along the first trench A according to the dashed line shown in Fig. 12. The second cross section shown in Fig. 15 is made along the second trench B according to the dashed line shown in Fig. 14. The third cross section shown in Fig. 17 is made perpendicular to the first trench A on the edge of the semiconductor device, according to line A-A shown in Fig. 16. the dashed line The 4th cross section shown in Fig. 19 is made perpendicular to the first trench A, according to the dashed line shown in Fig. 18. The 5th cross section shown in Fig. 21 is made perpendicular to the first trench A along the runner layer 7, according to the dashed line shown in Fig. 20.
[0055] Second example is a continues (extending to the edge of the semiconductor device) first trench A array and no continuous (not extending to the edge of the semiconductor device) second trench B. This example is shown in the Fig. 22.
[0056] The third example is a continues (extending to the edge of the semiconductor device) second trench B array and no continuous first trench A. This example is shown in the Fig. 23.
[0057] Another example of a semiconductor device formed as trench FET structures adopting the proposed shielding region 6 for reducing the electric field and reduce the on- resistance. Another example of a semiconductor device is a power MOSFETs based on wide bandgap semiconductor material configured to operate at high voltages ( more than 600V) made from silicon carbide having a N-channel MOSFET with n-type drift layer 4.
[0058] LIST OF REFERENCE NUMERALS USED
[0059] I. First layer (1st conductivity type) 2. Second layer (2nd conductivity type)
[0060] 3. Conductive element (3rd conductivity type)
[0061] 4. Drift layer
[0062] 5. Isolating layer
[0063] 6. Shielding region 7. Runner layer
[0064] 8. Shielding trench
[0065] 9. Substrate
[0066] 10. Metal layer
[0067] I I . Oxide layer 12. Ohmic contact
[0068] 13. p+ layer
[0069] A. first trench
[0070] B. second trench
[0071] CSL - Current Spreading Layer
Claims
9CLAIMS1. A semiconductor device, having a top surface and a bottom surface opposite to the top surface comprising: a. a first layer having a first conductivity type located at the top surface; b. a second layer having a second conductivity type located under the first layer; c. a drift layer under the second layer which further extends to the bottom surface; d. a conductive element having a third conductivity type; e. an at least one pair of first trenches acting as gate electrode, wherein each of first trench extends from the top surface through the first layer further through the second layer and partially into the drift layer, each of the trenches comprises an isolating layer and a conductive element having a third conductivity type, wherein the isolating layer is arranged at least between the conductive element and the first layer and the second layer; f. one second trench acting as gate electrode that extends from the top surface through the first layer further through the second layer and partially into the drift layer, each of the trenches comprises an isolating layer and a conductive element having a third conductivity type, wherein the isolating layer is arranged at least between the conductive element and the first layer and the second layer and the drift layer wherein second trench is located between the first trenches; g. a shielding region located under the first trenches at the bottom of the first trenches, wherein the shielding region extends partially into the drift layer from the bottom of the first trenches towards the bottom surface covering at least partially the bottom of the first trenches.
2. The semiconductor device according to claim 1 , wherein the isolating layer has substantially uniform thickness on the trench walls and on the trench bottom.
3. The semiconductor device according to claim 1 , wherein the isolating layer has substantially smaller thickness on the trench walls and bigger thickness on the trench bottom.
4. The semiconductor device according to claim 1 , 2 or 3, wherein the shielding region has substantially the same width as the first trench and covers the whole width of the first trench.
5. The semiconductor device according to claim 1 , 2, 3 or 4 further comprising at least one additional shielding trench located between the first trench and the second trench extending from the top surface through the first layer and partially into the second layer.
6. The semiconductor device, according to any of the claims from 1 to 5 wherein the first trench extends deeper into the drift layer than the second trench.
7. The semiconductor device according any of the claims from 1 to 6 wherein between the drift layer and the second layer there is additional current spreading layer which extends to the at least shielding region.
8. The semiconductor device, according to any of the claims from 1 to 7 wherein the at least one first trench is wider than the second trench.
9. The semiconductor device according to any of the claims from 1 to 8 wherein the first trenches and the second trenches are electrically interconnected using an additional runner layer located on the top surface.
10. The semiconductor device, according to any of the claims from 1 to 9 wherein under the drift layer there is a substrate layer.
11. The semiconductor device according to any of the claims from 1 to 10 wherein the shielding region is electrically connected with a surface contact in the semiconductor device layout.
12. The semiconductor device according to any of the claims from 5 to 10 wherein the shielding region and shielding trench are electrically connected with a surface contact in the semiconductor device layout.
13. The semiconductor device according to any of the claims from 1 to 12 wherein first layer conductivity type is a n+ and second layer conductivity type is a p- and drift layer conductivity type is n- and shielding region conductivity type is p+.
14. A MOSFET device according to any of claims from 1 to 13 configured to operate at voltages higher than 600 V made from silicon carbide having a N-channel MOSFET with an n-type drift layer.