Method of manufacturing a current spreading layer as well as a semiconductor device
By forming trench and protrusion sections and using plug materials like amorphous silicon or tungsten, the method improves the implantation profile of current spreading layers in semiconductor devices, addressing inefficiencies in existing methods and enhancing device performance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- NEXPERIA BV
- Filing Date
- 2025-12-12
- Publication Date
- 2026-06-18
AI Technical Summary
Existing methods for manufacturing current spreading layers in semiconductor devices are inefficient as they lack the ability to separately adjust the implantation profile depth under the p-well and into the p+ shielding region, leading to suboptimal trade-offs between on-state resistance and electrical field shielding.
A method involving the formation of trench sections and protrusion areas in semiconductor devices, followed by ion implantation and deposition of plug materials like amorphous silicon, polysilicon, or tungsten, to create a current spreading layer that extends into specific areas, allowing for improved control over the implantation profile.
This approach enhances the manufacturing process by optimizing the current spreading layer's distribution, resulting in better performance and reduced manufacturing complexity, particularly for small semiconductor devices.
Smart Images
Figure EP2025086937_18062026_PF_FP_ABST
Abstract
Description
[0001] TITLE
[0002] Method of manufacturing a Current Spreading Layer as well as a semiconductor device.
[0003] TECHNICAL FIELD
[0004] The present disclosure relates to the field of manufacturing an adjusted current spreading layer topology in the semiconductor device as well as a semiconductor device.
[0005] BACKGROUND OF THE DISCLOSURE
[0006] The disclosure is related to a method of manufacturing an adjusted current spreading layer topology in the semiconductor device. The present disclosure provides a current spreading layer that improves trade-off between the on-state resistance and shielding of the electrical field in the oxide.
[0007] In the known solutions, the current spreading layer implantation profile depth is only adjustable through masking or implantation of doses and energies. In the state of the art the implantation of current spreading layer under p-well and into p+ shielding region cannot be separated.
[0008] The known solutions are not efficient, therefore the present disclosure is proposed to improve the process of manufacturing an adjusted current spreading layer in the semiconductor device.
[0009] SUMMARY OF THE DISCLOSURE
[0010] A first example of the disclosure is a method of manufacturing a Current Spreading Layer, CSL. The method of manufacturing comprises forming of a first trench section and a second trench sections in a semiconductor such that after this step the semiconductor comprises a base section which has a first side and a second side. Next, the method comprises two protrusion sections extending in the same direction from the second side of the base section in protrusion areas, wherein the two protrusion sections are separated with a first trench section in a first trench area. The two second trench sections are located in second trench areas, wherein each one of the two second trench sections are adjacent to one of the two protrusion sections. The plug material is being deposited in the first trench section between the protrusion sections and in the second trench sections. The CSL is created by implantation of ions, such that the CSL is located at least in the protrusion areas and extends substantially to the first trench section and the second trench section. The plug material is removed from the first trench section and the second trench sections.
[0011] Preferably, the plug material is made of amorphous silicon, polysilicon or tungsten.
[0012] Preferably, the CSL is located in a first trench area and / or a second trench area and is adjacent to the first trench section and / or the second trench section respectively.
[0013] A semiconductor device, according to the method of manufacturing a current spreading layer, comprises a base section, two protrusion sections and two second trench sections. The base section has a first side and a second side. The two protrusion sections extend in the same direction from the second side of the base section to protrusion areas, wherein the two protrusion sections are separated with a first trench section in a first trench area. The two second trench sections are located in second trench areas, wherein each one of the two second trench sections are adjacent to one of the two protrusion sections.
[0014] The base section comprises a substrate layer and an epitaxy layer. The substrate layer has a first side and a second side. The epitaxy layer has a first side and a second side, and the first side of the epitaxy layer is in contact with the second side of the substrate layer.
[0015] Each of the protrusion sections comprise the epitaxial layer, a n+ region and a p-well region. The n+ region has a first side and a second side, wherein the n+ region is located in a part of the protrusion section which is the farthest away from the base section. The p-well region has a first side and a second side, wherein the second side of the p-well region is in contact with the first side of the n+ region.
[0016] The semiconductor device further comprises a Current Spreading Layer, CSL, manufactured as disclosed in the method of manufacturing a current spreading layer. The CSL has a first side and a second side, and the CSL is located at least in the protrusion areas where it extends substantially to the first trench section and the second trench section. Either the second side of the second section of the CSL is in contact with the first side of the p-well region and the first side of the second section of the CSL is in contact with the second side of the epitaxial layer or the first side of the p-well region is in contact with the second side of the epitaxial layer and the second section of the CSL is surrounded by the epitaxial layer and preferably the second section of the CSL is extending towards the substrate layer or the p-well region.
[0017] Preferably, the second side of the CSL is located in the first trench area and / or the second trench area and is adjacent to the first trench section and / or the second trench section respectively.
[0018] Preferably, the semiconductor device comprises two p+ regions with a first side and a second side wherein each of the p+ regions is L-shaped and is surrounding the second trench section such that it first side is in contact with the n+ region, the p-well region, the SCL and epitaxy layer.
[0019] Preferably, the substrate layer and / or epitaxy layer is made of H-SiC.
[0020] Preferably, the semiconductor device further comprises a Gate Oxide, GOX, an Inter Layer Dielectric, ILD, and a polysilicon, PolySi. The Gate Oxide is located in the first trench, and it is adjacent to the base section and two protrusion sections. The Inter Layer Dielectric is adjacent to the parts which are the furthest away from the base section of the two protrusion sections such that the ILD extends away from base section. The PolySi is located between the GOX and ILD.
[0021] Preferably, the semiconductor device further comprises a power metallization encapsulating the ILD, the two protrusion sections and the base section in the second trench section.
[0022] Preferably, the semiconductor device further comprises a polyimide passivation that is in contact with the power metallization, and the polyimide passivation is extending away from the base section.
[0023] Preferably, the semiconductor device further comprises a backside metallization is in contact with the substrate layer and is extending away from the base section.
[0024] BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The disclosure will now be discussed with reference to the figures which show in:
[0026] Figure 1 a cross-section of a standard semiconductor device structure, Figure 2 a cross-section of a new semiconductor device structure with a
[0027] CSL, Figure 3 a cross-section of a new semiconductor device during the step of creating a CSL with the low stopping power plug material,
[0028] Figure 4 a simulation for amorphous silicon as a plug material,
[0029] Figure 5 a cross-section of a new semiconductor device in the step of creating a CSL with the high stopping power plug material,
[0030] Figure 6 a cross-section of a final structure of a new semiconductor device,
[0031] Figure 7 a graph of a doping profile from typical CSL implantation,
[0032] Figure 8 a graph of doping profiles with high stopping power plug material,
[0033] Figure 9 a graph of a box doping profiles with low stopping power plug material,
[0034] Figure 10 a graph of doping profiles with low stopping power plug material,
[0035] Figure 11 a graph of doping profiles with low stopping power plug material,
[0036] Figure 12 a graph of a box doping profiles with low stopping power plug material,
[0037] Figure 13 a comparison between the plug materials.
[0038] DETAILED DESCRIPTION OF THE DISCLOSURE
[0039] For a proper understanding of the disclosure, in the detailed description below corresponding elements or parts of the disclosure will be denoted with identical reference numerals in the drawings.
[0040] Fig. 1 shows a semiconductor device known in prior art. The base section 16 comprises a substrate layer 1 and an epitaxy layer 2, as well as a backside metallization 11 . The substrate layer 1 has a first side and a second side. The epitaxy layer 2 has a first side and a second side, and the first side of the epitaxy layer 2 is in contact with the second side of the substrate layer 1.
[0041] Each protrusion sections 17 comprise the epitaxial layer 2, a n+ region 3 and a p-well region 4. The n+ region 3 has a first side and a second side, wherein the n+ region 3 is located in a part of the protrusion section 17 which is the farthest away from the base section 16. The p-well region 4 has a first side and a second side, wherein the second side of the p-well region 4 is in contact with the first side of the n+ region 3.
[0042] The semiconductor device further comprises a Current Spreading Layer, CSL, 6 which is present in the CSL area 6a. In the prior art an ion implementation is done first and after that trenches are made in which a gate oxide 7 and a plug material 8 are placed. After that an Inter Layer Dielectric, ILD, 9 is provided and a power metallization 10. Finally, a polyimide passivation 12 is provided. The semiconductor device further comprises two p+ regions 5 with a first side and a second side wherein each of the p+ regions 5 is L-shaped and is surrounding the second trench section 19 such that it first side is in contact with the n+ region 3, the p-well region 4, the CSL 6 and the epitaxy layer 2.
[0043] In the prior art the CSL 6 is provided in the CSL area 6a, where an ion doping distribution is such that, regardless of position, an ion concentration in the CSL 6 is getting lower while getting closer to the substrate layer 1.
[0044] In fig. 2 the semiconductor device according to the disclosure is presented. The main difference with respect to the semiconductor device from fig. 1 is that the CSL 6 is present essentially in a protrusion area 17a. It is however possible to manufacture the semiconductor device according to the disclosure where the CSL 6 is present in the additional areas - such a case will be shown in the next examples. In this example, the semiconductor device further comprises a Gate Oxide, GOX 7, an Inter Layer Dielectric, ILD, 9 and a polysilicon, PolySi, 20. The Gate Oxide 7 is located in the first trench 18 and it is adjacent to the base section 16 and two protrusion sections 17. The Inter Layer Dielectric 9 is adjacent to the parts which are the furthest away from the base section 16 of the two protrusion sections 17 such that the ILD 9 extends away from base section 16. The PolySi 20 is located between the GOX 7 and ILD 9.
[0045] In this disclosure, the substrate layer 1 and / or epitaxy layer 2 layer is made of 4H-SiC. It should be, however, noted that other materials are also possible and the person skilled in the art will know what material to use.
[0046] Fig. 3 shows essential steps of manufacturing the CSL 6 according to the disclosure. After forming of a first trench section 18 and second trench sections 19 in a semiconductor such that after this step the semiconductor comprises a base section 16 which has a first side and a second side. The semiconductor device comprises two protrusion sections 17 extending in the same direction from the second side of the base section 16 in protrusion areas 17a, wherein the two protrusion sections 17 are separated with a first trench section 18 in a first trench area 18a. The two second trench sections 19 are located in second trench areas 19a, wherein each one of the two second trench sections 19 are adjacent to one of the two protrusion sections 17. It should be noted that method of forming the first trench section 18 and the second trench sections 19 are not discussed in this disclosure since this is done by means of standard techniques known to the person skilled in the art.
[0047] Next, in step a, the plug material 8 is being deposited in the first trench section 18 between the protrusion sections 17 and in the second trench sections 19. In the first example, the plug material 8 is made of amorphous silicon. In another example, the plug material 8 is made of polysilicon or another low stopping power material. In yet another example, the plug material 8 is made of tungsten or another high stopping power material.
[0048] In step b, the CSL 6 is created by implantation of ions, such that the CSL 6 is located at least in the protrusion areas 17a and extends substantially to the first trench section 18 and the second trench section 19. In this solution, the CSL 6 is located in a first trench area 18a and / or a second trench area 19a and is adjacent the first trench section 18 and / or the second trench section 19 respectively.
[0049] In step c, the plug material 8 is removed from the first trench section 18 and the second trench sections 19. It should be noted that plug material 8 in a final semiconductor device is placed after the first one is removed after the ion implantation - the purpose of the plug material 8 prior to the step c is to block ions, and after step c the plug material 8 becomes a gate electrode material.
[0050] It should be noted that the shape of the CSL 6 will depend on an energy, dose and element of the implantation of the implantation and material used in the plug material 8. In fig. 4 a simulation results are shown where a material for the plug material 8, with low stopping power, allows for the ions to travel deeper into the epitaxy layer 2 than in the protrusion regions 17 and let some ions pass through it.
[0051] It results in a CSL 6 in a form of a wave with high concentrations of ions shown in area designated as 6. It should be noted that transition between each high- density area is essentially a step change. There are two levels of the CSL 6 - first one, closer to the ion source, located in the protrusion sections 17, and second one, which is located deeper into the semiconductor in the areas below the second trench sections 18 and the plug material 8.
[0052] The semiconductor device further comprises a Current Spreading Layer, CSL, 6 manufactured as disclosed in the method of manufacturing a current spreading layer. The CSL 6 has a first side and a second side, and the CSL 6 is located at least in the protrusion areas 17a where it extends substantially to the first trench section 18 and the second trench section 19. Either the second side of the second section 20 of the CSL 6 is in contact with the first side of the p-well region 4 and the first side of the second section 20 of the CSL 6 is in contact with the second side of the epitaxial layer 2 or the first side of the p-well region 4 is in contact with the second side of the epitaxial layer 2 and the second section of the CSL 6 is surrounded by the epitaxial layer 2 and preferably the second section of the CSL 6 is extending towards the substrate layer 1 or the p-well region 4. In this example, the CSL 6 is extending toward the first trench area 18a and / or the second trench area 19a such that the second side of the CSL 6 is located in the first trench area 18a and / or the second trench area 19a and is adjacent the first trench section 18 and / or the second trench section 19 respectively.
[0053] Another example of the disclosure is presented in fig. 5. In this example the same steps are performed as in fig. 3, however the plug material 8 is made of a different material which slows down ions more than a semiconductor in the protrusion sections 17. This may result in different ways - in a first one, as shown in fig. 2, the CSL will be present only in the protrusion area 17a after removal of the plug material 8 since no ions will pass through the plug material 8. In other case the ions will pass through the plug material 8, however the ions in the protrusion areas 17a will go deeper which will also result in the form of the wave where level depths will be reversed - the first level of the wave will be buried deeper in the semiconductor, while the second of the wave level will be closer to the ion source.
[0054] In fig. 6 the semiconductor device is shown in which the CSL 6 differs from the one in fig. 2 in that the CSL 6 is also present in the first trench area 18a and the second trench area 19a.
[0055] Figs. 7-12 show the differences of doping profiles while using different plug materials.
[0056] Fig. 7 shows doping for trench-last Trench MOS technology for, that is p+ doping profile 23, p-well doping profile 25 and CSL doping profile 24.
[0057] Fig. 8 shows doping for plug material with high stopping power, that is a p+ doping profile 23, a p-well doping profile 25 and a single-implant CSL-regions, that is a CSL in MESA doping profile 26 and a CSL in trench doping profile 27, where the CSL in MESA doping profile 26 is depicting the depth of the CSL 6 under the first trench area 18a and the second trench area 19a, and the CSL in trench doping profile 27 is depicting the CSL 6 in the protrusion area 17a. Fig. 9 shows doping for plug material with high stopping power, that is the p+ doping profile 23, the p-well doping profile 25 and a multi-implant CSL-regions, that is the CSL in MESA doping profile 26 and the CSL in trench doping profile 27, where the CSL in MESA doping profile 26 is depicting the depth of the CSL 6 under the first trench area 18a and the second trench area 19a and the CSL in trench doping profile 27 is depicting the CSL 6 in the protrusion area 17a.
[0058] Fig. 10 shows doping for plug material with high stopping power, that is the p+ doping profile 23, the p-well doping profile 25 and the single-implant CSL- regions, that is the CSL in MESA doping profile 26 and the CSL in trench doping profile 27, where the CSL in MESA doping profile 26 is depicting the depth of the CSL 6 under the first trench area 18a and the second trench area 19a and the CSL in trench doping profile 27 is depicting the CSL 6 in the protrusion area 17a. Fig. 10 is similar to Fig. 8 but depicts the effect of using a material with even higher stopping power than for the distribution in Fig. 8.
[0059] Fig. 11 shows doping for plug material with low stopping power, that is the p+ doping profile 23, the p-well doping profile 25 and the single-implant CSL- regions, that is the CSL in MESA doping profile 26 and the CSL in trench doping profile 27, where the CSL in MESA doping profile 26 is depicting the depth of the CSL 6 under the first trench area 18a and the second trench area 19a and the CSL in trench doping profile 27 is depicting the CSL 6 in the protrusion area 17a.
[0060] Fig. 12 shows doping for plug material with low stopping power, that is the p+ doping profile 23, the p-well doping profile 25 and the multi-implant CSL- regions, that is the CSL in MESA doping profile 26 and the CSL in trench doping profile 27, where the CSL in MESA doping profile 26 is depicting the depth of the CSL 6 under the first trench area 18a and the second trench area 19a and the CSL in trench doping profile 27 is depicting the CSL 6 in the protrusion area 17a.
[0061] Fig. 13 shows comparison between the plug material 8 made of different materials where on x-axis an electric oxide field is represented and on y-axis a figure of merit is shown. The “figure of merit” performance of four different semiconductor devices is shown on the graph: no CSL (circles), a homogeneous CSL as in prior art (triangles), a CSL made with use of a polysilicon plug (squares) and a CSL made with use of a tungsten plug (diamonds). The higher the value, the performance of the semiconductor device is better. From the graph it can be read that the best performance is when using tungsten as a plug material which results in the CSL 6 as in, for example, fig. 2, where the CSL 6 is in the protrusion area 17a only. The second- best performance is when using the solution known from the prior art. The plug material made from the low stopping power material, in this case the polysilicon plug, is third best in terms of performance, but this solution is easier to manufacture than the prior art since no masks are needed later on which may be especially beneficial during manufacturing of a small semiconductor device (in a range of few-few dozen nanometers).
[0062] LIST OF REFERENCE NUMERALS USED
[0063] 1 Substrate layer
[0064] 2 Epitaxy layer
[0065] 3 n+ region
[0066] 4 p-well region
[0067] 5 p+ region
[0068] 6 Current Spreading Layer, CSL
[0069] 6a CSL area
[0070] 7 Gate Oxide, GOX
[0071] 8 plug material
[0072] 9 Inter Layer Dielectric, ILD
[0073] 10 power metallization
[0074] 11 backside metallization
[0075] 12 polyimide passivation
[0076] 16 base section
[0077] 17 protrusion section
[0078] 17a protrusion area
[0079] 18 first trench section
[0080] 18a first trench area
[0081] 19 second trench section
[0082] 19a second trench area
[0083] 20. polysilicon, PolySi
[0084] 23 p+-ohmic doping profile
[0085] 24 CSL doping profile
[0086] 25 p-well doping profile
[0087] 26 CSL in MESA doping profile
[0088] 27 CSL in trench doping profile
Claims
CLAIMS1. A method of manufacturing a Current Spreading Layer (6), CSL, comprising steps of: forming of a first trench section (18) and a second trench sections (19) in a semiconductor such that after this step the semiconductor comprises a base section (16) which has a first side and a second side; two protrusion sections (17) extending in the same direction from the second side of the base section (16) in protrusion areas (17a), wherein the two protrusion sections (17) are separated with a first trench section (18) in a first trench area (18a), two second trench sections (19) located in second trench areas (19a), wherein each one of the two second trench sections (19) are adjacent to one of the two protrusion sections (17); a) depositing of a plug material (8) in the first trench section (18) between the protrusion sections (17) and in the second trench sections (19), b) creating a CSL (6) by implantation of ions, such that the CSL (6) is located at least in the protrusion areas (17a) and extends substantially to the first trench section (18) and the second trench section (19), c) removing the plug material (8) from the first trench section (18) and the second trench sections (19),2. The method of manufacturing according to claim 1 , wherein in step a) there the plug material (8) is made of amorphous silicon, polysilicon or tungsten.
3. The method of manufacturing according to claim 1 or 2, wherein the CSL (6) is located in a first trench area (18a) and / or a second trench area (19a) and is adjacent the first trench section (18) and / or the second trench section (19) respectively.
4. A semiconductor device as manufactured with the method according to any one or more of the claims 1-3, comprising: a base section (16) which has a first side and a second side; two protrusion sections (17) extending in the same direction from the second side of the base section (16) in protrusion areas (17a), wherein the two protrusion sections (17) are separated with a first trench section (18) in a first trench area (18a),two second trench sections (19) located in second trench areas (19a), wherein each one of the two second trench sections (19) are adjacent to one of the two protrusion sections (17); wherein the base section (16) comprising a substrate layer (1) that has a first side and a second side; an epitaxy layer (2), that has a first side and a second side, and the first side of the epitaxy layer (2) is in contact with the second side of the substrate layer (1), wherein each of the protrusion sections (17) comprising the epitaxial layer (2); a n+ region (3) that has a first side and a second side, wherein the n+ region (3) is located in a part of the protrusion section (17) which is the farthest away from the base section (16); a p-well region (4) that has a first side and a second side, wherein the second side of the p-well region (4) is in contact with the first side of the n+ region (3), wherein the semiconductor device further comprising a Current Spreading Layer, CSL, (6) manufactured as disclosed in claims 1-3, wherein the CSL (6) has a first side and a second side, and the CSL (6) is located at least in the protrusion areas (17a) where it extends substantially to the first trench section (18) and the second trench section (19), wherein either the second side of the second section (20) of the CSL (6) is in contact with the first side of the p-well region (4) and the first side of the second section (20) of the CSL (6) is in contact with the second side of the epitaxial layer (2), or the first side of the p-well region (4) is in contact with the second side of the epitaxial layer (2) and the second section of the CSL (6) is surrounded by the epitaxial layer (2) and preferably the second section of the CSL (6) is extending towards the substrate layer (1) or the p-well region (4).
5. The semiconductor device according to claim 4, wherein the second side of the CSL (6) located in the first trench area (18a) and / or the second trench area (19a) is adjacent the first trench section (18) and / or the second trench section (19) respectively.
6. The semiconductor device according to claim 4 or 5, wherein it comprises two p+ regions (5) with a first side and a second side wherein each of thep+ regions (5) is L-shaped and is surrounding the second trench section (19) such that it first side is in contact with the n+ region (3), the p-well region (4), the SCL (6) and epitaxy layer (2).
7. The semiconductor device according to anyone of the claims 4-6, wherein the substrate layer (1) and / or epitaxy layer (2) layer is made of 4H-SiC.
8. The semiconductor device according to anyone of the claims 4-7, wherein it further comprises: a Gate Oxide, GOX (7), that is located in the first trench (18) and it is adjacent to the base section (16) and two protrusion sections (17); an Inter Layer Dielectric, ILD, (9) which is adjacent parts which are the furthest away from the base section (16) of the two protrusion sections (17) such that the ILD (9) extends away from base section (16); a polysilicon, PolySi, (20) which is located between the GOX (7) and ILD (9).
9. The semiconductor device according to claim 8, wherein it further comprises: a power metallization (10) encapsulating the ILD (9), the two protrusion sections (17) and the base section (16) in the second trench section (19)10. The semiconductor device according to claim 9, wherein it further comprises: a polyimide passivation (12) that is in contact with the power metallization (10), and the polyimide passivation (12) is extending away from the base section (16).11 . The semiconductor device according to anyone of claims 5-11 , wherein it further comprises: a backside metallization (11) is in contact with the substrate layer (1) and is extending away from the base section (16).