A semiconductor device comprising sets of trenches and corresponding method and package

Abstract

A semiconductor device comprising: a plurality of source regions; sets of trenches, wherein each of the sets of trenches intersect one of the plurality of source regions; wherein each of the trenches comprises a shield electrode; and wherein the shield electrodes of a set of trenches are electrically and mechanically connected at a contact region located in a central region of a length direction of the set of trenches.

Description

[0001] A semiconductor device comprising sets of trenches and corresponding method and package

[0002] Technical field

[0003] The present disclosure relates to semiconductor devices comprising sets of trenches connected to a bus-bar.

[0004] Background

[0005] Electronic devices may be manufactured in large quantities using wafers made of semiconductor material. These wafers are thin, disc-shaped objects with a significantly larger diameter compared to their height. One of the processes involves creating trenches in the wafer, which are grooves that extend from the front surface of the wafer.

[0006] Trenches serve different functions depending on the type of electronic device being manufactured. Insulating trenches are filled with electrically insulating materials, such as silicon oxide, to separate electronic components like resistors and transistors. Deep trenches partially lined with an oxide layer and subsequently filled with polysilicon constitute key part of a modern trench MOSFET as a way to achieve charge balance (RESURF) in the device.

[0007] However, the trench formation process can cause wafer warping. This occurs when trenches deviate from their intended path due to factors like trench density, wafer size, and differences in the chemical or physical properties of the materials used. Warping creates uneven surfaces, which complicates subsequent manufacturing steps like planarization and the formation of metallization layers. If not addressed, warping can lead to imperfections, reducing the structural integrity and performance of the final electronic devices.

[0008] Summary

[0009] A summary of aspects of certain examples disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects and / or a combination of aspects that may not be set forth.

[0010] In order to prevent warping, the semiconductor device may be divided into four zones. These zones comprise trenches divided over the plurality of zones. The plurality of trenches is characterized in that the trenches in neighboring zones are directed perpendicularly from each other. This prevents warping, because mechanical stress associated with deep trenches liner with oxide and filled with polysilicon, is equally divided within the 2 planes on the wafer (vertical-horizontal).

[0011] Further, the zones require an efficient connection to the gates are source terminals, which may take up space on the wafer.

[0012] According to an aspect of the present disclosure, there is provided a semiconductor device. The semiconductor device may include four rectangularly shaped source regions arranged in a two-by-two orientation in the semiconductor device. The semiconductor device may further include a gate bus-bar separating the four source regions. Each of the source regions may include a set of trenches, wherein the set of trenches of two adjacent source regions are perpendicularly oriented. The gate bus-bar may be located at three sides of each of the four source regions. The gate bus-bar between two adjacent source regions may be one and the same. One outer edge of each of the four source regions may be free of gate bus-bar. The one outer edge free of gate bus-bar of two adjacent source regions may be perpendicularly oriented. The gate bus-bar may be arranged to provide an electrical connection to gates of the sets of trenches of each of the source regions.

[0013] The inventors have found that providing a gate bus-bar located at three sides of each of the four source regions may be beneficial. This is because they have found that by freeing one of the sides of the respective source region, which is a side at the outside perimeter of the source region, valuable space may be saved.

[0014] Saving space on a semiconductor device may be of importance as it enables higher channel density, allowing a reduction to the MOSFET on-resistance (Rdson).

[0015] Therefore, by providing a gate bus-bar at three sides, the space that would otherwise be occupied by the gate bus-bar at the fourth side will be saved.

[0016] The two-by-two orientation will be explained further with reference to the figures. But in words, it represents a configuration of the source regions from a top view of the semiconductor device. Herein there is provided a northwestern source region, a northeastern source region, a southeastern source region and a southwestern source region. As mentioned, these source regions are separated by the gate bus-bar. This gate bus-bar may therefore comprise a plus / cross shape which separates the regions.

[0017] The set of trenches of two adjacent source regions may be perpendicularly oriented, because this solves the aforementioned problem of warping, which may be important as warpage may cause degradation of the performance of the device.

[0018] In an example of the disclosure, the four rectangularly shaped source regions are connected to an outer shield electrode provided around the four rectangularly shaped source regions.

[0019] Each of the, e.g., four, source top metal segments in this design may serve three purposes: (1) transfers source potential to MESA; (2) transfers source potential to the polysilicon inside deep trenches (this is also known as the “central electrode”); and (3) via a “buried connection” using the conductive polysilicon as a transfer medium and the contact vias (this is the “outer shield electrode”).

[0020] A same piece of metal (source metal) as you look it from the top, may serve all the above three functions at the same time. The design may be segmented in x 4 pieces of source metal, physically separated to each other but electrically connected to each other via the “outer shield electrode”.

[0021] The inventors have found that in support of the provided semiconductor device configuration, an outer shield electrode is provided to establish electrical connection between the aforementioned 4 source regions of the device.

[0022] In an example of the disclosure the outer shield electrode comprises a plurality of tracks, preferably two tracks, each provided around the four rectangularly shaped source regions.

[0023] The inventors have found that a plurality of tracks may be used in the outer shield electrode for the enabling of the connection between source regions. A plurality of tracks allows for a more stable connection.

[0024] The inventors have also recognized that two tracks may be preferable, as this allows a more stable connection, but also saves space as much as possible. As mentioned before, space is a valuable resource in semiconductor device, so this tradeoff is to be carefully managed. In an example of the disclosure, the semiconductor device comprises vertical vias, wherein the outer shield electrode is connected to each of the source regions through said vertical vias, wherein vias of the vertical vias are connected to the outer shield electrode and to a source region of the four rectangularly shaped source regions.

[0025] In order to connect the source regions to each other, the outer shield electrode is provided. The inventors have found that to connect the respective source regions to the outer shield electrode, vertical vias may be used, providing an electrical connection from the outer shield electrode and the source regions.

[0026] This allows an efficient semiconductor layout, as it may negate the need for extra contacts outside of the trenches and / or trench area. Moreover, it allows the gate polysilicon to be contacted at both ends of the trenches. Contacting the gate polysilicon at both ends may result in a more uniform and efficient electrical connection along the entire trench. This reduces electrical resistance in the gate region, which leads to faster switching speeds and improved overall device performance.

[0027] In an example of the disclosure, the central electrode is provided in a connection layer wherein the connection layer is provided at a different layer of the semiconductor device than a layer of the four rectangularly shaped source regions and a layer of the outer shield electrode.

[0028] The inventors have found that the outer shield electrode is provided at a perimeter outside of the perimeter of the source regions, and also of the gate bus-bar. This results in the outer shield electrode being isolated from the source regions. Therefore, a connection should be made between the source region and the outer shield electrode. This may be done through the aforementioned vias.

[0029] In an example of the disclosure, one of the four rectangularly shaped source regions comprises a gate pad that is electrically connected to the gate bus-bar. The semiconductor device may include bonding means for providing electrical connection from external circuitry to the gate bus-bar. The gate pad is arranged to receive the bonding means.

[0030] The inventors have found that in order to contact the gate bus-bar from external circuitry, a gate pad is to be provided. This gate pad is connected to the gate bus-bar and is located in a source region of the four source regions. A gate pad for receiving a bonding means is used in semiconductor devices to provide a secure connection between the integrated circuit and external circuitry. This connection ensures efficient signal transmission and a robust durability in operation.

[0031] In an example of the disclosure, the gate bus-bar may be a gammadion shaped gate bus-bar or a fylfot shaped gate bus-bar.

[0032] The inventors have found that by providing the continuous bus-bar in any of these shapes allows for an efficient contacting of the gate electrodes, which, as mentioned, are at ends of the trenches. These layouts may consume a relatively small area of the semiconductor die. As area and size are a premium resource in the field of semiconductors, this is beneficial.

[0033] In an example of the disclosure, the ends of the trenches of the sets of trenches may be located at neighboring parallel sections of fins of the gate bus-bar

[0034] The inventors have found that by using the above-mentioned shape allows for the connection of the ends of the trenches to the continuous bus-bar. Herein, the fins of the gammadion or fylfot shapes may connect to neighboring parallel sections.

[0035] In an example of the disclosure, the trenches comprise split-gate trenches.

[0036] Split gate trenches have an advantage of improving control over the electric field distribution in the transistor. By dividing the gate into two sections, this may reduce the electric field concentration. Another benefit that the inventors have identified is the reduced capacitance between the gate and drain. Reducing this capacitance may reduce the switching losses and increase the switching speeds. This follows the previous advantage of increasing switching due to the layout.

[0037] The split gate trenches synergize to provide high switching speeds. High switching speeds are desirable because they reduce the time a transistor spends in the linear region, where the transistor is in between on and off and where power dissipation is highest. Faster switching reduces the energy lost in these transitions.

[0038] In a further aspect of the disclosure there is provided a semiconductor package including a semiconductor device according to the disclosure. The semiconductor package may further include a source, a drain and a gate terminal, each operatively connected to the semiconductor device. The semiconductor package may further include an encapsulant at least substantially encapsulating the semiconductor package. At least part of the source, drain and gate terminal are exposed to allow electrical connection to the semiconductor package. The same benefits described for the semiconductor device apply to corresponding embodiments of the semiconductor package of the present disclosure.

[0039] It may be beneficial to encapsulate the semiconductors according to the disclosure as this may be of important in protecting sensitive electronic components from external factors. Encapsulation may provide an insulating barrier that shields the device. It may also help in dissipating heat generated during operation, which may be importance for preventing overheating.

[0040] It may then be further beneficial to provide gate, source and drain contacts to the semiconductor package, which are not insulated to external circuitry, as they allow electrical connected to the package.

[0041] Brief description of the Drawings

[0042] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbol indicate corresponding parts, in which:

[0043] Fig. 1 shows a top-view of a semiconductor device in accordance with the disclosure;

[0044] Fig. 2 shows a top-view of a set of trenches of a semiconductor device in accordance with the disclosure;

[0045] Fig. 3A and Fig. 3B show top-views of different orientations of bus-bars in a semiconductor device in accordance with the disclosure; and

[0046] Fig. 4 shows a top view of shield electrodes in a semiconductor device in accordance with the disclosure.

[0047] The figures are intended for illustrative purposes only, and do not serve as restriction of the scope of the protection as laid down by the claims.

[0048] Detailed description

[0049] It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0050] The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the present disclosure is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0051] Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present disclosure should be or are in any single example of the present disclosure. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same example.

[0052] Furthermore, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure. Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0053] The present disclosure relates to semiconductor devices comprising sets of trenches connected to a bus-bar. A bus-bar is a conductive pathway used to distribute electrical power among various components within a power module or system. One of its functions is to carry high current loads from power sources to various semiconductor devices. Moreover, they provide a stable and low resistance path for current from multiple semiconductor devices. The bus-bar typically comprises a conductive material, such as copper, aluminum or brass, and may serve as an electrical connection point for the trenches and other possible electrical components. Bus-bars may handle high current loads and may be scaled to meet the demands of growing electrical systems. Their modular nature allows for the addition of more connections as needed. Therefore, if more trenches are to be added, the bus-bar may allow for this.

[0054] In Fig. 1 , an example embodiment of a semiconductor device 100 is shown. In Fig. 100, four source regions 101 are present, which are placed in a two-by-two orientation as may be observed. These source regions 101 are separated by a gate bus-bar 102, in this example depicted in a gammadion shape.

[0055] A gammadion shape refers to a cross with extra fins on the ends of the cross, all directing in the same anti-clockwise direction. Float shape refers to a cross similar to the gammadion shape, with extra fins on the ends of the cross, all directing in the same clockwise direction.

[0056] As mentioned before, a primary function of a gate bus-bar is to carry high current loads from power sources to various semiconductor devices or to connect multiple devices in parallel, such as the gates of the parallel trenches as shown in Fig. 1.

[0057] In Fig. 1 , a set of trenches is connected to the bus-bar at each of the fins of the shape. Fins of the shape, in this case a gammadion or fylfot shape, are the extra protrusions or sections of the cross running in a counterclockwise or clockwise direction. When combined in a cross, this allows for four U-shaped sections to be formed. In between a U-shape, the trenches may connect from one side of U to the other side of U. Neighboring sections of the fylfot or gammadion shape are perpendicular to each other. Therefore, the trenches running in between the U-shape will also be perpendicular or orthogonal.

[0058] The sets of trenches 103 may be oriented orthogonally to neighboring trenches. This configuration allows for an efficient layout, as there is no need for extra contacts outside of the trenches. The contacts are located at a central region of the trenches, which will be further illustrated in Fig. 2. This configuration also allows fast switching as it allows the gate polysilicon to be contacted at both ends of the trenches.

[0059] Further, this layout only consumes a small area of the die as there is an efficient contacting of the gate electrodes due to the shape of the continuous bus-bar.

[0060] In Fig. 2, an embodiment of a set of trenches in accordance with the present disclosure is depicted. Herein, a trench 103 comprises two ends, which are located in end regions 201 , where the gate is contacted by the continuous bus-bar. As mentioned before, the gate bus-bar may conduct current to the four separate source regions, specifically to the gates of the trenches of the respective source region. This configuration minimizes voltage drops over this connection. This is of importance in maintaining a sufficient efficiency in power systems. The gate electrode in semiconductor devices is responsible for controlling the collective state of the semiconductor. By applying a voltage to the gate, an electric field is generated in the trench region, allowing charge carriers to be attracted to the channel and enabling current flow.

[0061] In Fig. 2, the trench 204 is separated from its neighboring trench by a sidewall 203. The set of trenches may comprise a contact region 202, which is located in a central region of the set of trenches. This contact region comprises a set of contacts 205, which contacts the trenches and allows for an electrical connection to the source of the trench 204.

[0062] Fig. 3A shows an example embodiment of a semiconductor device 300A having a gammadion-oriented bus-bar 302A. The orientation of the trenches in each of the four source regions 301 is depicted by the arrows 303. In the example of Fig. 3A, a gate pad 304 is connected to the bus-bar 302A.

[0063] Fig. 3B shows an example embodiment of a semiconductor device 300B having a fylfot-oriented bus-bar 302B. The orientation of the trenches in each of the four source regions 301 is depicted by the arrows 302. In the example of Fig. 3B, a gate pad 304 is connected to the bus-bar 302B.

[0064] Fig. 4 shows an example embodiment of a semiconductor device 400, wherein the four source regions are interconnected using shield electrodes. The four rectangles are zoomed in at the sides of Fig. 4 to show the shield electrodes 402, in this example two continuous shield electrodes run around the die, wherein source metal is contacted down to the shield electrode 402. The source potential from the top metal plate travels though a source via into source polysilicon within deep trenches in the outer periphery of the device (“the tracks” of the shield electrodes 402), “travels” around the device and then resurfaces from polysilicon within deep trench, through the vias, to connect the metal plates again. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope thereof.

Claims

CLAIMS1. A semiconductor device comprising: four rectangularly shaped source regions arranged in a two-by-two orientation in the semiconductor device; and a gate bus-bar separating the four source regions, wherein each of the source regions comprises a set of trenches, wherein the set of trenches of two adjacent source regions are perpendicularly oriented, wherein the gate bus-bar is located at three sides of each of the four source regions, wherein the gate bus-bar between two adjacent source regions is one and the same, wherein one outer edge of each of the four source regions is free of gate busbar, wherein the one outer edge free of gate bus-bar of two adjacent source regions are perpendicularly oriented; and wherein the gate bus-bar is arranged to provide an electrical connection to gates of the sets of trenches of each of the source regions.

2. The semiconductor device according to claim 1 , wherein the four rectangularly shaped source regions are connected to an outer shield electrode provided around the four rectangularly shaped source regions.

3. The semiconductor device according to claim 2 wherein the outer shield electrode comprises a plurality of tracks, preferably two tracks, each provided around the four rectangularly shaped source regions.

4. The semiconductor device according to claim 2 or claim 3, wherein the semiconductor device comprises vertical vias, wherein the outer shield electrode is connected to each of the source regions through said vertical vias, wherein the vertical vias are connected to the outer shield electrode and to a source region of the four rectangularly shaped source regions.

5. The semiconductor device according to any one of the preceding claims, wherein one of the four rectangularly shaped source regions comprises a gate pad that is electrically connected to the gate bus-bar; and wherein the semiconductor device comprises bonding means for providing electrical connection from external circuitry to the gate bus-bar; wherein the gate pad is arranged to receive the bonding means.

6. The semiconductor device according to any one of the claims 1-5, wherein the gate bus-bar is a gammadion shaped gate bus-bar.

7. The semiconductor device according to any one of the claims 1-5, wherein the gate bus-bar is a fylfot shaped gate bus-bar.

8. The semiconductor device according to any one of the preceding claims, wherein the trenches comprise split-gate trenches.

9. A semiconductor package comprising a semiconductor device according to any one of the claims 1-8, the semiconductor package further comprising: a source, a drain and a gate terminal, each operatively connected to the semiconductor device; and an encapsulant at least substantially encapsulating the semiconductor package, wherein at least part of the source, drain and gate terminal are exposed to allow electrical connection to the semiconductor package.

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