A process of metal gate integration in trench semiconductor devices

Abstract

A process of fabricating a trench semiconductor device, the trench semiconductor device thus fabricated and a semiconductor package including such semiconductor device are presented. The gate metal is formed before interlayer dielectric (ILD) deposition. A nitride-based spacer (8) and a sacrificial layer (10) are formed at the location of the gate metal before forming the gate metal. The nitride-based spacer and the sacrificial layer protect a gate oxide (4) during formation of the active region of the trench semiconductor device. The sacrificial layer is removed after the formation of the active region and before forming the gate metal.

Description

[0001] A process of metal gate integration in trench semiconductor devices

[0002] Technical field

[0003] The present disclosure relates to trench semiconductor devices. More specifically, the present disclosure is related to a process of fabricating the gate metal of a trench semiconductor device, a semiconductor device fabricated using this process, and a semiconductor package including such semiconductor device.

[0004] Background

[0005] A trench metal-oxide-semiconductor field-effect transistors (MOSFET) is characterized by its vertical structure designed to enhance efficiency and current handling capabilities. A critical element of this device is the gate metal, which facilitates precise control of current flow through the semiconductor device by modulating the formation of a conductive channel in the silicon substrate.

[0006] The trench MOSFET structure begins with a silicon wafer, into which deep vertical trenches are etched. These trenches house the gate metal, which is typically a conductive material such as heavily doped polysilicon in earlier designs or advanced materials like tungsten, titanium nitride or any suitable metal alloys in contemporary implementations. The gate metal is electrically isolated from the silicon substrate by a thin insulating layer of silicon dioxide or, in advanced nodes, high-k dielectric materials. This insulation allows the gate metal to influence the silicon's electrical properties without direct current flow.

[0007] When a voltage is applied to the gate metal, it generates an electric field that penetrates the trench walls and modifies the silicon's electrical behavior. Specifically, this field induces an inversion layer along the trench sidewalls, forming a conductive channel between the source and drain regions. This channel's conductivity is dynamically controlled by the gate voltage, enabling the MOSFET to act as a switch or amplifier.

[0008] The vertical arrangement of the trench gate offers significant electrical and thermal advantages over planar designs. The vertical structure reduces the on- resistance (Roson), a critical parameter in power devices, by increasing the channel density per unit area. This reduction in resistance minimizes energy losses and heat generation, enhancing the device's efficiency. Furthermore, the vertical alignment enables the MOSFET to handle higher currents, making it ideal for applications such as motor control, power converters, and power supplies.

[0009] Despite these benefits, the implementation of the gate metal in trench MOSFETs presents engineering challenges. The process of uniformly depositing the gate metal within the narrow trenches requires advanced techniques to ensure consistent electrical performance. Additionally, the trench geometry may increase the gate-to- drain capacitance (Miller capacitance), which can affect switching speed and energy efficiency.

[0010] Summary

[0011] A summary of aspects of certain examples disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects and / or a combination of aspects that may not be set forth.

[0012] The present disclosure enables metal gate integration in trench power MOSFETs in an efficient manner. By protecting the gate oxide with a nitride spacer during the fabrication process and using a sacrificial gate layer with high-density plasma (HDP) oxide or any other suitable sacrificial material, allows to integrate the metal gate after active region formation.

[0013] According to an aspect of the present disclosure, a process of fabricating a trench semiconductor device is presented, wherein a gate metal is formed before interlayer dielectric (ILD) deposition.

[0014] In an embodiment, a nitride-based spacer and a sacrificial layer may be formed at the location of the gate metal before forming the gate metal. The nitride-based spacer and the sacrificial layer may protect a gate oxide during formation of an active region of the trench semiconductor device. The sacrificial layer may be removed after the formation of the active region and before forming the gate metal.

[0015] In an embodiment, the nitride-based spacer may include a silicon-nitride (SiN) layer. In an embodiment, the sacrificial layer may be a high-density plasma (HDP) oxide.

[0016] In an embodiment, the sacrificial layer may be a tetraethyl orthosilicate (TEOS).

[0017] In an embodiment, the sacrificial layer may be a silicon suboxide (SiOx).

[0018] In an embodiment, the sacrificial layer may be a silicon oxynitride (SiON).

[0019] In an embodiment, the process may include depositing a first nitride-based spacer on top of the gate oxide. The process may further include depositing the sacrificial layer at the location of the to-be-formed gate metal. The sacrificial layer may cover a part of the first nitride-based spacer at the location of the to-be-formed gate metal. The process may further include etching a part of the first nitride-based spacer that is not covered by the sacrificial layer. The process may further include implanting a body of the trench semiconductor device resulting in an implanted body. The process may further include creating a source region in the implanted body. The process may further include depositing a second nitride-based spacer. The process may further include wet striping a part of the second nitride-based spacer located above the sacrificial layer. The process may further include wet etching the sacrificial layer. The process may further include wet striping the remaining first and second nitride-based spacer. The process may further include depositing a titanium nitride (TiN) barrier layer. The process may further include depositing a tungsten (W) layer on top of the TiN barrier layer. The process may further include planarizing the tungsten layer and etching the TiN barrier layer located at the top. The process may further include depositing the IDL layer.

[0020] In an embodiment, the depositing of the first nitride-based spacer and the depositing of the second nitride-based spacer may include a SiN deposition.

[0021] In an embodiment, the depositing of the sacrificial layer may include a HDP oxide deposition followed by a HDP chemical mechanical planarization (CMP).

[0022] In an embodiment, the source region may be an N+ region. The creating of the source region may include a rapid thermal processing (RTP) anneal of the body and the source region, and a source implanting.

[0023] In an embodiment, the wet striping of the part of the second nitride-based spacer located above the sacrificial layer may include applying a litho gate using a mask design above the gate oxide before the wet striping, leaving a gap above the sacrificial layer. In an embodiment, the gate metal may include the TiN barrier layer and a tungsten (W) layer or any other suitable metal alloy layer.

[0024] According to an aspect of the present disclosure, a semiconductor device is presented. The semiconductor device may include a gate metal that has been fabricated using a process having one or more of the above described features.

[0025] In an embodiment, the semiconductor device may be a trench power MOSFET.

[0026] According to an aspect of the present disclosure, a semiconductor package is presented. The semiconductor package may include one or more semiconductor devices described above.

[0027] Brief description of the Drawings

[0028] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbol indicate corresponding parts, in which:

[0029] Fig. 1A-1O are cross-sectional side views of a semiconductor device during different fabrication steps; and

[0030] Fig. 2 is an abstract representation of a semiconductor package including a semiconductor device.

[0031] The figures are intended for illustrative purposes only, and do not serve as restriction of the scope of the protection as laid down by the claims.

[0032] Detailed description

[0033] It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the present disclosure is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0034] Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present disclosure should be or are in any single example of the present disclosure. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same example.

[0035] Furthermore, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure. Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0036] In semiconductor devices such as trench MOSFETs, creating a gate metal before completing the active region requires a dedicated tool for gate metal-based technology, which is very expensive to the foundry business. The solution of the present disclosure enables a gate metal fabrication process, wherein the metal gate trench MOSFET may be fabricated in the fab, after completing the FEOL process and before ILD deposition, in a manner that is less costly to the foundry. Thereby, creating such metal gate becomes a viable solution. In an embodiment of the present disclosure, the gate metal may be formed before ILD deposition, e.g., at the start of a back-end of line (BEOL) process of the fab with no or very minimum tool dedication.

[0037] In an example embodiment of the present disclosure, a nitride-based spacer may be used to protect the gate oxide and a sacrificial layer, such as HDP oxide or any suitable material, to form a gate first, i.e., before forming the gate metal. This sacrificial layer may be removed after the active region formation, and any suitable metal or metal alloy may be deposited as the gate. The gate may then be sealed with an undoped oxide layer, non-limiting examples of which are HDP oxide, TEOS, SiOx, SiON, or any suitable interlayer dielectric layer.

[0038] As explained above, the solution of the present disclosure enables the creation of metal gates in an economically viable manner. Using a metal gate has significant advantages in reducing the gate resistance (Rg) compared to a poly gate and therewith significantly improves switching performance. Furthermore, this allows optimization of the die design with the elimination of gate fingers (bus bars), optimizing the active area and reducing the specific contact resistance (Rspec). Elimination of gate finger / busbar may increase the active area up to 15% on the biggest die. Moreover, an increase in short-circuit protection efficiency may be achieve, e.g., an increase in efficiency by +0.7% at 30A and +1.3% at 60A in an example trench MOSFET.

[0039] Furthermore, metal gates offer better thermal stability compared to polysilicon gates. Metal gates can also help to reduce gate capacitance slightly due to elimination of Polysilicon depletion capacitance. The combination of lower gate resistance, lower capacitance and increase in active area with reduced Rspec leads to overall improved performance in terms of faster switching, lower power dissipation, and higher efficiency.

[0040] Another advantage of using gate metal is an increase in power MOSFET efficiency of around 1%.

[0041] In an embodiment, the fabrication process may include a nitride spacer to protect a gate oxide and using a sacrificial gate layer to complete the formation of the active region for metal gate integration before the ILD layer.

[0042] In an embodiment, a very thin TiN barrier layer using metal-organic chemical vapor deposition or plasma-enhanced chemical vapor deposition (MOCVD / PCVD) and tungsten filling as the gate metal may be used. A CMP process may be used to etch back tungsten later. Tungsten may be deposited by the chemical vapor deposition (CVD) process. Tungsten hexafluoride (WF6) is often used as a precursor gas in CVD processes. To avoid reactions with SiO2, a barrier layer such as TiN may be used between the tungsten and the gate oxide. This barrier prevents diffusion and potential reactions during deposition and subsequent thermal cycles, ensuring the longevity and performance of the semiconductor device. This TiN layer functions almost similar to Poly-silicon and may function as a main gate metal as being in direct contact with gate oxide. Advantageously, there is substantially no change in threshold voltage (Vth) when using TiN as gate metal.

[0043] In an embodiment, the solution of using a CVD TiN barrier layer and tungsten filling as the gate metal may be integrated in a middle gate design for trench power MOSFETs.

[0044] Figures 1A-1O illustrate a part of an example process flow of fabricating a semiconductor device, wherein integrating a metal gate in a trench of a semiconductor device according to an aspect of the present disclosure. Figures 1A-1O show a cross- sectional side view (in an abstract representation) of a semiconductor device during different fabrication steps, focusing on the trench and its surroundings. Non-limiting examples of such semiconductor device are a trench power MOSFET or any trench MOSFET using Polysilicon gate metal.

[0045] The fabrication process semiconductor device may follow a standard, known per se process flow up to and including step 100 of Fig. 1A. Step 100 of the standard process may involve a gate oxidation to create a gate oxide layer 4, e.g., based on thermal interlayer passivation oxide (IPO), HDP oxide IPO or any other known process. Also shown in Fig. 1A are a substrate 2 and a source poly 6 created in one or more earlier steps.

[0046] An example embodiment of the present disclosure of integrating a metal gate in trenches of a semiconductor device is shown in figures 1 B-1O.

[0047] In step 102 shown in Fig. 1 B, a nitride-based spacer 8 may be created, e.g., thru nitride deposition to form a nitride layer. An example material for the nitride-based spacer 8 is SiN oxide. The deposited nitride 8 protects the gate oxide 4 in later processing steps.

[0048] In step 104 shown in Fig. 1 C, a sacrificial layer 10 may be created, e.g., using HDP deposition and HDP CMP resulting in HDP oxide being present as a stop on the nitride below the HDP oxide 10 for later processing steps. In step 106 shown in Fig. 1 D, the nitride layer 8 that is not covered by the HDP oxide 10, i.e., at the locations 12, may be etched. The exposed gate oxide 4 at the surface at locations 12 may become screen oxide for body / source implantation in later processing steps.

[0049] In step 108 shown in Fig. 1 E, the body may be implanted resulting in implanted body 14.

[0050] In step 110 shown in Fig. 1 F, a source region 16, e.g., an N+ region, may be created. Step 110 may include, e.g., a RTP anneal of the body and the source, e.g., at 1100°C for 30s, a photoresist (PR) strip and the source implanting. Both the body and the source may be annealed in one step by adjusting implant recipes.

[0051] In step 112 shown in Fig. 1G, a nitride-based spacer 18 may be deposited again, e.g., in the form of a SiN oxide layer.

[0052] In step 114 shown in Fig. 1 H, the nitride 18 above the HDP oxide 10 may be wet striped resulting in the area 22 above the HDP oxide 10 to be free of nitride 18. Hereto, a litho gate 20 may be applied using a mask design with smaller critical dimension (CD) to avoid the nitride 18 above the gate oxide 4 the be wet etched and to avoid exposing the gate oxide 4 while etching the nitride layer 18. Wet etching is preferred over dry etching in step 114 to avoid potential issues with charge injection to the gate oxide 4. The wet striping of the nitride 18 may use, e.g., hot phosphoric acid to wet etch the nitride 18 above the HDP oxide 10.

[0053] In step 116 shown in Fig. 11, the HDP oxide 10 may be wet etched as depicted by the arrow 24. The PR 20 may be removed by wet stripping.

[0054] In step 118 shown in Fig. 1 J, the exposed, remaining nitride 18 may be wet stripped at the locations 26, e.g., using hot phosphoric acid.

[0055] In step 120 shown in Fig. 1 K, a TiN barrier layer 28 may be deposited, e.g., using MOCVD or PCVD. The TiN barrier layer 28 forms part of the metal gate to be formed in the semiconductor device.

[0056] In step 122 shown in Fig. 1 L, a tungsten (W) layer 30 may be deposited, e.g., using CVD. The tungsten (W) forms part of the metal gate to be formed in the semiconductor device.

[0057] In step 124 shown in Fig. 1 M, the tungsten (W) layer 30 may be planarized, e.g., using CMP, stopping on the TiN barrier layer 30, and the TiN barrier layer 30 at the then exposed top 32 may be etched. In optional step 126 shown in Fig. 1 N, an HDP oxide layer 34 may be deposited and CMP. Step 126 may be skipped.

[0058] In step 128 shown in Fig. 10, any IDL layer 36 may be deposited, i.e., the IDL layer 36 is not limited to undoped oxide / doped oxide and / or oxy nitride. After step 128 of Fig. 10, the fabrication process may follow a standard, known per se process flow again to form, e.g., contact, metal, passivation and top contact.

[0059] Using the above described fabrication process, a metal gate trench semiconductor device 200 may be manufactured, which semiconductor device 200 may be part of a semiconductor package 202, as abstractly illustrated in Fig. 2. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope thereof.

Claims

CLAIMS1. A process (100-128) of fabricating a trench semiconductor device (200), wherein a gate metal (28, 30) is formed (120, 124) before interlayer dielectric,ILD, deposition (128).

2. The process according to claim 1 , wherein a nitride-based spacer (8, 18) and a sacrificial layer (10) are formed at the location of the gate metal before forming the gate metal, wherein the nitride-based spacer and the sacrificial layer protect a gate oxide (4) during formation of an active region of the trench semiconductor device, and wherein the sacrificial layer is removed after the formation of the active region and before forming the gate metal.

3. The process according to claim 2, wherein the nitride-based spacer comprises a silicon-nitride, SiN, layer.

4. The process according to claim 2 or claim 3, wherein the sacrificial layer comprises one of: a high-density plasma, HDP, oxide; a tetraethyl orthosilicate, TEOS; a silicon suboxide, SiOx; a silicon oxynitride, SiON.

5. The process according to any one of the claims 2-4, comprising: depositing (102) a first nitride-based spacer (8) on top of the gate oxide (4); depositing (104) the sacrificial layer (10) at the location of the to-be-formed gate metal, the sacrificial layer covering a part of the first nitride-based spacer at the location of the to-be-formed gate metal; etching (106) a part (12) of the first nitride-based spacer that is not covered by the sacrificial layer; implanting (108) a body of the trench semiconductor device resulting in an implanted body (14);creating (110) a source region (16) in the implanted body (14); depositing (112) a second nitride-based spacer (18); wet striping (114) a part (22) of the second nitride-based spacer located above the sacrificial layer (10); wet etching (116) the sacrificial layer (10); wet striping (118) the remaining first (8) and second (18) nitride-based spacer; depositing (120) a titanium nitride, TiN, barrier layer (28); depositing (122) a tungsten, W, layer (30) on top of the TiN barrier layer; planarizing (124) the tungsten layer (30) and etching the TiN barrier layer located at the top; depositing (128) the IDL layer (36).

6. The process according to claim 5, wherein the depositing (102) of the first nitridebased spacer (8) and the depositing (112) of the second nitride-based spacer (18) comprises a silicon-nitride, Si N , deposition.

7. The process according to claim 5 or claim 6, wherein the depositing (104) of the sacrificial layer comprises a high-density plasma, HDP, oxide deposition followed by a HDP chemical mechanical planarization, CMP.

8. The process according to any one of the claims 5-7, wherein the source region is an N+ region and wherein the creating (110) of the source region comprises a rapid thermal processing, RTP, anneal of the body and the source region, and a source implanting.

9. The process according to any one of the claims 5-8, wherein the wet striping (114) of the part of the second nitride-based spacer located above the sacrificial layer (10) comprises applying a litho gate (20) using a mask design above the gate oxide (4) before the wet striping (114), leaving a gap above the sacrificial layer (10).

10. The process according to any one of the claims 5-9, wherein the gate metal comprises the TiN barrier layer (28) and a tungsten, W, layer (30) or any other suitable metal alloy layer.

11. A semiconductor device (200) comprising a gate metal (28, 30) that has been fabricated using the process according to any one of the claims 1-10.

12. The semiconductor device according to claim 11 , wherein the semiconductor device is a trench power metal-oxide-semiconductor field-effect transistor, MOSFET.

13. A semiconductor package (2020) comprising one or more semiconductor devices (200) according to claim 11 or claim 12.

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