A lead frame for semiconductor package, a semiconductor device and a method of manufacturing the lead frame

Abstract

The object of the present disclosure is to provide a led frame allowing to provide robust stress buffering and thus minimize die crack risk during eutectic die bonding process. According to the first aspect, there is a lead frame for semiconductor package, comprising a lead frame body made of copper or copper alloy and a dual layer plating formed on the lead frame body, the lead frame body having a first surface for attaching a semiconductor die and a second surface opposite to said first surface. The dual layer plating comprises a metallic, stress buffer layer directly coupled to the lead frame body, and a cladding layer covering the stress buffer layer, made of metal able to form a eutectic or diffusion bond. An important benefit of incorporating such stress-buffering layer into the lead frame eliminates the need for adding additional stress-buffer layers to the back-metal stack. The invention also provides a semiconductor package comprising said lead frame. There is also disclosed a method of manufacturing of a lead frame is provided, comprising: providing a metal sheet made of copper or copper alloy, being a preform of a lead frame body; plating at least a surface intended to be a die attach surface of a first surface of the lead frame, the first surface being intended for attaching a semiconductor die, with a stress buffer layer; plating the stress buffer layer with a cladding layer made of metal able to form eutectic or diffusion bond stamping the plated metal sheet to obtain final lead frame geometry. The step of stamping may be alternatively performed before the step of plating.

Description

[0001] TITLE

[0002] A lead frame for semiconductor package, a semiconductor device and a method of manufacturing the lead frame

[0003] TECHNICAL FIELD

[0004] The present disclosure relates to stress buffering in a semiconductor package. More specifically, the present disclosure relates to stress buffering of a semiconductor die coupled to a lead frame, in particular to a Cu-based lead frame, by eutectic die bonding.

[0005] BACKGROUND OF THE DISCLOSURE

[0006] Eutectic die bonding, also referred to as eutectic die attach or eutectic soldering, is a method used in semiconductor and microelectronics manufacturing to attach a semiconductor die to a substrate or another component using an eutectic alloy as the bonding material. It ensures mechanical stability and efficient thermal and electrical connection between the die and the substrate. Eutectic bonding process uses an intermediate solder alloy to form a continuous bond between their surfaces. Said method is used in high-performance applications where a reliable thermal and electrical interface is necessary, for example in devices that require enhanced heat dissipation, such as high- power amplifiers. Eutectic die bonding allows to produce hermetically sealed assemblies and electrical interconnection within a single process.

[0007] To achieve eutectic bond, typically an eutectic alloy is applied between two components. Instead of the eutectic alloy, layers between which intermetallic conversion occurs may be used. The temperature of the assembly is brought up to just above the melting point of the solder (to the eutectic temperature), for example by heating the base on which the assembly rests or by flowing heated gas over the assembly. Heating causes the alloy to melt and wet both surfaces (die and substrate). Then the assembly is cooled to below the reflow temperature to solidify the eutectic alloy and thus create a robust mechanical and thermal connection. The process is often performed in a vacuum or inert atmosphere to prevent oxidation and ensure high reliability.

[0008] An eutectic alloy is a mixture of two or more elements that melts and solidifies at a single, fixed temperature, known as the eutectic point. Eutectic alloys thus transform directly from solid to liquid state or vice versa at a specific temperature without passing a two-phase equilibrium, i.e. liquid and solid state. The eutectic temperature may be much lower than the melting temperature of the two or more pure elements. The temperature of the eutectic bonding process is dependent on the used materials. The bonding happens at a specific temperature and at specific weight ratio of elements of an alloy.

[0009] Traditional approaches to eutectic bonding commonly utilize gold-germanium (AuGe) eutectic solder or, in the case of Au-free backmetals, intermetallic conversion of tin (Sn) to copper-tin (CuSn) or intermetallic conversion of tin (Sn) to silver-tin (AgSn). Backmetal, or back-side metal (BSM), refers to a thin metal layer(s) deposited on the backside of a silicon die to facilitate electrical, thermal, and mechanical integration in electronic packaging. Eutectic bonds typically have a thickness of 1 to 5 pm and a wideness of > 50 pm.

[0010] Common alloys used for die bonding include also gold-tin (Au-Sn) or gold-silicon (Au-Si). These alloys have good thermal and electrical conductivity and ability to create a strong, reliable bond. Other exemplary alloys that may be used include gold-indium (Au- In), aluminium-germanium (Al-Ge) or aluminium-silicon (Al-Si). Choosing the alloy is determined by the processing temperature and compatibility of the materials.

[0011] Both processes, i.e. utilizing eutectic alloys or intermetallic conversion, are conducted in high temperatures, which inherently generate thermomechanical stresses. Such stresses are particularly problematic when bonding silicon dies to copper (Cu) lead frames, as they can lead to die cracks, mainly due to the brittle nature of the die and the thermal expansion mismatch between materials. Precise temperature control is important to avoid damaging the die or the substrate.

[0012] In the state of the art, several approaches have been employed to mitigate the thermomechanical stresses introduced during high-temperature eutectic bonding.

[0013] One solution involves the use of Cu-plated lead frames made of Alloy42. Alloy42, an iron-nickel alloy, is chosen for its low coefficient of thermal expansion (CTE), which closely matches that of silicon. However, Alloy42 is an expensive material with relatively low thermal conductivity.

[0014] In other solutions, to buffer the stress when using Cu-based lead frames, and thus avoid die cracking, an additional aluminium (Al) or silver (Ag) layer is included in the backmetal stack, or a thick Ag plating is applied to the lead frame. While effective in reducing stress, these solutions introduce new challenges.

[0015] Ag-plated Cu-based lead frames, although capable of buffering thermomechanical stresses, cause significant delamination of the mold compound (encapsulant), particularly at the interface with the Ag layer. This delamination compromises the reliability of the device and therefore, to mitigate this issue, a costly spot plating of Ag often has to be employed.

[0016] The incorporation of Al in the back-metal stack complicates the deposition process of the metals and may cause significant burr formation during dicing of the wafer, as said Al layers are prone to burr formation. The resulting burr disturbs the die attach significantly, such that volume production is not possible.

[0017] Ag spot plating of lead frames is a known technique which involves applying a localized Ag layer on the lead frame to buffer the thermomechanical stresses generated during bonding. When the Ag layer is sufficiently thick, it forms a ductile interface that absorbs stress, thus improving the overall reliability of the bond. However, the adhesion of Ag to mould compound is known to be weak, what often results in increased delamination, particularly at the interfaces where Ag is exposed to encapsulation materials. Additionally, for applications requiring small spot plating dimensions, the process becomes technically challenging or unfeasible. Furthermore, thick Ag plating, while improving stress buffering, is associated with high costs and reduced production efficiency.

[0018] In summary, while existing methods provide partial solutions to the challenges associated with eutectic die bonding, they are accompanied by significant drawbacks, including material cost, process complexity, and reliability issues. The need for solutions that provide better delamination performance by maintaining strong adhesion to mold compounds, allow to eliminate burr formation, provide robust stress buffering and thus minimize die crack risk during eutectic die bonding process, particularly for Cu-based lead frames, remains a pressing issue in semiconductor manufacturing.

[0019] SUMMARY OF THE INVENTION

[0020] Accordingly, the present disclosure provides a lead frame design allowing to eliminate the risk of die cracking during eutectic die bonding process.

[0021] The present disclosure, in a first aspect, provides a lead frame for semiconductor package, comprising a lead frame body made of copper or copper alloy and a dual layer plating formed on the lead frame body, the lead frame body having a first surface for attaching a semiconductor die and a second surface opposite to said first surface. The dual layer plating comprises a metallic, stress buffer layer directly coupled to the lead frame body, and a cladding layer covering the stress buffer layer, made of metal able to form a eutectic or diffusion bond. An important benefit of incorporating such stress-buffering layer into the lead frame eliminates the need for adding additional stress-buffer layers to the back-metal stack. This provides more flexibility in designing the back-metal stack, simplifies the sawing process and facilitates the eutectic die bonding process.

[0022] The cladding layer may be made of metal able to form intermetallic compounds with tin. This is useful when the package comprises a bonding layer structure comprising tin.

[0023] In the present solution, different thermal expansion of silicon and copper needs to be buffered with as little stress as possible. Therefore it is preferable if the Young’s modulus of the stress buffer layer is lower than the Young’s modulus of copper.

[0024] Additionally or alternatively, the yield stress of the stress buffer layer is lower than the yield stress of pure copper, in order to yield quicker than copper.

[0025] For example, the stress buffer layer may be made of aluminium. In another example, the stress buffer layer is made of silver. Another suitable examples for the stress buffer layer are palladium or gold or vanadium or platinum or niobium or lead.

[0026] The stress buffer layer preferably has an ability to deform plastically to more extent than the Cu-based lead frame body. Therefore, the ductility of the stress buffer layer expressed with Poisson’s ratio v is preferably higher than 0.3.

[0027] In an exemplary embodiment, the melting temperature of the stress buffer layer is higher than 231 , 9°C, which is the melting temperature of tin, to avoid the risk that it will be consumed in the process of bonding.

[0028] The cladding layer is for example made of copper. The cladding layer may also be made of silver (if the stress buffer layer is not made of silver). The cladding layer may also be made of palladium (if the stress buffer layer is not made of palladium). The cladding layer may also be made of gold (if the stress buffer layer is not made of gold). In another example, the cladding layer may be made of nickel or iron or manganese or cobalt.

[0029] In one example of the present disclosure, the dual layer plating covers both the first surface of the lead frame body and the second surface of the lead frame body.

[0030] In another example of the present disclosure, the dual layer plating covers only the first surface of the lead frame body. In more specific example, the dual layer plating covers only the die pad area of the lead frame body available for die bonding, i.e. the area to which the semiconductor die is attached.

[0031] For example, the stress buffer layer may have a thickness of at least 0.5 pm.

[0032] For example, the cladding layer may have a thickness of at least 0.5 pm.

[0033] According to second aspect of the present invention, a semiconductor package is provided, comprising: a semiconductor die; a lead frame as described above; and a bonding layer structure coupling the semiconductor die to the lead frame. The bonding layer structure is coupled to the cladding layer of the dual layer plating.

[0034] In one example, the bonding layer structure comprises eutectic solder.

[0035] In another example, the bonding layer structure comprises a first diffusion bonding layer made of tin and a second diffusion bonding layer made of material able to form intermetallic compounds with tin. In such an example, the first diffusion bonding layer is coupled to the cladding layer of the dual layer plating. The second diffusion bonding layer may for example comprise copper or silver.

[0036] At least one back side metal layer may be arranged between the semiconductor die and the bonding layer structure, to facilitate electrical, thermal, and mechanical integration in electronic packaging.

[0037] According to another aspect of the present disclosure, a method of manufacturing of a lead frame is provided, comprising: providing a metal sheet made of copper or copper alloy, being a preform of a lead frame body; plating at least a surface intended to be a die attach surface of a first surface of the lead frame, the first surface being intended for attaching a semiconductor die, with a stress buffer layer; plating the stress buffer layer with a cladding layer made of metal able to form eutectic or diffusion bond stamping the plated metal sheet to obtain final lead frame geometry.

[0038] This applies to employing spot plating technique, where only a surface intended to be a die attach surface of the lead frame body is plated.

[0039] However, the method may comprise the step of plating the whole first surface of the lead frame, the first surface being intended for attaching a semiconductor die.

[0040] Additionally, the method may comprise plating a second surface, arranged oppositely to the first surface, with the with stress buffer layer. In such case, both the first and the second surface of the lead frame are double plated.

[0041] According to another way of manufacturing of the lead frame, the step of stamping may be performed before plating. In such a case, the method comprises: providing a metal sheet made of copper or copper alloy, being a preform of a lead frame body; stamping the plated metal sheet to obtain final lead frame geometry; plating at least a surface intended to be a die attach surface of a first surface of the lead frame, the first surface being intended for attaching a semiconductor die, with a stress buffer layer; plating the stress buffer layer with a cladding layer made of metal able to form eutectic or diffusion bond.

[0042] This applies to employing spot plating technique, where only a surface intended to be a die attach surface of the lead frame body is plated.

[0043] However, the method may comprise the step of plating the whole first surface of the lead frame, the first surface being intended for attaching a semiconductor die.

[0044] Additionally, the method may comprise plating a second surface, arranged oppositely to the first surface, with the with stress buffer layer. In such case, both the first and the second surface of the lead frame are double plated.

[0045] The optional and / or preferred features of each aspect of the disclosure as set out herein are also applicable to any other aspects of the disclosure where appropriate.

[0046] BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The disclosure of the present invention will now be discussed, by way of example only, with reference to the accompanying drawings in which:

[0048] Figure 1A shows a semiconductor die coupled to a lead frame body by eutectic bonding in the form of eutectic solder, according to the state of the art;

[0049] Figure 1 B shows a semiconductor die coupled to a lead frame body by eutectic bonding in the form of a first diffusion bonding layer and a second diffusion bonding layer, according to the state of the art;

[0050] Figure 1C shows a semiconductor die coupled to a lead frame body by a first diffusion bonding layer and a second diffusion bonding layer, whereby the semiconductor die has back-side metal layers, according to the state of the art;

[0051] Figure 1 D shows a semiconductor die coupled to a lead frame body by a first diffusion bonding layer and a second diffusion bonding layer, whereby the semiconductor die has back-side metal layers, between which a stress buffer layer is arranged, according to the state of the art;

[0052] Figure 2 shows a lead frame according to the present disclosure, having dual layer plating comprising a stress buffer layer and a cladding layer;

[0053] Figure 3A shows a semiconductor package according to the present invention, having a lead frame as shown in Fig. 2 and a semiconductor die coupled to the lead frame by eutectic solder layer;

[0054] Figure 3B shows a semiconductor package according to the present invention, having a lead frame as shown in Fig. 2 and a semiconductor die coupled to the lead frame by diffusion bonding layers;

[0055] Figure 4 shows a semiconductor package according to the present invention, having a lead frame as shown in Fig. 2 and a semiconductor die coupled to the lead frame by eutectic bonding, whereby the semiconductor die has the back-side metal layers applied;

[0056] Figure 5 shows the simulation results of the stress buffering capability for various semiconductor packages;

[0057] Figure 6 shows a semiconductor package having a lead frame with onesided dual layer plating where the dual layer plating is spot plated in the die attach area;

[0058] Figure 7 shows a semiconductor package having a lead frame with onesided dual layer plating;

[0059] Figure 8 shows a semiconductor package having a lead frame with two-sided dual layer plating.

[0060] DETAILED DESCRIPTION OF THE DISCLOSURE

[0061] Figures 1A to 1 D, in general, depict a silicon semiconductor die 10 coupled to a lead frame body 20 by a bonding layer structure 30 in known manner.. Lead frame body 20 is a substrate made, for example, of copper or of a material comprising copper.

[0062] As shown in Fig. 1A, the eutectic bonding may be achieved by using eutectic solder 30, whereby the bonding layer structure 30 is an eutectic alloy 31. Eutectic alloy 31 may be for example gold-germanium (AuGe) or gold-tin (Au-Sn) or gold-silicon (Au-Si), having good thermal and electrical conductivity and ability to create a reliable bond. Other exemplary eutectic alloys 31 include gold-indium (Au-ln), copper-tin (Cu-Sn), aluminiumgermanium (Al-Ge) or aluminium-silicon (Al-Si). However, the eutectic alloy 31 is not limited to the examples mentioned above. Choosing the alloy is determined by the processing temperature and compatibility of the materials. The eutectic (melting) temperature of the bonding layer structure 30 depends on the eutectic alloy 31 used. For example, eutectic temperature of Au-Ge (72 / 28 wt-%) is approximately 361 °C, eutectic temperature of Au- Sn (80 I 20 wt-%) is approx. 280°C, and eutectic temperature of Au-Si (97.15 / 2.85 wt-%) is approx. 370°C.

[0063] The bonding layer structure 30 made of eutectic alloy 31 preferably has a thickness of 0,5 to 5 pm, for example 1 ,5 pm. As shown in Fig.l B, the bonding layer structure 30, in the case of Au-free backmetal layers, may be achieved by intermetallic conversion, by using two metallic layers. Backmetal, or back-side metal (BSM) layer 40, refers to a thin metal layer or stack of layers deposited on the backside of a silicon semiconductor die 10 to facilitate electrical, thermal, and mechanical integration in electronic packaging. Intermetallic conversion refers to the formation of intermetallic compounds when the elements react. Therefore, the bonding layer structure 30 may be achieved by employing a first diffusion bonding layer 32, proximal to the lead frame body 20, and a second diffusion bonding layer 33. For example, the first diffusion bonding layer 32 may comprise tin (Sn), while the second diffusion bonding layer 33 may comprise copper (Cu) or silver (Ag) or nickel (Ni). Thus, bonding layer structure 30 may for example be achieved by intermetallic conversion of tin (Sn) to coppertin (CuSn) or silver-tin (AgSn) or nickel-tin (NiSn).

[0064] The first diffusion bonding layer 32 may for example have a thickness in the range from 1 pm to 4 pm, preferably 2 pm, and the second diffusion bonding layer 33 may have a thickness in the range from 0,3 pm to 3 pm, preferably 0,5 pm.

[0065] As shown in Fig. 1C, the semiconductor die 10 may have at least one back-side metal layer 40 deposited on it, at the side facing the lead frame body 20 and bonding layer structure 30. As shown in Fig. 1 C, the back-side metal layer 40 may include a first backside metal layer 41 , proximal to the lead frame body 20 and distal to the semiconductor die 10, and a second back-side metal layer 42, proximal to the semiconductor die 10 and distal to the lead frame body 20. The first back-side metal layer 41 may for example comprise NiV (nickel-vanadium) or Ni (nickel) and may have a thickness of 0,15 pm to 0,3 pm, for example 0,25 pm. The second back-side metal layer 42 may for example comprise Ti (titanium) and may have a thickness of 0,1 pm to 0,2 pm, for example 0,1 pm.

[0066] In known solutions, the back-side metal layer 40 may comprise a back-side stress buffer layer 43, for example aluminium layer or copper layer arranged between the first back-side metal layer 41 and the second back-side metal layer 42. This is shown in Fig. 1 D. The back-side stress buffer layer 43 may for example have a thickness of 0,25 pm to 5 pm, for example 1 pm or 2 pm. However, although the aluminium or copper back-side stress buffer layer 43 slightly buffers the stress when using Cu-based lead frames, the incorporation of Al or Cu (or other metals) in the back-side metal layer 40 stack complicates the deposition process of the metals and usually causes significant burr formation during dicing of the wafer, as said back-side stress buffer layers 43 are prone to burr formation. In case the burr formation is too strong, the bonding layer structure 30 is not in sufficient contact with the lead frame body 20. This causes incomplete die attach of fly dies. On the other hand, skipping the back-side stress buffer layer 43 causes occurrence of die cracks.

[0067] Therefore, there is a need to provide a solution allowing for better delamination performance, metal burr elimination and minimizing die crack risk during eutectic die bonding process.

[0068] Therefore, according to one aspect of the disclosure there is provided a lead frame having a lead frame body 20 coated with a dual soft metal layer plating 50, the dual metal layer plating 50 comprising a stress buffer layer 51 coupled to the lead frame body 20 and an eutectic bond contact layer 52 arranged on top of said stress buffer layer 51 and covering said stress buffer layer 51 . The lead frame body 20 having said dual layer plating 50 applied is shown in Figure 2. The stress buffer layer 51 is a lower layer, in direct contact with the lead frame body 20, whereby the cladding layer 52 is an upper layer, arranged on top of the stress buffer layer 51. The stress buffer layer 51 has an ability to form eutectic or diffusion bonding with the bonding layer structure 30 - respectively, eutectic bond in the case of the eutectic alloy 31 or diffusion bond in the case of diffusion bonding layers 32, 33.

[0069] According to another aspect of the disclosure there is provided a semiconductor package comprising the lead frame, the lead frame having the lead frame body 20 with said dual soft metal layer plating 50. The arrangement of the lead frame body 20 having said dual layer plating 50 applied, with the semiconductor die 10 coupled through the bonding layer structure 30 achieved by a layer of the eutectic alloy 31 , as shown in Fig. 3A, or achieved by the first diffusion bonding layer 32 and the second diffusion bonding layer 33, as shown in Figure 3B.

[0070] The semiconductor die 10 of the semiconductor package may optionally have the back-side metal layer 40 stack applied on its surface facing the bonding layer structure 30, as shown in Figure 4. The back-side metal layer 40 stack acts as a contact layer and diffusion barrier.

[0071] Moreover, the semiconductor package may have the back-side stress buffer layer 43 arranged in the back-side metal layer 40 stack, as described with reference to Fig. 1 D. However, the presence of such a back-side stress buffer layer 43 may cause burr formation.

[0072] The presence of the dual layer plating 50 according to the disclosure reduces die stress below critical level and minimizes the die crack risk during eutectic bonding process.

[0073] When the stack (i.e. the layers of the semiconductor package as described above) is assembled, the cladding layer 52 faces the first diffusion bonding layer 32 of the bonding layer structure 30. Therefore, the cladding layer 52 may be referred to as an eutectic bonding contact layer. As mentioned above, the first diffusion bonding layer 32 may be a tin layer.

[0074] The proposed dual layer plating 50 puts the stress buffer capability into the lead frame body 20, such that the silicon semiconductor die 10 back-side metal layer 40 stack must only provide an ohmic contact and have coupling ability to the eutectic soft solder. The coverage of the stress buffer layer 51 in the lead frame body 20 with the eutectic bond contact layer 52 ensures high adhesion of the package epoxy mould compound, also referred to as encapsulant (not shown).

[0075] The stress buffer layer 51 reduces stress and thus eliminates die crack formation during eutectic bonding process.

[0076] The eutectic bond contact layer 52 is arranged on top of the stress buffer layer 51 and allows to form intermetallic compounds with the first diffusion bonding layer 32 of the bonding layer structure 30 and allows to ensure reliable adhesion of encapsulant (not shown).

[0077] To be effective in stress buffering, the stress buffer layer 51 should be a ductile material. This is due to that the stress buffer layer 51 has to be plastically deformable to effectively buffer stress. Preferably, the stress buffer layer 51 has ability to deform plastically to more extent than the Cu-based lead frame body 20 (and the second diffusion bonding layer 33 if made of Cu).

[0078] Ductility is a material property that measures a material's ability to deform plastically under tensile stress without breaking. In other words, ductility indicates how much a material can stretch or elongate before failure. Materials with high ductility (such as copper and aluminium) can undergo large plastic deformation, whereas brittle materials like ceramics and glass exhibit little to no plastic deformation.

[0079] Ductility may be expressed in percent elongation (%EL). Percent elongation measures the increase in length (strain) of a material under tensile stress before failure and is expressed as percentage as: if — Ln

[0080] %EL = — - X 100 io where Lfstands for final gauge length after fracture, and Lostands for original gauge length.

[0081] The length may be replaced by a reduction of the cross-sectional area of the material (%RA). Then, the value obtained is referred to as percent reduction of area: 100 where Afstands for cross-sectional area at the fracture, and Lostands for original cross- sectional area.

[0082] A higher %EL or %RA indicates a more ductile material. Percent elongation is a straightforward measure but depends heavily on the geometry and gauge length of the test specimen.

[0083] A significant plastic deformation before fracture, i.e. the percent elongation for ductile materials, according to the literature, denotes 5% - for example according to Shigley's Mechanical Engineering Design (Budynas, Richard G., Shigley's Mechanical Engineering Design — 10th ed., p. 233., 2015).

[0084] The ductility index, by incorporating normalized or comparative values, can provide more insight into the material's behaviour in specific design contexts or compared to benchmarks. Thus, while the ductility index is often derived from percent elongation, it refines the raw data for practical engineering comparisons. In most cases, the ductility index is directly proportional to percent elongation. Materials with higher percent elongation exhibit higher ductility indices, indicating greater ability to deform plastically before fracture. A simple form of ductility index can be expressed as:

[0085] %EL

[0086] Ductility Index = — - - - —

[0087] Reference value where the "Reference value" could be a benchmark %EL for a specific application or material class. Some approaches normalize percent elongation to make comparisons across materials, especially in cases where absolute values vary greatly due to testing conditions or geometry. This provides a dimensionless index that highlights relative ductility compared to a standard material.

[0088] The ductility index can also be calculated using the Poisson's ratio (v) in certain cases, as Poisson's ratio defines the material properties by measuring the ratio of lateral strain to axial strain under uniaxial stress. In other words, Poisson’s ratio is the ratio of the relative contraction strain (transverse, lateral or radial strain) normal to the applied load, to the relative extension strain (axial strain) in the direction of the applied load. Strain is defined as deformation of a solid due to stress.

[0089] Poisson's ratio (v) may be defined as: lateral strain Etv = - — - : — = — axial strain £t

[0090] The ductility index can be qualitatively related to Poisson's ratio because materials with higher Poisson's ratios tend to exhibit greater plastic deformation before failure. A higher Poisson's ratio suggests that the material has a better ability to redistribute stress, allowing for more significant deformation (i.e., higher ductility). A lower Poisson's ratio indicates less capacity for plastic deformation, making the material more prone to brittle failure. Ductile materials typically have higher Poisson's ratios, i.e. v > 0.3, typically v = 0,33 to 0,5. Not ductile (brittle) materials have lower Poisson's ratios, i.e. v < 0.3, typically v = 0,1 to 0,25.

[0091] Axial (or longitudinal) strain E(can be expressed as E(= y, where E(is longitudinal or axial strain, dl is change in length, L is initial length. Lateral (or contraction or transverse or radial) strain can be expressed as Et= where Etis transverse, lateral or radial strain, dr is change in radius, r is initial radius. The above equations can be combined to:

[0092] While no universal equation directly relates Poisson's ratio to ductility index, the ductility index and Poisson's ratio are related qualitatively.

[0093] When conducting the tensile stress test, some parameters could affect the results of the test. It’s not only vital to know what these parameters are but also to keep them uniform to ensure the most accurate results. Gage length is a critical parameter to observe, when conducting a tensile stress test. However, as the gage length increases, the value of elongation becomes less dependent on the gage length. The cross-sectional area of a specimen has a direct effect on the elongation measures. It’s important to keep the specimen dimensions uniform during the test to obtain accurate results. A higher or faster strain will have an adverse effect on ductility hence decreasing the elongation value. Brittle materials are more sensitive to strain rate and the elongation values decrease, as strain rate increases across the board.

[0094] Therefore, the exact numeric values of ductility, calculated or experimentally obtained, may slightly vary. Nevertheless, the relative differences between ductility of materials remain the same. In other words, the order of ductility values among elements or alloys or other materials remains the same.

[0095] The stress buffer layer 51 should also be made of material which is malleable. Ductility and malleability are both properties of materials related to their ability to deform under stress, but they refer to deformation under different types of forces. Ductility is the ability of a material to undergo significant plastic deformation under tensile (pulling) stress before fracture, and is typically measured by %EL or %RA during a tensile test. Malleability is the ability of a material to deform plastically under compressive (squeezing) stress without cracking. Materials with high malleability can be hammered or rolled into thin sheets. Malleability is not as formally defined as ductility but observed through processes like rolling, forging, or stamping.

[0096] Another suitable definition of the stress buffer layer 51 refers to its Young’s modulus and yield stress.

[0097] In the present solution, different thermal expansion of silicon and copper needs to be buffered with as little stress as possible.

[0098] Therefore, the Young’s modulus of the stress buffer layer 51 should be lower than the Young’s modulus of copper.

[0099] Young’s modulus (E) is a measure of a material's stiffness or rigidity in the elastic deformation range. It is defined as the ratio of stress (a) to strain (e) in the linear region of the stress-strain curve: a E = - £

[0100] This property characterizes how much a material deforms under a given load within its elastic limit. Young’s modulus is determined through tensile or compressive testing and varies based on factors such as specimen purity, temperature, and measurement accuracy. However, it is intrinsic to the material and primarily depends on atomic bonding.

[0101] Typically, copper has a Young’s modulus of approximately 110-130 GPa (for example, 127 GPa). Its high modulus indicates it resists deformation in its elastic range.

[0102] Additionally or alternatively, the yield stress of the stress buffer layer 51 should also be lower than the yield stress of copper. Yield stress (o-y) is the stress at which a material begins to deform plastically (permanent deformation starts). Beyond this point, permanent deformation occurs even if the applied stress is removed. Yield stress depends on dislocation motion, grain structure, and processing. In practice, yield stress is often determined using a 0.2% offset method, where a line parallel to the elastic portion of the stress-strain curve is drawn to define the yield point.

[0103] The yield stress of pure copper is approximately 70-100 MPa, for example 85 MPa.

[0104] Materials with a high Young’s modulus often have strong atomic bonds, which can also contribute to higher yield stress.

[0105] The stress buffer layer 51 , to be effective as the stress buffer, should then have the Young’s modulus lower than copper, and preferably also lower yield stress than copper, what means that it should be less stiff and yield quicker than copper. Although these properties are determined experimentally, in the same conditions the relative differences between said properties of various materials are constant and differentiable. Therefore, the suitable materials for the stress buffer layer 51 may be appointed. Moreover, for many materials these properties are relatively invariant, because they depend on the atomic bonding and crystal structure, which are intrinsic to the material and do not change significantly with external conditions.

[0106] Additionally, it is preferable if the ductility of the stress buffer layer 51 is higher than 0,3, when defined using Poisson’s ratio.

[0107] Aluminium is one of the possible materials for use in the stress buffer layer 51. Aluminium has a yield stress of approx. 50 MPa (or even in the range of 15 to 20 MPa for pure annealed aluminium) and an elastic constant (Young’s modulus) typically approx. 70 GPa.

[0108] Another suitable material for use as the stress buffer layer is silver, having Young’s modulus (YM) of approx. 83 GPa, and yield stress (YS) of approx. 55 MPa.

[0109] Other suitable metals for stress buffer layer 51 include, for example: gold (YM: approx. 79 GPa; YS: approx. 35 MPa) or palladium (YM: approx. 121 GPa; YS: approx. 70 MPa). Other appropriate metals may be selected from a group comprising, for example, vanadium (V), platinum (Pt), niobium (Nb) or lead (Pb). The stress buffer layer 51 is not limited to pure elements and may be made of their alloys, which are sometimes more stiff compared to the pure materials due to the structure of their crystal lattice.. Preferably, the stress buffer layer has even higher ductility than pure Cu.

[0110] Preferably, the stress buffer layer 51 also has higher melting temperature than tin, i.e. melting temperature exceeding 231 , 9°C. Therefore, although tin is sufficiently ductile to serve as the stress buffer layer 51 , using tin as the base material for the stress buffer layer 51 introduces a risk that it would be consumed in the process of eutectic bonding. Heat applied during eutectic bonding process could cause tin to react with copper (present in the second diffusion bonding layer 33 and / or in the cladding layer 52) to form CuSn intermetallic compounds. Therefore, there may not be enough remaining tin in the stress buffer layer 51 (i.e. the stress buffer layer 51 will not be thick enough after reaction). Furthermore, CuSn intermetallics lack the necessary ductility to ensure buffering properties.

[0111] The exemplary materials mentioned above, which may be used for the stress buffer layer 51 , have preferably higher melting temperatures than tin, which are, approximately: 961 , 8°C for Ag; 1064°C for Au; 660, 3°C for Al; 1555°C for Pd; 1910°C for V; 1768°C for Pt; 2477°C for Nb; 327, 5°C for Pb.

[0112] The cladding layer 52, also referred to as eutectic bonding contact layer, arranged on top of the stress buffer layer 51 is made of a material allowing to form intermetallic compounds with the first diffusion bonding layer 32 of the bonding layer structure 30. If the eutectic alloy 31 is used, the cladding layer 52 has the ability to form eutectic boding.

[0113] In the exemplary embodiment, where the first diffusion bonding layer 32 comprises tin (or other materials such as bismuth or antimony), the cladding layer 52 may comprise for example copper, silver or palladium. Another possible materials of the cladding layer 52 may be selected from nickel (Ni), iron (Fe), gold (Au), manganese (Mn) or cobalt (Co).

[0114] The thickness of the stress buffer layer 51 may be in the range from 0,5 pm to 3 pm, for example 2 pm.

[0115] The thickness of the cladding layer 52 may be in the range from 0,5 pm to 3 pm, for example 2 pm. In general, the cladding layer 52 should be sufficiently thick to avoid its entire consumption during soldering process.

[0116] Various exemplary combinations of the specific materials chosen for the stress buffer layer 51 and the bond contact layer 52 are possible. These layers may comprise the materials selected from the examples which have been provided above. However, the stress buffer layer 51 and the cladding layer 52 should comprise different materials from one another, i.e. if the stress buffer layer 51 is made of Ag, the cladding layer 52 is not made of Ag.

[0117] In one specific exemplary variant, the stress buffer layer 51 comprises Ag and the cladding layer 52 comprises Cu.

[0118] In another specific exemplary variant, the stress buffer layer 51 comprises Ag and the cladding layer 52 comprises Pd.

[0119] In another specific exemplary variant, the stress buffer layer 51 comprises Al and the cladding layer 52 comprises Cu.

[0120] In another specific exemplary variant, the stress buffer layer 51 comprises Al and the cladding layer 52 comprises Ag.

[0121] In another specific exemplary variant, the stress buffer layer 51 comprises Al and the cladding layer 52 comprises Pd.

[0122] In another specific exemplary variant, the stress buffer layer 51 comprises Au and the cladding layer 52 comprises Cu.

[0123] In another specific exemplary variant, the stress buffer layer 51 comprises Au and the cladding layer 52 comprises Ag.

[0124] In another specific exemplary variant, the stress buffer layer 51 comprises Au and the cladding layer 52 comprises Pd.

[0125] In another specific exemplary variant, the stress buffer layer 51 comprises Pt and the cladding layer 52 comprises Cu. In another specific exemplary variant, the stress buffer layer 51 comprises Pt and the cladding layer 52 comprises Ag.

[0126] In another specific exemplary variant, the stress buffer layer 51 comprises Pt and the cladding layer 52 comprises Pd.

[0127] To measure actual stress buffering capability of the lead frame body 20 with dual layer plating 50, the exemplary stacks according to the state of the art and according to the present disclosure were analysed in more detail. The term “stack” refers to the lead frame body 20 coupled with the semiconductor die 10 by bonding layer structure 30 and (optionally) back-side metal layer 40 according to the state of the art. In the present disclosure, the stack comprises the lead frame body 20 coated with the dual layer plating 50 as described above. The simulation results, which are shown in Fig. 5, confirm actual advantage of the lead frame according to the disclosure in comparison to known solutions.

[0128] The first stack A (reference state of the art, as in Fig. 1C) comprised the following layers in the following order: a lead frame body 20 made of Cu and having a thickness of 0,25 mm; a first diffusion bonding layer 32 made of Sn and having a thickness of 2 pm; a second diffusion bonding layer 33 made of Cu and having a thickness of 0,5 pm; a first back-side metal layer 41 made of NiV having a thickness of 0,25 pm; a second back-side metal layer 41 made of Ti and having a thickness of 0,1 pm; and a silicon die 10.

[0129] The second stack B (reference state of the art, as in Fig. 1 D) was arranged similarly as the first stack A, but it comprised an additional back-side stress buffer layer 43 made of Al, arranged between the first back-side metal layer 41 and the second back-side metal layer 42, and having a thickness of 1 ,5 pm.

[0130] The third stack C (according to the present disclosure, as in Fig. 4) comprised the following layers in the following order: a lead frame body 20 made of Cu and having a thickness of 0,25 mm; a stress buffer layer 51 made of Ag and having a thickness of 2 pm; an cladding layer 52 made of Cu and having a thickness of 2 pm; a first diffusion bonding layer 32 made of Sn and having a thickness of 2 pm; a second diffusion bonding layer 33 made of Cu and having a thickness of 0,5 pm; a first back-side metal layer 41 made of NiV having a thickness of 0,25 pm; a second back-side metal layer 42 made of Ti and having a thickness of 0,1 pm; and a silicon die 10. The fourth stack D (according to the present disclosure, as in Fig. 4) was arranged similarly as the third stack C, but the stress buffer layer 51 comprised Al instead of Ag.

[0131] The simulation results are presented in Fig. 5, which shows the die stress in MPa (1stprincipal stress) for each stack A, B, C and D, at the die corner of the silicon semiconductor die 10. The dotted line indicates critical stress limit for silicon die, which is approx. 240 MPa. The critical stress limit is the tensile stress limit which is known to form die cracks in silicon.

[0132] Looking at the first principal stress at the corner of the silicon semiconductor die 10, it was confirmed that the stress of the stack A exceeds the critical limit of tensile stress significantly. Stack B, comprising a back-side stress buffer layer 43 made of Al, disposed between first back-side metal layer 41 and second back-side metal layer 42, reached the limit of the silicon semiconductor die 10 capability, and even exceeded this limit. Stack C, in which the lead frame body 20 had the dual layer plating 50 applied, where the dual layer plating 50 comprised the stress buffer layer 51 made of Ag and the cladding layer 52 made of Cu, exhibited the best properties among the compared stacks. Stack C achieved a safe stress level in the silicon semiconductor die 10, slightly above 150 MPa. Stack D, comprising the stress buffer layer 51 made of Al and the cladding layer 52 made of Cu, also exhibited good stress buffering properties and achieved a safe stress level in the die 10, slightly above 200 MPa. Therefore, the experiment has shown that dual metal layer plating 50 of the lead frame body 20 significantly reduces die stress below critical level and thus minimizes the die crack risk during eutectic bonding process.

[0133] Additionally, it has to be emphasized that stacks C and D, with the lowest stress levels, have a back-side metal layer 40 without soft back-side stress buffer layer 43 as in stack B. This lowers the formation of metal burrs upon dicing, which is critical to the eutectic die bonding.

[0134] The lead frame may be provided with full (two-sided) dual layer plating 50 or with partial (one-sided) dual layer plating 50, whereby the partial dual layer plating 50 may be uniform or may be achieved by spot plating, which is a technique known in the state of the art. Figures 6, 7 and 8 show the semiconductor assembly comprising lead frame body 20, semiconductor die 10 coupled to the lead frame by bonding layer structure 30, whereby the lead frame body 20 has dual layer plating 50 applied. The semiconductor die 10 is connected to the lead frame body 20 by conductive bonding 60. Conductive bonding 60 may be for example wire bonding using bond wires, whereby the bond wires are thin wires, often made of gold, copper or aluminum. Conductive bonding 60, in another example, may be provided in the form of an electrically conductive bond clip, such as copper clip. The semiconductor package also comprises an encapsulant 70, which is shown in Figures 6, 7, 8 with a dashed line. Figs. 6, 7, 8 show the contouring of the encapsulant 70 schematically, to show its exemplary arrangement.

[0135] In one example, shown in Fig. 8, the lead frame body 20 has full two-sided dual layer plating 50, i.e. the stress buffer layer 51 and the cladding layer 52 cover whole lead frame body 20, such that both opposite surfaces 21 , 22 of the lead frame body 20 are plated (covered). Therefore, in case of two-sided dual layer plating 50, a first surface 21 of the lead frame body 20 is plated with said dual layer plating 50, as well as a second surface 22 of the lead frame body 20, arranged oppositely to said first surface 21 , is covered with said dual layer plating 50. The first surface 21 of the lead frame body 20 is a die attach surface, i.e. this first surface 21 of the lead frame body 20 is intended to face the semiconductor die 10 after assembly. The second surface 22 of the lead frame body 20, after assembly, faces away from the semiconductor die 10.

[0136] In another example, shown in Fig. 7, the lead frame body 20 has one-sided dual layer plating 50, i.e. the stress buffer layer 51 and the cladding layer 52 cover only the first surface 21 of the lead frame body 20. Therefore, only the first surface 21 , to which the semiconductor die 10 is coupled, has said dual layer plating 50 applied (as explained above, the first surface 21 , after assembly, faces the semiconductor die 10). Only a part of said first surface 21 may be covered by dual layer plating 50, i.e. part of the first surface 21 to which the semiconductor die 10 is coupled (through the bonding layer structure 30). In Fig. 7 an uniform one-sided dual layer plating is shown.

[0137] In another example, shown in Fig. 6, the lead frame body 20 has one-sided dual layer spot plating 50, i.e. the stress buffer layer 51 and the eutectic bond contact layer 52 cover only the first surface 21 of the lead frame body 20, but limited to the die attach area. In contrast to the example shown in Fig. 7, the dual layer plating 50 is in the form of a spot on the leadframe, such that the first surface 21 of the lead frame body 20 has the stress buffer layer 51 and the eutectic bond contact layer 51 applied only to a selected area of the lead frame body 20. Thus, spot plating means that only a spot (part) of the lead frame body 20 is plated. This is performed through a rubber mask.

[0138] The two possible arrangements, i.e. two-sided dual layer plating 50 or one-sided dual layer plating 50, imply two possible method flows of manufacturing of the lead frame body 20 according to the disclosure. Thus, another aspect of the disclosure is a method of manufacturing of the lead frame body 20. In the first manufacturing method flow, applying of dual layer plating 50 is performed prior to stamping, while in the second manufacturing method flow, applying of dual layer plating 50 is performed after stamping (also referred to as punching).

[0139] Stamping is a semiconductor manufacturing process step, more precisely a lead frame manufacturing process step, used to shape lead frames from a thin sheet of metal using a press. Typically, a metal sheet, which is a pre-form of the lead frame, is fed into a stamping machine, for example high-speed stamping machine. The metal sheet is typically in a form of a roll. The metal sheet is pierced along both edges to create indexing holes that position the metal sheet during further processing. The location holes are used to advance the metal sheet strip through the stamping machine. The machine's dies cut and shape (stamp) the sheet into the desired lead frame pattern. Die-and-punch sets specific to the desired lead frame geometry are used. The process is typically accomplished by a series of stamping operations that progressively approach the final lead frame geometry, the number of steps being entirely dependent on the complexity of the geometry of the lead frame.

[0140] Therefore, the creation of the dual layer plating 50 can be done prior to or after the stamping process.

[0141] Applying of the dual layer plating performed prior to stamping is applicable to obtain one-sided dual layer plating 50 or two-sided dual layer plating 50. In such a process flow, the lead frame body 20 pre-form, i.e. metal sheet, is provided. Then, the lead frame body

[0142] 20 pre-form metal sheet’s die attach surface, i.e. the first surface 21 , is plated with stress buffer layer 51. Alternatively, both opposite surfaces 21 , 22 of the lead frame body 20 preform metal sheet’s are plated with stress buffer layer 51 . Then, the stress buffer layer 51 (applied on the lead frame’s 20 pre-form metal sheet’s die attach surface or on both opposite surfaces 21 , 22) is plated with cladding layer 52. Finally, the metal sheet is stamped to obtain the final lead frame body 20 geometry.

[0143] Alternatively, when applying of the dual layer plating 50 is performed prior to stamping to obtain one-sided dual layer plating 50, one-sided dual layer plating 50 may be provided by spot plating, as explained above.

[0144] Applying of the dual layer plating 50 performed after stamping is applicable to obtain one-sided dual layer plating 50 or two-sided dual layer plating 50. One side plating is possible using the spot plating technique, but applied to the full lead frame body 20. In such a process flow, firstly, the lead frame body 20 pre-form metal sheet is provided. The metal sheet is stamped to obtain the final lead frame body 20 geometry. Then, the first surface

[0145] 21 of the lead frame body 20 is plated with stress buffer layer 51 .Alternatively, the whole lead frame body 20, i.e. its first surface 21 and its second surface 22, are plated with stress buffer layer 51. Then, the stress buffer layer 51 , already applied to the first surface 21 of the lead frame body 20 or to the first surface 21 and to the second surface 22 of the lead frame body 20, is plated with cladding layer 52.

[0146] The dual layer plating 50 may be applied for example by immersing the lead frame body 20 (or its pre-form) in an electroplating solution with plating anode, and applying a current. Another possible method of plating is electroless plating.

[0147] LIST OF REFERENCE NUMERALS USED

[0148] 10 semiconductor die

[0149] 20 lead frame body

[0150] 21 first surface of the lead frame

[0151] 22 second surface of the lead frame

[0152] 30 bonding layer structure

[0153] 31 eutectic alloy

[0154] 32 first diffusion bonding layer

[0155] 33 second diffusion bonding layer

[0156] 40 back-side metal layer stack

[0157] 41 first back-side metal layer

[0158] 42 second back-side metal layer

[0159] 43 back-side stress buffer layer

[0160] 50 dual layer plating

[0161] 51 stress buffer layer

[0162] 52 cladding layer

[0163] 60 conductive bonding

[0164] 70 encapsulant

Claims

CLAIMS1. A lead frame for semiconductor package, comprising a lead frame body made of copper or copper alloy and a dual layer plating formed on the lead frame body, the lead frame body having a first surface for attaching a semiconductor die and a second surface opposite to said first surface, wherein the dual layer plating comprises: a metallic, stress buffer layer directly coupled to the lead frame body, and a cladding layer covering the stress buffer layer, made of metal able to form a eutectic or diffusion bond.

2. The lead frame according to claim 1 , wherein the cladding layer is made of metal able to form intermetallic compounds with tin.

3. The lead frame according to claim 1 or 2, wherein the Young’s modulus of the stress buffer layer is lower that the Young’s modulus of pure copper.

4. The lead frame according to claim 1 or 2 or 3, wherein the yield stress of the stress buffer layer is lower than the yield stress of pure copper.

5. The lead frame according to claim 1 or 2 or 3 or 4, wherein the stress buffer layer is made of aluminium.The lead frame according to claim 1 or 2 or 3 or 4, wherein the stress buffer layer is made of silver.

7. The lead frame according to claim 1 or 2 or 3 or 4, wherein the stress buffer layer is made of palladium.The lead frame according to claim 1 or 2 or 3 or 4, wherein the stress buffer layer is made of gold.

9. The lead frame according to claim 1 or 2 or 3 or 4, wherein the stress buffer layer is made of vanadium or platinum or niobium or lead.

10. The lead frame according any of the preceding claims, wherein the ductility of the stress buffer layer expressed with Poisson’s ratio v is higher than 0.3.

11. The lead frame according to any of the preceding claims, wherein the melting temperature of the stress buffer layer is higher than 231 , 9°C.

12. The lead frame according to any of the preceding claims, wherein the cladding layer is made of copper.

13. The lead frame according to claim 1 or 2 or 3 or 4 or 5 or 7 or 8 or 9 or 10 or 11 , wherein the cladding layer is made of silver.

14. The lead frame according to claim 1 or 2 or 3 or 4 or 5 or 6 or 8 or 9 or 10 or 11 , wherein the cladding layer is made of palladium.

15. The lead frame according to claim 1 or 2 or 3 or 4 or 5 or 6 or 7 or 9 or 10 or 11 , wherein the cladding layer is made of gold.

16. The lead frame according to any one of the claims from 1 to 11 , wherein the cladding layer is made of nickel or iron or manganese or cobalt.

17. The lead frame according to any of the preceding claims, wherein the dual layer plating covers the first surface of the lead frame body and the second surface of the lead frame body.

18. The lead frame according to any of the preceding claims, wherein the dual layer plating covers the first surface of the lead frame body.

19. The lead frame according to claim 18, wherein the dual layer plating covers only the die pad area of the lead frame body available for die bonding.

20. The lead frame according to any of the preceding claims, wherein the stress buffer layer has a thickness of at least 0.5 pm.

21. The lead frame according to any of the preceding claims, wherein the cladding layer has a thickness of at least 0.5 pm.

22. A semiconductor package comprising: a semiconductor die; a lead frame according to any of the claims from 1 to 21 ;a bonding layer structure coupling the semiconductor die to the lead frame, wherein the bonding layer structure is coupled to the cladding layer of the dual layer plating.

23. A semiconductor package according to claim 22, wherein the bonding layer structure comprises eutectic solder.

24. A semiconductor package according to claim 22, wherein the bonding layer structure comprises a first diffusion bonding layer made of tin and a second diffusion bonding layer made of material able to form intermetallic compounds with tin, and wherein the first diffusion bonding layer is coupled to the cladding layer of the dual layer plating.

25. A semiconductor package according to claim 24, wherein the second diffusion bonding layer comprises copper.

26. A semiconductor package according to claim 24, wherein the second diffusion bonding layer comprises silver.

27. A semiconductor package according to any one of the claims from 22 to 26, wherein at least one back side metal layer is arranged between the semiconductor die and the bonding layer structure.

28. A method of manufacturing of a lead frame is provided, comprising: providing a metal sheet made of copper or copper alloy, being a preform of a lead frame body; plating at least a surface intended to be a die attach surface of a first surface of the lead frame, the first surface being intended for attaching a semiconductor die, with a stress buffer layer; plating the stress buffer layer with a cladding layer made of metal able to form eutectic or diffusion bond stamping the plated metal sheet to obtain final lead frame geometry.

29. The method according to claim 28, wherein it comprises the step of plating of the whole first surface of the lead frame, the first surface being intended for attaching a semiconductor die.

30. The method according to claim 28 or 29, wherein it comprises the step of plating of a second surface, arranged oppositely to the first surface, with the with stress buffer layer.

31. A method of manufacturing of a lead frame is provided, comprising: providing a metal sheet made of copper or copper alloy, being a preform of a lead frame body; stamping the plated metal sheet to obtain final lead frame geometry; plating at least a surface intended to be a die attach surface of a first surface of the lead frame, the first surface being intended for attaching a semiconductor die, with a stress buffer layer; plating the stress buffer layer with a cladding layer made of metal able to form eutectic or diffusion bond.

32. The method according to claim 31 , wherein it comprises the step of plating of the whole first surface of the lead frame, the first surface being intended for attaching a semiconductor die.

33. The method according to claim 31 or 32, wherein it comprises the step of plating of a second surface, arranged oppositely to the first surface, with the with stress buffer layer.

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