Analog to digital converter

The sigma-delta ADC with chopper elements and feedback loop enhances dynamic range and reduces noise and power consumption, addressing the limitations of existing ADCs for neural recording and stimulation.

WO2026125875A1PCT designated stage Publication Date: 2026-06-18THE UNIV COURT OF THE UNIV OF EDINBURGH
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
THE UNIV COURT OF THE UNIV OF EDINBURGH
Filing Date
2025-12-11
Publication Date
2026-06-18

AI Technical Summary

⚠Technical Problem

Existing analog to digital converters (ADCs) face challenges such as saturation, insufficient dynamic range, high power consumption, large channel areas, and noise issues, particularly in applications like neural recording and stimulation, which require high input impedance, low noise, and scalable design.

⚗Method used

A sigma-delta ADC with a continuous time/discrete time hybrid configuration, incorporating chopper elements and a feedback loop with a DAC, which includes a compensation feedback input, and a high-pass filter to reduce noise and increase dynamic range, while maintaining low power consumption and small footprint.

🎯Benefits of technology

The solution provides an ADC with improved dynamic range, low noise, high input impedance, and reduced power consumption, suitable for neural recording and stimulation systems, addressing the limitations of existing ADCs.

✦ Generated by Eureka AI based on patent content.

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Abstract

An analog to digital converter comprising a first input for receiving a first input signal, a first output for providing an output signal, an integrator element comprising a first integrator input coupled to the first input, and a first integrator output, a quantizer comprising a quantizer input coupled to the first integrator output, and a quantizer output coupled to the first output, a feedback element comprising a first filter element having a first filter input coupled to the first output and a first filter output coupled to the first integrator input, and a first digital to analog converter (DAC) having a first DAC input coupled to the first filter output, and a first DAC output coupled to a compensation feedback input of the integrator element. In some examples, the first filter element is a tap finite impulse response filter and the first DAC provides feedback compensation and excess loop delay compensation to the integrator element.
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