SiC EPITAXIAL WAFER, AND METHOD FOR MANUFACTURING SiC EPITAXIAL WAFER
By correcting bonding defects with specific criteria in SiC epitaxial wafers, interfacial dislocations are minimized, ensuring high-quality SiC epitaxial wafers for semiconductor applications.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- RESONAC CORP
- Filing Date
- 2024-12-09
- Publication Date
- 2026-06-18
AI Technical Summary
SiC epitaxial wafers often contain interfacial dislocations and defects due to bonding issues between high-quality SiC single-crystal substrates and lower-cost base substrates, which can lead to device failures.
The method involves bonding a SiC single-crystal substrate to a base substrate, identifying and correcting bonding defects with an aspect ratio greater than 1.5 and area of 0.02 mm², and ensuring no specific defective areas are present to minimize interfacial dislocations.
This approach reduces the likelihood of interfacial dislocations, resulting in high-quality SiC epitaxial wafers suitable for semiconductor devices, even when using lower-cost base substrates.
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