SiC EPITAXIAL WAFER, AND METHOD FOR MANUFACTURING SiC EPITAXIAL WAFER

By correcting bonding defects with specific criteria in SiC epitaxial wafers, interfacial dislocations are minimized, ensuring high-quality SiC epitaxial wafers for semiconductor applications.

WO2026126303A1PCT designated stage Publication Date: 2026-06-18RESONAC CORP

Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
RESONAC CORP
Filing Date
2024-12-09
Publication Date
2026-06-18

AI Technical Summary

Technical Problem

SiC epitaxial wafers often contain interfacial dislocations and defects due to bonding issues between high-quality SiC single-crystal substrates and lower-cost base substrates, which can lead to device failures.

Method used

The method involves bonding a SiC single-crystal substrate to a base substrate, identifying and correcting bonding defects with an aspect ratio greater than 1.5 and area of 0.02 mm², and ensuring no specific defective areas are present to minimize interfacial dislocations.

🎯Benefits of technology

This approach reduces the likelihood of interfacial dislocations, resulting in high-quality SiC epitaxial wafers suitable for semiconductor devices, even when using lower-cost base substrates.

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Abstract

This SiC epitaxial wafer comprises: a base substrate; an SiC single crystal substrate layer bonded to the base substrate; and an SiC epitaxial layer laminated on the SiC single crystal substrate layer. The SiC epitaxial wafer does not have, among bonding defects in which the SiC single crystal substrate layer has not been formed on the base substrate, a specific defect that satisfies both a first condition and a second condition. The first condition is that the aspect ratio obtained by dividing the length of the long side, of the smallest quadrangle circumscribing the bonding defect, by the length of the short side of the same is 1.5 or greater. The second condition is that the area of the quadrangle is 0.02 mm2 or greater.
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