Bias circuit and variable gain amplifier

Abstract

This bias circuit includes: a variable current source for outputting a variable current; a constant current source for outputting a fixed current; and a voltage generation unit for generating, on the basis of the variable current and the fixed current, a first bias voltage for changing the current of a first supply destination at a positive change rate and a second bias voltage for changing the current of a second supply destination at a negative change rate, or a first bias voltage for changing the current of a first supply destination at a negative change rate and a second bias voltage for changing the current of a second supply destination at a positive change rate.

Description

Bias Circuit and Variable Gain Amplifier 【0001】 The present invention relates to a bias circuit and a variable gain amplifier. This application claims priority based on Japanese Patent Application No. 2024-218503 filed in Japan on December 13, 2024, and incorporates its content herein by reference. 【0002】 Patent Document 1 discloses an exponential function generator and a variable gain amplifier using the same. This variable gain amplifier includes input means for amplifying a differential input signal and outputting a voltage signal having a limited fixed gain value, and first and second curve generation means for sampling each of the input control voltages and generating signals that change with different slopes. It also includes exponential function generation means for adding the signals output from the first and second curve generation means and outputting a signal having an approximate exponential function value, control current generation means for generating an exponential control current in response to the output signal of the exponential function generation means, and at least one or more variable voltage amplification means for variably amplifying the voltage signal output from the input means in response to the exponential control current, and is implemented by a CMOS process. 【0003】 Further, Patent Document 2 discloses an amplifier system including a control variable gain amplifier that limits gain variation while allowing changes in supply voltage, ambient temperature, and / or manufacturing process. In this amplifier system, the variable gain amplifier has a differential pair transistor, a degeneration element connected to the differential pair transistor, and a collector load of the same type as the degeneration element and connected to the differential pair transistor, and the gain of the variable gain amplifier is determined by the physical dimension ratio of the collector load to the degeneration element at a differential input control voltage equal to zero volts. 【0004】 Japanese Patent Laid-Open No. 2003-198290, Japanese Patent Publication No. 2007-500966 【0005】 In the above background art, in order to realize a variable gain amplifier with high linearity, a plurality of amplifiers are paralleled and combined, and the linearity is improved by the combined output obtained by synthesizing the outputs of each amplifier. However, when a plurality of amplifiers are paralleled and combined, it is necessary to prepare a bias circuit for each amplifier, so the circuit area increases. 【0006】 The present invention has been made in view of the above circumstances and aims to provide a bias circuit and a variable gain amplifier that can suppress an increase in circuit area. 【0007】 A bias circuit according to a first aspect of the present invention includes a variable current source that outputs a variable current, a constant current source that outputs a fixed current, and a voltage generation unit that generates a first bias voltage that changes the current of a first supply destination by a positive rate of change and a second bias voltage that changes the current of a second supply destination by a negative rate of change, or a first bias voltage that changes the current of the first supply destination by a negative rate of change and a second bias voltage that changes the current of the second supply destination by a positive rate of change, based on the variable current and the fixed current. 【0008】 A bias circuit according to a second aspect of the present invention is a bias circuit according to a first aspect, wherein the voltage generation unit comprises a first current mirror circuit that uses the spun current of the variable current as a first reference current; a first output transistor that uses the difference current between the variable current and the spun current as a second reference current and constitutes a second current mirror circuit with a first supply destination transistor provided at the first supply destination; and a second output transistor that uses the difference current between the fixed current and the spun current as a third reference current and constitutes a third current mirror circuit with a second supply destination transistor provided at the second supply destination. 【0009】 A bias circuit according to a third aspect of the present invention is a bias circuit according to the first or second aspect, wherein the first supply destination is an amplifier that amplifies an input signal, and the first bias voltage sets the amplification gain of the amplifier. 【0010】 A bias circuit according to a fourth aspect of the present invention is a bias circuit according to a third aspect, wherein the second supply destination is a load unit whose first end is connected to the output terminal of the amplification unit, and the second bias voltage sets the load current flowing to the load unit. 【0011】Furthermore, a variable gain amplifier according to one aspect of the present invention comprises a bias circuit according to any of the first to fourth aspects, an amplification unit that amplifies and outputs an input signal with an amplification current set based on the first bias voltage, and a load unit whose first end is connected to the output terminal of the amplification unit and whose load current is set based on the second bias voltage. 【0012】 According to one aspect of the present invention, it is possible to provide a bias circuit and a variable gain amplifier that can suppress an increase in circuit area. 【0013】 This is a circuit diagram showing the configuration of a variable gain amplifier according to one embodiment of the present invention. This is a circuit diagram showing the detailed configuration of a bias circuit according to one embodiment of the present invention. This is a characteristic diagram showing the operation of the bias circuit and variable gain amplifier according to one embodiment of the present invention. This is a characteristic diagram showing the performance of a variable gain amplifier according to one embodiment of the present invention. 【0014】 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. As shown in Figure 1, the variable gain amplifier A according to this embodiment includes an input terminal Tin, a first transistor 1, a second transistor 2, a first ground terminal Tg1, a third transistor 3, a first bias circuit 4, a second bias circuit 5, a load circuit 6, a power supply terminal Td, a fourth transistor 7, a second ground terminal Tg2, a fifth transistor 8, a sixth transistor 9, a capacitor 10, and an output terminal Tout. 【0015】 Of the first transistor 1, second transistor 2, third transistor 3, fourth transistor 7, fifth transistor 8, and sixth transistor 9, the first transistor 1, second transistor 2, and third transistor 3 are connected in series on their output sides, as shown in the figure. In addition, the fourth transistor 7, fifth transistor 8, and sixth transistor 9 are connected in series on their output sides, separately from the first transistor 1, second transistor 2, and third transistor 3. 【0016】Of the components of the variable gain amplifier A, the first transistor 1, the second transistor 2, the third transistor 3, and the load circuit 6 constitute the amplification unit AM in this invention. As will be described in detail later, the amplification unit AM in this embodiment functions as an inverting amplifier that inverts and amplifies the input signal (high-frequency signal) of the variable gain amplifier A and outputs it from the output terminal. The amplification unit AM also corresponds to the first supply destination in this invention. 【0017】 Furthermore, the fourth transistor 7, the fifth transistor 8, the sixth transistor 9, and the capacitor 10 constitute the load section LO in the present invention. As will be described in detail later, the first end (one end) of the load section LO in this embodiment is connected to the output terminal of the amplifier section AM and functions as a load for the amplifier section AM. The load section LO also corresponds to the second supply destination in the present invention. Furthermore, the first bias circuit 4 in the variable gain amplifier A corresponds to the bias circuit according to the present invention. 【0018】 In variable gain amplifier A, input terminal Tin is connected to the gate terminal of the first transistor 1. Input terminal Tin is also connected to a signal source outside of variable gain amplifier A. A high-frequency signal of a predetermined frequency, for example, in the range of several to tens of GHz, is input to input terminal Tin from the signal source. 【0019】 The first transistor 1 is an n-type MOS transistor, as shown in the figure. The gate terminal of the first transistor 1 is connected to the input terminal Tin, the source terminal is connected to the drain terminal of the second transistor 2, and the drain terminal is connected to the source terminal of the third transistor 3. 【0020】 A high-frequency signal is input to the gate terminal of the first transistor 1 via the input terminal Tin from a signal source, and a bias voltage (amplification bias voltage) is also applied via the input terminal Tin. With the gate voltage set by the amplification bias voltage, the first transistor 1 inverts and amplifies the high-frequency signal and outputs it to the drain terminal. 【0021】Alternatively, instead of setting the gate voltage of the first transistor 1 using the amplification bias voltage supplied from the signal source, a bias circuit for setting the gate voltage of the first transistor 1 may be added to the variable gain amplifier A. In this case, only the high-frequency signal, which is an AC component, is input to the input terminal Tin from the signal source. 【0022】 The second transistor 2 is an n-type MOS transistor, similar to the first transistor 1. The gate terminal of the second transistor 2 is connected to the first output terminal of the first bias circuit 4, the source terminal is connected to the first ground terminal Tg1, and the drain terminal is connected to the source terminal of the first transistor 1. The amplified drain current Ids of the second transistor 2 is set based on the first bias voltage Vgs1 (DC voltage) input to the gate terminal from the first bias circuit 4. 【0023】 The first grounding terminal Tg1 is connected to the source terminal of the second transistor 2. Furthermore, the first grounding terminal Tg1 is connected to ground potential (GND) outside of the variable gain amplifier A. The first grounding terminal Tg1 sets the source terminal of the second transistor 2 to ground potential (GND). 【0024】 The third transistor 3 is an n-type MOS transistor, similar to the first transistor 1 and the second transistor 2. The gate terminal of the third transistor 3 is connected to the output terminal of the second bias circuit 5, the source terminal is connected to the drain terminal of the first transistor 1, and the drain terminal is connected to the first terminal of the load circuit 6, the gate and drain terminals of the sixth transistor 9, and the first terminal of the capacitor 10. The operating point of the third transistor 3 is set based on the third bias voltage Vgs3 (DC voltage) input to the gate terminal from the second bias circuit 5. 【0025】 The first transistor 1, the second transistor 2, and the third transistor 3 that constitute the amplification section AM are all amplification transistors of the same size. In other words, the first transistor 1, the second transistor 2, and the third transistor 3 are process-designed to have the same element size. 【0026】Furthermore, the combined size of the first transistor 1, the second transistor 2, and the third transistor 3 (amplifying transistors) is set to be smaller than the combined size of the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9 (load transistors) that constitute the load section LO. 【0027】 In this embodiment, the first transistor 1, second transistor 2, and third transistor 3 (amplifying transistors) constituting the amplification section AM are all n-type MOS transistors of the same size. However, other types of transistors may be used for the first transistor 1, second transistor 2, and third transistor 3. For example, p-type MOS transistors may be used for the first transistor 1, second transistor 2, and third transistor 3. 【0028】 The first bias circuit 4 has its first output terminal connected to the gate terminal of the second transistor 2. The first bias circuit 4 generates a first bias voltage Vgs1 that is variable within a predetermined voltage range and applies the first bias voltage Vgs1 to the gate terminal of the second transistor 2 as the gate bias voltage. 【0029】 In other words, the first bias circuit 4 outputs a first bias voltage Vgs1 to the amplifier AM, which is the first supply destination. The first bias circuit 4 is a variable voltage source that sets the amplification drain current Ids of the first transistor 1, the second transistor 2, and the third transistor 3, whose output sides are connected in series with each other, to a predetermined value using the first bias voltage Vgs1. 【0030】 Furthermore, the second output terminal of the first bias circuit 4 is connected to the gate terminal of the fourth transistor 7. The first bias circuit 4 generates a second bias voltage Vgs2 that is variable within a predetermined voltage range, and applies the second bias voltage Vgs2 as the gate bias voltage to the gate terminal of the fourth transistor 7. 【0031】In other words, the first bias circuit 4 outputs the second bias voltage Vgs2 to the load LO, which is the second supply destination. The first bias circuit 4 sets the load drain currents Ivds of the fourth transistor 7, fifth transistor 8, and sixth transistor 9, whose output sides are connected in series with each other, to a predetermined value using the second bias voltage Vgs2. 【0032】 The output terminal of the second bias circuit 5 is connected to the gate terminal of the third transistor 3. The second bias circuit 5 is a fixed voltage source that generates a fixed voltage, the third bias voltage Vgs3, and applies the third bias voltage Vgs3 as the gate bias voltage to the gate terminal of the third transistor 3. The second bias circuit 5 sets the operating point of the third transistor 3. 【0033】 The load circuit 6 is a two-terminal circuit in which the first terminal is connected to the drain terminal of the third transistor 3, the gate and drain terminals of the sixth transistor 9, and the first terminal of the capacitor 10, and the second terminal (the other terminal) is connected to the power supply terminal Td. The load circuit 6 has a predetermined impedance and sets the voltage amplification factor of the first transistor 1. 【0034】 Here, the drain terminal of the third transistor 3, which is interconnected in the amplification unit AM, and the first terminal of the load circuit 6 are the output terminals of the amplification unit AM. That is, the output terminal of the amplification unit AM is connected to the first terminal of the load unit LO, and it outputs an amplified signal, obtained by inverting and amplifying the input signal (high-frequency signal), to the load unit LO. The voltage amplification factor of the amplification unit AM is varied by changing the amplification drain current Ids (amplification current) flowing through it. 【0035】 The power supply terminal Td is connected to the second end of the load circuit 6. The power supply terminal Td is also connected to a DC power supply of a predetermined voltage outside the variable gain amplifier A. The power supply terminal Td supplies operating power to the first transistor 1, the second transistor 2, and the third transistor 3 via the load circuit 6. 【0036】The fourth transistor 7 is an n-type MOS transistor, similar to the first to third transistors 1 to 3. The gate terminal of the fourth transistor 7 is connected to the second output terminal of the first bias circuit 4, the source terminal is connected to the second ground terminal Tg2, and the drain terminal is connected to the source terminal of the fifth transistor 8. The load drain current Ivds of the fourth transistor 7 is set by the second bias voltage Vgs2 input to the gate terminal from the first bias circuit 4. 【0037】 The second grounding terminal Tg2 is connected to the source terminal of the fourth transistor 7. Furthermore, the second grounding terminal Tg2 is connected to ground potential (GND) outside of the variable gain amplifier A. The second grounding terminal Tg2 sets the source terminal of the fourth transistor 7 to ground potential (GND). 【0038】 The fifth transistor 8 is an n-type MOS transistor, similar to the fourth transistor 7. The gate terminal of the fifth transistor 8 is connected to its own drain terminal and the source terminal of the sixth transistor 9, and its drain terminal is connected to its own gate terminal and the source terminal of the sixth transistor 9, and its source terminal is connected to the drain terminal of the fourth transistor 7. In other words, the gate terminal and drain terminal of the fifth transistor 8 are connected in common. 【0039】 The sixth transistor 9 is an n-type MOS transistor, similar to the fourth transistor 7 and the fifth transistor 8. The gate terminal of the sixth transistor 9 is connected to its own drain terminal, the drain terminal of the third transistor 3, the first terminal of the load circuit 6, and the first terminal of the capacitor 10. The drain terminal of the sixth transistor 9 is also connected to its own gate terminal, the drain terminal of the third transistor 3, the first terminal of the load circuit 6, and the first terminal of the capacitor 10. The source terminal is connected to the drain terminal and gate terminal of the fifth transistor 8. In other words, the gate terminal and drain terminal of the sixth transistor 9 are commonly connected, similar to the fifth transistor 8. 【0040】The fourth transistor 7, the fifth transistor 8, and the sixth transistor 9 that constitute the load section LO are load transistors of the same size. That is, the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9 are process-designed so that their element sizes are the same. 【0041】 Also, the total size of the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9 (load transistors) is set to be larger than the total size of the first transistor 1, the second transistor 2, and the third transistor 3 (amplifying transistors). 【0042】 In this embodiment, n-type MOS transistors are employed as the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9 that constitute the load section LO, but other types of transistors may be employed for the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9. For example, p-type MOS transistors may be employed as the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9. 【0043】 The capacitor 10 has its first end connected to the drain terminal of the third transistor 3, the first end of the load circuit 6, as well as the gate terminal and the drain terminal of the sixth transistor 9, and its second end (the other end) is connected to the output terminal Tout. The capacitor 10 is a coupling capacitor having a predetermined capacitance, and outputs only the amplified signal (high-frequency signal), which is an AC component, among the amplified signal (high-frequency signal) input from the output end of the amplifying section AM to the first end and the drain voltage (DC voltage), to the output terminal Tout. 【0044】 Here, the gate terminal and the drain terminal of the sixth transistor 9 that are interconnected, as well as the first end of the capacitor 10, correspond to the first end of the load section LO connected to the output end of the amplifying section AM. The load section LO functions as a load for the amplifying section AM. Also, the load drain current Ivds is an amount that sets the degree of the load on the amplifying section AM of the load section LO. 【0045】The output terminal Tout is connected to the second terminal of the capacitor 10. Also, the output terminal Tout is connected to the input terminal of the subsequent-stage circuit outside the variable gain amplifier A. The output terminal Tout outputs an amplified signal (high-frequency signal), which is the output signal of the variable gain amplifier A, toward the subsequent-stage circuit. 【0046】 Next, the four first bias circuits according to the present embodiment, that is, the bias circuit according to the present invention, will be described in detail with reference to FIG. 2. As shown in FIG. 2, the first bias circuit 4 includes a variable current source 11, a seventh transistor 12, an eighth transistor 13, a constant current source 14, a ninth transistor 15, a tenth transistor 16, a second power supply terminal Td2, a third ground terminal Tg3, a first bias output terminal Tb1, and a second bias output terminal Tb2. 【0047】 In the first bias circuit 4, the seventh transistor 12, the eighth transistor 13, the ninth transistor 15, and the tenth transistor 16 excluding the variable current source 11 and the constant current source 14 constitute the voltage generation unit VG in the present embodiment. That is, the first bias circuit 4 in the present embodiment includes a variable current source 11, a constant current source 14, and a voltage generation unit VG. 【0048】 The input terminal of the variable current source 11 is connected to the second power supply terminal Td2 and the input terminal of the constant current source 14, and the output terminal is connected to the gate terminal and drain terminal of the seventh transistor 12 and the gate terminal and drain terminal of the eighth transistor 13. The variable current source 11 generates a variable current Iv that can be freely varied within a predetermined range based on the DC power supply input from the second power supply terminal Td2, and outputs the variable current Iv to the seventh transistor 12 and the eighth transistor 13. 【0049】 The seventh transistor 12 is an n-type MOS transistor similar to the first transistor 1. The gate terminal of the seventh transistor 12 is connected to its own drain terminal, the output terminal of the variable current source 11, the gate terminal and drain terminal of the eighth transistor 13, and the gate terminal of the ninth transistor 15, and the drain terminal is connected to its own gate terminal, the output terminal of the variable current source 11, the gate terminal and drain terminal of the eighth transistor 13, and the gate terminal of the ninth transistor 15. 【0050】 Furthermore, the source terminal of the seventh transistor 12 is connected to the third ground terminal Tg3, the source terminal of the eighth transistor 13, the source terminal of the ninth transistor 15, and the source terminal of the tenth transistor 16. In other words, the gate terminal and drain terminal of the seventh transistor 12 are connected in common. 【0051】 The seventh transistor 12, together with the ninth transistor 15, constitutes a first current mirror circuit. The first current mirror circuit uses the shunt current Ia of the variable current Iv as the reference current (first reference current). That is, the drain current Ia flowing from the drain terminal to the source terminal of the ninth transistor 15 is the same current value as the first reference current flowing from the drain terminal to the source terminal of the seventh transistor 12. 【0052】 The eighth transistor 13 is an n-type MOS transistor, similar to the second transistor 2. The gate terminal of the eighth transistor 13 is connected to its own drain terminal, the output terminal of the variable current source 11, the gate and drain terminals of the seventh transistor 12, the gate terminal of the ninth transistor 15, and the first bias output terminal Tb1, while the drain terminal of the eighth transistor 13 is connected to its own gate terminal, the output terminal of the variable current source 11, the gate and drain terminals of the seventh transistor 12, the gate terminal of the ninth transistor 15, and the first bias output terminal Tb1. 【0053】 Furthermore, the source terminal of the eighth transistor 13 is connected to the third ground terminal Tg3, the source terminal of the seventh transistor 12, the source terminal of the ninth transistor 15, and the source terminal of the tenth transistor 16. In other words, the gate terminal and drain terminal of the eighth transistor 13 are connected in common. 【0054】 The eighth transistor 13 is provided in the amplification section AM (first supply destination) and forms a second current mirror circuit with the second transistor 2, whose gate terminals are commonly connected via the first bias output terminal Tb1. The eighth transistor 13 corresponds to the first output transistor of the present invention. 【0055】The second current mirror circuit uses the difference between the variable current Iv and the shunt current Ia as the reference current (second reference current). That is, the amplified drain current Ids flowing from the drain terminal to the source terminal of the second transistor 2 is the same current value as the second reference current flowing from the drain terminal to the source terminal of the eighth transistor 13. 【0056】 The constant current source 14 has its input terminal connected to the second power supply terminal Td2 and the input terminal of the variable current source 11, and its output terminal connected to the drain terminal of the ninth transistor 15 and the gate terminal and drain terminal of the tenth transistor 16. The constant current source 14 generates a predetermined fixed current Is based on the DC power supply input from the second power supply terminal Td2 and outputs the fixed current Is to the ninth transistor 15 and the tenth transistor 16. 【0057】 The ninth transistor 15 is an n-type MOS transistor, similar to the seventh transistor 12. The gate terminal of the ninth transistor 15 is connected to the gate and drain terminals of the seventh transistor 12, the output terminal of the variable current source 11, the gate and drain terminals of the eighth transistor 13, and the first bias output terminal Tb1. The drain terminal of the ninth transistor 15 is connected to the output terminal of the constant current source 14, the gate and drain terminals of the tenth transistor 16, and the second bias output terminal Tb2. 【0058】 Furthermore, the source terminal of the ninth transistor 15 is connected to the third ground terminal Tg3, the source terminal of the seventh transistor 12, the source terminal of the eighth transistor 13, and the source terminal of the tenth transistor 16. The drain current Ia of the ninth transistor 15 is the same as the drain current Ia of the seventh transistor 12. 【0059】 The tenth transistor 16 is an n-type MOS transistor, similar to the fourth transistor 7. The gate terminal of the tenth transistor 16 is connected to its own drain terminal, the output terminal of the constant current source 14, the drain terminal of the ninth transistor 15, and the second bias output terminal Tb2. 【0060】Furthermore, the source terminal of the 10th transistor 16 is connected to the third ground terminal Tg3, the source terminal of the 7th transistor 12, the source terminal of the 8th transistor 13, and the source terminal of the 9th transistor 15. In other words, the gate terminal and drain terminal of the 10th transistor 16 are connected in common. 【0061】 The tenth transistor 16 is located in the load section LO (second supply destination) and forms a third current mirror circuit with the fourth transistor 7, whose gate terminals are commonly connected via the second bias output terminal Tb2. The tenth transistor 16 corresponds to the second output transistor of the present invention. 【0062】 The third current mirror circuit uses the difference between the fixed current Is and the shunt current Ia as the reference current (third reference current). That is, the load drain current Ivds flowing from the drain terminal to the source terminal of the fourth transistor 7 is the same current value as the third reference current flowing from the drain terminal to the source terminal of the tenth transistor 16. 【0063】 Here, the drain terminals of the 10th transistor 16 and the 9th transistor 15 are commonly connected to the output terminal of the constant current source 14, as shown in the figure. Therefore, the drain current of the 10th transistor 16 is the current value obtained by subtracting the drain current Ia of the 9th transistor 15 from the fixed current Is output from the constant current source 14 to the 10th transistor 16 and the 9th transistor 15. 【0064】 Furthermore, the drain current Ia of the ninth transistor 15 is the same value as the drain current Ia of the seventh transistor 12, and the drain terminals of the seventh transistor 12 and the eighth transistor 13 are commonly connected to the output terminal of the variable current source 11. Therefore, the drain current Ia of the ninth transistor 15 is the current value obtained by subtracting the drain current of the eighth transistor 13 (amplified drain current Ids) from the variable current Iv of the variable current source 11. 【0065】In other words, in the variable gain amplifier A according to this embodiment, the following equations (1) and (2) hold true for the amplified drain current Ids and the load drain current IVds. Ids = Iv - Ia (1) IVds = Is - Ia = Is - (Iv - Ids) = (Is + Ids) - Iv (2) 【0066】 As shown by equations (1) and (2), a constant relationship exists between the amplified drain current Ids and the load drain current IVds. Furthermore, the amplified drain current Ids increases as the variable current Iv increases. In contrast, the load drain current IVds decreases as the variable current Iv increases. 【0067】 In other words, the voltage generation unit VG of the first bias circuit 4 generates a first bias voltage Vgs1 that changes the amplification drain current Ids of the amplification unit AM (first supply destination) by a positive or negative rate of change, and a second bias voltage Vgs2 that changes the load drain current Ivds of the load unit LO (second supply destination) by a negative or positive rate of change, based on the variable current Iv input from the variable current source 11 and the fixed current Is input from the constant current source 14. 【0068】 The second power supply terminal Td2 is connected to the input terminals of the variable current source 11 and the constant current source 14. Furthermore, like the power supply terminal Td, the second power supply terminal Td2 is connected to a DC power supply of a predetermined voltage outside the variable gain amplifier A. The second power supply terminal Td2 supplies operating power to the variable current source 11 and the constant current source 14. 【0069】 The third grounding terminal Tg3 is connected to the source terminals of the seventh transistor 12, the eighth transistor 13, the ninth transistor 15, and the tenth transistor 16. Furthermore, like the first grounding terminal Tg1 and the second grounding terminal Tg2, the third grounding terminal Tg3 is connected to ground potential (GND) outside of the variable gain amplifier A. The third grounding terminal Tg3 sets the source terminals of the seventh transistor 12, the eighth transistor 13, the ninth transistor 15, and the tenth transistor 16 to ground potential (GND). 【0070】 The first bias output terminal Tb1 is connected to the gate and drain terminals of the eighth transistor 13, the output terminal of the variable current source 11, the gate and drain terminals of the seventh transistor 12, and the gate terminal of the ninth transistor 15. In addition, the first bias output terminal Tb1 is connected to the gate terminal of the second transistor 2 outside the first bias circuit 4. The first bias output terminal Tb1 supplies the first bias voltage Vgs1 to the gate terminal of the second transistor 2. 【0071】 The second bias output terminal Tb2 is connected to the gate and drain terminals of the tenth transistor 16, the output terminal of the constant current source 14, and the drain terminal of the ninth transistor 15. Furthermore, the second bias output terminal Tb2 is connected to the gate terminal of the fourth transistor 7 outside the first bias circuit 4. The second bias output terminal Tb2 supplies the second bias voltage Vgs2 to the gate terminal of the fourth transistor 7. 【0072】 Next, the operation of the variable gain amplifier A according to this embodiment will be described in detail with reference to Figures 2 and 3. 【0073】 In variable gain amplifier A, the first bias circuit 4 outputs a first bias voltage Vgs1 to the gate terminal of the second transistor 2 and a second bias voltage Vgs2 to the gate terminal of the fourth transistor 7. The second bias circuit 5 outputs a third bias voltage Vgs3 to the gate terminal of the third transistor 3. 【0074】 The second transistor 2 sets the amplification drain current Ids of the amplification unit AM (first power source), that is, the drain current of the first transistor 1, to a current value corresponding to the first bias voltage Vgs1. In addition, the third transistor 3 of the amplification unit AM (first power source) is set to an operating point corresponding to the third bias voltage Vgs3. 【0075】Then, the first transistor 1 of the amplification unit AM (first supply destination) inverts and amplifies the input signal (high-frequency signal) input to its gate terminal with a gain corresponding to the amplification drain current Ids and the impedance of the load circuit 6, etc., while the second transistor 2 and the third transistor 3 are operating. 【0076】 The first transistor 1 then outputs an amplified signal, which is in opposite phase to the input signal (high-frequency signal), to its drain terminal, that is, to the source terminal of the third transistor 3. The third transistor 3 outputs the amplified signal input from the first transistor 1 to its drain terminal, that is, to the output terminal of the amplification unit AM (first supply destination), without inverting its phase, while remaining in phase. 【0077】 The amplification gain gm of the amplification unit AM (first supply destination) changes in accordance with the amplification drain current Ids, i.e., the first bias voltage Vgs1. That is, when the first bias voltage Vgs1 (amplification drain current Ids) increases at a positive rate of change, the amplification gain gm of the amplification unit AM (first supply destination) increases, and when the first bias voltage Vgs1 (amplification drain current Ids) decreases at a negative rate of change, the amplification gain gm of the amplification unit AM (first supply destination) decreases. 【0078】 Here, the first bias circuit 4 has a change characteristic in which the second bias voltage Vgs2 decreases as the first bias voltage Vgs1 increases, as described above. That is, when increasing the amplification gain gm of the amplification section AM, for example, the first bias circuit 4 increases the first bias voltage Vgs1 to increase the amplification drain current Ids, as shown in Figure 3. 【0079】 In this case, the first bias circuit 4, contrary to the first bias voltage Vgs1, reduces the second bias voltage Vgs2 as shown in Figure 3, thereby decreasing the load drain current Ivds of the load section LO at a negative rate of change. That is, the load section LO reduces the load drain current Ivds at a negative rate of change by lowering the gate voltage of the fourth transistor 7 with the second bias voltage Vgs2, thereby reducing the load amount of the amplifier section AM. 【0080】Here, the load LO functions as a load together with the load circuit 6 in the inverting amplification of the input signal (high-frequency signal) in the amplification unit AM. That is, since the first end of the load LO is connected to the output terminal of the amplification unit AM, just like the first end of the load circuit 6, it acts as part of the load in the inverting amplification process of the input signal (high-frequency signal) in the first transistor 1. 【0081】 In other words, when the amplification gain gm of the amplification unit AM is increased by increasing the amplification drain current Ids at a positive rate of change, the load drain current Ivds decreases at a negative rate of change. Figure 4 is a characteristic diagram showing the linearity of the variable gain amplifier A according to this embodiment. As shown in Figure 4, the linearity of the variable gain amplifier A is improved compared to the reference example without a load unit LO. Note that in the characteristic diagram of Figure 4, the improvement in linearity is not clearly visible because the horizontal axis is on a linear scale, but the improvement in linearity can be clearly seen when the horizontal axis is on a log (log) scale. 【0082】 The first bias circuit 4 in this embodiment includes a variable current source 11 that outputs a variable current Iv, a constant current source 14 that outputs a fixed current Is, and a voltage generation unit VG that generates a first bias voltage Vgs1 that changes the amplification drain current Ids of the amplification unit AM (first supply destination) at a positive or negative rate of change, and a second bias voltage Vgs2 that changes the load drain current Ivds of the load unit LO (second supply destination) at a negative or positive rate of change, based on the variable current Iv and the fixed current Is. 【0083】 The first bias circuit 4 generates a pair of bias voltages, namely a first bias voltage Vgs1 and a second bias voltage Vgs2, which generate currents with different rates of change based on a variable current Iv and a fixed current Is. According to this embodiment, since separate bias circuits are not provided for generating the first bias voltage Vgs1 and the second bias voltage Vgs2, it is possible to provide a first bias circuit 4 (bias circuit) that can suppress an increase in circuit area. 【0084】Furthermore, in the first bias circuit 4 (bias circuit) according to this embodiment, the voltage generation unit VG includes a first current mirror circuit that uses the diverged current Ia of the variable current Iv as the first reference current, an eighth transistor 13 (first output transistor) that forms a second current mirror circuit with a second transistor 2 (first supply destination transistor) provided in the amplification unit AM (first supply destination) and uses the difference current between the variable current Iv and the diverged current Ia as the second reference current, and a tenth transistor 16 (second output transistor) that forms a third current mirror circuit with a fourth transistor 7 (second supply destination transistor) provided in the load unit LO (second supply destination) and uses the difference current between the fixed current Is and the diverged current Ia as the third reference current. 【0085】 According to this embodiment, since the first bias voltage Vgs1 and the second bias voltage Vgs2 are generated based on the variable current Iv and the fixed current Is, it is possible to set the amplified drain current Ids and the load drain current IVds with high accuracy. 【0086】 Furthermore, in the first bias circuit 4 (bias circuit) according to this embodiment, the first supply destination is the amplifier AM that amplifies the input signal, and the first bias voltage Vgs1 sets the amplification gain gm of the amplifier AM. According to this embodiment, it is possible to set the amplification gain gm of the amplifier AM with high accuracy. 【0087】 Furthermore, in the first bias circuit 4 (bias circuit) according to this embodiment, the second supply destination is the load unit LO, whose first end is connected to the output terminal of the amplifier unit AM, and the second bias voltage Vgs2 sets the load drain current Ivds (load current) flowing to the load unit LO. According to this embodiment, it is possible to set the load amount of the load unit LO with high accuracy. 【0088】Furthermore, the variable gain amplifier A according to this embodiment includes a first bias circuit 4 (bias circuit), an amplification unit AM that amplifies and outputs an input signal with an amplified drain current Ids set based on a first bias voltage Vgs1, and a load unit LO whose first end is connected to the output terminal of the amplification unit AM, and whose load drain current Ivds (load current) is set based on a second bias voltage Vgs2. According to this embodiment, it is possible to provide a variable gain amplifier A that can ensure linearity while suppressing an increase in circuit area. 【0089】 The present invention is not limited to the above embodiments, and the following modifications are possible, for example: (1) In the above embodiments, the case in which the first bias voltage Vgs1 is supplied to the amplification unit AM (first supply destination) and the second bias voltage Vgs2 is supplied to the load unit LO (second supply destination) has been described, but the present invention is not limited thereto. That is, the first supply destination may be a circuit or circuit element other than the amplification unit AM, and the second supply destination may be a circuit or circuit element other than the load unit LO. 【0090】 (2) In the above embodiment, the case in which the voltage generation unit VG is configured by the seventh transistor 12, the eighth transistor 13, the ninth transistor 15, and the tenth transistor 16 has been described, but the present invention is not limited thereto. That is, the voltage generation unit VG may adopt a circuit configuration other than the one shown in Figure 2. 【0091】 (3) In the above embodiment, the circuit configuration of the amplification section AM was a common-source inverting amplifier, but the present invention is not limited thereto. That is, the amplification section AM may be configured as a circuit other than a common-source inverting amplifier. 【0092】(4) In the above embodiment, the first transistor 1, second transistor 2, third transistor 3, fourth transistor 7, fifth transistor 8, sixth transistor 9, seventh transistor 12, eighth transistor 13, ninth transistor 15, and tenth transistor 16 are unipolar n-type MOS transistors or p-type MOS transistors, but the present invention is not limited thereto. For example, bipolar transistors may be used instead of unipolar transistors for the first transistor 1, second transistor 2, third transistor 3, fourth transistor 7, fifth transistor 8, sixth transistor 9, seventh transistor 12, eighth transistor 13, ninth transistor 15, and tenth transistor 16. 【0093】 A...Variable gain amplifier, Tin...Input terminal, Tg1...First ground terminal, Tg2...Second ground terminal, Td...Power supply terminal, Tout...Output terminal, 1...First transistor, 2...Second transistor, 3...Third transistor, 4...First bias circuit, 5...Second bias circuit, 6...Load circuit, 7...Fourth transistor, 8...Fifth transistor, 9...Sixth transistor, 10...Capacitor, 11...Variable current source, 12...Seventh transistor, 13...Eighth transistor, 14...Constant current source, 15...Ninth transistor, 16...Tenth transistor, Td2...Second power supply terminal, Tg3...Third ground terminal, Tb1...First bias output terminal, Tb2...Second bias output terminal

Claims

1. A bias circuit comprising: a variable current source that outputs a variable current; a constant current source that outputs a fixed current; and a voltage generation unit that generates a first bias voltage that changes the current of a first supply destination by a positive rate of change and a second bias voltage that changes the current of a second supply destination by a negative rate of change, or a first bias voltage that changes the current of the first supply destination by a negative rate of change and a second bias voltage that changes the current of the second supply destination by a positive rate of change, based on the variable current and the fixed current.

2. The bias circuit according to claim 1, wherein the voltage generation unit comprises: a first current mirror circuit that uses the shunt current of the variable current as a first reference current; a first output transistor that uses the difference current between the variable current and the shunt current as a second reference current and constitutes a second current mirror circuit with a first supply destination transistor provided at the first supply destination; and a second output transistor that uses the difference current between the fixed current and the shunt current as a third reference current and constitutes a third current mirror circuit with a second supply destination transistor provided at the second supply destination.

3. The bias circuit according to claim 1 or 2, wherein the first supply destination is an amplification unit that amplifies an input signal, and the first bias voltage sets the amplification gain of the amplification unit.

4. The bias circuit according to claim 3, wherein the second supply destination is a load unit whose first end is connected to the output terminal of the amplification unit, and the second bias voltage sets the load current flowing through the load unit.

5. A variable gain amplifier comprising: a bias circuit according to any one of claims 1 to 4; an amplification unit that amplifies and outputs an input signal with an amplification current set based on the first bias voltage; and a load unit whose first end is connected to the output terminal of the amplification unit and whose load current is set based on the second bias voltage.

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